Current integral mode phase interpolator and method

Abstract

The invention belongs to the field of integrated circuits, and discloses a current integration mode phase interpolator and a method. The phase interpolator integrates a multimode frequency divider, a pulse generation module, a phase interpolator array and a reset module comprising an anti-interference unit and a self-reset feedback unit; effective frequency division of an input clock signal, accurate phase interpolation pulse signal generation and efficient reset operation are realized; the anti-interference unit can effectively isolate the interference of environment change, such as temperature change and power supply voltage fluctuation, on the performance of the phase interpolator; meanwhile, the self-reset feedback unit significantly improves the charge reset rate, thereby jointly improving the phase linearity and precision of the phase interpolator, ensuring the synchronism, integrity and stability of data transmission, and meeting the strict requirements for data transmission quality and system stability in practical engineering.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a current integral mode phase interpolator and a method thereof. Background Art

[0002] In the field of integrated circuits, phase interpolators are a key component that is often used to accurately adjust the delay of data or clock signals. This function is essential to ensure the synchronization and integrity of data transmission. It can be seen that the performance of the phase interpolator, especially its phase linearity, directly determines the overall performance of the system to which it belongs.

[0003] Taking the clock and data recovery system as an example, the phase interpolator plays an important role in adjusting the clock delay. In order to minimize the jitter introduced in the clock and data recovery process, the phase interpolator needs to have excellent accuracy and extremely high phase linearity. Only in this way can the stability and accuracy of the data during transmission be ensured.

[0004] However, traditional phase interpolators face a series of challenges in practical applications. Since they are often easily disturbed by environmental factors such as temperature changes and power supply voltage fluctuations, these interference factors will lead to the degradation of phase interpolator performance, especially the lack of phase linearity; this deficiency will directly affect the quality of data transmission and the stability of the system, and thus cannot meet the stringent requirements in actual engineering. Summary of the invention

[0005] The present invention provides a current integral mode phase interpolator and method to solve the technical problem that the existing phase interpolator is easily disturbed by environmental factors, resulting in insufficient linearity of the phase interpolator.

[0006] In order to achieve the above object, the present invention adopts the following technical solution: In a first aspect, the present invention provides a current integrating mode phase interpolator, comprising: a multi-mode frequency divider, a pulse generating module, a phase interpolator array and a reset module; The multi-mode frequency divider is used to divide the frequency of the input clock signal; The pulse generating module is used to receive the clock signal divided by the multi-mode frequency divider, and generate a pulse signal for phase interpolation and a reset signal for resetting according to the divided clock signal; The phase interpolator array is used to receive the pulse signal of the pulse generating module and generate an output signal according to the pulse signal; The reset module is used to receive the reset signal of the pulse generation module and the output signal of the phase interpolator array, and to reset the phase interpolator according to the reset signal and the output signal; The reset module includes an anti-interference unit for isolating clock interference and a self-reset feedback unit for increasing the charge reset rate.

[0007] A further improvement of the present invention is that the output end of the multi-mode divider is connected to the first input end of the pulse generating module; the input end of the multi-mode divider is connected in parallel to the second input end of the pulse generating module; the first output end of the pulse generating module is connected to the first input end of the reset module; the second output end of the pulse generating module is connected to the second input end of the reset module; the third output end of the pulse generating module is connected to the first input end of the phase interpolator array; the fourth output end of the pulse generating module is connected to the second input end of the phase interpolator array; the output end of the phase interpolator array is connected to the third input end of the reset module.

[0008] A further improvement of the present invention is that the pulse generating module includes a first trigger DFF1, a second trigger DFF2, a third trigger DFF3, a fourth trigger DFF4, a fifth trigger DFF5, and a sixth trigger DFF6; The input end of the multi-mode divider, the clock input end of the first trigger DFF1, the clock input end of the second trigger DFF2, the clock input end of the third trigger DFF3, the clock input end of the fourth trigger DFF4, the clock input end of the fifth trigger DFF5 and the clock input end of the sixth trigger DFF6 are connected in parallel.

[0009] A further improvement of the present invention is that the pulse generating module further comprises: a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a first capacitor array C0 and a second capacitor array C1; The output end of the multi-mode frequency divider is connected to the data input end of the first flip-flop DFF1 and the data input end of the third flip-flop DFF3 respectively; The output terminal of the first flip-flop DFF1 is connected to the data input terminal of the second flip-flop DFF2 and the input terminal of the first inverter INV1 respectively; The output end of the second flip-flop DFF2 is connected to the input end of the second inverter INV2; The output terminal of the third flip-flop DFF3 is connected to the data input terminal of the fourth flip-flop DFF4 and the data input terminal of the fifth flip-flop DFF5 respectively; The output terminal of the fourth flip-flop DFF4 is connected to the data input terminal of the sixth flip-flop DFF6; The output end of the fifth trigger DFF5 is connected to the upper plate of the first capacitor array C0 and the input end of the third inverter INV3 respectively; The output end of the sixth flip-flop DFF6 is connected to the upper plate of the second capacitor array C1 and the input end of the fourth inverter INV4 respectively; The output end of the first inverter INV1 is connected to the first input end of the reset module; The output end of the second inverter INV2 is connected to the second input end of the reset module; The output end of the third inverter INV3 is connected to the first input end of the phase interpolator array; An output terminal of the fourth inverter INV4 is connected to a second input terminal of the phase interpolator array.

[0010] A further improvement of the present invention is that the pulse generating module further comprises: a lower plate of the first capacitor array C0 is connected to GND; and a lower plate of the second capacitor array C1 is connected to GND.

[0011] A further improvement of the present invention is that the phase interpolator array comprises a plurality of phase interpolator core modules connected in parallel; The phase interpolator core module includes a first NMOS tube M1, a second NMOS tube M2, a third NMOS tube M4, a first PMOS tube M3, a two-select-one switch SEL, a fifth inverter INV5 and a sixth inverter INV6; The gate terminal of the first NMOS transistor M1 is connected to the input terminal EN, the source terminal of the first NMOS transistor M1 is connected to the input terminal Vbn, and the drain terminal of the first NMOS transistor M1 is connected to the gate terminal of the second NMOS transistor M2; The source end of the second NMOS tube M2 is connected to the drain end of the first PMOS tube M3 and the drain end of the third NMOS tube M4 respectively, and the drain end of the second NMOS tube M2 is connected to the third input end of the reset module; The source end of the first PMOS transistor M3 is connected to VDD, and the gate end of the first PMOS transistor M3 is connected to the gate end of the third NMOS transistor M4 and the output end of the two-select-one switch SEL respectively; The source end of the third NMOS tube M4 is connected to GND; The input end of the two-select-one switch SEL can be selectively connected to the output end of the fifth inverter INV5 or the output end of the sixth inverter INV6 respectively; An input end of the fifth inverter INV5 is connected to an output end of the third inverter INV3 ; an input end of the sixth inverter INV6 is connected to an output end of the fourth inverter INV4 .

[0012] A further improvement of the present invention is that the reset module includes a second PMOS tube M5, a third PMOS tube M7, a fourth NMOS tube M6, a fifth NMOS tube M8, a capacitor C2 and a seventh inverter INV7; wherein the anti-interference unit is the fifth NMOS tube M8; the self-reset feedback unit is the fourth NMOS tube M6; The gate end of the second PMOS tube M5 is connected to the first output end of the pulse generating module, the source end of the second PMOS tube M5 is connected to VDD, and the drain end of the second PMOS tube M5 is connected to the output end of the phase interpolator array; The upper plate of the capacitor C2 is connected to VDD, and the lower plate of the capacitor C2 is connected to the output end of the phase interpolator array; The gate end of the fourth NMOS tube M6 is connected to the output end of the seventh inverter INV7, the drain end of the fourth NMOS tube M6 is connected to VDD, and the source end of the fourth NMOS tube M6 is connected to the output end of the phase interpolator array; The gate end of the third PMOS tube M7 is connected to the second output end of the pulse generating module, the source end of the third PMOS tube M7 is connected to VDD, and the drain end of the third PMOS tube M7 is respectively connected to the source end of the fifth NMOS tube M8 and the input end of the seventh inverter INV7; The gate terminal of the fifth NMOS tube M8 is connected to the VBN port, and the drain terminal of the fifth NMOS tube M8 is connected to the output terminal of the phase interpolator array.

[0013] In a second aspect, the present invention provides a working method of a current integral mode phase interpolator, based on the above-mentioned current integral mode phase interpolator, comprising: The multi-mode frequency divider divides the input clock signal; The pulse generating module generates a pulse signal for phase interpolation and a reset signal for resetting according to the received divided clock signal; The phase interpolator array generates an output signal based on the received pulse signal; The reset module resets the phase interpolator according to the received reset signal and the output signal; Among them, the anti-interference unit is used to isolate the clock interference, and the charge reset rate is increased through the self-reset feedback unit.

[0014] A further improvement of the present invention is that The pulse generating module generates two clock signals with a phase difference of 2π and two reset signals according to the received divided clock signal.

[0015] A further improvement of the present invention is that The self-resetting feedback unit starts working according to the working signal, and adopts the node charging method to offset the discharge current of the phase interpolator array, so as to improve the charge reset rate.

[0016] Compared with the prior art, the present invention has the following beneficial effects: The present invention provides a current integration mode phase interpolator, which realizes effective frequency division of input clock signal, accurate phase interpolation pulse signal generation, and efficient reset operation by integrating a multi-mode frequency divider, a pulse generation module, a phase interpolator array, and a reset module including an anti-interference unit and a self-reset feedback unit; its anti-interference unit can effectively isolate environmental changes, such as temperature changes and power supply voltage fluctuations, from interfering with the performance of the phase interpolator; at the same time, the self-reset feedback unit significantly improves the charge reset rate, thereby jointly improving the phase linearity and accuracy of the phase interpolator, ensuring the synchronization, integrity and stability of data transmission, and meeting the stringent requirements for data transmission quality and system stability in actual engineering. Compared with traditional phase interpolators, this phase interpolator improves the linearity of the current integration mode phase interpolator, enhances the ability to resist environmental interference, reduces power consumption, and has engineering application advantages.

[0017] Preferably, in the present invention, multiple triggers are introduced into the pulse generation module to achieve accurate control and processing of the clock signal, thereby providing a guarantee for generating high-quality phase interpolation pulse signals.

[0018] Preferably, in the present invention, by introducing an inverter and a capacitor array, the function and flexibility of the pulse generation module are further enhanced, and the accuracy and stability of phase interpolation are improved.

[0019] Preferably, in the present invention, the lower plate of the capacitor array is grounded to ensure the normal operation of the capacitor and the stable transmission of the signal.

[0020] Preferably, in the present invention, a plurality of parallel phase interpolator core modules are used to achieve parallel processing of input signals, thereby improving the efficiency and accuracy of phase interpolation.

[0021] Preferably, in the present invention, the anti-interference unit and the self-reset feedback unit in the reset module respectively improve the system's resistance to clock interference and the charge reset rate, thereby ensuring the stability and accuracy of the phase interpolator.

[0022] The present invention provides a working method of a current integrating mode phase interpolator. Based on the above current integrating mode phase interpolator, the method effectively divides the input clock signal by a multi-mode frequency divider, generates accurate phase interpolation pulses and reset signals according to the frequency division signal by a pulse generation module, generates output signals according to the pulse signal by a phase interpolator array, and realizes efficient reset by combining an anti-interference unit and a self-reset feedback unit with a reset module. The method not only enhances the resistance of the phase interpolator to clock interference, but also significantly improves the charge reset rate, thereby effectively improving the phase linearity and accuracy of the phase interpolator, ensuring the synchronization and integrity of data transmission, and meeting the stringent requirements for high-performance phase interpolators in practical engineering, especially when dealing with environmental factors such as temperature changes and power supply voltage fluctuations. .

[0023] Preferably, in the present invention, by generating two clock signals with a phase difference of 2π and two reset signals, a rich control signal is provided for the phase interpolator, thereby improving the flexibility and accuracy of phase interpolation.

[0024] Preferably, in the present invention, the self-resetting feedback unit offsets the discharge current of the phase interpolator array by node charging, which significantly improves the charge reset rate, thereby ensuring the fast response and stability of the phase interpolator. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of the structure of a current integral mode phase interpolator provided by an embodiment of the present invention; Figure 2 A working principle diagram of a phase interpolator array provided in an embodiment of the present invention; Figure 3 A circuit diagram of a reset module provided by an embodiment of the present invention; Figure 4 A schematic diagram of a reset module provided in an embodiment of the present invention; Figure 5 A schematic diagram of the linearity performance of a current integral mode phase interpolator provided in an embodiment of the present invention; wherein (a) is a differential nonlinearity (DNL) performance diagram of the phase interpolator; and (b) is a integral nonlinearity (INL) performance diagram of the phase interpolator. DETAILED DESCRIPTION

[0026] In order to further understand the content of the present invention, the present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the embodiments are only for explaining the present invention and are not intended to limit it.

[0027] As mentioned in the background technology, currently, traditional phase interpolators face a series of challenges in practical applications. Since they are often easily disturbed by environmental factors, such as temperature changes, power supply voltage fluctuations, etc., these interference factors will cause the performance of the phase interpolator to deteriorate, especially the lack of phase linearity; this deficiency will directly affect the quality of data transmission and the stability of the system, and thus cannot meet the stringent requirements in actual engineering.

[0028] In order to solve the above problems, the present embodiment provides a current integrating mode phase interpolator. The present embodiment adopts two-phase clock phase interpolation, adds a calibration module, designs a phase interpolation unit with a transistor plus resistor stacking structure, adds an NMOS switch and a self-resetting feedback transistor in the phase interpolator reset circuit and other technologies, and designs a current integrating mode phase interpolator. Compared with the traditional phase interpolator, the linearity of the current integrating mode phase interpolator is improved, the ability to resist environmental interference is enhanced, the power consumption is reduced, and it has engineering application advantages.

[0029] The present embodiment provides a current integrating mode phase interpolator, comprising: a multi-mode divider, a pulse generating module, a phase interpolator array and a reset module; the multi-mode divider is used to divide the input clock signal; the pulse generating module is used to receive the clock signal divided by the multi-mode divider, and generate a pulse signal for phase interpolation and a reset signal for resetting according to the divided clock signal; the phase interpolator array is used to receive the pulse signal of the pulse generating module, and generate an output signal according to the pulse signal; the reset module is used to receive the reset signal of the pulse generating module and the output signal of the phase interpolator array, and reset the phase interpolator according to the reset signal and the output signal; wherein the reset module comprises an anti-interference unit for isolating clock interference and a self-resetting feedback unit for increasing the charge reset rate.

[0030] The output end of the multi-mode frequency divider is connected to the first input end of the pulse generating module; the input end of the multi-mode frequency divider is connected in parallel to the second input end of the pulse generating module; the first output end of the pulse generating module is connected to the first input end of the reset module; the second output end of the pulse generating module is connected to the second input end of the reset module; the third output end of the pulse generating module is connected to the first input end of the phase interpolator array; the fourth output end of the pulse generating module is connected to the second input end of the phase interpolator array; the output end of the phase interpolator array is connected to the third input end of the reset module.

[0031] It can be seen that the phase interpolator realizes effective frequency division of the input clock signal, accurate phase interpolation pulse signal generation, and efficient reset operation by integrating a multi-mode divider, a pulse generation module, a phase interpolator array, and a reset module including an anti-interference unit and a self-reset feedback unit; its anti-interference unit can effectively isolate environmental changes, such as temperature changes and power supply voltage fluctuations, from interfering with the performance of the phase interpolator; at the same time, the self-reset feedback unit significantly improves the charge reset rate, thereby jointly improving the phase linearity and accuracy of the phase interpolator, ensuring the synchronization, integrity and stability of data transmission, and meeting the stringent requirements for data transmission quality and system stability in actual engineering.

[0032] The current integral mode phase interpolator provided in this embodiment is further explained below in conjunction with the accompanying drawings: like Figure 1 As shown, the present application provides a current integrating mode phase interpolator, including: a multi-mode divider, a pulse generating module, a phase interpolator array and a reset module; the output end of the multi-mode divider is connected to the first input end of the pulse generating module; the second input end of the multi-mode divider is connected to the second input end of the pulse generating module; the first output end and the second output end of the pulse generating module are connected to the first input end and the second input end of the reset module; the third output end and the fourth output end of the pulse generating module are connected to the first input end and the second input end of the phase interpolator array; the output end of the phase interpolator array is connected to the third input end of the reset module.

[0033] The pulse generating module comprises: a first trigger DFF1, a second trigger DFF2, a third trigger DFF3, a fourth trigger DFF4, a fifth trigger DFF5, a sixth trigger DFF6, a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a first capacitor array C0 and a second capacitor array C1; wherein the output end of the multi-mode frequency divider is respectively connected to the data input end of the first trigger DFF1 and the third trigger DFF3; the input end of the multi-mode frequency divider, the first trigger DFF1, the second trigger DFF2, the third trigger DFF3, the fourth trigger DFF4, the clock input end of the fifth trigger DFF5 and the sixth trigger DFF6 are connected in parallel; the output end of the first trigger DFF1 is respectively connected to the data input end of the second trigger DFF2 and the input end of the first inverter INV1; the output end of the second trigger DFF2 is connected to the input end of the second inverter INV2 The output end of the third trigger DFF3 is respectively connected to the data input end of the fourth trigger DFF4 and the data input end of the fifth trigger DFF5; the output end of the fourth trigger DFF4 is connected to the data input end of the sixth trigger DFF6; the output end of the fifth trigger DFF5 is respectively connected to the upper plate of the first capacitor array C0 and the input end of the third inverter INV3; the output end of the sixth trigger DFF6 is respectively connected to the upper plate of the second capacitor array C1 and the input end of the fourth inverter INV4; the lower plate of the first capacitor array C0 is connected to GND; the lower plate of the second capacitor array C1 is connected to GND; the output end of the first inverter INV1 is connected to the first input end of the reset module; the output end of the second inverter INV2 is connected to the second input end of the reset module; the output end of the third inverter INV3 is connected to the first input end of the phase interpolator array; the output end of the fourth inverter INV4 is connected to the second input end of the phase interpolator array.

[0034] The phase interpolator array includes: N phase interpolator core modules connected in parallel, where N≥2. The phase interpolator core module includes a first NMOS tube M1, a second NMOS tube M2, a third NMOS tube M4, a first PMOS tube M3, a two-choice switch SEL, a fifth inverter INV5 and a sixth inverter INV6; the gate end of the first NMOS tube M1 is connected to the input end EN, the source end of the first NMOS tube M1 is connected to the input end Vbn, the drain end of the first NMOS tube M1 is connected to the gate end of the second NMOS tube M2; the source end of the second NMOS tube M2 is respectively connected to the drain end of the first PMOS tube M3 and the drain end of the third NMOS tube M4, and the second NMOS tube M2 is connected to the drain end of the third NMOS tube M4. The drain terminal of the first PMOS tube M3 is connected to the third input terminal of the reset module; the source terminal of the first PMOS tube M3 is connected to VDD, and the gate terminal of the first PMOS tube M3 is respectively connected to the gate terminal of the third NMOS tube M4 and the output terminal of the two-select-one switch SEL; the source terminal of the third NMOS tube M4 is connected to GND; the input terminal of the two-select-one switch SEL can be selectively connected to the output terminal of the fifth inverter INV5 or the output terminal of the sixth inverter INV6; the input terminal of the fifth inverter INV5 is connected to the output terminal of the third inverter INV3; the input terminal of the sixth inverter INV6 is connected to the output terminal of the fourth inverter INV4.

[0035] The reset module includes: a second PMOS transistor M5, a third PMOS transistor M7, a fourth NMOS transistor M6, a fifth NMOS transistor M8, a capacitor C2 and a seventh inverter INV7. The gate terminal of the second PMOS tube M5 is connected to the output terminal of the first inverter INV1, the source terminal of the second PMOS tube M5 is connected to VDD, and the drain terminal of the second PMOS tube M5 is connected to the drain terminal of the second NMOS tube M2; the upper plate of the capacitor C2 is connected to VDD, and the lower plate of the capacitor C2 is connected to the drain terminal of the second NMOS tube M2; the gate terminal of the fourth NMOS tube M6 is connected to the output terminal of the seventh inverter INV7, the drain terminal of the fourth NMOS tube M6 is connected to VDD, and the source terminal of the fourth NMOS tube M6 is connected to the drain terminal of the second NMOS tube M2; the gate terminal of the third PMOS tube M7 is connected to the output terminal of the second INV2, the source terminal of the third PMOS tube M7 is connected to VDD, and the drain terminal of the third PMOS tube M7 is respectively connected to the source terminal of the fifth NMOS tube M8 and the input terminal of the seventh inverter INV7; the gate terminal of the fifth NMOS tube M8 is connected to the VBN port, and the drain terminal of the fifth NMOS tube M8 is connected to the drain terminal of the second NMOS tube M2.

[0036] The current integral mode phase interpolator provided in this embodiment has the following advantages: only two-phase clocks are used for phase interpolation, which reduces power consumption, and also eliminates the phase nonlinearity caused by the transmission delay mismatch of different phases at the output end of the phase selector of the traditional phase interpolator, thereby improving the phase linearity; A variable capacitor array is added after the pulse generation module to calibrate the phase difference between the two-phase clocks, thereby improving the accuracy of the phase difference between the two-phase clocks and enhancing the circuit's ability to resist environmental interference; The phase interpolation unit is designed with a transistor + resistor stack structure to reduce the impact of environmental changes on linearity; The gate of the current source in the phase interpolation unit has no voltage bias requirement and is single-edge phase interpolation. There is no need to consider the strength mismatch between PMOS and NMOS in the phase interpolation unit, thus reducing the phase nonlinearity caused by current mismatch. An NMOS switch is added to the reset circuit to reduce the influence of the inverter threshold voltage change on the linearity of the phase interpolator, and enhance the circuit's ability to resist environmental interference; A self-resetting feedback tube is added to the reset circuit to construct a negative feedback loop, which reduces the discharge time of the phase interpolator output node and reduces power consumption. At the same time, it weakens the instability of the slope of the phase interpolator output waveform, improves the circuit robustness, and enhances the circuit's ability to resist environmental interference.

[0037] This embodiment provides a current integral mode phase interpolator, and the specific working principle is as follows: The multi-mode frequency divider divides the input clock signal; the pulse generation module generates a pulse signal for phase interpolation and a reset signal for resetting according to the received divided clock signal; the phase interpolator array generates an output signal according to the received pulse signal; the reset module resets the phase interpolator according to the received reset signal and the output signal; wherein, the anti-interference unit is used to isolate the clock interference, and the self-reset feedback unit is used to increase the charge reset rate. In this embodiment, by adding a fifth NMOS tube M8 in the reset module, the clock interference is isolated, and by adding a feedback tube M6 in the reset module, the charge reset rate is increased. This current integration mode phase interpolator has good linearity compared to the traditional phase interpolator.

[0038] The working principle of this embodiment is further described with reference to the accompanying drawings: like Figure 1 As shown, the multi-mode divider generates a divided clock signal; the pulse generating module generates two clock signals CK0 and CK1 with a phase difference of 2π, ie, pulse signals, according to the divided clock signal; and there are also two reset signals vslop_set1 and vslop_set2.

[0039] The phase interpolator array generates an interpolated clock signal based on two pulse signals with a phase difference of 2π. The interpolated clock phase offset is related to the number of current paths on CK0 and CK1. The total number of current paths on CK0 and CK1 remains unchanged. The working principle of the phase interpolator array is as follows: Figure 2As shown, the current drop rate in region I is related to the number of current paths on CK0 and CK1, and the current drop rate in region II is constant.

[0040] Combination Figure 3 and Figure 4 As shown, the reset module includes: a PMOS tube M5, a third PMOS tube M7, a fourth NMOS tube M6, a fifth NMOS tube M8, a capacitor C2, and a seventh inverter INV7; The vslop_set1 signal is the reset signal of the Vx node, and vslop_set2 is the reset signal of the Vy node. After the Vx point signal passes through the NMOS switch tube, the variable slope working area disappears, the constant slope working area range becomes larger, and the inverter threshold voltage Vth range is expanded from V1~V2 to V1~VDD, which improves the circuit's anti-PVT characteristics and does not require threshold voltage calibration; when the Vo node signal jumps from 0 to 1, the self-reset feedback tube, that is, the fourth NMOS tube M6 starts to work, charges the Vx node, offsets the discharge current of the phase interpolator array, and prevents the Vx node voltage from continuing to drop, reducing the phase interpolator output node discharge time and reducing power consumption; the Vx node signal has the largest slope fluctuation at the extreme value of the swing, and now the negative feedback loop allows the Vx node signal to avoid the swing of 0, thereby improving the robustness of the circuit and enhancing the circuit's anti-PVT capability.

[0041] like Figure 5 As shown, specifically Figure 5 (a) and Figure 5 As shown in (b), the differential nonlinearity (DNL) of the current integrating mode phase interpolator varies in the range of -0.045~0.033LSB, the peak-to-peak value of DNL is 0.078LSB, and the integral nonlinearity (INL) varies in the range of -0.1~0.45LSB, and the peak-to-peak value of INL is 0.55LSB, which is sufficient to prove that the current integrating mode phase interpolator provided in this embodiment has excellent phase linearity.

[0042] In summary, the present invention provides a current integral mode phase interpolator and method, which adopts technologies such as adding an NMOS switch and a self-resetting feedback tube to a reset module, and can ultimately achieve excellent accuracy and excellent linearity performance under different processes; compared with the existing phase interpolator, it has the following advantages: First, functional integration and high efficiency: This current integrating mode phase interpolator integrates a multi-mode divider, a pulse generation module, a phase interpolator array and a reset module to form a complete and efficient phase adjustment system; this integrated design not only simplifies the circuit structure, but also improves the accuracy and efficiency of phase interpolation.

[0043] Second, strong anti-interference ability: The reset module contains an anti-interference unit for isolating clock interference, which can effectively reduce the interference of external clock signals on the phase interpolation process and ensure the stability and accuracy of phase interpolation.

[0044] Third, the charge reset rate is improved: the self-reset feedback unit in the reset module can offset the discharge current of the phase interpolator array through node charging, thereby significantly improving the charge reset rate. This helps to speed up the phase adjustment process and improve overall performance.

[0045] Fourth, flexibility and scalability: The multi-mode divider can process clock signals of different frequencies, so that the phase interpolator can adapt to a variety of application scenarios; at the same time, the phase interpolator array is composed of multiple parallel phase interpolator core modules, which provides good scalability and facilitates the adjustment of the accuracy and range of phase interpolation according to actual needs.

[0046] Fifth, optimization of working method: The present invention also provides an efficient working method, in which the clock signal is divided by a multi-mode frequency divider, the pulse generation module generates the pulse signal and reset signal required for phase interpolation, the phase interpolator array generates an output signal according to the pulse signal, and finally the reset module performs a reset operation. This method not only has a clear process, but also can make full use of the functions of each module to achieve efficient phase interpolation.

[0047] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the relevant field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A current integral mode phase interpolator, characterized in that: include: Multi-mode frequency divider, pulse generation module, phase interpolator array and reset module; The multi-mode frequency divider is used to divide the frequency of the input clock signal; The pulse generating module is used to receive the clock signal divided by the multi-mode frequency divider, and generate a pulse signal for phase interpolation and a reset signal for resetting according to the divided clock signal; The phase interpolator array is used to receive the pulse signal of the pulse generating module and generate an output signal according to the pulse signal; The reset module is used to receive the reset signal of the pulse generation module and the output signal of the phase interpolator array, and to reset the phase interpolator according to the reset signal and the output signal; The reset module includes an anti-interference unit for isolating clock interference and a self-reset feedback unit for increasing the charge reset rate.

2. The current integral mode phase interpolator according to claim 1, characterized in that: The output end of the multi-mode frequency divider is connected to the first input end of the pulse generating module; the input end of the multi-mode frequency divider is connected in parallel to the second input end of the pulse generating module; the first output end of the pulse generating module is connected to the first input end of the reset module; the second output end of the pulse generating module is connected to the second input end of the reset module; the third output end of the pulse generating module is connected to the first input end of the phase interpolator array; the fourth output end of the pulse generating module is connected to the second input end of the phase interpolator array; the output end of the phase interpolator array is connected to the third input end of the reset module.

3. The current integral mode phase interpolator according to claim 2, characterized in that: The pulse generating module includes a first trigger DFF1, a second trigger DFF2, a third trigger DFF3, a fourth trigger DFF4, a fifth trigger DFF5, and a sixth trigger DFF6; The input end of the multi-mode divider, the clock input end of the first trigger DFF1, the clock input end of the second trigger DFF2, the clock input end of the third trigger DFF3, the clock input end of the fourth trigger DFF4, the clock input end of the fifth trigger DFF5 and the clock input end of the sixth trigger DFF6 are connected in parallel.

4. The current integral mode phase interpolator according to claim 3, characterized in that: The pulse generating module further includes: a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a first capacitor array C0 and a second capacitor array C1; The output end of the multi-mode frequency divider is connected to the data input end of the first flip-flop DFF1 and the data input end of the third flip-flop DFF3 respectively; The output terminal of the first flip-flop DFF1 is connected to the data input terminal of the second flip-flop DFF2 and the input terminal of the first inverter INV1 respectively; The output end of the second flip-flop DFF2 is connected to the input end of the second inverter INV2; The output terminal of the third flip-flop DFF3 is connected to the data input terminal of the fourth flip-flop DFF4 and the data input terminal of the fifth flip-flop DFF5 respectively; The output terminal of the fourth flip-flop DFF4 is connected to the data input terminal of the sixth flip-flop DFF6; The output end of the fifth trigger DFF5 is connected to the upper plate of the first capacitor array C0 and the input end of the third inverter INV3 respectively; The output end of the sixth flip-flop DFF6 is connected to the upper plate of the second capacitor array C1 and the input end of the fourth inverter INV4 respectively; The output end of the first inverter INV1 is connected to the first input end of the reset module; The output end of the second inverter INV2 is connected to the second input end of the reset module; The output end of the third inverter INV3 is connected to the first input end of the phase interpolator array; An output terminal of the fourth inverter INV4 is connected to a second input terminal of the phase interpolator array.

5. The current integral mode phase interpolator according to claim 4, characterized in that: The pulse generating module further includes: a lower plate of the first capacitor array C0 is connected to GND; and a lower plate of the second capacitor array C1 is connected to GND.

6. The current integral mode phase interpolator according to claim 2, characterized in that: The phase interpolator array includes a plurality of phase interpolator core modules connected in parallel; The phase interpolator core module includes a first NMOS tube M1, a second NMOS tube M2, a third NMOS tube M4, a first PMOS tube M3, a two-select-one switch SEL, a fifth inverter INV5 and a sixth inverter INV6; The gate terminal of the first NMOS transistor M1 is connected to the input terminal EN, the source terminal of the first NMOS transistor M1 is connected to the input terminal Vbn, and the drain terminal of the first NMOS transistor M1 is connected to the gate terminal of the second NMOS transistor M2; The source end of the second NMOS tube M2 is connected to the drain end of the first PMOS tube M3 and the drain end of the third NMOS tube M4 respectively, and the drain end of the second NMOS tube M2 is connected to the third input end of the reset module; The source end of the first PMOS transistor M3 is connected to VDD, and the gate end of the first PMOS transistor M3 is connected to the gate end of the third NMOS transistor M4 and the output end of the two-select-one switch SEL respectively; The source end of the third NMOS tube M4 is connected to GND; The input end of the two-select-one switch SEL can be selectively connected to the output end of the fifth inverter INV5 or the output end of the sixth inverter INV6 respectively; An input end of the fifth inverter INV5 is connected to an output end of the third inverter INV3 ; an input end of the sixth inverter INV6 is connected to an output end of the fourth inverter INV4 .

7. The current integral mode phase interpolator according to claim 1, characterized in that: The reset module includes a second PMOS tube M5, a third PMOS tube M7, a fourth NMOS tube M6, a fifth NMOS tube M8, a capacitor C2 and a seventh inverter INV7; wherein the anti-interference unit is the fifth NMOS tube M8; the self-reset feedback unit is the fourth NMOS tube M6; The gate end of the second PMOS tube M5 is connected to the first output end of the pulse generating module, the source end of the second PMOS tube M5 is connected to VDD, and the drain end of the second PMOS tube M5 is connected to the output end of the phase interpolator array; The upper plate of the capacitor C2 is connected to VDD, and the lower plate of the capacitor C2 is connected to the output end of the phase interpolator array; The gate end of the fourth NMOS tube M6 is connected to the output end of the seventh inverter INV7, the drain end of the fourth NMOS tube M6 is connected to VDD, and the source end of the fourth NMOS tube M6 is connected to the output end of the phase interpolator array; The gate end of the third PMOS tube M7 is connected to the second output end of the pulse generating module, the source end of the third PMOS tube M7 is connected to VDD, and the drain end of the third PMOS tube M7 is respectively connected to the source end of the fifth NMOS tube M8 and the input end of the seventh inverter INV7; The gate terminal of the fifth NMOS tube M8 is connected to the VBN port, and the drain terminal of the fifth NMOS tube M8 is connected to the output terminal of the phase interpolator array.

8. A working method of a current integral mode phase interpolator, based on the current integral mode phase interpolator according to any one of claims 1 to 7, characterized in that: include: The multi-mode frequency divider divides the input clock signal; The pulse generating module generates a pulse signal for phase interpolation and a reset signal for resetting according to the received divided clock signal; The phase interpolator array generates an output signal based on the received pulse signal; The reset module resets the phase interpolator according to the received reset signal and the output signal; Among them, the anti-interference unit is used to isolate the clock interference, and the charge reset rate is increased through the self-reset feedback unit.

9. The working method of the current integral mode phase interpolator according to claim 8, characterized in that: The pulse generating module generates two clock signals with a phase difference of 2π and two reset signals according to the received divided clock signal.

10. The working method of the current integral mode phase interpolator according to claim 8, characterized in that: The self-resetting feedback unit starts working according to the working signal, and adopts the node charging method to offset the discharge current of the phase interpolator array, so as to improve the charge reset rate.

Images