Device for electrostatic discharge protection

Abstract

The invention relates to an apparatus for electrostatic discharge protection. An apparatus is provided that includes a first power rail, a second power rail, and input / output terminals. The electrostatic discharge protection device is coupled between the input / output terminal and at least one of the first supply rail and the second supply rail. A trigger circuit is coupled to the first supply rail and the second supply rail, and is configured to detect an electrostatic discharge event at the input / output terminal based on at least one of a voltage at the first supply rail and a voltage at the second supply rail. In response to detecting the electrostatic discharge event, the electrostatic discharge protection device is turned on.

Description

Technical Field

[0001] The present application relates to an apparatus for electrostatic discharge protection. Background Art

[0002] Semiconductor integrated circuits are often sensitive to electrostatic discharge (ESD) events in which high charges are applied to the terminals of the integrated circuit. Such charges may be applied, for example, when a human touches the terminals of the circuit and may result in voltages on the order of several hundred volts and above, which are much higher than the voltages for which the circuit was designed and may therefore damage the circuit.

[0003] Therefore, ESD protection circuits are used to protect the terminals of semiconductor devices. A common method of protecting input / output (IO) terminals is to couple the IO terminals to a power rail providing a supply voltage via ESD protection diodes, which are designed so that they do not conduct during normal operation, e.g., the voltage occurring during normal operation of the circuit does not exceed the forward voltage of the diode. In the event of an ESD event, at least one of the diodes becomes conductive, thereby deflecting the charge and preventing a high voltage drop on the core circuit of the device (i.e., the circuit that performs the actual function of the device).

[0004] However, the residual charge or voltage drop may still have the potential to damage the device, especially as semiconductor structures become smaller and supply voltages decrease, which makes the device more sensitive to overvoltage. Summary of the invention

[0005] According to an embodiment, there is provided an apparatus comprising:

[0006] - First supply rail,

[0007] - Second supply rail,

[0008] - Input / output terminals, and

[0009] - An electrostatic discharge protection device comprising at least two stacked transistors coupled between an input / output terminal and one of a first power supply rail and a second power supply rail.

[0010] The device also includes a trigger circuit coupled to the first power rail and the second power rail. The trigger circuit is configured to detect an electrostatic discharge event at the input / output terminal based on at least one of a voltage at the first power rail and a voltage at the second power rail, and turn on the electrostatic discharge protection device in response to detecting the electrostatic discharge event.

[0011] According to another embodiment, there is provided an apparatus comprising:

[0012] - First supply rail,

[0013] - Second supply rail,

[0014] - Input / output terminals, and

[0015] - an electrostatic discharge protection switch coupled between the input / output terminal and one of the first power supply rail and the second power supply rail.

[0016] The device also includes a detection circuit coupled to the first power rail and the second power rail and configured to detect an electrostatic discharge event at the input / output terminal based on at least one of a voltage at the first power rail and a voltage at the second power rail, and generate a detection signal in response to detecting the electrostatic discharge event. The device also includes an amplifier circuit configured to amplify the detection signal to generate a control signal for the electrostatic discharge protection switch.

[0017] The above summary merely gives a brief overview of some embodiments and is not to be construed as limiting, as other embodiments may include other features in addition to those listed above. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a diagram showing a device according to an embodiment.

[0019] Figure 2 is a diagram showing a device according to an embodiment.

[0020] Figure 3 is a circuit diagram showing a device according to an embodiment.

[0021] FIG. 4A to FIG. 4E is a diagram showing a bias circuit that can be used in various embodiments.

[0022] Figure 5 is a circuit diagram showing a device according to an embodiment.

[0023] Figure 6 is a circuit diagram showing a device according to another embodiment. DETAILED DESCRIPTION

[0024] Hereinafter, various embodiments will be described in detail with reference to the accompanying drawings. These embodiments are given by way of example only and should not be construed as limiting in any way.

[0025] In some of the embodiments described below, transistors are used. Although specific types of transistors, such as metal oxide semiconductor field effect transistors (MOSFETs), may be shown in the drawings, in other embodiments, other types of transistors, such as bipolar junction transistors (BJTs) or insulated gate bipolar transistors (IGBTs), may be used. In some embodiments, stacked transistors may be used. A stacked transistor refers to one or more transistors whose load paths are coupled in series. In the case of a field effect transistor, the term "load path" refers to the path between the source and the drain, and in the case of a BJT or an IGBT, the term "load path" refers to the path between the collector and the emitter.

[0026] Unless otherwise specified, any connection or coupling described herein shown in the drawings refers to an electrical connection or coupling. Such a connection or coupling may be modified, for example, by adding elements or removing elements, as long as the function of the connection or coupling is maintained, such as providing voltage or current, transmitting signals, providing control, etc. In this sense, the coupling should be regarded as a functional coupling, that is, the elements are electrically coupled to provide the functions described herein.

[0027] Features from different embodiments may be combined to form other embodiments. Variations and modifications described with respect to one of the embodiments may also be applied to the other embodiments, and therefore will not be described repeatedly.

[0028] The same reference numerals are used throughout the drawings to designate corresponding or equivalent elements.

[0029] Embodiments described herein relate to devices including secondary electrostatic discharge (ESD) protection. Such secondary ESD protection can be combined with any primary ESD protection. In some embodiments, the primary ESD protection is shown as including two diodes, but any other primary ESD protection, such as using a transistor or other ESD protection element coupled as a diode, can also be used.

[0030] Figure 1 A block diagram of an apparatus according to an embodiment is shown.

[0031] Figure 1 An embodiment includes providing a first supply voltage V DD The first supply rail 10 and the second supply voltage V SS The second supply rail 11. Although V DD and V SS is shown as an example for supply voltage, but in other embodiments, other supply voltages may be provided, such as V in bipolar logic CC and V EE Or a positive voltage and ground.

[0032] In addition, an input / output (IO) terminal 12 is provided. Although a single IO terminal 12 is shown, the device may include multiple IO terminals that can be protected from ESD events as described herein. In other embodiments, one or more of the multiple IO terminals may be protected as described herein, and other IO terminals may be provided without protection or with different ESD protection.

[0033] Supply rails 10 and 11 provide power to any core circuits of the device. Figure 1 The core circuit is a circuit that performs the intended function of the device (such as a logic function, a control function, a computing function, etc.). Since the present application relates to electrostatic discharge protection, the core circuit will not be further specified, and the embodiments described herein can be used to protect any core circuit from electrostatic discharge events. The IO terminal 12 can be used to provide input signals to the core circuit, to provide output signals from the core circuit to the outside world, or to provide both. In this regard, the term "IO terminal" also includes the case where the terminal is only used for input signals (pure input terminal) and only for output signals (pure output terminal).

[0034] The power rails 10, 11 are protected by power supply protection 16, which can be implemented in any conventional manner, such as reducing the high voltage between the power rails 10 and 11 caused by an electrostatic discharge event. Since the present application focuses on the protection of IO terminals such as IO terminal 12, the power supply protection will not be described in particular detail, and the power supply protection may or may not be provided.

[0035] The primary ESD protection level for the IO terminal 12 is provided by two diodes 13A, 13B. As shown, the diode 13A is coupled between the IO terminal 12 and the first power supply rail 10, and as shown, the diode 13B is arranged between the IO terminal 12 and the second power supply rail 11. Depending on the polarity of the electrostatic discharge event at the IO terminal 12 compared with the power supply rails 10, 11, the diode 13A and / or the diode 13B becomes conductive, thereby deviating the ESD voltage. During normal operation (except for ESD events), the diodes 13A, 13B are substantially non-conductive, so that the device can work as expected. Since in some applications, such primary ESD protection may not always be sufficient, in addition to the diodes or similar devices mentioned above used as the primary ESD protection level, a secondary protection level as described below is also used to further minimize the risk of device damage.

[0036] The IO terminal 12 is coupled to the core circuit via a resistor 14 and a secondary ESD protection stage 15. A specific implementation of the secondary ESD protection stage 15 will be described below. In the event of an ESD event, the resistor 14 limits the current flowing to the core circuit. Other or additional current limiting elements, such as capacitors, may also be used.

[0037] As will be further described in more detail below, in the embodiments described herein, the secondary ESD protection stage 15 detects an ESD event at the input / output terminal 12 based on the voltage at the first power rail 10 and / or the second power rail 11. As will be described below, when an ESD event occurs and the diode 13A or 13B becomes conductive, this also changes the voltage at the corresponding power rail 10 or 11, which can be detected by the secondary ESD protection stage 15 to trigger an electrostatic discharge protection device, such as a switch. By providing a detection circuit between the power rails 10, 11, in some embodiments, leakage at the IO terminal 12 can be reduced.

[0038] Figure 2 is a diagram showing an apparatus according to another embodiment. Figure 2 The secondary ESD protection stage 15 comprises an electrostatic discharge protection device 20 comprising a transistor switch 25. The load path of the transistor switch 25 is coupled between the IO terminal 12 (particularly, the node between the resistor 14 and the core circuit) and the power supply rail 11. Alternatively or additionally, a transistor switch coupling the IO terminal 12 (particularly, the node between the resistor 14 and the core circuit) to the first power supply rail 10 may be provided.

[0039] also, Figure 2 The secondary ESD protection stage includes a detection circuit 22, which is composed of Figure 2 The block 24 in the circuit diagram indicates that it detects an ESD event based on the voltage at the first power rail 10 and the second power rail 11. As explained above, when an ESD event at the IO terminal 12 occurs and deviates to at least one of the power rails 10 and 11 via the diodes 13A, 13B, the voltage at the first power rail 10 and / or the second power rail 11 changes, which can be detected by the block 24. Possible circuit implementations of the block 24 will be further described below. Possible implementations of the block 24 include a voltage divider circuit or an RC (resistor-capacitor) filter circuit.

[0040] Block 24 generates a detection signal which is provided to amplifier circuit 21. Figure 22 is represented by amplifier 23. Amplifier circuit 21 provides a control signal to ESD protection device 20 based on the detection signal. In an example including transistor switch 25, the control signal is provided to the gate terminal of the transistor. Detection circuit 22 and amplifier circuit 21 are also collectively referred to herein as a trigger circuit.

[0041] Figure 3 is a circuit diagram of a device according to an embodiment, which includes an implementation example of an ESD protection device 20 , an amplifier circuit 21 , and a detection circuit 22 . Figure 3 The detection circuit 22 in the example of includes a voltage divider circuit including a chain of diode-coupled transistors 30 and a resistor 31 coupled in series between the first power supply rail 10 and the second power supply rail 11. The detection circuit 22 generates a detection signal at a node 32. The number and forward voltage of the diode-coupled transistors 30 and the resistance value of the resistor 31 are selected so that during normal operation, substantially no leakage current occurs via the detection circuit 22, and the voltage at the node 32 is such that the ESD protection circuit 20 is not triggered. When the voltage at the first power supply rail 10 and / or the second power supply rail 11 changes due to an ESD event at the IO terminal 12 deviated via the diode 13A and / or the diode 13B, the voltage at the node 32 reflects this change, which ultimately triggers the ESD protection device 20. Instead of the diode-coupled transistor 30, other types of diodes such as a pn diode or a pin diode may be used.

[0042] Figure 3 The amplifier circuit 21 in the embodiment includes three converter stages 34A to 34C. The number of three converter stages is only an example, and more or fewer converter stages can also be provided. The first converter stage 34A will be described in more detail below. The second converter stage 34B and the third converter stage 34C are basically similar to the first converter stage 34A, with the only difference being that the resistor 33 is arranged in the first converter stage 34A and is omitted in the second converter 34B and the third converter stage 34C.

[0043] Converter stage 34A includes an input node 37 coupled to node 32 as shown and an output node 38 coupled to a corresponding input node of converter stage 34B.

[0044] Converter stage 34A also includes a pair of stacked PMOS transistors 35A, 35B and a pair of stacked NMOS transistors 36A, 36B. Using stacked transistors can provide a higher voltage tolerance than using a single transistor. In this way, amplifier circuit 21 can be implemented with relatively low voltage technology and can still handle the required voltage.

[0045] As shown, the PMOS transistor 35A and the NMOS transistor 36B are coupled to the input node 37. The load paths of the PMOS transistors 35A, 35B are coupled between the output node 38 and the first end of the resistor 33, and the second end of the resistor 33 is coupled to the first power supply rail 10. The resistor 33 can have a resistance value in the kilo-ohm range, and can be omitted in other embodiments. The load paths of the NMOS transistors 36A, 36B are coupled between the output node 38 and the second power supply rail 11. The gate terminal of the PMOS transistor 35B is biased by the voltage Bias 1, and the gate of the NMOS transistor 36A is biased by the voltage Bias 2. FIG. 4A to FIG. 4E The generation of the bias voltages Bias 1 and Bias 2 is further described. Generally, the bias voltages are selected so that in normal operation, the transistors are turned off to prevent leakage current, and when the transistor 35A or the transistor 36B is turned on by the detection signal output by the detection circuit 22, by the corresponding source voltages respectively provided to the transistors 35B or 36A in this way, when the transistor 35A is turned on, the transistor 35B is also turned on, or when the transistor 36B is turned on, the transistor 36A is also turned on.

[0046] Except for omitting resistor 33 as mentioned above, second converter stage 34B and third converter stage 34C are configured as first converter stage 34A with stacked transistors, where one transistor in each pair (PMOS or NMOS) is coupled to a corresponding input node and the other transistor is coupled to a corresponding bias voltage Bias 1 or Bias 2. As shown, the input node of second stage 34B is coupled to output node 38, and the input node of third stage 34C is coupled to the output node of second stage 34B, such that the first, second and third stages are coupled in series.

[0047] Thus, although only one transistor in each stacked pair is coupled to the respective input node 37, the stages operate as conventional converters.

[0048] The ESD protection device 20 includes a pair of PMOS transistors 39A, 39B and a pair of stacked NMOS transistors 310A, 310B. Similar to the converter stages 34A to 34C, the PMOS transistor 39B is biased by Bias 1 and the NMOS transistor 310A is biased by Bias 2. The gate terminal of the PMOS transistor 39A is coupled to the output node of the converter stage 34C, and the gate terminal of the NMOS transistor 310B is coupled to the output node of the converter stage 34B, so that the signal applied to the gate terminal of the PMOS transistor 39A is opposite to the signal applied to the gate terminal of the NMOS transistor 310B (one converter stage apart). Therefore, in the case of an ESD event, the transistors 39A and 310B are turned on, which then also turn on the transistors 39B, 310A through the bias (the gate-source voltage subsequently established), so that the charge is further deviated from the IO terminal 12 to the first power supply rail 10 and the second power supply rail 11.

[0049] As shown, the PMOS transistors of the converter stages 34A to 34C and the PMOS transistors of the electrostatic discharge protection device 20 are biased by VDD at their body terminals, and the NMOS transistors are biased by VSS at their body terminals. Note that "VDD" or "VSS" is the voltage modified by the ESD pulse in the case of an ESD event, or is the voltage provided by the ESD pulse alone in the case of the device being off (no power), which then powers the ESD protection circuit.

[0050] Now refer to FIG. 4A to FIG. 4E Discussion Generation Figure 3 Various possibilities for the bias voltages Bias 1 and Bias 2.

[0051] As shown, Figure 4A is a first example, where voltages Bias 1 and Bias 2 are generated by a resistor divider comprising resistors 40A, 40B between the first supply rail 10 and the second supply rail 11. The resistors 40A and 40B may be high ohmic (eg, over 100 kΩ) to reduce leakage currents.

[0052] In this case, the voltages Bias 1 and Bias 2 are equal and approximately halfway between VDD and VSS. If VSS is considered to be zero level, the voltages Bias 1 and Bias 2 are approximately VDD / 2. It should be noted that this does not need to be exact, so that resistors 40A and 40B do not need to be exactly equal. For example, a variation of + / -10% around VDD / 2 may be acceptable.

[0053] Figure 4B Another possibility for biasing is shown, where instead of Figure 4A, a capacitive voltage divider using capacitors 41A, 41B is shown. The use of capacitors can reduce leakage current between VDD and VSS. In an embodiment, the capacitance values ​​of capacitors 41A, 41B are equal (again with some allowable tolerance), so that Bias 1 and Bias 2 are also equal and in the middle between VDD and VSS, that is, about VDD / 2 (e.g., with a tolerance of + / - 10%) when VSS is used as the zero point of the voltage scale.

[0054] exist Figure 4C In FIG. 4 , the voltage divider is formed by two diode chains 42A, 42B. The number of diodes can be selected based on the voltage VDD relative to VSS and leakage requirements, with more diodes causing reduced leakage. Here too, the two diode chains 42A, 42B can be substantially equal, so that Bias 1 and Bias 2 are also approximately VDD / 2, allowing for corresponding variations of, for example, approximately + / -10%.

[0055] exist Figures 4A to 4C In the above implementation, Bias 1 and Bias 2 are equal. In this case, Figure 3 , a single line for bias can be used, i.e., separate lines for Bias 1 and Bias 2 are not required. Now, refer to Figure 4D and Figure 4E , different implementations of Bias 1 and Bias 2 will be shown.

[0056] exist Figure 4D , Bias 1 is generated by a first diode chain-based voltage divider including diode chains 43A, 43B between the first power supply rail 10 and the IO terminal 12, and Bias 2 is generated by a second diode chain-based voltage divider including diode chains 43C, 43D between the IO terminal 12 and the second power supply rail 11. The diode chains 43A, 43B may be substantially equal, and the diode chains 43C, 43D may be substantially equal. In some embodiments, all four diode chains 43A to 43D may be substantially equal. Instead of a diode chain-based voltage divider, a diode chain such as Figure 4A The resistor divider in Figure 4B The capacitive voltage divider in Figure 4C As noted, the number of diodes in each diode chain may depend on the voltages involved and leakage requirements.

[0057] exist Figure 4DIn an embodiment of the present invention, Bias 1 is equal to (VDD-VIO) / 2, and Bias 2 is equal to (VIO-VSS) / 2, where VIO is the voltage at the IO terminal 12. Here again, for example, a variation of + / - 10% is acceptable.

[0058] Figure 4E Shows Figure 4D A variation of the embodiment of Figure 4E In addition to Figure 4D In addition to the components discussed, a first capacitor 44A is coupled between the first power rail 10 and a node providing Bias 2 between the diode chain 43C, 43D, and a second capacitor 44B is provided between the second power rail 11 and a node providing Bias 1 between the diode chain 43A, 43B. The capacitors 44A, 44B can enhance the ESD behavior of the secondary stage because the capacitors can help to build up the bias voltage faster for turning on the electrostatic discharge protection device 20. Otherwise, regarding Figure 4D The description also applies to Figure 4E , including the resulting bias voltages Bias1, Bias 2 and changes such as using a resistor divider or a capacitive divider instead of a diode chain based voltage divider.

[0059] Figure 5 A device according to another embodiment is shown. Figure 5 The implementation method is Figure 3 A variation of the embodiment of Figure 3 In the embodiment, stacked transistors are used for the converter stage and for the electrostatic discharge protection device 20, while in Figure 5 In FIG. 1 , a single transistor is used for the converter stages 54A, 54B, and 54C of the amplifier circuit 21 and for the electrostatic discharge protection device 20. Specifically, each converter stage 54A, 54B, and 54C includes a PMOS transistor 55 and an NMOS transistor 56, the gate terminals of the PMOS transistor 55 and the NMOS transistor 56 are coupled to the input node 57 of the corresponding converter, and the output node 58 of the corresponding converter is between the transistors 55 and 56. Figure 3 The resistor 33 illustrated is again provided only in converter stage 54A and not in converter stages 54B and 54C.

[0060] The ESD protection device 20 includes a PMOS transistor 59 (similar to the PMOS transistor 59) having a gate coupled to the output terminal of the converter stage 54C. Figure 3 PMOS transistor 39A) and an NMOS transistor 510 (similar to Figure 3 NMOS transistor 310B). In addition to not using stacked transistors, Figure 5 The operation and Figure 3 The operation described corresponds to the Figure 5 The device can be used in technologies where a single transistor (rather than stacked transistors) can withstand the voltages involved.

[0061] Figure 6 A device according to another embodiment is shown. As will be described below, Figure 6 The implementation of the device with respect to the detection circuit 22, the amplifier circuit 21 and the ESD protection device 20 is different from the previous embodiment.

[0062] In addition, Figure 6 , the core circuit is represented by a simple input stage 63.

[0063] Compared with previous implementations, Figure 6 The detection circuit 22 in the device is not based on a voltage divider circuit, but includes an RC filter, which includes a resistor 60A coupled between the first power supply rail 10 and the IO terminal 12 (via the resistor 14), and a capacitor 60B coupled between the IO terminal 12 and the second power supply rail 11 (via the resistor 14). The resistance value of the resistor 60A and the capacitance value of the capacitor 60B are selected so that when the voltage rise at the IO terminal 12 has a time constant corresponding to the typical time constant of the voltage rise of the ESD event, a detection signal is generated that eventually activates the ESD protection device 20. The use of an RC circuit to detect an ESD event is known per se to a person skilled in the art, however, in Figure 6 In this case, the ESD event at the IO terminal 12 is detected by the RC circuit coupled between the first supply rail 10 and the second supply rail 11, thereby detecting the change in the supply voltage caused by the ESD event via the diode 13A and / or the diode 13B.

[0064] It should be noted that in the previous embodiment, instead of a voltage divider based detection circuit, an RC based detection circuit 22 may also be used.

[0065] exist Figure 6 The detection signal in the case of is generated at a node between the resistor 60A and the capacitor 60B. Figure 6 The amplifier circuit 21 in the embodiment of the embodiment comprises a single stage having a first converter 61A and a second converter 61B, each converter comprising a PMOS transistor and an NMOS transistor. In other embodiments, the amplifier circuit 21 may be used as shown in FIG. Figure 5 Multiple converter stages in and / or as Figure 3 In contrast, in other embodiments, Figure 6 The amplifier circuit 21 can also be used Figure 3 or Figure 5 implementation method.

[0066] exist Figure 6 In, similar to Figure 5 The ESD protection device 20 includes an NMOS transistor 62A and an NMOS transistor 62B. The gate terminal of the NMOS transistor 62A is coupled to the output terminal of the converter 61A, and the gate terminal of the NMOS transistor 62B is coupled to the output terminal of the converter 61B. Figure 6 In the case of an ESD event, both transistors 62A or 62B are turned on. Figure 6 In, as reference Figure 3 As explained, in the ESD protection device 20, stacked transistors may be used instead of a single transistor.

[0067] Some embodiments are defined by the following examples:

[0068] Example 1. An apparatus comprising:

[0069] - First supply rail,

[0070] - Second supply rail,

[0071] - Input / output terminals,

[0072] - an electrostatic discharge protection device comprising at least two stacked transistors coupled between an input / output terminal and one of a first power supply rail and a second power supply rail,

[0073] - a trigger circuit coupled to the first power supply rail and the second power supply rail and configured to detect an electrostatic discharge event at the input / output terminal based on at least one of a voltage at the first power supply rail and a voltage at the second power supply rail, and to turn on the electrostatic discharge protection device in response to detecting the electrostatic discharge event.

[0074] Example 2. The device according to Example 1,

[0075] wherein the at least two stacked transistors include a first transistor and a second transistor controlled by a trigger circuit, and wherein the apparatus further includes a bias circuit configured to bias a control terminal of the second transistor to a predefined voltage value.

[0076] Example 3. The apparatus of Example 2, wherein the predefined voltage value is between 40% and 60% of an average of a first voltage at the first supply rail and a second voltage at the second supply rail.

[0077] Example 4. The device of any of Examples 1 to 3, wherein the electrostatic discharge protection device comprises at least two further stacked transistors coupled between the input / output terminal and the other of the first power supply rail and the second power supply rail.

[0078] Example 5. The apparatus according to Example 4 and Example 2,

[0079] wherein the at least two further stacked transistors include a first further transistor and a second further transistor controlled by the trigger circuit, and wherein the bias circuit is further configured to bias a control terminal of the second further transistor to a further predefined voltage value.

[0080] Example 6. An apparatus according to Example 5, wherein the further predefined voltage value is equal to the predefined voltage value.

[0081] Example 7. An apparatus according to Example 5, wherein at least two stacked transistors are coupled between an input / output terminal and a first power supply rail, wherein at least two other stacked transistors are coupled between the input / output terminal and a second power supply rail, wherein the predefined voltage value is between 40% and 60% of an average value of a first voltage at the first power supply rail and a third voltage at the input / output terminal, and wherein the other predefined voltage value is between 40% and 60% of an average value of a second voltage at the second power supply rail and the third voltage at the input / output terminal.

[0082] Example 8. The apparatus of any one of Examples 1 to 7, further comprising a first electrostatic discharge protection element coupled between a first node coupled to the input / output terminal and the first power rail, and a second electrostatic discharge protection element coupled between the first node and the second power rail,

[0083] wherein the electrostatic discharge protection device is coupled between a second node coupled to the input / output terminal and one of the first power supply rail and the second power supply rail,

[0084] The first node is between the input / output terminal and the second node.

[0085] Example 9. The apparatus of Example 8 further comprising a current limiting element coupled between the first node and the second node.

[0086] Example 10. An apparatus according to any of Examples 1 to 9, wherein the trigger circuit includes a detection circuit configured to generate a detection signal indicative of an electrostatic discharge event.

[0087] Example 11. The apparatus of Example 10, wherein the detection circuit comprises a voltage divider circuit coupled between the first power supply rail and the second power supply rail, wherein an output of the voltage divider circuit is configured to provide the detection signal.

[0088] Example 12. The apparatus of Example 11, wherein the voltage divider circuit comprises at least one diode in series with a resistor, wherein an output of the voltage divider circuit is at a node between the at least one transistor and the resistor.

[0089] Example 13. The apparatus of Example 10, wherein the detection circuit comprises an RC filter circuit coupled between the first power supply rail and the second power supply rail, wherein an output of the RC filter circuit is configured to provide the detection signal.

[0090] Example 14. The device of any one of Examples 10 to 13 further includes an amplifier circuit configured to amplify the detection signal to generate a control signal for an electrostatic discharge protection device.

[0091] Example 15. The apparatus of Example 14, wherein the amplifier circuit comprises one or more converter stages.

[0092] Example 16. An apparatus according to Example 15, wherein each converter stage includes a first pair of stacked transistors coupled between a first power supply rail and an output node of the corresponding converter stage, and a second pair of stacked transistors coupled between the output node of the corresponding converter stage and a second power supply rail.

[0093] Example 17. The apparatus according to example 16 and example 5,

[0094] wherein at least two stacked transistors are coupled between an input / output terminal and a first power supply rail, wherein at least two further stacked transistors are coupled between an input / output terminal and a second power supply rail,

[0095] wherein a first transistor of the first pair of stacked transistors and a first transistor of the second pair of stacked transistors are coupled to an input node of a corresponding converter stage,

[0096] Wherein the bias circuit is configured to bias a control terminal of a second transistor in a first pair of stacked transistors to a predefined voltage value, and to bias a control terminal of a second transistor in a second pair of stacked transistors to another predefined voltage value.

[0097] Example 18. An apparatus comprising:

[0098] - First supply rail,

[0099] - Second supply rail,

[0100] - Input / output terminals,

[0101] - an electrostatic discharge protection switch coupled between the input / output terminal and one of the first power supply rail and the second power supply rail,

[0102] a detection circuit coupled to the first supply rail and the second supply rail and configured to detect an electrostatic discharge event at the input / output terminal based on at least one of a voltage at the first supply rail and a voltage at the second supply rail, and to generate a detection signal in response to detecting the electrostatic discharge event, and

[0103] - an amplifier circuit configured to amplify the detection signal to generate a control signal for the electrostatic discharge protection switch.

[0104] Example 19. An apparatus according to Example 18, wherein the amplifier circuit includes one or more converter stages, wherein each converter stage includes a first pair of stacked transistors coupled between a first power supply rail and an output node of the corresponding converter stage, and a second pair of stacked transistors coupled between the output node of the corresponding converter stage and a second power supply rail.

[0105] Example 20. The apparatus according to Example 19,

[0106] Also includes bias circuit,

[0107] wherein a first transistor of the first pair of stacked transistors and a first transistor of the second pair of stacked transistors are coupled to an input node of a corresponding converter stage,

[0108] The bias circuit is configured to bias a control terminal of a second transistor in a first pair of stacked transistors to a first predefined voltage, and to bias a control terminal of a second transistor in a second pair of stacked transistors to a second predefined voltage.

[0109] Example 21. The apparatus of Example 20, wherein the first predefined voltage value and the second predefined voltage value are each between 40% and 60% of an average of a first voltage at the first power rail and a second voltage at the second power rail.

[0110] Example 22. The apparatus of Example 21, wherein the first predefined voltage value is equal to the second predefined voltage value.

[0111] Example 23. An apparatus according to Example 20, wherein the first predefined voltage value is between 40% and 60% of an average value of a first voltage at the first power supply rail and a third voltage at the input / output terminal, and the second predefined voltage value is between 40% and 60% of an average value of a second voltage at the second power supply rail and the third voltage at the input / output terminal.

[0112] Example 24. The apparatus of any one of Examples 18 to 23, further comprising a first electrostatic discharge protection element coupled between a first node coupled to the input / output terminal and the first power rail, and a second electrostatic discharge protection element coupled between the first node and the second power rail,

[0113] wherein the electrostatic discharge protection switch is coupled between a second node coupled to the input / output terminal and one of the first power supply rail and the second power supply rail,

[0114] The first node is between the input / output terminal and the second node.

[0115] Example 25. The apparatus of Example 24, further comprising a current limiting element coupled between the first node and the second node.

[0116] Example 26. An apparatus according to any of Examples 18 to 25, wherein the detection circuit includes a voltage divider circuit coupled between the first power supply rail and the second power supply rail, wherein an output of the voltage divider circuit is configured to provide a detection signal.

[0117] Example 27. The apparatus of Example 26, wherein the voltage divider circuit comprises at least one diode in series with a resistor, wherein an output of the voltage divider circuit is at a node between the at least one transistor and the resistor.

[0118] Example 28. An apparatus according to any of Examples 18 to 24, wherein the detection circuit includes an RC filter circuit coupled between the first power supply rail and the second power supply rail, wherein an output of the RC filter circuit is configured to provide a detection signal.

[0119] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that various alternative implementations and / or equivalent implementations may replace the specific embodiments shown and described without departing from the scope of the invention. The present application is intended to cover any adaptation or variation of the specific embodiments discussed herein. Therefore, the present invention is intended to be limited only by its claims and their equivalents.

Claims

1. A device for electrostatic discharge protection, comprising: - a first supply rail (10), - a second supply rail (11), - Input / output terminals (12), - an electrostatic discharge protection device (20) comprising at least two stacked transistors (39A, 39B, 310A, 310B) coupled between the input / output terminal (12) and one of the first power supply rail (10) and the second power supply rail (11), - a trigger circuit (21, 22) coupled to the first power supply rail (10) and the second power supply rail (11), and configured to detect an electrostatic discharge event at the input / output terminal (12) based on at least one of a voltage at the first power supply rail (10) and a voltage at the second power supply rail (11), and to switch on the electrostatic discharge protection device (20) in response to detecting the electrostatic discharge event.

2. The device according to claim 1, in, The at least two stacked transistors (39A, 39B, 310A, 310B) include a first transistor (39A, 310B) and a second transistor (39B, 310A) controlled by the trigger circuit (21, 22), and wherein the device for electrostatic discharge protection also includes a bias circuit, which is configured to bias the control terminal of the second transistor (39B, 310A) to a predefined voltage value (Bias 1, Bias 2).

3. The device according to claim 2, wherein: The predefined voltage values ​​(Bias 1, Bias 2) are between 40% and 60% of an average value of a first voltage (VDD) at the first power supply rail (10) and a second voltage (VSS) at the second power supply rail (11).

4. The device according to claim 2 or 3, wherein: The electrostatic discharge protection device (20) includes at least two further stacked transistors (310A, 310B, 39A, 39B) coupled between the input / output terminal (12) and the other of the first power supply rail (10) and the second power supply rail (11).

5. The device according to claim 4, in, The at least two additional stacked transistors (310A, 310B, 39A, 39B) include a first additional transistor (310B, 39A) and a second additional transistor (310A, 39B) controlled by the trigger circuit (21, 22), and wherein the bias circuit is further configured to bias the control terminal of the second additional transistor (310A, 39B) to an additional predefined voltage value (Bias 2, Bias 1).

6. The device according to claim 5, wherein: The further predefined voltage value (Bias2, Bias 1) is equal to the predefined voltage value (Bias 1, Bias 2).

7. The device according to claim 5, wherein: The at least two stacked transistors (39A, 39B) are coupled between the input / output terminal (12) and the first power supply rail (10), wherein the at least two further stacked transistors (310A, 310B) are coupled between the input / output terminal (12) and the second power supply rail (11), wherein the predefined voltage value (Bias1) is between 40% and 60% of an average value of a first voltage (VDD) at the first power supply rail (10) and a third voltage at the input / output terminal (12), and the further predefined voltage value (Bias 2) is between 40% and 60% of an average value of a second voltage (VSS) at the second power supply rail (11) and the third voltage at the input / output terminal (12).

8. The device according to any one of claims 1 to 7, further comprising a first electrostatic discharge protection element (13A) coupled between a first node coupled to the input / output terminal (12) and the first power supply rail (10), and a second electrostatic discharge protection element (13B) coupled between the first node and the second power supply rail (11), in, The electrostatic discharge protection device (20) is coupled between a second node coupled to the input / output terminal (12) and one of the first power supply rail (10) and the second power supply rail (11), The first node is between the input / output terminal (12) and the second node.

9. The apparatus of claim 8, further comprising a current limiting element (14) coupled between the first node and the second node.

10. The device according to any one of claims 5 to 7, wherein: The trigger circuit (21, 22) includes a detection circuit (22) configured to generate a detection signal indicative of the electrostatic discharge event.

11. The device according to claim 10, wherein: The detection circuit (22) comprises a voltage divider circuit coupled between the first power supply rail (10) and the second power supply rail (11), wherein an output terminal (32) of the voltage divider circuit is configured to provide the detection signal.

12. The device according to claim 11, wherein The voltage divider circuit comprises at least one diode (30) connected in series with a resistor (31), wherein an output terminal (32) of the voltage divider circuit is at a node between the at least one diode (30) and the resistor (31).

13. The device according to claim 10, wherein: The detection circuit (22) comprises an RC filter circuit (60A, 60B) coupled between the first power supply rail (10) and the second power supply rail (11), wherein an output of the RC filter circuit (60A, 60B) is configured to provide the detection signal.

14. The device according to any one of claims 10 to 13, further comprising an amplifier circuit (21), the amplifier circuit (21) being configured to amplify the detection signal to generate a control signal for the electrostatic discharge protection device (20).

15. The device according to claim 14, wherein: The amplifier circuit (21) includes one or more converter stages (34A to 34C, 54A to 54C, 61A, 61B).

16. The device according to claim 15, wherein: Each converter stage (34A to 34C) includes a first pair of stacked transistors (35A, 35B) coupled between the first power supply rail (10) and an output node (38) of the corresponding converter stage, and a second pair of stacked transistors (36A, 36B) coupled between the output node (38) of the corresponding converter stage (34A to 34C) and the second power supply rail (11).

17. The device according to claim 16, in, The at least two stacked transistors (39A, 39B) are coupled between the input / output terminal (12) and the first power supply rail (10), wherein the at least two further stacked transistors (310A, 310B) are coupled between the input / output terminal (12) and the second power supply rail (11), wherein a first transistor (35A) of the first pair of stacked transistors (35A, 35B) and a first transistor (36B) of the second pair of stacked transistors (36A, 36B) are coupled to an input node (37) of a corresponding converter stage (34A to 34C), The bias circuit is configured to bias the control terminal of the second transistor (35B) in the first pair of stacked transistors (35A, 35B) to the predefined voltage value (Bias 1), and to bias the control terminal of the second transistor (36A) in the second pair of stacked transistors (36A, 36B) to the other predefined voltage value (Bias 2).

18. A device for electrostatic discharge protection, comprising: - a first supply rail (10), - a second supply rail (11), - Input / output terminals (12), - an electrostatic discharge protection switch (25, 39A, 39B, 310A, 310B, 59, 510, 62A, 62B) coupled between the input / output terminal (12) and one of the first power supply rail (10) and the second power supply rail (11), - a detection circuit (22) coupled to the first power supply rail (10) and the second power supply rail (11) and configured to detect an electrostatic discharge event at the input / output terminal (12) based on at least one of a voltage at the first power supply rail (10) and a voltage at the second power supply rail (11), and to generate a detection signal in response to detecting the electrostatic discharge event, and - an amplifier circuit (21) configured to amplify the detection signal to generate a control signal for the electrostatic discharge protection switch (25, 39A, 39B, 310A, 310B, 59, 510, 62A, 62B).

19. The device according to claim 18, wherein: The amplifier circuit (21) includes one or more converter stages (34A to 34C), wherein each converter stage (34A to 34C) includes a first pair of stacked transistors (35A, 35B) coupled between the first power supply rail (10) and an output node (38) of the corresponding converter stage (34A to 34C), and a second pair of stacked transistors (36A, 36B) coupled between the output node (38) of the corresponding converter stage (34A to 34C) and the second power supply rail (11).

20. The device according to claim 19, Also includes bias circuit, in, A first transistor (35A) of the first pair of stacked transistors (35A, 35B) and a first transistor (36B) of the second pair of stacked transistors (36A, 36B) are coupled to input nodes (37) of respective converter stages (34A to 34C), The bias circuit is configured to bias the control terminal of the second transistor (35B) in the first pair of stacked transistors (35A, 35B) to a first predefined voltage (Bias 1), and to bias the control terminal of the second transistor (36A) in the second pair of stacked transistors (36A, 36B) to a second predefined voltage (Bias 2).

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