An input acquisition module for an isolation safety barrier circuit

Abstract

The present invention discloses an input acquisition module for an isolated safety barrier circuit. The collector of an N-type transistor Q3 of the input acquisition module is connected to one end of a sampling resistor RX2, and the other end of the sampling resistor RX2 is connected to the source of an NMOS transistor MQ8. The two ends of the sampling resistor RX2 use a differential acquisition method to input a differential signal into an operational amplifier. After amplification and filtering by the operational amplifier, the signal is sent to an external analog-to-digital converter, which converts the analog signal into a digital signal and inputs it into a single-chip microcomputer. The source and gate of the NMOS transistor MQ8 are also connected in parallel with a resistor R43, and the source of the NMOS transistor MQ8 is also connected to the source of the NMOS transistor MQ9. The present invention can monitor in real time whether there are any abnormalities in the current passing through the sampling resistor RX2, thereby improving the safety of the entire circuit system. At the same time, the current signal monitored by the sampling resistor RX2 is not only stable and reliable, but also highly accurate, thereby enabling precise monitoring and further improving the safety of the circuit system.

Description

Technical Field

[0001] The present invention relates to the technical field of isolation circuits, and in particular to an input acquisition module of an isolation safety barrier circuit. Background Art

[0002] In the complex environment of industrial and electronic systems, the process of sensors sending signals to other electronic devices often encounters a series of interference problems, among which electromagnetic interference and ground loop interference are particularly prominent. They are like invisible stumbling blocks, hindering the smooth transmission of signals and may even cause fluctuations or abnormalities in equipment performance.

[0003] Isolation circuits play a crucial role in overcoming these interference barriers. They cleverly create an electrical isolation "safety net" between two critical nodes in the circuit. This barrier acts like a solid defense, effectively blocking the infiltration of interfering signals and providing a solid foundation for pure signal transmission. In this way, isolation circuits not only significantly mitigate the negative impacts of electromagnetic interference and ground loop interference, but also ensure that signals reach the receiving end reliably and consistently, providing an essential guarantee for the smooth operation of the entire system. In addition to providing electrical isolation and signal conversion, isolation circuits also provide safety protection. Electrical isolation separates high-voltage and low-voltage circuits, preventing safety issues such as electrical shock and electric shock caused by unstable or faulty high-voltage and high-frequency power supplies. Furthermore, isolation circuits protect against hazardous power supplies and high-frequency circuits, enhancing the stability and safety of the entire system. However, if the isolation circuit itself or the front-end components cause abnormal output current signals, these abnormal currents cannot be detected by the back-end through the isolation circuit's output, posing a safety hazard to the entire circuit system. Summary of the Invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides an input acquisition module for an isolation safety barrier circuit. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0005] According to a first aspect of an embodiment of the present invention, an input acquisition module for an isolated safety barrier circuit is provided, wherein a collector of an N-type transistor Q3 of the input acquisition module for the isolated safety barrier circuit is connected to one end of a sampling resistor RX2, and the other end of the sampling resistor RX2 is connected to the source of an NMOS transistor MQ8; both ends of the sampling resistor RX2 are electrically connected to an operational amplifier, the operational amplifier is electrically connected to an external analog-to-digital converter, and the external analog-to-digital converter is electrically connected to a single-chip microcomputer;

[0006] The two ends of the sampling resistor RX2 input the differential signal into the operational amplifier through differential acquisition. After being processed by the operational amplifier, the differential signal is sent to the external analog-to-digital converter. The external analog-to-digital converter converts the analog signal into a digital signal and then inputs it into the single-chip microcomputer.

[0007] The source and gate of the NMOS transistor MQ8 are also connected in parallel with the resistor R43 , and the source of the NMOS transistor MQ8 is also connected to the source of the NMOS transistor MQ9 .

[0008] In one embodiment of the present invention, when the oscillating current is in a positive cycle, the current passes through the diode group, the fuse-type isolating switch FS3, the second pin and the first pin of the transformer T2, the NMOS transistor MQ8, and then passes through the sampling resistor RX2, the N-type transistor Q3, the resistor RX1, and then connects to the ground terminal;

[0009] When the oscillating current is in a negative cycle, the current passes through the diode group, the fuse-type isolating switch FS3, the second pin and the third pin of the transformer T2, the NMOS tube MQ9, and then passes through the sampling resistor RX2, the N-type transistor Q3, the resistor RX1 and then connects to the ground terminal.

[0010] In one embodiment of the present invention, the single chip microcomputer is electrically connected to a relay, and the relay is electrically connected to an alarm.

[0011] In one embodiment of the present invention, the diode group includes: a diode D10A, a diode D10B, a diode D11A, a diode D11B, a diode D12A, and a diode D12B;

[0012] Diodes D10A and D10B are connected in parallel and in series with a parallel circuit of diodes D11A and D11B, and then in series with a parallel circuit of diodes D12A and D12B.

[0013] The cathode of diode D12A and diode D12B is connected to one end of fuse-type isolating switch FS3, the other end of fuse-type isolating switch FS3 is connected to the second pin of the transformer and one end of capacitor C34, the other end of capacitor C34 is grounded, the first pin of the transformer is connected to the drain of NMOS transistor MQ8, the source and gate of NMOS transistor MQ8 are connected in parallel with resistor R43, the source of NMOS transistor MQ8 is also connected to one end of sampling resistor RX2, the other end of sampling resistor RX2 is connected to the collector of N-type transistor Q3. The electrodes are connected, the base of the N-type transistor Q3 is connected to the collector of the N-type transistor Q2 and one end of the resistor R38, the other end of the resistor R38 is connected to the power supply, the base of the N-type transistor Q2 is connected to the emitter of the N-type transistor Q3 and one end of the resistor RX1, the other end of the resistor RX1 is connected to the emitter of the N-type transistor Q2, and the emitter of the N-type transistor Q2 is grounded; the gate of the NMOS transistor MQ8 is also connected in series with the resistor R32, the resistor R32 is connected in series with the capacitor C41, and the capacitor C41 is connected to the positive electrode of the oscillation module;

[0014] The third pin of the mutual inductor is connected to the drain of the NMOS tube MQ9, the source and gate of the NMOS tube MQ9 are connected in parallel with the resistor R44, the gate of the NMOS tube MQ9 is also connected in series with the resistor R33, the resistor R33 is connected in series with the capacitor C42, and the capacitor C42 is connected to the negative electrode of the oscillation module.

[0015] Beneficial effects of the present invention:

[0016] The present invention uses sampling resistor RX2 to input the voltage of sampling resistor RX2 into the single-chip microcomputer, thereby obtaining the magnitude of the current passing through sampling resistor RX2. This allows for real-time monitoring of whether the current passing through sampling resistor RX2 is abnormal, thereby improving the safety of the overall circuit system. Furthermore, the current signal monitored through sampling resistor RX2 is not only stable and reliable, but also highly accurate, enabling precise monitoring and further improving the safety of the circuit system.

[0017] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present invention. The purposes and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings.

[0018] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0020] Figure 1 A schematic diagram of the circuit principle of an input acquisition module of an isolation safety barrier circuit provided by an embodiment of the present invention;

[0021] Figure 2 This is a schematic diagram of the circuit principle of an input acquisition module of an isolation safety barrier circuit in the prior art;

[0022] Figure 3 This is a schematic diagram of another sampling resistor position of an input acquisition module of an isolation safety barrier circuit. DETAILED DESCRIPTION

[0023] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0024] like Figure 1 As shown, an embodiment of the present invention provides an input acquisition module for an isolated safety barrier circuit. The collector of an N-type transistor Q3 of the input acquisition module is connected to one end of a sampling resistor RX2, and the other end of the sampling resistor RX2 is connected to the source of an NMOS transistor MQ8. The two ends of the sampling resistor RX2 are electrically connected to an operational amplifier, which is electrically connected to an external analog-to-digital converter, which is electrically connected to a single-chip microcomputer. The two ends of the sampling resistor RX2 use differential acquisition to input a differential signal into the operational amplifier. After amplification and filtering by the operational amplifier, the signal is sent to an external analog-to-digital converter, which converts the analog signal into a digital signal and then inputs it into the single-chip microcomputer. The source and gate of the NMOS transistor MQ8 are also connected in parallel to a resistor R43, and the source of the NMOS transistor MQ8 is also connected to the source of the NMOS transistor MQ9. The single-chip microcomputer is electrically connected to a relay, which is electrically connected to an alarm. When the single-chip microcomputer detects a fault in the input signal, the single-chip microcomputer IO pin controls the photocoupler to further control the relay contacts to close, causing the alarm to issue an alarm signal.

[0025] When the oscillating current input to the acquisition module is in a positive cycle, the current passes through the diode group, the fuse-type isolation switch FS3, the second pin and the first pin of the transformer T2, the NMOS tube MQ8, and then passes through the sampling resistor RX2, the N-type transistor Q3, the resistor RX1, and then connects to the ground terminal.

[0026] When the oscillating current input to the acquisition module is in a negative cycle, the current passes through the diode group, the fuse-type isolation switch FS3, the second pin and the third pin of the transformer T2, the NMOS tube MQ9, and then passes through the sampling resistor RX2, the N-type transistor Q3, the resistor RX1 and then connects to the ground terminal.

[0027] In this embodiment, it should be noted that a sampling resistor RX2 is added while the input acquisition module circuit of the existing isolation barrier remains unchanged. This allows the sampling resistor RX2 to be connected to a single-chip microcomputer, and the voltage across the sampling resistor RX2 is fed into the microcontroller. The microcontroller then calculates the current value of the circuit's current input based on the voltage. The microcontroller can then calculate the magnitude of the current flowing through the sampling resistor RX2, thereby monitoring whether the current in the isolation barrier circuit is normal and enabling timely detection of abnormal currents. When the microcontroller detects a fault in the input signal, the microcontroller's IO pin controls the photocoupler to further close the relay contacts, causing the alarm to sound an alarm signal. This prevents damage to back-end equipment caused by abnormal current flow, thereby ensuring the safety of the circuit system and equipment.

[0028] In this embodiment, the circuit schematic diagram of the input acquisition module of the isolation safety barrier circuit is as follows: Figure 1 As shown, the signal input terminal J3A, the signal input terminal J3B and the signal input terminal J3C are the signal input terminals of the input acquisition module. A bidirectional transient suppression diode TVS4 is connected in parallel between the signal input terminal J3A and the signal input terminal J3C. A bidirectional transient suppression diode TVS2 is connected in parallel between the signal input terminal J3B and the signal input terminal J3C. The bidirectional transient suppression diode TVS2 is connected in parallel with the capacitor C38. The two ends of the capacitor C38 are respectively connected in series with the inductor L7 and the inductor L8. One end of the inductor L7 and one end of the inductor L8 are connected in parallel with the voltage regulator diodes Z10, Z11 and Z12 in sequence. The positive electrodes of the voltage regulator diodes Z10, Z11 and Z12 are grounded.

[0029] A diode group includes diode D10A, diode D10B, diode D11A, diode D11B, diode D12A, and diode D12B. The cathode of voltage regulator diode Z12 is connected to the anodes of diodes D10A and D10B. Diodes D10A and D10B are connected in parallel, connected in series with the parallel circuit of diodes D11A and D11B, and then connected in series with the parallel circuit of diodes D12A and D12B.

[0030] The cathode of diode D12A and diode D12B is connected to one end of fuse-type isolating switch FS3, the other end of fuse-type isolating switch FS3 is connected to the second pin of transformer and one end of capacitor C34, the other end of capacitor C34 is grounded, the first pin of transformer is connected to the drain of NMOS tube MQ8, the source and gate of NMOS tube MQ8 are connected in parallel with resistor R43, the source of NMOS tube MQ8 is also connected to one end of sampling resistor RX2, the other end of sampling resistor RX2 is connected to the collector of N-type transistor Q3, N-type The base of transistor Q3 is connected to the collector of N-type transistor Q2 and one end of resistor R38, the other end of resistor R38 is connected to a power supply, the base of N-type transistor Q2 is connected to the emitter of N-type transistor Q3 and one end of resistor RX1, the other end of resistor RX1 is connected to the emitter of N-type transistor Q2, and the emitter of N-type transistor Q2 is grounded and connected to the positive electrode of voltage regulator Z12; the gate of NMOS transistor MQ8 is also connected in series with resistor R32, resistor R32 is connected in series with capacitor C41, and capacitor C41 is connected to the positive electrode of the oscillation module;

[0031] The third pin of the mutual inductor is connected to the drain of the NMOS tube MQ9, the source and gate of the NMOS tube MQ9 are connected in parallel with the resistor R44, the gate of the NMOS tube MQ9 is also connected in series with the resistor R33, the resistor R33 is connected in series with the capacitor C42, and the capacitor C42 is connected to the negative electrode of the oscillation module.

[0032] The other end of the fuse-type disconnector FS3 is also connected to one end of the capacitor C30 and one end of the resistor R26. The other end of the resistor R26 is connected to the winding resistor WR1. The winding resistor WR1 has one end connected to ground and the other end connected to the positive electrode of the Zener diode Z5. The negative electrode of the Zener diode Z5 is connected to the positive electrode of the Zener diode Z1. The negative electrode of the Zener diode Z1 is connected to the other end of the capacitor C30. The other end of the capacitor C30 is also connected to the power supply and one end of the fuse-type disconnector FS2. The other end of the fuse-type disconnector FS2 is connected in series with resistors R25, R24, R23, R22, R21, and inductor L6. Inductor L6 is connected to one end of the bidirectional transient voltage suppressor diode TVS2.

[0033] The zener diode Z4 and the zener diode Z8 are connected in series, the positive electrode of the zener diode Z8 is connected in series with the capacitor C29, the zener diode Z4, the zener diode Z8, and the capacitor C29 are connected in parallel in the circuit between the other end of the fuse-type disconnect switch FS2 and the inductor L6 and the bidirectional transient suppression diode TVS2, the zener diode Z3 and the zener diode Z7 are connected in series and then connected in parallel across the zener diode Z4 and the zener diode Z8, and the zener diode Z2 and the zener diode Z6 are connected in series and then connected in parallel across the zener diode Z4 and the zener diode Z8.

[0034] The effect of the present invention is further described below by experiments:

[0035] When the sampling resistor is set at other positions in the circuit, the output current is unstable and the accuracy is low.

[0036] Specifically, if Figure 2 As shown in the figure, if the resistor RX1 of the input acquisition module of the original isolation safety barrier circuit is used as the sampling resistor, the left side of the resistor RX1 is grounded. Under ideal conditions, the left end of the resistor RX1 is at zero potential. If the current passing through the resistor RX1 needs to be obtained, the voltage at the right end of the resistor RX1 is collected. However, in actual applications, there is noise interference at the ground end, which causes signal fluctuations. The final current value fluctuates greatly and cannot meet the accuracy requirements.

[0037] No other components are allowed to be installed on the explosion-proof circuit of the circuit. If the current limiting resistor R27 of the explosion-proof circuit of the input acquisition module of the original isolation safety barrier circuit is used as a sampling resistor, if a fault occurs in the front end, such as a short circuit, the current limiting resistor R27 itself will have a large current or voltage. This large current or voltage will be transmitted to the back end, causing damage to the back end devices.

[0038] In addition, in the pre-turn-on state before the N-type transistor Q3 is turned on, a voltage drop is generated, which affects the voltage at the right end of the sampling resistor RX2, resulting in poor accuracy of the obtained current.

[0039] like Figure 3 As shown, if the sampling resistor RXa is set between the drain of the NMOS tube MQ8 and the first pin of the transformer, or the sampling resistor RXb is set between the drain of the NMOS tube MQ9 and the third pin of the transformer, there is also the problem of the influence of the tube turning on on the voltage, resulting in poor current accuracy.

[0040] By placing the sampling resistor RX2 between the collector of the N-type transistor Q3 and the source of the NMOS transistor MQ8, sampling across the sampling resistor RX2 and taking the difference between the voltages at both ends can cancel out the fluctuation interference at both ends without being affected by the switching transistor. The monitored current signal is not only stable and reliable, but also highly accurate. Furthermore, the sampling resistor RX2 is located at the back end of the loop and does not affect the loop.

[0041] The monitoring current of the sampling resistors at various positions is shown in Table 1:

[0042] Table 1

[0043]

[0044]

[0045] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0046] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0047] In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," "connect," "fixed," etc. should be understood broadly. For example, they may refer to fixed connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0048] In the present invention, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Furthermore, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0049] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

[0050] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. An input acquisition module for an isolation safety barrier circuit, characterized in that: The collector of the N-type transistor Q3 of the input acquisition module of the isolation safety gate circuit is connected to one end of the sampling resistor RX2, and the other end of the sampling resistor RX2 is connected to the source of the NMOS transistor MQ8; the two ends of the sampling resistor RX2 are electrically connected to the operational amplifier, the operational amplifier is electrically connected to the external analog-to-digital converter, and the external analog-to-digital converter is electrically connected to the single-chip microcomputer; The two ends of the sampling resistor RX2 input the differential signal into the operational amplifier through differential acquisition. After being processed by the operational amplifier, the differential signal is sent to the external analog-to-digital converter. The external analog-to-digital converter converts the analog signal into a digital signal and then inputs it into the single-chip microcomputer. The source and gate of the NMOS tube MQ8 are also connected in parallel with the resistor R43, and the source of the NMOS tube MQ8 is also connected to the source of the NMOS tube MQ9; When the oscillating current is in a positive cycle, the current passes through the diode group, the fuse-type isolating switch FS3, the second pin and the first pin of the transformer T2, the NMOS tube MQ8, and then passes through the sampling resistor RX2, the N-type transistor Q3, the resistor RX1, and then connects to the ground terminal; When the oscillating current is in a negative cycle, the current passes through the diode group, the fuse-type isolating switch FS3, the second pin and the third pin of the transformer T2, the NMOS tube MQ9, and then passes through the sampling resistor RX2, the N-type transistor Q3, the resistor RX1 and then connects to the ground terminal.

2. The input acquisition module of the isolation safety barrier circuit according to claim 1, characterized in that: The single chip microcomputer is electrically connected to a relay, and the relay is electrically connected to an alarm.

3. The input acquisition module of the isolation safety barrier circuit according to claim 1, characterized in that: The diode group includes: a diode D10A, a diode D10B, a diode D11A, a diode D11B, a diode D12A and a diode D12B; Diodes D10A and D10B are connected in parallel and in series with a parallel circuit of diodes D11A and D11B, and then in series with a parallel circuit of diodes D12A and D12B. The cathode of diode D12A and diode D12B is connected to one end of fuse-type isolating switch FS3, the other end of fuse-type isolating switch FS3 is connected to the second pin of the transformer and one end of capacitor C34, the other end of capacitor C34 is grounded, the first pin of the transformer is connected to the drain of NMOS transistor MQ8, the source and gate of NMOS transistor MQ8 are connected in parallel with resistor R43, the source of NMOS transistor MQ8 is also connected to one end of sampling resistor RX2, the other end of sampling resistor RX2 is connected to the collector of N-type transistor Q3. The electrodes are connected, the base of the N-type transistor Q3 is connected to the collector of the N-type transistor Q2 and one end of the resistor R38, the other end of the resistor R38 is connected to the power supply, the base of the N-type transistor Q2 is connected to the emitter of the N-type transistor Q3 and one end of the resistor RX1, the other end of the resistor RX1 is connected to the emitter of the N-type transistor Q2, and the emitter of the N-type transistor Q2 is grounded; the gate of the NMOS transistor MQ8 is also connected in series with the resistor R32, the resistor R32 is connected in series with the capacitor C41, and the capacitor C41 is connected to the positive electrode of the oscillation module; The third pin of the mutual inductor is connected to the drain of the NMOS tube MQ9, the source and gate of the NMOS tube MQ9 are connected in parallel with the resistor R44, the gate of the NMOS tube MQ9 is also connected in series with the resistor R33, the resistor R33 is connected in series with the capacitor C42, and the capacitor C42 is connected to the negative electrode of the oscillation module.

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