Ceramic electronic component, package, circuit board, and method for manufacturing ceramic electronic component

Abstract

This ceramic electronic component is characterized by comprising: a substantially rectangular parallelepiped-shaped laminated sheet in which a plurality of dielectric layers and a plurality of internal electrode layers having Ni as the main component are alternately laminated, said laminated sheet being formed such that the plurality of internal electrode layers are alternately exposed on first and second end surfaces of the substantially rectangular parallelepiped shape, said first and second end surfaces facing each other; and a pair of external electrodes provided on the first end surface and the second end surface, in which the main component of a contact layer in contact with the first end surface and the second end surface is Cu, and a low-melting-point metal having a lower melting point than Cu is added to the plurality of internal electrode layers and the contact layer. Among one or more internal electrode layers from the outermost layer among the plurality of internal electrode layers, the width of a connection portion connected to the external electrode is narrower than the width of other regions.

Description

Technical Field

[0001] The present invention relates to a ceramic electronic component, a package, a circuit board and a method for manufacturing the ceramic electronic component. Background Art

[0002] In recent years, electronic devices such as portable information terminals have been miniaturized, and the mounting area of ​​ceramic electronic components on circuit boards has been limited. On the other hand, due to the high functionality of devices, there is a demand for further large-capacity multilayer ceramic capacitors.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: International Publication No. 2014 / 175034

[0006] Patent Document 2: Japanese Patent Application Publication No. 2022-067608

[0007] Patent Document 3: Japanese Patent Application Publication No. 2014-212295

[0008] Patent Document 4: Japanese Patent Application Publication No. 2011-134943 Summary of the invention

[0009] Technical problem to be solved by the invention

[0010] In order to realize the large capacity of ceramic electronic components, thinning and increasing the number of layers, and reducing the cover layer and side edge (outer protection portion) are being promoted. However, when the area and number of layers of the internal electrode layer are increased, and the cover layer and side edge are thinned, when the Cu external electrode is sintered, cracks may occur in the portion covered by the external electrode and where the cover layer overlaps with the side edge. In order to suppress the cracks, it is possible to suppress the diffusion of Cu (for example, refer to Patent Document 1). As a method of suppressing the diffusion of Cu, it is generally known that there is a method of reducing the sintering temperature by adjusting the composition of glass added to the conductive paste that forms the external electrode (for example, refer to Patent Document 1) and adding a low melting point metal such as Sn (for example, refer to Patent Document 2).

[0011] However, when the sintering temperature is excessively lowered to a level that does not cause cracks, there are problems that the density of the external electrode is reduced, reliability cannot be ensured, and the bonding strength between the external electrode and the ceramic body is reduced.

[0012] In addition, in order to achieve a large capacity of a multilayer ceramic capacitor, it is important to increase the total relative area of ​​the internal electrode layers. In order to achieve a large capacity without expanding the mounting area, it is possible to consider increasing the number of internal electrode layers (for example, refer to Patent Document 3). However, when the number of layers is large, positional deviation is likely to occur during stacking, and it is difficult to cut the stacked body before firing perpendicular to the stacking direction.

[0013] Therefore, it is possible to increase the width of the internal electrode layer while reducing the number of layers. However, when the width of the internal electrode layer becomes larger, the adhesive may not be fully removed (Patent Document 4). When the adhesive is not fully removed, cracks may occur.

[0014] The present invention has been made in view of the above-mentioned technical problems, and an object of the present invention is to provide a ceramic electronic component, a package, a circuit board, and a method for manufacturing a ceramic electronic component that can suppress the occurrence of cracks.

[0015] Means for solving technical problems

[0016] The ceramic electronic component of the present invention is characterized in that it includes: a laminated sheet having a substantially rectangular parallelepiped shape in which a plurality of dielectric layers and a plurality of internal electrode layers having Ni as a main component are alternately laminated, wherein the plurality of internal electrode layers are alternately exposed at first and second end faces opposite to each other in the substantially rectangular parallelepiped shape; and a pair of external electrodes provided at the first and second end faces, wherein the main component of the contact layers in contact with the first and second end faces is Cu, a low-melting-point metal having a melting point lower than that of Cu is added to the plurality of internal electrode layers and the contact layers, and wherein in one or more internal electrode layers from the outermost layer among the plurality of internal electrode layers, the width of the connection portion connected to the external electrode is narrower than the width of other regions.

[0017] In the above ceramic electronic component, the low melting point metal may include at least any one of Ga, In, Sn, Bi, Zn, and Al.

[0018] In the ceramic electronic component, the number of the one or more internal electrode layers from the outermost layer may account for 10% or more of the total number of laminated layers of the plurality of internal electrode layers.

[0019] In the ceramic electronic component, the width of the connection portion may be not less than 1 / 2 and not more than 4 / 5 of the width of the internal electrode layers in a region where the internal electrode layers connected to different external electrodes face each other.

[0020] In the above-mentioned ceramic electronic component, the length of the connecting portion in the direction relative to the first end face and the second end face may be greater than 1 / 3 of the distance that the pair of external electrodes extend from the first end face or the second end face on at least any one of the four faces of the laminate sheet other than the first end face and the second end face.

[0021] In the above-mentioned ceramic electronic component, it may be that, when the directions orthogonal to the directions relative to the first end face and the second end face and orthogonal to each other are set as the first direction and the second direction, and the direction in which the multiple internal electrode layers are stacked is set as the first direction, the dimension of the ceramic electronic component in the first direction is more than 1.3 times the dimension in the second direction.

[0022] In the above-mentioned ceramic electronic component, it may be that, when the directions orthogonal to the directions relative to the first end face and the second end face and orthogonal to each other are set as the first direction and the second direction, and the direction in which the multiple internal electrode layers are stacked is set as the second direction, the dimension of the ceramic electronic component in the first direction is more than 1.3 times the dimension in the second direction.

[0023] In the above ceramic electronic component, each of the plurality of internal electrode layers may have a thickness of 0.1 μm to 2 μm.

[0024] In the above ceramic electronic component, each of the plurality of dielectric layers may have a thickness of 0.3 μm or more and 10 μm or less.

[0025] The packaging body of the present invention is characterized in that it includes: any one of the above-mentioned ceramic electronic components; a carrier tape having a sealing surface perpendicular to a first direction, and a recessed portion recessed from the sealing surface in the first direction for accommodating the ceramic electronic component, wherein the first direction is the first direction between the first direction and the second direction that are perpendicular to the direction relative to the first end face and the second end face and are perpendicular to each other; and a top tape adhered to the sealing surface and capable of covering the recessed portion.

[0026] The circuit board of the present invention is characterized in that it includes: any one of the above-mentioned ceramic electronic components; and a mounting substrate, which has a mounting surface perpendicular to a first direction, and a pair of connecting electrodes arranged on the mounting surface and connected to the pair of external electrodes of the ceramic electronic component via solder, respectively, wherein the first direction is the first direction of the first direction and the second direction that are orthogonal to the direction relative to the first end face and the second end face and are orthogonal to each other.

[0027] The method for manufacturing a ceramic electronic component of the present invention is characterized in that it includes: a step of firing a laminated body obtained by stacking a plurality of stacking units, wherein an internal electrode pattern having Ni as a main component and to which a low-melting-point metal having a lower melting point than Cu is added is formed on a dielectric green sheet; and a step of forming a layer having Cu as a main component and containing the low-melting-point metal on first and second end surfaces of the laminated body that are opposite to each other when firing the laminated body or after firing the laminated body, wherein the width of a connection portion connected to the layer containing the low-melting-point metal in one or more internal electrode patterns from the outermost layer among the plurality of internal electrode patterns is narrower than the width of other regions.

[0028] The ceramic electronic component of the present invention is characterized in that the dimension of the ceramic electronic component in the first direction is 1.3 times or more of the dimension in the second direction orthogonal to the first direction, and the ceramic electronic component includes: a laminated sheet having a substantially rectangular parallelepiped shape, in which a plurality of dielectric layers and a plurality of internal electrode layers having Ni as a main component are alternately laminated in the second direction, and the laminated sheet is formed in such a manner that the plurality of internal electrode layers are alternately exposed at a first end face and a second end face that are opposite to each other in a third direction orthogonal to the first direction and the second direction; and a pair of external electrodes provided on the first end face and the second end face, the main component of the portions of the external electrodes in contact with the first end face and the second end face being Cu, and at least any one of the interior of the plurality of internal electrode layers and the interface between the plurality of internal electrode layers and the plurality of dielectric layers having a low melting point metal having a lower melting point than Cu.

[0029] In the above ceramic electronic component, the low melting point metal may include any one of Ga, In, Sn, Bi, Pb, and Zn.

[0030] In the ceramic electronic component, in one or more of the plurality of internal electrode layers from the outermost layer, the width of the connection portion connected to the external electrode in the first direction may be narrower than that of other regions.

[0031] In the ceramic electronic component, the number of the one or more internal electrode layers from the outermost layer may be equal to or greater than 10% and equal to or less than 50% of the total number of laminated layers of the plurality of internal electrode layers.

[0032] In the ceramic electronic component, the width of the connection portion in the first direction may be not less than 1 / 2 and not more than 4 / 5 of the width of the internal electrode layers in the first direction in a region where internal electrode layers connected to different external electrodes face each other.

[0033] In the above ceramic electronic component, each of the plurality of internal electrode layers may have a thickness of 0.1 μm to 2 μm.

[0034] In the ceramic electronic component, each of the plurality of dielectric layers may have a thickness of 0.3 μm or more and 3 μm or less.

[0035] The packaging body of the present invention is characterized in that it includes: any one of the above-mentioned ceramic electronic components; a carrier tape having a sealing surface perpendicular to the first direction, and a recessed portion recessed from the sealing surface in the first direction for accommodating the ceramic electronic component; and a top tape adhered to the sealing surface and capable of covering the recessed portion.

[0036] The circuit board of the present invention is characterized in that it includes: any one of the above-mentioned ceramic electronic components; and a mounting substrate, which has a mounting surface perpendicular to the first direction, and a pair of connecting electrodes arranged on the mounting surface and connected to the pair of external electrodes of the ceramic electronic component via solder respectively.

[0037] The method for manufacturing a ceramic electronic component of the present invention is a method for manufacturing a ceramic electronic component in which a dimension in a first direction is 1.3 times or more of a dimension in a second direction orthogonal to the first direction, and is characterized in that it includes: a step of firing a laminated body, wherein the laminated body is obtained by stacking a plurality of laminated units in the second direction, wherein the laminated units are obtained by forming an internal electrode pattern having Ni as a main component and adding a low-melting-point metal having a lower melting point than Cu on a dielectric green sheet; and a step of forming a layer having Cu as a main component on a first end face and a second end face of the laminated body that are opposite to each other in a third direction orthogonal to the first direction and the second direction when firing the laminated body or after firing the laminated body.

[0038] Effects of the Invention

[0039] According to the present invention, it is possible to provide a ceramic electronic component, a package, a circuit board, and a method for producing a ceramic electronic component that can suppress the occurrence of cracks. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 (a) and (b) are partial cross-sectional perspective views of the multilayer ceramic capacitor according to the first embodiment.

[0041] Figure 2 yes Figure 1 (a) AA line cross-sectional view.

[0042] Figure 3 yes Figure 1 (a) BB line cross-sectional view.

[0043] Figure 4 This is an enlarged cross-sectional view near the external electrode.

[0044] Figure 5 This is a diagram illustrating an example of a crack.

[0045] Figure 6 This is a diagram illustrating the first area and the second area.

[0046] Figure 7 This is a diagram illustrating the dimension e.

[0047] Figure 8 It is a diagram illustrating the flow of a method for manufacturing a multilayer ceramic capacitor.

[0048] Fig. 9 This is a side view of a circuit board including a multilayer ceramic capacitor.

[0049] Fig.10 It is a partial plan view of the packaging body.

[0050] Fig.11 It is a cross-sectional view of the package body.

[0051] Fig.12 (a) and (b) are diagrams illustrating a multilayer ceramic capacitor according to a second embodiment.

[0052] Fig.13 (a) and (b) are diagrams illustrating a multilayer ceramic capacitor according to a third embodiment.

[0053] Fig.14 It is a diagram illustrating a lamination process.

[0054] Fig.15 (a) and (b) are diagrams illustrating a multilayer ceramic capacitor according to a fourth embodiment.

[0055] Fig.16 (a) and (b) are diagrams illustrating a multilayer ceramic capacitor according to a fifth embodiment.

[0056] Fig.17 It is a partial cross-sectional perspective view of a multilayer ceramic capacitor according to a sixth embodiment.

[0057] Fig.18 yes Fig.17 AA line cross-section diagram.

[0058] Fig.19 yes Fig.17 BB line cross-section diagram.

[0059] Fig. 20 This is an enlarged cross-sectional view near the external electrode.

[0060] Fig.21A diagram illustrating a multilayer ceramic capacitor having a large number of layers stacked.

[0061] Fig. 22 This is a diagram illustrating an example of a binder removal crack.

[0062] Fig.23 It is a diagram illustrating the flow of a method for manufacturing a multilayer ceramic capacitor.

[0063] Fig.24 It is a diagram illustrating a lamination process.

[0064] Fig.25 This is a side view of a circuit board including a multilayer ceramic capacitor.

[0065] Fig.26 It is a partial plan view of the packaging body.

[0066] Fig. 27 It is along Fig.26 Cross-sectional view of the packaging body of the DD line.

[0067] Fig.28 This is a diagram illustrating a crack at a corner near an external electrode.

[0068] Fig.29 It is a diagram illustrating a multilayer ceramic capacitor according to a seventh embodiment.

[0069] Fig.30 This is a diagram illustrating the dimension e.

[0070] Fig.31 It is a diagram illustrating a lamination process.

[0071] Fig.32 It is a diagram illustrating a multilayer ceramic capacitor according to an eighth embodiment.

[0072] Fig.33 It is a diagram illustrating a lamination process. DETAILED DESCRIPTION

[0073] Hereinafter, embodiments will be described with reference to the drawings.

[0074] (First embodiment)

[0075] Figure 1 (a) and Figure 1 (b) is a partial cross-sectional perspective view of the multilayer ceramic capacitor 100 according to the first embodiment. Figure 2 yes Figure 1 (a) AA line cross-sectional view. Figure 3 yes Figure 1 (a) is a cross-sectional view of line BB. Figure 1As shown in the example, the laminated ceramic capacitor 100 includes: a laminated sheet 10 having a substantially rectangular parallelepiped shape; and external electrodes 20a and 20b provided on any two opposite end faces of the laminated sheet 10. In addition, the two faces at both ends of the lamination direction of the laminated sheet 10 among the four faces other than the two end faces are referred to as the upper face and the lower face. The two faces other than the two end faces, the upper face and the lower face are referred to as the side faces. The external electrodes 20a and 20b extend on the upper face, the lower face and the two side faces of the laminated sheet 10 in the lamination direction. However, the external electrodes 20a and the external electrodes 20b are spaced apart from each other.

[0076] In addition, Figure 1 (a)~ Figure 3 In the figure, the T direction (first direction) is the height direction of the multilayer ceramic capacitor 100, and is orthogonal to the direction in which the external electrode 20a and the external electrode 20b are opposite to each other (length direction: L direction). The W direction (second direction) is orthogonal to the T direction and the L direction. In the present embodiment, the T direction corresponds to the stacking direction of the internal electrode layer 12, and is the direction in which the upper surface and the lower surface of the laminate 10 are opposite to each other. The W direction is the direction in which the two side surfaces of the laminate 10 are opposite to each other. The L direction is the direction in which the two end surfaces of the laminate 10 are opposite to each other.

[0077] When the height of the multilayer ceramic capacitor 100 in the T direction is denoted as height T0, the width of the multilayer ceramic capacitor 100 in the W direction is denoted as width W0, and the length of the multilayer ceramic capacitor 100 in the L direction is denoted as length L0, the multilayer ceramic capacitor 100 has a relationship of T0=W0. In addition, the height T0, the width W0, and the length L0 are the maximum dimensions in the T direction, the W direction, and the L direction, respectively.

[0078] The laminated sheet 10 has a structure in which dielectric layers 11 including ceramic materials that function as dielectrics and internal electrode layers 12 mainly composed of metals are alternately laminated. In other words, the laminated sheet 10 includes: a plurality of internal electrode layers 12 facing each other; and dielectric layers 11 sandwiched between the plurality of internal electrode layers 12. The end edges of the directions in which the internal electrode layers 12 extend are alternately exposed on the first end face of the laminated sheet 10 where the external electrode 20a is provided and the second end face where the external electrode 20b is provided. The internal electrode layer 12 connected to the external electrode 20a is not connected to the external electrode 20b. The internal electrode layer 12 connected to the external electrode 20b is not connected to the external electrode 20a. Therefore, each internal electrode layer 12 is alternately conductive with the external electrode 20a and the external electrode 20b. In addition, in the laminate of the dielectric layer 11 and the internal electrode layer 12, the internal electrode layer 12 is arranged at the uppermost layer in the lamination direction, and the internal electrode layer 12 is also arranged at the lowermost layer in the lamination direction, and both end faces of the laminate in the lamination direction are covered by the cover layer 13. The cover layer 13 contains a ceramic material as a main component. For example, the main component of the cover layer 13 is the same as the main component of the dielectric layer 11.

[0079] The dielectric layer 11 is mainly composed of a ceramic material having a perovskite structure represented by the general formula ABO3. In addition, the perovskite structure contains ABO3 deviating from the stoichiometric composition. 3-α For example, as the ceramic material, BaTiO3 (barium titanate), CaZrO3 (calcium zirconate), CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), MgTiO3 (magnesium titanate), BaTiO3 (calcium titanate) and a perovskite structure can be used. 1-x-y Ca x Sr y Ti 1-z Zr z At least one of O3 (0≤x≤1, 0≤y≤1, 0≤z≤1), etc. 1-x- y Ca x Sr y Ti 1-z Zr z O3 is barium strontium titanate, barium calcium titanate, barium zirconate, barium titanate zirconate, calcium titanate zirconate and barium calcium titanate, etc.

[0080] Additives may be added to the dielectric layer 11. Examples of additives added to the dielectric layer 11 include oxides of magnesium (Mg), manganese (Mn), molybdenum (Mo), vanadium (V), chromium (Cr), rare earth elements (yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and ytterbium (Yb)), or oxides containing cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K), or silicon (Si), or glass containing Co, Ni, Li, B, Na, K, or Si.

[0081] The thickness of each dielectric layer 11 in the stacking direction is, for example, 0.3 μm to 10 μm, or 0.4 μm to 8 μm, or 0.5 μm to 5 μm. The thickness of each dielectric layer 11 can be measured as follows: Figure 2 After the cross section is exposed, an average value of thickness at 10 locations is obtained by using an image taken with a microscope such as a scanning transmission electron microscope.

[0082] The internal electrode layer 12 contains Ni as a main component. The thickness of each internal electrode layer 12 in the stacking direction is, for example, 0.1 μm or more and 2 μm or less. The thickness of each internal electrode layer 12 can be measured as follows: Figure 2 After the cross section is exposed, an average value of thickness at 10 locations is obtained by using an image taken with a microscope such as a scanning transmission electron microscope.

[0083] like Figure 2 As illustrated, the region where the internal electrode layer 12 connected to the external electrode 20a and the internal electrode layer 12 connected to the external electrode 20b face each other is a region where electrostatic capacitance is generated in the multilayer ceramic capacitor 100. Therefore, the region where electrostatic capacitance is generated is referred to as a capacitor portion 14. That is, the capacitor portion 14 is a region where adjacent internal electrode layers connected to different external electrodes face each other.

[0084] The region where the internal electrode layers 12 connected to the external electrode 20a are opposite to each other without being separated by the internal electrode layer 12 connected to the external electrode 20b is called the end edge 15. In addition, the region where the internal electrode layers 12 connected to the external electrode 20b are opposite to each other without being separated by the internal electrode layer 12 connected to the external electrode 20a is also the end edge 15. That is, the end edge is a region where the internal electrode layers connected to the same external electrode are opposite to each other without being separated by the internal electrode layers connected to different external electrodes. The end edge 15 is a region where electrostatic capacitance is not generated. The end edge 15 can be the same composition as the dielectric layer 11 of the capacitor part 14, or it can be a composition different from the dielectric layer 11 of the capacitor part 14.

[0085] like Figure 3 As shown in the example, in the laminated sheet 10, the area from the two side surfaces to the internal electrode layer 12 is called the side edge 16. The side edge 16 is also an area where no electrostatic capacitance is generated. The side edge 16 can be the same composition as the dielectric layer 11 of the capacitor part 14, or it can be a composition different from the dielectric layer 11 of the capacitor part 14.

[0086] Figure 4 is an enlarged cross-sectional view of the vicinity of the external electrode 20a. Figure 4 In the figure, hatching is omitted. Figure 4 As illustrated, the external electrode 20a has a structure in which a plating layer 22 is provided on a base layer 21 as a contact layer in contact with the first end face of the laminated sheet 10. The base layer 21 contains Cu as a main component. The base layer 21 may also contain a glass component. The plating layer 22 contains a metal such as Cu, Ni, aluminum (Al), zinc (Zn), Sn, or an alloy of two or more thereof as a main component. The plating layer 22 may be a plating layer of a single metal component or a plurality of plating layers of metal components different from each other. For example, the plating layer 22 has a structure in which a first plating layer 23, a second plating layer 24, and a third plating layer 25 are formed in sequence from the base layer 21 side. The first plating layer 23 is, for example, a Sn plating layer. The second plating layer 24 is, for example, a Ni plating layer. The third plating layer 25 is, for example, a Sn plating layer. In addition, in Figure 4 In FIG. 1 , the external electrode 20 a is illustrated, but the external electrode 20 b also has the same stacked structure.

[0087] In order to achieve a larger capacity of multilayer ceramic capacitors, thinning and increasing the number of layers, and reducing the cover layer and side edges are being promoted. However, when the area of ​​the internal electrode layer and the number of layers are increased and the cover layer and side edges are thinned, when the external electrode is sintered, there is a possibility that the portion covered by the external electrode and where the cover layer overlaps with the side edge (the corner near the external electrode) may produce the following Figure 5 Such a crack 40 situation.

[0088] This is caused based on the following mechanism. When the internal electrode layer 12 reacts with the base layer 21 during the sintering process of the base layer 21, Cu, which is a metal component of the base layer 21, diffuses to the Ni side of the internal electrode layer 12, and the internal electrode layer 12 expands. Due to the expansion of the internal electrode layer 12, stress toward the outside is generated in the cover layer 13 and the side edge 16, thereby generating cracks. In order to suppress the cracks, it is possible to suppress the diffusion of Cu. As a method of suppressing the diffusion of Cu, for example, a method of lowering the sintering temperature by adjusting the composition of the glass added to the conductive paste used to form the base layer 21 or adding a low melting point metal such as Sn can be considered.

[0089] However, when the sintering temperature is lowered to a level where cracks do not occur, the compactness of the base layer 21 is reduced, reliability cannot be ensured, and the bonding strength between the base layer 21 and the laminated sheet 10 is reduced. In addition, when cracks 40 occur in the portion covered by the external electrodes 20a and 20b, it cannot be confirmed from the appearance, which becomes a major technical problem.

[0090] Therefore, the multilayer ceramic capacitor 100 of the present embodiment has a structure capable of suppressing the occurrence of cracks due to the diffusion of Cu without excessively lowering the sintering temperature.

[0091] First, the internal electrode layer 12 and the base layer 21 contain a low melting point metal having a lower melting point than Cu which is the main component metal of the base layer 21. The low melting point metal is not particularly limited as long as it has a melting point lower than Cu, and examples thereof include Ga (gallium), In (indium), Sn, Bi (bismuth), Zn, Al, and the like.

[0092] In the internal electrode layer 12, the low melting point metal may be alloyed with Ni, which is the main component of the internal electrode layer 12, or may be configured as a single metal. For example, the low melting point metal may be uniformly dispersed in the internal electrode layer 12, or may be segregated at the interface between the internal electrode layer 12 and the dielectric layer 11.

[0093] In the base layer 21, the low melting point metal may be alloyed with Cu as the main component of the base layer 21, or may be configured as a single metal. For example, the low melting point metal may be uniformly dispersed in the base layer 21, or may be segregated at the interface between the base layer 21 and the laminated sheet 10.

[0094] In addition, the dimensions of the internal electrode layers 12 in the in-plane direction are varied. Specifically, Figure 6 As illustrated, the internal electrode layer 12 connected to the external electrode 20a has: a first region 121 (connection portion) connected to the external electrode 20a in a region corresponding to the end edge 15 and having a size W1 in the W direction; and a second region 122 having a size W2 in the W direction in a region corresponding to the capacitor portion 14. The size W1 is smaller than the size W2. In the W direction, the first region 121 is located at an inner side than the second region 122. In the internal electrode layer 12 connected to the external electrode 20b, the first region 121 having a size W1 and the second region 122 having a size W2 are also provided. For example, the center of the first region 121 in the W direction coincides with the center of the second region 122 in the W direction.

[0095] With this structure, even if a base layer 21 containing a low melting point metal such as Ga, In, Sn, Bi, Zn, Al, etc. is used to prevent the degradation of the insulation resistance caused by hydrogen generated in the plating process, or an internal electrode layer 12 containing a low melting point metal such as Ga, In, Sn, Bi, Zn, Al, etc. is used to change the potential barrier at the interface with the dielectric layer 11 to improve the high temperature load life, the moving distance from the base layer 21 to the internal electrode layer 12 at the corner is also increased, so that the diffusion from the base layer 21 to the internal electrode layer 12 can be suppressed. Thus, the generation of the crack 40 can be suppressed. According to the above content, even if the sintering treatment temperature is not excessively lowered, the generation of the crack can be suppressed. As a result, the density of the base layer 21 can be ensured.

[0096] When W1 / W2 is small, the connectivity between the external electrodes 20a, 20b and the internal electrode layer 12 is reduced, and good conduction may not be obtained. Therefore, it is preferable to set a lower limit for W1 / W2. On the other hand, when W1 / W2 is large, it may not be possible to make the moving distance from the external electrodes 20a, 20b to the internal electrode layer 12 sufficiently long. Therefore, it is preferable to set an upper limit for W1 / W2. According to the above content, W1 / W2 is preferably greater than 1 / 2, and more preferably greater than 2 / 3. In addition, W1 / W2 is preferably less than 4 / 5, and more preferably less than 3 / 4.

[0097] Here, if Figure 7 As shown in the example, the dimension of the external electrodes 20a and 20b extending in the L direction from both end surfaces of the laminated sheet 10 is referred to as dimension e. From the viewpoint of suppressing the crack 40 at the corner, the dimension of the first region 121 in the L direction is preferably 1 / 3 or more of dimension e, more preferably 1 / 2 or more.

[0098] When a sufficient amount of low-melting-point metal is not added to the base layer 21, it may not be possible to prevent the degradation of the insulation resistance caused by the hydrogen generated in the plating process. Therefore, it is preferable to set a lower limit on the addition concentration of the low-melting-point metal relative to the base layer 21. In the present embodiment, the addition concentration of the low-melting-point metal is preferably 1 at% or more, more preferably 3 at% or more, and further preferably 5 at% or more. In addition, the addition concentration of the low-melting-point metal is the addition amount (at%) of the low-melting-point metal when Cu is set to 100 at% in the entire base layer 21. In the case of containing multiple low-melting-point metals, the addition concentration of the low-melting-point metal is the total amount of the multiple low-melting-point metals.

[0099] On the other hand, when the amount of low melting point metal added to the base layer 21 is large, it may not be possible to sufficiently suppress the diffusion of Cu into the internal electrode layer 12. Therefore, it is preferable to set an upper limit on the addition concentration of the low melting point metal. In the present embodiment, the addition concentration of the low melting point metal is preferably 20 at% or less, more preferably 15 at% or less, and further preferably 10 at% or less.

[0100] When a sufficient amount of low-melting-point metal is not added to the internal electrode layer 12, the potential barrier change for improving the high-temperature load life may not be achieved. Therefore, it is preferred to set a lower limit on the addition concentration of the low-melting-point metal relative to the internal electrode layer 12. In the present embodiment, the addition concentration of the low-melting-point metal is preferably 0.1 at% or more, more preferably 0.3 at% or more, and further preferably 0.5 at% or more. In addition, the addition concentration of the low-melting-point metal is the addition amount (at%) of the low-melting-point metal when Ni is set to 100 at% in the entire internal electrode layer 12 between two adjacent dielectric layers 11. In the case of multiple low-melting-point metals, the addition concentration of the low-melting-point metal is the total amount of the multiple low-melting-point metals.

[0101] On the other hand, when the amount of low melting point metal added to the internal electrode layer 12 is large, spheroidization of the internal electrode and abnormal grain growth of the dielectric layer due to oversintering may occur. Therefore, it is preferable to set an upper limit on the addition concentration of the low melting point metal in the internal electrode layer 12. In the present embodiment, the addition concentration of the low melting point metal is preferably 10 at% or less, more preferably 5 at% or less, and further preferably 2 at% or less.

[0102] In the T direction, the stacking density of the internal electrode layers 12 is, for example, 500 layers / mm or more, 750 layers / mm or more, or 1000 layers / mm or more and 1500 layers / mm or less.

[0103] Next, a method for manufacturing the multilayer ceramic capacitor 100 according to the first embodiment will be described. Figure 8 2 is a diagram illustrating a flow of a method for manufacturing the multilayer ceramic capacitor 100 .

[0104] (Raw material powder production process)

[0105] First, a dielectric material for forming the dielectric layer 11 is prepared. The A-site element and the B-site element contained in the dielectric layer 11 are usually contained in the dielectric layer 11 in the form of a sintered body of ABO3 particles. For example, BaTiO3 is a tetragonal compound having a perovskite structure and exhibits a high dielectric constant. The BaTiO3 can usually be obtained by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate to synthesize barium titanate. Various methods have been known in the past for synthesizing ceramics as the main component of the dielectric layer 11, such as a solid phase method, a sol-gel method, a hydrothermal method, etc. In this embodiment, any of these methods can be used.

[0106] In the obtained ceramic powder, a predetermined additive compound may be added according to the purpose. As the additive compound, oxides of Mg, Mn, Mo, V, Cr, rare earth elements (Y, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm and Yb), or oxides containing Co, Ni, Li, B, Na, K or Si, or glasses containing Co, Ni, Li, B, Na, K or Si may be cited. Among them, SiO2 mainly acts as a sintering aid.

[0107] For example, a compound including an additive compound is wet-mixed with a ceramic raw material powder, and then dried and pulverized to prepare a ceramic material. For example, the ceramic material obtained as described above can be pulverized as needed to adjust the particle size, or can be combined with a classification process to adjust the particle size. Through the above process, a dielectric material is obtained.

[0108] (Lamination process)

[0109] Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol and toluene, and a plasticizer are added to the obtained raw material powder and wet mixed. The obtained slurry is used to apply a dielectric green sheet on a substrate by, for example, a die coating method or a doctor blade method and then dried. The substrate is, for example, a polyethylene terephthalate (PET) film.

[0110] Next, an internal electrode pattern is formed on the dielectric green sheet. The dielectric green sheet with the internal electrode pattern formed thereon is used as a stacking unit (stacked unit). The internal electrode pattern uses Ni powder containing a low melting point metal having a lower melting point than Cu. The film forming method may be printing, sputtering, vapor deposition, etc.

[0111] Next, the dielectric green sheet is peeled off from the substrate, and the stacking units are stacked. Next, a predetermined number (e.g., 2 to 10 layers) of cover sheets are stacked on top and bottom of the stacked body obtained by stacking the stacking units and thermally pressed. The cover sheets can be formed by the same method as the dielectric green sheet.

[0112] (Binder removal process)

[0113] The laminated body obtained as described above is subjected to a binder removal treatment in a N2 atmosphere. The heat treatment temperature is about 250°C to 700°C.

[0114] (Firing process)

[0115] Then, at an oxygen partial pressure of 10 -5 ~10 -8 The laminated sheet 10 is fired in a reducing atmosphere of 100 to 1300° C. for 10 minutes to 2 hours.

[0116] (Reoxidation treatment process)

[0117] Then, a reoxidation treatment may be performed at 600° C. to 1000° C. in a N 2 gas atmosphere.

[0118] (Coating process)

[0119] Next, a metal paste to be the base layer 21 is applied to the first side surface of the laminate by dipping or the like. The metal paste contains a glass component such as glass frit and a low melting point metal having a melting point lower than that of Cu.

[0120] (Sintering process)

[0121] Next, the metal paste is sintered at a temperature of about 700° C. to 900° C. to form the base layer 21 .

[0122] (Plating process)

[0123] Then, a metal coating such as copper, nickel, or tin may be applied to the base layer 21 by plating. For example, the first plating layer 23, the second plating layer 24, and the third plating layer 25 are sequentially formed on the base layer 21. Thus, the multilayer ceramic capacitor 100 is completed.

[0124] According to the manufacturing method of this embodiment, the moving distance from the base layer 21 to the internal electrode layer 12 at the corner is increased, so that the diffusion from the base layer 21 to the internal electrode layer 12 can be suppressed. As a result, the generation of the crack 40 can be suppressed. According to the above, even if the sintering temperature is not excessively lowered, the generation of the crack can be suppressed. As a result, the density of the base layer 21 can be ensured.

[0125] In the above-described manufacturing method, the base layer 21 is sintered after the laminated sheet 10 is fired, but the present invention is not limited thereto. For example, the base layer 21 may be fired simultaneously with the laminated sheet 10 being fired.

[0126] Here, the mounting of the multilayer ceramic capacitor 100 will be described. Fig. 91 is a side view of a circuit board 200 including a multilayer ceramic capacitor 100. The circuit board 200 has a mounting substrate 210 for mounting the multilayer ceramic capacitor 100. The mounting substrate 210 has: a base material 211 extending along a plane in the L direction and the W direction and having a mounting surface G perpendicular to the T direction; and a pair of connection electrodes 212 provided on the mounting surface G.

[0127] In the circuit board 200 , the external electrodes 20 a and 20 b of the multilayer ceramic capacitor 100 are connected to a pair of connection electrodes 212 of the mounting substrate 210 via solder H. Thus, in the circuit board 200 , the multilayer ceramic capacitor 100 is fixed to the mounting substrate 210 and electrically connected.

[0128] The multilayer ceramic capacitor 100 is prepared in a packaged state as a package body 300 when mounted on a mounting substrate 210 . Fig.10 and Fig.11 It is a figure which illustrates the package 300. Fig.10 It is a partial plan view of the packaging body 300. Fig.11 It is along Fig.10 A cross-sectional view of the package body 300 along the CC line.

[0129] Package 300 includes multilayer ceramic capacitor 100, carrier tape 310, and top tape 320. Carrier tape 310 is configured as a long strip extending in the W direction. Carrier tape 310 has a plurality of recesses 311 arranged at intervals in the W direction for accommodating multilayer ceramic capacitors 100 one by one.

[0130] Carrier tape 310 has sealing surface P which is an upward surface orthogonal to direction T, and a plurality of recesses 311 are recessed downward from sealing surface P in direction T. That is, carrier tape 310 is configured so that multilayer ceramic capacitors 100 in recesses 311 can be taken out from sealing surface P side.

[0131] In the carrier tape 310, a plurality of feed holes 312 are arranged in the W direction at intervals and penetrate in the T direction at positions offset from the rows of the plurality of recesses 311 in the L direction. The feed holes 312 are configured as engagement holes for the tape conveying mechanism to convey the carrier tape 310 in the W direction.

[0132] In package 300 , top tape 320 is attached to sealing surface P of carrier tape 310 along the rows of recesses 311 , and recesses 311 containing multilayer ceramic capacitors 100 are collectively covered by top tape 320 . Thus, multilayer ceramic capacitors 100 are held in recesses 311 .

[0133] like Fig.11As shown, in the multilayer ceramic capacitor 10 in the recess 311 of the carrier tape 310, the first main surface M1 of the multilayer sheet 10 facing upward in the T direction faces the top tape 320. In addition, the second main surface M2 of the multilayer sheet 10 facing downward in the T direction faces the bottom surface of the recess 311.

[0134] When installing the multilayer ceramic capacitor 100 packaged as package 300 , top tape 320 is peeled off from sealing surface P of carrier tape 310 in direction W. Thus, in package 300 , multiple recesses 311 containing multiple multilayer ceramic capacitors 100 can be opened sequentially in the T direction upward.

[0135] The multilayer ceramic capacitor 100 accommodated in the open recess 311 is taken out with the first main surface M1 of the multilayer sheet 10 facing upward in the T direction being sucked by the front end of the suction nozzle of the mounting device. The mounting device moves the multilayer ceramic capacitor 100 on the mounting surface G of the mounting substrate 210 by moving the suction nozzle.

[0136] Next, the mounting device positions the second main surface M2 of the laminated sheet 10 opposite to the mounting surface G, and releases the suction nozzle from the first main surface M1 of the laminated sheet 10 while the external electrodes 20a and 20b are aligned on the pair of connection electrodes 212 coated with solder paste. Thus, the laminated ceramic capacitor 100 is placed on the mounting surface G.

[0137] Then, the solder paste is melted and solidified in a reflow furnace or the like on the mounting substrate 210 with the multilayer ceramic capacitor 100 mounted on the mounting surface G. Thus, the external electrodes 20a and 20b are connected to the pair of connection electrodes 212 of the mounting substrate 210 via the solder H, thereby obtaining Fig. 9 The circuit board 200 is shown.

[0138] (Second embodiment)

[0139] Fig.12 (a) and Fig.12 (b) is a partial cross-sectional stereoscopic view of the multilayer ceramic capacitor 100a of the second embodiment. The multilayer ceramic capacitor 100a differs from the multilayer ceramic capacitor 100 of the first embodiment in the ratio of T0 / W0. In this embodiment, T0 / W0 is 1.3 times or more. In this structure, the number of stacked internal electrode layers 12 can be increased, so the electrostatic capacitance can be increased. From the viewpoint of increasing the electrostatic capacitance, T0 / W0 is preferably 1.5 times or more.

[0140] (Third embodiment)

[0141] Fig.13 (a) and Fig.13(b) is a partial cross-sectional perspective view of the multilayer ceramic capacitor 100b of the third embodiment. The multilayer ceramic capacitor 100b is different from the multilayer ceramic capacitor 100 of the first embodiment in that not all of the internal electrode layers 12 have the first region 121 and the second region 122, but a portion of the internal electrode layers 12 have the first region 121 and the second region 122. For example, Fig.13 (a) and Fig.13 As shown in (b), one or more internal electrode layers 12 from the outermost internal electrode layer 12 to the inner side have a first region 121 and a second region 122. The internal electrode layer 12 having the first region 121 and the second region 122 is referred to as the internal electrode layer 12 in the outer region. The internal electrode layer 12 which is closer to the inner side than the internal electrode layer 12 in the outer region and has a substantially constant dimension in the W direction is referred to as the internal electrode layer 12 in the inner region.

[0142] From the viewpoint of suppressing diffusion from the external electrodes 20a, 20b to the internal electrode layer 12, it is preferred that 10% or more of the internal electrode layers 12 in total relative to the total number of layers are the internal electrode layers 12 in the outer region, and it is more preferred that 25% or more of the internal electrode layers 12 in total are the internal electrode layers 12 in the outer region. On the other hand, from the viewpoint of reducing poor connection between the external electrodes 20a, 20b and the internal electrode layer 12, it is preferred that 50% or less of the internal electrode layers 12 in total relative to the total number of layers are the internal electrode layers 12 in the outer region, and it is more preferred that 40% or less of the internal electrode layers 12 in total are the internal electrode layers 12 in the outer region.

[0143] The number of internal electrode layers 12 in the outer region on one side in the T direction relative to the inner region is preferably the same as the number of internal electrode layers 12 in the outer region on the other side in the T direction relative to the inner region.

[0144] Furthermore, the electrostatic capacitance can be increased by increasing the number of stacked internal electrode layers 12. From the viewpoint of increasing the electrostatic capacitance, T0 / W0 is preferably 1.3 times or more, and more preferably 1.5 times or more.

[0145] The multilayer ceramic capacitor 100b of the present embodiment is, for example, Fig.14 As illustrated, it can be obtained by laminating a dielectric green sheet 51 on which the internal electrode patterns 52 a having the sizes W1 and W2 are formed, and a dielectric green sheet 51 on which the internal electrode patterns 52 having a constant size in the W direction are formed.

[0146] (Fourth embodiment)

[0147] Fig.15 (a) and Fig.15 (b) is a partial cross-sectional stereoscopic view of the laminated ceramic capacitor 100c of the fourth embodiment. The difference between the laminated ceramic capacitor 100c and the laminated ceramic capacitor 100 of the first embodiment lies in the stacking direction of the internal electrode layer 12. In the present embodiment, the W direction corresponds to the stacking direction of the internal electrode layer 12, and is the direction in which the upper surface and the lower surface of the laminate 10 are relative to each other. The T direction is the direction in which the two side surfaces of the laminate 10 are relative to each other. The L direction is the direction in which the two end surfaces of the laminate 10 are relative to each other. Therefore, in the present embodiment, the dimension W1 in the first embodiment can be replaced by the dimension T1 in the T direction, and the dimension W2 in the first embodiment can be replaced by the dimension T2 in the T direction.

[0148] When the multilayer ceramic capacitor 100 c is mounted on the mounting substrate 210 , one of the two side surfaces of the multilayer ceramic capacitor 100 c is opposed to the mounting substrate 210 .

[0149] It is known that in the multilayer ceramic capacitor 100c, when the circuit board 200 is driven, when a voltage is applied to the external electrodes 20a and 20b via the connection electrodes 212 of the mounting substrate 210, electrostriction occurs in the multilayer sheet 10 due to the piezoelectric effect. The electrostriction generated in the multilayer sheet 10 causes the internal electrode layers 12 to deform relatively greatly in the stacking direction.

[0150] In the circuit board 200, due to repeated electrostriction in the multilayer ceramic capacitor 100c to which an AC voltage is applied, vibration in the thickness direction may occur in the base material 211 of the mounting substrate 210. In the circuit board 200, when the vibration generated in the base material 211 increases, a phenomenon called "howling" occurs in which noise is generated from the base material 211.

[0151] However, in the multilayer ceramic capacitor 100c of the present embodiment, the stacking direction of the internal electrode layers 12 is in the in-plane direction of the substrate 211, so that it is difficult for the substrate 211 to vibrate in the thickness direction due to the electrostriction of the laminated sheet 10. In addition, in the multilayer ceramic capacitor 100d, the number of stacked internal electrode layers 12 is small, and the amount of deformation due to electrostriction is suppressed to be small. Therefore, even if vibration occurs in the substrate 211, it is difficult to become a large vibration that generates noise.

[0152] (Fifth embodiment)

[0153] Fig.16 (a) and Fig.16(b) is a partial cross-sectional perspective view of the multilayer ceramic capacitor 100d of the fifth embodiment. The multilayer ceramic capacitor 100d is different from the multilayer ceramic capacitor 100c of the fourth embodiment in that not all of the internal electrode layers 12 have the first region 121 and the second region 122, but a portion of the internal electrode layers 12 have the first region 121 and the second region 122. For example, Fig.13 (a) and Fig.13 As shown in (b), one or more internal electrode layers 12 from the outermost internal electrode layer 12 to the inner side have a first region 121 and a second region 122. The internal electrode layer 12 having the first region 121 and the second region 122 is referred to as the internal electrode layer 12 in the outer region. The internal electrode layer 12 which is closer to the inner side than the internal electrode layer 12 in the outer region and has a substantially constant dimension in the T direction is referred to as the internal electrode layer 12 in the inner region.

[0154] From the viewpoint of suppressing diffusion from the external electrodes 20a, 20b to the internal electrode layer 12, it is preferred that 10% or more of the internal electrode layers 12 in total relative to the total number of layers are the internal electrode layers 12 in the outer region, and it is more preferred that 25% or more of the internal electrode layers 12 in total are the internal electrode layers 12 in the outer region. On the other hand, from the viewpoint of reducing poor connection between the external electrodes 20a, 20b and the internal electrode layer 12, it is preferred that 50% or less of the internal electrode layers 12 in total relative to the total number of layers are the internal electrode layers 12 in the outer region, and it is more preferred that 40% or less of the internal electrode layers 12 in total are the internal electrode layers 12 in the outer region.

[0155] The number of internal electrode layers 12 in the outer region on the W direction side relative to the inner region is preferably the same as the number of internal electrode layers 12 in the outer region on the other side relative to the inner region in the W direction.

[0156] When the multilayer ceramic capacitor 100 d is mounted on the mounting substrate 210 , one of the two side surfaces of the multilayer ceramic capacitor 100 d is opposed to the mounting substrate 210 .

[0157] It is known that in the multilayer ceramic capacitor 100d, when the circuit board 200 is driven, when a voltage is applied to the external electrodes 20a and 20b via the connection electrodes 212 of the mounting substrate 210, electrostriction occurs in the multilayer sheet 10 due to the piezoelectric effect. The electrostriction generated in the multilayer sheet 10 causes the internal electrode layers 12 to deform relatively greatly in the stacking direction.

[0158] In the circuit board 200, due to repeated electrostriction in the multilayer ceramic capacitor 100d to which an AC voltage is applied, vibration in the thickness direction may occur in the base material 211 of the mounting substrate 210. In the circuit board 200, when the vibration generated in the base material 211 increases, a phenomenon called "howling" in which noise is generated from the base material 211 may occur.

[0159] However, in the multilayer ceramic capacitor 100d of the present embodiment, the stacking direction of the internal electrode layers 12 is in the in-plane direction of the substrate 211, so that it is difficult for the substrate 211 to vibrate in the thickness direction due to the electrostriction of the multilayer sheet 10. In addition, in the multilayer ceramic capacitor 100d, the number of stacked internal electrode layers 12 is small, and the amount of deformation due to electrostriction is suppressed to be small. Therefore, even if vibration occurs in the substrate 211, it is difficult to become a large vibration that generates noise.

[0160] (Sixth embodiment)

[0161] Fig.17 FIG. 1 is an external view of a multilayer ceramic capacitor 100 e according to a sixth embodiment. Fig.18 yes Fig.17 AA line cross-section diagram. Fig.19 yes Fig.17 BB line cross-section diagram. Figures 17 to 19 As shown in the example, the multilayer ceramic capacitor 100e includes: a multilayer sheet 10 having a substantially rectangular parallelepiped shape; and external electrodes 20a, 20b provided on any two opposite end surfaces of the multilayer sheet 10. In addition, the two surfaces at both ends of the stacking direction among the four surfaces other than the two end surfaces of the multilayer sheet 10 are called side surfaces. In the multilayer sheet 10, the two surfaces other than the two end surfaces and the two side surfaces are called the upper surface and the lower surface. The lower surface is a surface that functions as a mounting surface and is a surface that faces the mounting substrate when the multilayer ceramic capacitor 100e is mounted on the mounting substrate. The external electrodes 20a, 20b extend on the upper surface, the lower surface and the two side surfaces of the multilayer sheet 10. However, the external electrodes 20a and the external electrodes 20b are spaced apart from each other.

[0162] In addition, Figure 17 to Figure 19 In the figure, the T direction (first direction) is the height direction of the multilayer ceramic capacitor 100e, and is the direction in which the upper surface and the lower surface of the multilayer sheet 10 are opposite to each other. The W direction (second direction) is the stacking direction of the dielectric layer 11 and the internal electrode layer 12. The L direction (third direction) is the direction in which the two end surfaces of the multilayer sheet 10 are opposite to each other, and is the direction in which the external electrode 20a and the external electrode 20b are opposite to each other. The L direction, the W direction, and the T direction are orthogonal to each other.

[0163] The laminated sheet 10 has a structure in which dielectric layers 11 including ceramic materials that function as dielectrics and internal electrode layers 12 mainly composed of metals are alternately laminated. In other words, the laminated sheet 10 includes: a plurality of internal electrode layers 12 facing each other; and dielectric layers 11 sandwiched between the plurality of internal electrode layers 12. The end edges of the directions in which the internal electrode layers 12 extend are alternately exposed on the first end face of the laminated sheet 10 where the external electrode 20a is provided and the second end face where the external electrode 20b is provided. The internal electrode layer 12 connected to the external electrode 20a is not connected to the external electrode 20b. The internal electrode layer 12 connected to the external electrode 20b is not connected to the external electrode 20a. Therefore, each internal electrode layer 12 is alternately conductive with the external electrode 20a and the external electrode 20b. In addition, in the laminate of the dielectric layer 11 and the internal electrode layer 12, the internal electrode layer 12 is arranged at the uppermost layer in the lamination direction, and the internal electrode layer 12 is also arranged at the lowermost layer in the lamination direction, and the two side surfaces of the laminate are respectively covered by a cover layer 13. The cover layer 13 contains a ceramic material as a main component. For example, the main component of the cover layer 13 is the same as the main component of the dielectric layer 11.

[0164] The dielectric layer 11 is mainly composed of a ceramic material having a perovskite structure represented by the general formula ABO3. In addition, the perovskite structure contains ABO3 deviating from the stoichiometric composition. 3-α For example, as the ceramic material, BaTiO3 (barium titanate), CaZrO3 (calcium zirconate), CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), MgTiO3 (magnesium titanate), BaTiO3 (calcium titanate) and a perovskite structure can be used. 1-x-y Ca x Sr y Ti 1-z Zr z At least one of O3 (0≤x≤1, 0≤y≤1, 0≤z≤1), etc. 1-x- y Ca x Sr y Ti 1-z Zr z O3 is barium strontium titanate, barium calcium titanate, barium zirconate, barium titanate zirconate, calcium titanate zirconate and barium calcium titanate, etc.

[0165] Additives may be added to the dielectric layer 11. Examples of additives added to the dielectric layer 11 include oxides of magnesium (Mg), manganese (Mn), molybdenum (Mo), vanadium (V), chromium (Cr), rare earth elements (yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and ytterbium (Yb)), or oxides containing cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K), or silicon (Si), or glass containing Co, Ni, Li, B, Na, K, or Si.

[0166] The thickness of each dielectric layer 11 in the T direction is, for example, 0.3 μm or more and 3 μm or less. The thickness of each dielectric layer 11 in the T direction can be measured as follows: Fig.18 After the cross section is exposed, an average value of thickness at 10 locations is obtained by using an image taken with a microscope such as a scanning transmission electron microscope.

[0167] The internal electrode layer 12 contains Ni as a main component. The thickness of each internal electrode layer 12 in the T direction is, for example, 0.1 μm or more and 2 μm or less. The thickness of each internal electrode layer 12 in the T direction can be measured as follows: Fig.18 After the cross section is exposed, an average value of thickness at 10 locations is obtained by using an image taken with a microscope such as a scanning transmission electron microscope.

[0168] like Fig.18 As shown in the example, the region where the internal electrode layer 12 connected to the external electrode 20a and the internal electrode layer 12 connected to the external electrode 20b face each other is a region where electrostatic capacitance is generated in the multilayer ceramic capacitor 100e. Therefore, the region where electrostatic capacitance is generated is called a capacitor portion 14. That is, the capacitor portion 14 is a region where adjacent internal electrode layers connected to different external electrodes face each other.

[0169] The region where the internal electrode layers 12 connected to the external electrode 20a are opposite to each other without being separated by the internal electrode layer 12 connected to the external electrode 20b is called the end edge 15. In addition, the region where the internal electrode layers 12 connected to the external electrode 20b are opposite to each other without being separated by the internal electrode layer 12 connected to the external electrode 20a is also the end edge 15. That is, the end edge is a region where the internal electrode layers connected to the same external electrode are opposite to each other without being separated by the internal electrode layers connected to different external electrodes. The end edge 15 is a region where electrostatic capacitance is not generated. The end edge 15 can be the same composition as the dielectric layer 11 of the capacitor part 14, or it can be a composition different from the dielectric layer 11 of the capacitor part 14.

[0170] like Fig.19 As illustrated, in the laminated sheet 10, the region from the upper surface to the internal electrode layer 12 in the T direction and the region from the lower surface to the internal electrode layer 12 in the T direction are referred to as the side edge 16. That is, the side edge 16 is an area provided in a manner that covers the ends of the plurality of internal electrode layers 12 stacked in the above-mentioned stacked structure extending to the upper surface side and the lower surface side. The side edge 16 is also an area where electrostatic capacitance is not generated. The side edge 16 can be the same composition as the dielectric layer 11 of the capacitor section 14, or it can be a composition different from the dielectric layer 11 of the capacitor section 14.

[0171] Fig. 20 is an enlarged cross-sectional view of the vicinity of the external electrode 20a. Fig. 20 In the figure, hatching is omitted. Fig. 20 As illustrated, the external electrode 20a has a structure in which a plating layer 22 is provided on a base layer 21. The base layer 21 has Cu as a main component. The base layer 21 may also contain a glass component. The plating layer 22 has a metal such as Ni, aluminum (Al), zinc (Zn), Sn, or an alloy of two or more thereof as a main component. The plating layer 22 may be a plating layer of a single metal component, or may be a plurality of plating layers of metal components different from each other. For example, the plating layer 22 has a structure in which a first plating layer 23, a second plating layer 24, and a third plating layer 25 are formed in sequence from the base layer 21 side. The first plating layer 23 is, for example, a Sn plating layer. The second plating layer 24 is, for example, a Ni plating layer. The third plating layer 25 is, for example, a Sn plating layer. In addition, in Fig. 20 In FIG. 1 , the external electrode 20 a is illustrated, but the external electrode 20 b also has the same stacked structure.

[0172] When a multilayer ceramic capacitor with large capacitance is to be realized, it is important to increase the total relative area of ​​the internal electrode layers. In order to realize a large capacitance without increasing the mounting area, it is possible to increase the number of internal electrode layers. For example, Fig.21 As shown in the example, the number of internal electrode layers 12 stacked is increased while suppressing the increase in the area of ​​each internal electrode layer 12. By forming such a structure, the total relative area of ​​the internal electrode layer 12 is increased, so it is considered that a large capacitance can be achieved. However, when the number of stacked layers is large, positional deviation is likely to occur during stacking, and it is difficult to cut the stacked body before firing perpendicularly to the stacking direction.

[0173] Therefore, the multilayer ceramic capacitor 100e of the present embodiment has a structure in which the area of ​​each internal electrode layer is increased and the number of layers stacked is reduced. Fig.17As shown in the example, when the height in the T direction of the multilayer ceramic capacitor 100e is set to height T0, the width in the W direction is set to width W0, and the length in the L direction is set to length L0, the multilayer ceramic capacitor 100e has a relationship of T0 ≥ W0 × 1.3. By forming such a structure, the width of the internal electrode layer 12 can be increased, and on the other hand, the number of stacked internal electrode layers 12 can be suppressed, so that the positional deviation during stacking can be suppressed, and the pre-fired stack can be cut perpendicular to the stacking direction. In addition, the height T0, the width W0, and the length L0 are the maximum dimensions in the T direction, the W direction, and the L direction, respectively.

[0174] However, when the height of the internal electrode layer 12 in the T direction increases, even if a debinding process is performed to remove the organic binder contained in the laminate before firing, the discharge path of the binder becomes longer, so the binder may not be fully removed. Fig. 22 As exemplified above, decomposition gas of the binder remains inside the laminate, which may cause cracks (binder removal cracks) and layer separation.

[0175] Therefore, the multilayer ceramic capacitor 100 e of the present embodiment has a structure that can achieve good binder removal characteristics even in a structure where the relationship T0 ≥ W0 × 1.3 holds.

[0176] Specifically, a low melting point metal having a melting point lower than that of Cu, which is the main component of the base layer 21, is present inside the internal electrode layer 12 or at the interface between the internal electrode layer 12 and the dielectric layer 11. The low melting point metal is not particularly limited as long as it has a melting point lower than that of Cu, and may be, for example, Ga (gallium), In (indium), Sn, Bi (bismuth), Pb (lead), Zn, etc. The low melting point metal may be alloyed with Ni, which is the main component of the internal electrode layer 12, or may be configured as a single metal. For example, the low melting point metal may be uniformly dispersed in the internal electrode layer 12, or may be segregated at the interface between the internal electrode layer 12 and the dielectric layer 11.

[0177] By having a low melting point metal inside the internal electrode layer 12 or at the interface between the internal electrode layer 12 and the dielectric layer 11, the discharge start temperature of the adhesive becomes lower during the heat treatment of the adhesive removal process compared to the case where there is no low melting point metal. As a result, good adhesive removal properties can be achieved, and cracks and layer separation can be suppressed. It is believed that the adhesive discharge start temperature becomes lower because the low melting point metal melts at the adhesive discharge temperature, thereby playing a role in making the adhesive easy to discharge.

[0178] When a sufficient amount of low-melting-point metal is not added, sufficiently good debonding properties may not be obtained. Therefore, it is preferred to set a lower limit for the addition concentration of the low-melting-point metal. In the present embodiment, the addition concentration of the low-melting-point metal is preferably 0.1 at% or more, more preferably 0.3 at% or more, and further preferably 0.5 at% or more. In addition, the addition concentration of the low-melting-point metal is the addition amount (at%) of the low-melting-point metal when the Ni of the internal electrode layer 12 is set to 100 at% in the entire 1 layer of internal electrode layer 12 sandwiched by 2 adjacent dielectric layers. In the case of multiple low-melting-point metals, the addition concentration of the low-melting-point metal is the total amount of the multiple low-melting-point metals.

[0179] On the other hand, when the amount of low melting point metal added is large, it is possible to cause spheroidization of the internal electrode and abnormal grain growth of the dielectric layer due to over-sintering. Therefore, it is preferable to set an upper limit on the addition concentration of the low melting point metal. In this embodiment, the addition concentration of the low melting point metal is preferably 10at% or less, more preferably 5at% or less, and further preferably 2at% or less.

[0180] The height T0, width W0 and length L0 are not particularly limited. For example, the height T0 may be 0.15 mm to 1.0 mm, the width W0 may be 0.1 mm to 0.7 mm, and the length L0 may be 0.2 mm to 1.2 mm.

[0181] In the W direction, the stacking density of the internal electrode layers 12 is, for example, 500 layers / mm or more, 750 layers / mm or more, or 1000 layers / mm or more and 1500 layers / mm or less.

[0182] In order to achieve a high capacity, T0 is preferably 1.5 times or more, more preferably 2.0 times or more, of W0.

[0183] The maximum height of the internal electrode layer 12 in the T direction is assumed to be height T a , let the maximum width in the W direction be the width W a When, for example, T a W a The ratio of the height in the T direction to the width in the W direction of the capacitor portion 14 (T / W ratio) is, for example, 1.3 times or more, 1.5 times or more, or 2.0 times or more.

[0184] Next, a method for manufacturing the multilayer ceramic capacitor 100 e according to the sixth embodiment will be described. Fig.23 1 is a diagram illustrating the flow of a method for manufacturing the multilayer ceramic capacitor 100 e .

[0185] (Raw material powder production process)

[0186] First, a dielectric material for forming the dielectric layer 11 is prepared. The A-site element and the B-site element contained in the dielectric layer 11 are usually contained in the dielectric layer 11 in the form of a sintered body of ABO3 particles. For example, BaTiO3 is a tetragonal compound having a perovskite structure and exhibits a high dielectric constant. The BaTiO3 can usually be obtained by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate to synthesize barium titanate. Various methods have been known in the past for synthesizing ceramics as the main component of the dielectric layer 11, such as a solid phase method, a sol-gel method, a hydrothermal method, etc. In this embodiment, any of these methods can be used.

[0187] In the obtained ceramic powder, a predetermined additive compound may be added according to the purpose. As the additive compound, oxides of Mg, Mn, Mo, V, Cr, rare earth elements (Y, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm and Yb), or oxides containing Co, Ni, Li, B, Na, K or Si, or glasses containing Co, Ni, Li, B, Na, K or Si may be cited. Among them, SiO2 mainly acts as a sintering aid.

[0188] For example, a compound including an additive compound is wet-mixed with a ceramic raw material powder, and then dried and pulverized to prepare a ceramic material. For example, the ceramic material obtained as described above can be pulverized as needed to adjust the particle size, or can be combined with a classification process to adjust the particle size. Through the above process, a dielectric material is obtained.

[0189] (Lamination process)

[0190] Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol and toluene, and a plasticizer are added to the obtained raw material powder and wet mixed. The obtained slurry is used to apply a dielectric green sheet on a substrate by, for example, a die coating method or a doctor blade method and then dried. The substrate is, for example, a polyethylene terephthalate (PET) film.

[0191] Then, if Fig.24 As shown in the example, an internal electrode pattern 52 is formed on a dielectric green sheet 51. The dielectric green sheet 51 on which the internal electrode pattern 52 is formed is used as a stacking unit (stacking unit). The internal electrode pattern 52 uses Ni powder containing a low melting point metal having a lower melting point than Cu. The film forming method may be printing, sputtering, vapor deposition, etc.

[0192] Next, the dielectric green sheet 51 is peeled off from the substrate, and Fig.24Next, a predetermined number (eg, 2 to 10 layers) of cover sheets 53 are stacked on top and bottom of the stacked body obtained by stacking the stacked units and thermocompression bonded. The cover sheet 53 can be formed by the same method as the dielectric green sheet 51 .

[0193] (Binder removal process)

[0194] The laminated body obtained as described above is subjected to a binder removal treatment in a N2 atmosphere. The heat treatment temperature is about 250°C to 700°C, and the heat treatment time is about 5 minutes to 1 hour.

[0195] (Firing process)

[0196] Then, at an oxygen partial pressure of 10 -5 ~10 -8 The laminated sheet 10 is fired in a reducing atmosphere of 100° C. to 1300° C. for 10 minutes to 2 hours.

[0197] (Reoxidation treatment process)

[0198] Then, a reoxidation treatment may be performed at 600° C. to 1000° C. in a N 2 gas atmosphere.

[0199] (Coating process)

[0200] Next, a metal paste to be the base layer 21 is applied to the first side surface of the laminate by dipping or the like. The metal paste contains a glass component such as glass frit.

[0201] (Sintering process)

[0202] Next, the metal paste is sintered at a temperature of about 700° C. to 900° C. to form the base layer 21 .

[0203] (Plating process)

[0204] Then, a metal coating such as copper, nickel, or tin may be applied to the base layer 21 by plating. For example, the first plating layer 23, the second plating layer 24, and the third plating layer 25 are sequentially formed on the base layer 21. Thus, the multilayer ceramic capacitor 100e is completed.

[0205] According to the manufacturing method of this embodiment, a low melting point metal is added to the internal electrode pattern 52. By adding the low melting point metal, the temperature at which the binder is discharged becomes lower during the heat treatment in the binder removal process than when the low melting point metal is not added. Thus, good binder removal characteristics can be achieved, and cracks and layer separation can be suppressed.

[0206] In the above-described manufacturing method, the base layer 21 is sintered after the laminated sheet 10 is fired, but the present invention is not limited thereto. For example, the base layer 21 may be fired simultaneously with the laminated sheet 10 being fired.

[0207] Here, the mounting of the multilayer ceramic capacitor 100e will be described. Fig.25 1 is a side view of a circuit board 200 including a multilayer ceramic capacitor 100e. The circuit board 200 has a mounting substrate 210 for mounting the multilayer ceramic capacitor 100e. The mounting substrate 210 has: a base material 211 extending along a plane in the L direction and the W direction, having a mounting surface G perpendicular to the T direction; and a pair of connection electrodes 212 provided on the mounting surface G.

[0208] In the wiring board 200 , the external electrodes 20 a and 20 b of the multilayer ceramic capacitor 100 e are connected to a pair of connection electrodes 212 of the mounting substrate 210 via solder H. Thus, in the wiring board 200 , the multilayer ceramic capacitor 100 e is fixed to the mounting substrate 210 and electrically connected.

[0209] Here, it is known that in the multilayer ceramic capacitor 100e, when the circuit board 200 is driven, when a voltage is applied to the external electrodes 20a and 20b via the connection electrodes 212 of the mounting substrate 210, electrostriction occurs in the multilayer sheet 10 due to the piezoelectric effect. The electrostriction generated in the multilayer sheet 10 causes the internal electrode layers 12 to deform relatively greatly in the stacking direction.

[0210] In the circuit board 200, due to repeated electrostriction in the multilayer ceramic capacitor 100e to which an AC voltage is applied, vibration in the thickness direction may occur in the base material 211 of the mounting substrate 210. In the circuit board 200, when the vibration generated in the base material 211 becomes larger, a phenomenon called "howling" in which noise is generated from the base material 211 may occur.

[0211] However, in the multilayer ceramic capacitor 100e of the present embodiment, the stacking direction of the internal electrode layers 12 is in the in-plane direction of the substrate 211, so it is difficult for the substrate 211 to vibrate in the thickness direction due to the electrostriction of the multilayer sheet 10. In addition, in the multilayer ceramic capacitor 100e, the number of stacked internal electrode layers 12 is small, and the amount of deformation due to electrostriction is suppressed to be small. Therefore, even if vibration occurs in the substrate 211, it is difficult to become a large vibration that generates noise.

[0212] The multilayer ceramic capacitor 100 e is prepared in a packaged state as a package body 300 when mounted on a mounting substrate 210 . Fig.26 and Fig. 27 It is a figure which illustrates the package 300. Fig.26It is a partial plan view of the packaging body 300. Fig. 27 It is along Fig.26 A cross-sectional view of the package body 300 of the DD line.

[0213] Package 300 includes multilayer ceramic capacitor 100e, carrier tape 310, and top tape 320. Carrier tape 310 is configured as a long strip extending in the W direction. Carrier tape 310 has a plurality of recesses 311 arranged at intervals in the W direction for accommodating multilayer ceramic capacitors 100e one by one.

[0214] Carrier tape 310 has sealing surface P which is an upward surface orthogonal to direction T, and a plurality of recesses 311 are recessed downward from sealing surface P in direction T. That is, carrier tape 310 is configured so that multilayer ceramic capacitors 100e in recesses 311 can be taken out from sealing surface P side.

[0215] In the carrier tape 310, a plurality of feed holes 312 are arranged in the W direction at intervals and penetrate in the T direction at positions offset from the rows of the plurality of recesses 311 in the L direction. The feed holes 312 are configured as engagement holes for the tape conveying mechanism to convey the carrier tape 310 in the W direction.

[0216] In the package 300 , the top tape 320 is attached to the sealing surface P of the carrier tape 310 along the row of the plurality of recesses 311 , and the plurality of recesses 311 containing the plurality of multilayer ceramic capacitors 100 e are collectively covered by the top tape 320 . Thus, the plurality of multilayer ceramic capacitors 100 e are held in the plurality of recesses 311 .

[0217] like Fig. 27 As shown, in the multilayer ceramic capacitor 100e in the recess 311 of the carrier tape 310, the first main surface M1 of the laminated sheet 10 facing upward in the T direction faces the top tape 320. The second main surface M2 of the laminated sheet 10 facing downward in the T direction faces the bottom surface of the recess 311.

[0218] When installing the multilayer ceramic capacitor 100e packaged as the package 300, the top tape 320 is peeled off from the sealing surface P of the carrier tape 310 in the W direction. Thus, in the package 300, the plurality of recesses 311 containing the plurality of multilayer ceramic capacitors 100e can be opened sequentially in the T direction upward.

[0219] The multilayer ceramic capacitor 100e housed in the open recess 311 is taken out with the first main surface M1 of the multilayer sheet 10 facing upward in the T direction being sucked onto the front end of the suction nozzle of the mounting device. The mounting device moves the suction nozzle to move the multilayer ceramic capacitor 100e onto the mounting surface G of the mounting substrate 210.

[0220] Next, the mounting device positions the second main surface M2 of the laminated sheet 10 opposite to the mounting surface G, and releases the suction nozzle from the first main surface M1 of the laminated sheet 10 while the external electrodes 20a and 20b are aligned on the pair of connection electrodes 212 coated with solder paste. Thus, the laminated ceramic capacitor 100e is mounted on the mounting surface G.

[0221] Then, the solder paste is melted and solidified in a reflow furnace or the like on the mounting substrate 210 with the multilayer ceramic capacitor 100e mounted on the mounting surface G. Thus, the external electrodes 20a and 20b are connected to the pair of connection electrodes 212 of the mounting substrate 210 via the solder H, thereby obtaining Fig.25 The circuit board 200 is shown.

[0222] (Seventh Implementation Method)

[0223] In the cross section in the W direction and the T direction at the position of the external electrodes 20a and 20b, when the diffusion from the external electrodes 20a and 20b to the internal electrode layer 12 is excessive, as shown in FIG. Fig.28 As shown in the example, cracks 40 may be generated at the corners near the external electrodes. In particular, when the main component metal of the base layer 21 is Cu and the main component metal of the internal electrode layer 12 is Ni, diffusion is likely to occur. In addition, when the low melting point metal as described above is arranged in the internal electrode layer 12 or at the interface between the internal electrode layer 12 and the dielectric layer 11, diffusion from the base layer 21 may be promoted when the base layer 21 is formed. In addition, Fig.28 is equivalent to Fig.17 Figure 2. CC line cross section of the .

[0224] Therefore, in the multilayer ceramic capacitor 100f of the seventh embodiment, the dimensions of the internal electrode layers 12 in the T direction are varied. Fig.29 As shown in the example, the internal electrode layer 12 connected to the external electrode 20a has: a first region 121 (connection portion) connected to the external electrode 20a in the region corresponding to the end edge 15 and having a dimension T1 in the T direction; and a second region 122 having a dimension T2 in the T direction in the region corresponding to the capacitor portion 14. The dimension T1 is lower than the dimension T2. ​​In the T direction, the first region 121 is located at an inner side than the second region 122. With this structure, the moving distance from the external electrodes 20a and 20b to the internal electrode layer 12 at the corner becomes longer, so that the diffusion from the external electrodes 20a and 20b to the internal electrode layer 12 can be suppressed. As a result, the generation of the crack 40 can be suppressed. In the internal electrode layer 12 connected to the external electrode 20b, the first region 121 having the dimension T1 and the second region 122 having the dimension T2 are also provided.

[0225] For example, when T1 / T2 is small, the connectivity between the external electrodes 20a, 20b and the internal electrode layer 12 is reduced, and good conduction may not be obtained. Therefore, it is preferable to set a lower limit for T1 / T2. On the other hand, when T1 / T2 is large, it may not be possible to make the moving distance from the external electrodes 20a, 20b to the internal electrode layer 12 sufficiently long. Therefore, it is preferable to set an upper limit for T1 / T2. According to the above content, T1 / T2 is preferably greater than 1 / 2, and more preferably greater than 2 / 3. In addition, T1 / T2 is preferably less than 4 / 5, and more preferably less than 3 / 4.

[0226] Here, if Fig.30 As shown in the example, the dimension of the external electrodes 20a and 20b extending in the L direction from both end surfaces of the laminated sheet 10 is referred to as dimension e. From the viewpoint of suppressing the crack 40 at the corner, the dimension of the first region 121 in the L direction is preferably 1 / 3 or more of dimension e, more preferably 1 / 2 or more.

[0227] The multilayer ceramic capacitor 100f of the present embodiment is, for example, Fig.31 As illustrated, it can be obtained by stacking dielectric green sheets 51 on which internal electrode patterns 52 a having dimensions T1 and T2 are formed.

[0228] (Eighth Implementation Method)

[0229] In the seventh embodiment, all the internal electrode layers 12 have the first region 121 and the second region 122, but a part of the internal electrode layers 12 may have the first region 121 and the second region 122. For example, Fig.32 As illustrated, it is preferred that one or more internal electrode layers 12 from the outermost internal electrode layer 12 to the inner side have the first region 121 and the second region 122. The internal electrode layer 12 having the first region 121 and the second region 122 is referred to as the internal electrode layer 12 in the outer region. The internal electrode layer 12 which is closer to the inner side than the internal electrode layer 12 in the outer region and has a substantially constant height in the T direction is referred to as the internal electrode layer 12 in the inner region.

[0230] From the viewpoint of suppressing diffusion from the external electrodes 20a, 20b to the internal electrode layer 12, it is preferred that 10% or more of the internal electrode layers 12 in total relative to the total number of layers are the internal electrode layers 12 in the outer region, and it is more preferred that 25% or more of the internal electrode layers 12 in total are the internal electrode layers 12 in the outer region. On the other hand, from the viewpoint of reducing poor connection between the external electrodes 20a, 20b and the internal electrode layer 12, it is preferred that 50% or less of the internal electrode layers 12 in total relative to the total number of layers are the internal electrode layers 12 in the outer region, and it is more preferred that 40% or less of the internal electrode layers 12 in total are the internal electrode layers 12 in the outer region.

[0231] The number of internal electrode layers 12 in the outer region on the W direction side relative to the inner region is preferably the same as the number of internal electrode layers 12 in the outer region on the other side relative to the inner region in the W direction.

[0232] The multilayer ceramic capacitor 100g of the present embodiment is, for example, Fig.33 As illustrated, it can be obtained by laminating a dielectric green sheet 51 on which the internal electrode patterns 52 a having the dimensions T1 and T2 are formed, and a dielectric green sheet 51 on which the internal electrode patterns 52 having a constant dimension in the T direction are formed.

[0233] In addition, in the above-mentioned embodiments, a multilayer ceramic capacitor is described as an example of a ceramic electronic component, but the present invention is not limited thereto. For example, the configuration of the above-mentioned embodiments can also be applied to other multilayer ceramic electronic components such as a varistor and a thermistor.

[0234] [Example]

[0235] Next, a multilayer ceramic capacitor according to each embodiment was produced and its characteristics were examined.

[0236] (Example 1)

[0237] In Example 1, a laminated ceramic capacitor described in the first embodiment was produced. First, a slurry containing BaTiO3 as a main component was prepared and coated to obtain a dielectric green sheet. An internal electrode pattern was printed on each dielectric green sheet. Nickel powder was used for the internal electrode pattern, and Sn powder was added. The added concentration of Sn relative to Ni was 1.0 at%. 250 layers of the obtained laminated units were laminated to obtain a laminate.

[0238] A slurry with BaTiO3 as the main component is prepared and applied to obtain a covering sheet. Multiple covering sheets are stacked and pressed on the upper and lower sides of the stacking direction of the above-mentioned stacked body, and then a debonding process is performed. Then, it is fired and reoxidized. A metal paste with Cu as the main component is applied to the two end faces of the obtained stacked sheet, and a sintering process is performed at about 800°C. After these processes, a stacked ceramic capacitor with 250 internal electrode layers is produced with a length L0: 0.6mm, a width W0: 0.3mm, and a height T0: 0.3mm.

[0239] In the fired multilayer ceramic capacitor, the thickness of each internal electrode layer in the T direction is 0.5 μm, and the thickness of each dielectric layer in the T direction is 0.5 μm. The thickness of each cover layer in the T direction is 25 μm. The thickness of each side edge in the W direction is 25 μm. In each internal electrode layer, the dimension W2 in the W direction is increased in the capacitor part, and the dimension W1 in the W direction is smaller than W2 at the end edge. The dimension W2 of the internal electrode layer in the capacitor part is 250 μm, and the dimension W1 of the internal electrode layer in the end edge is 150 μm. The length of each end edge in the L direction is 15 μm. The dimension e of each external electrode extending in the L direction from the two end faces of the laminate is 20 μm.

[0240] (Example 2-1)

[0241] In Example 2-1, the multilayer ceramic capacitor described in the second embodiment was produced. The number of internal electrode layers stacked was 350. The length L0 was 0.6 mm, the width W0 was 0.3 mm, and the height T0 was 0.4 mm. Other conditions were the same as in Example 1.

[0242] (Example 2-2)

[0243] In Example 2-2, the multilayer ceramic capacitor described in the second embodiment was produced. The number of internal electrode layers stacked was 450. The length L0 was 0.6 mm, the width W0 was 0.3 mm, and the height T0 was 0.5 mm. Other conditions were the same as those in Example 1.

[0244] (Example 3)

[0245] In Example 3, a stacked ceramic capacitor described in the third embodiment is produced. The number of stacked internal electrode layers is 450. The length L0 is 0.6 mm, the width W0 is 0.3 mm, and the height T0 is 0.5 mm. In each of the 50 internal electrode layers in the outer region, the dimension W2 in the W direction is increased in the capacitor portion, and the dimension W1 in the W direction is smaller than W2 at the end edge. The dimension W2 of the internal electrode layer in the capacitor portion is 250 μm, and the dimension W1 of the internal electrode layer in the end edge is 150 μm. In each of the 350 internal electrode layers in the inner region, the dimension of the internal electrode layer in the W direction in the capacitor portion and the dimension of the internal electrode layer in the W direction at the end edge are 250 μm. Other conditions are the same as in Example 1.

[0246] (Example 4-1)

[0247] In Example 4-1, a multilayer ceramic capacitor described in the fourth embodiment is produced. The number of internal electrode layers stacked is 250. In the fired multilayer ceramic capacitor, the length L0 is 0.6 mm, the width W0 is 0.3 mm, and the height T0 is 0.5 mm. The thickness of each internal electrode layer in the W direction is 0.5 μm, and the thickness of each dielectric layer in the W direction is 0.5 μm. The thickness of each covering layer in the W direction is 25 μm. The thickness of each side edge in the T direction is 25 μm. In each internal electrode layer, the dimension T2 in the T direction is increased in the capacitor part, and the dimension T1 in the T direction is smaller than T2 at the end edge. The dimension T2 of the internal electrode layer in the capacitor part is 450 μm, and the dimension T1 of the internal electrode layer in the end edge is 300 μm. The length of each end edge in the L direction is 15 μm. The dimension e of each external electrode extending in the L direction from the two end faces of the laminate is 20 μm.

[0248] (Example 4-2)

[0249] In Example 4-2, a multilayer ceramic capacitor described in the fourth embodiment is produced. The number of internal electrode layers stacked is 250. In the fired multilayer ceramic capacitor, the length L0 is 0.6 mm, the width W0 is 0.3 mm, and the height T0 is 0.4 mm. The thickness of each internal electrode layer in the W direction is 0.5 μm, and the thickness of each dielectric layer in the W direction is 0.5 μm. The thickness of each covering layer in the W direction is 25 μm. The thickness of each side edge in the T direction is 25 μm. In each internal electrode layer, the dimension T2 in the T direction is increased in the capacitor part, and the dimension T1 in the T direction is smaller than T2 at the end edge. The dimension T2 of the internal electrode layer in the capacitor part is 350 μm, and the dimension T1 of the internal electrode layer in the end edge is 250 μm. The length of each end edge in the L direction is 15 μm. The dimension e of each external electrode extending in the L direction from the two end faces of the laminate is 20 μm.

[0250] (Example 5)

[0251] In Example 5, a multilayer ceramic capacitor described in the fifth embodiment is produced. In each of the 50 layers of internal electrode layers in the outer region, the dimension T2 in the T direction is increased in the capacitor portion, and the dimension T1 in the T direction is smaller than T2 in the end edge. The dimension T2 of the internal electrode layer in the capacitor portion is 450 μm, and the dimension T1 of the internal electrode layer in the end edge is 300 μm. In each of the 150 layers of internal electrode layers in the inner region, the dimension of the internal electrode layer in the T direction in the capacitor portion and the dimension of the internal electrode layer in the T direction in the end edge are 450 μm. Other conditions are the same as those in Example 4.

[0252] Table 1 shows the conditions of Examples 1 to 5 and Comparative Examples 1 and 2.

[0253] [Table 1]

[0254]

[0255] For Comparative Examples 1 and 2 and Examples 1 to 5, 100 samples were prepared respectively. In Examples 1 to 5, no cracks were confirmed. No cracks were confirmed, which is considered to be because, in the internal electrode layers of more than one layer from the outermost layer among the multiple internal electrode layers, the width of the connection portion connected to the external electrode is narrower than the width of other regions, so that the moving distance from the base layer to the internal electrode layer at the corner becomes longer, and the diffusion from the base layer to the internal electrode layer is suppressed. In Comparative Examples 1 and 2, cracks were confirmed. Cracks were confirmed, which is considered to be because the moving distance from the base layer to the internal electrode layer at the corner becomes shorter, which promotes the diffusion from the base layer to the internal electrode layer.

[0256] [Table 2]

[0257] Whether there are cracks Example 1 none Example 2-1 none Example 2-2 none Example 3 none Example 4-1 none Example 4-2 none Example 5 none Comparative Example 1 have Comparative Example 2 have

[0258] (Example 6)

[0259] In Example 6, a laminated ceramic capacitor described in the sixth embodiment was produced. First, a slurry containing BaTiO3 as a main component was prepared and coated to obtain a dielectric green sheet. An internal electrode pattern was printed on each dielectric green sheet. Nickel powder was used for the internal electrode pattern, and Sn powder was added. The added concentration of Sn relative to Ni was 1.0 at%. In the T direction, the height of each internal electrode pattern was made lower than the height of the dielectric green sheet. 250 layers of the obtained stacking unit were stacked to obtain a stacked body.

[0260] A slurry with BaTiO3 as the main component is prepared and applied to obtain a covering sheet. Multiple covering sheets are stacked and pressed on the upper and lower sides of the stacking direction of the above-mentioned stacked body, and then roller grinding is performed to remove the binder. Then, firing and reoxidation treatment are performed. A metal paste with Cu as the main component is applied to the two end surfaces of the obtained stacked sheet, and sintering treatment is performed at about 800°C. After these steps, a stacked ceramic capacitor with 250 internal electrode layers stacked is produced with a length L0: 0.6mm, a width W0: 0.3mm, and a height T0: 0.5mm.

[0261] In the fired laminated ceramic capacitor, the thickness of each internal electrode layer in the W direction is 0.5 μm, and the thickness of each dielectric layer in the W direction is 0.5 μm. The thickness of each cover layer in the W direction is 25 μm. The thickness of each side edge in the T direction is 25 μm. The dimension of each internal electrode layer in the T direction (T1=T2) is 450 μm. The length of each end edge in the L direction is 40 μm.

[0262] (Example 7)

[0263] In Example 7, the multilayer ceramic capacitor described in the seventh embodiment was produced. In each internal electrode layer, the dimension T2 in the T direction was increased in the capacitor portion, and the dimension T1 in the T direction was smaller than T2 at the end edge. The dimension T2 of the internal electrode layer in the capacitor portion was 450 μm, and the dimension T1 of the internal electrode layer at the end edge was 300 μm. Other conditions were the same as those in Example 6.

[0264] (Example 8)

[0265] In Example 8, a multilayer ceramic capacitor described in the eighth embodiment is produced. In each of the 50 layers of internal electrode layers in the outer region, the dimension T2 in the T direction is increased in the capacitor portion, and the dimension T1 in the T direction is smaller than T2 at the end edge. The dimension T2 of the internal electrode layer in the capacitor portion is 450 μm, and the dimension T1 of the internal electrode layer in the end edge is 300 μm. In each of the 150 layers of internal electrode layers in the inner region, the dimension T2 of the internal electrode layer in the capacitor portion and the dimension T1 of the internal electrode layer in the end edge are 450 μm. Other conditions are the same as those in Example 6.

[0266] (Example 9)

[0267] In Example 9, the printing width of the internal electrode pattern of Example 6 was changed so that the dimension of each internal electrode layer in the T direction became 350 μm, and a laminated ceramic capacitor having 250 internal electrode layers was manufactured with a length L0 of 0.6 mm, a width W0 of 0.3 mm, and a height T0 of 0.4 mm. Other conditions were the same as those of Example 6.

[0268] (Comparative Example 3)

[0269] In Comparative Example 3, Sn was not added to the internal electrode pattern. Other conditions were the same as those of Example 6.

[0270] Table 3 shows the conditions of Examples 6 to 9 and Comparative Example 3.

[0271] [Table 3]

[0272]

[0273] For Comparative Example 3 and Examples 6 to 9, 100 samples were prepared respectively. As shown in Table 4, no cracks were confirmed in Examples 6 to 9. No cracks were confirmed, which can be considered to be because the binder discharge start temperature was lowered in the binder removal process by having a low melting point metal inside the internal electrode layer or at the interface between the internal electrode layer and the dielectric layer, and the binder was fully removed. On the other hand, cracks were confirmed in Comparative Example 3. This can be considered to be because the binder was not fully removed due to the lack of addition of a low melting point metal.

[0274] [Table 4]

[0275] Whether there are cracks Example 6 none Example 7 none Example 8 none Example 9 none Comparative Example 3 have

[0276] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to these specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims.

[0277] Description of Reference Numerals

[0278] 10 stacked sheets, 11 dielectric layers, 12 internal electrode layers, 13 covering layers, 14 capacitor portions, 15 end edges, 16 side edges, 20a, 20b external electrodes, 21 base layers, 22 plating layers, 23 first plating layers, 24 second plating layers, 25 third plating layers, 51 dielectric green sheets, 52 internal electrode patterns, 53 covering sheets, 100 stacked ceramic capacitors, 121 first regions, 122 second regions.

Claims

1. A ceramic electronic component, characterized in that: include: A laminated sheet having a substantially rectangular parallelepiped shape in which a plurality of dielectric layers and a plurality of internal electrode layers having Ni as a main component are alternately laminated, wherein the plurality of internal electrode layers are alternately exposed at first and second end faces opposite to each other in the substantially rectangular parallelepiped shape; and A pair of external electrodes provided on the first end surface and the second end surface, wherein a contact layer in contact with the first end surface and the second end surface is mainly composed of Cu, A low melting point metal having a melting point lower than that of Cu is added to the plurality of internal electrode layers and the contact layer. In one or more of the plurality of internal electrode layers from the outermost layer, the width of the connection portion connected to the external electrode is narrower than the width of the other regions.

2. The ceramic electronic component according to claim 1, characterized in that: The low melting point metal includes at least any one of Ga, In, Sn, Bi, Zn, and Al.

3. The ceramic electronic component according to claim 1 or 2, characterized in that: The number of the at least one internal electrode layer from the outermost layer accounts for 10% or more of the total number of the plurality of internal electrode layers stacked.

4. The ceramic electronic component according to claim 1 or 2, characterized in that: The width of the connection portion is not less than 1 / 2 and not more than 4 / 5 of the width of the internal electrode layers in a region where the internal electrode layers connected to different external electrodes face each other.

5. The ceramic electronic component according to claim 1 or 2, characterized in that: The length of the connecting portion in the direction relative to the first end face and the second end face is greater than 1 / 3 of the distance that the pair of external electrodes extend from the first end face or the second end face on at least any one of the four faces of the laminate sheet other than the first end face and the second end face.

6. The ceramic electronic component according to claim 1 or 2, characterized in that: When the directions orthogonal to the directions relative to the first end face and the second end face and to each other are set as the first direction and the second direction, and when the direction in which the multiple internal electrode layers are stacked is set as the first direction, the dimension of the ceramic electronic component in the first direction is more than 1.3 times the dimension in the second direction.

7. The ceramic electronic component according to claim 1 or 2, characterized in that: When the directions orthogonal to the directions relative to the first end face and the second end face and to each other are set as the first direction and the second direction, and the direction in which the multiple internal electrode layers are stacked is set as the second direction, the dimension of the ceramic electronic component in the first direction is more than 1.3 times the dimension in the second direction.

8. The ceramic electronic component according to claim 1 or 2, characterized in that: The thickness of each of the plurality of internal electrode layers is not less than 0.1 μm and not more than 2 μm.

9. The ceramic electronic component according to claim 1 or 2, characterized in that: The thickness of each of the plurality of dielectric layers is not less than 0.3 μm and not more than 10 μm.

10. A packaging body, characterized in that: include: The ceramic electronic component according to claim 1 or 2; A carrier tape having a sealing surface perpendicular to a first direction, and a recessed portion recessed from the sealing surface in the first direction for accommodating the ceramic electronic component, wherein the first direction is the first direction of the first direction and the second direction which are perpendicular to the direction in which the first end face and the second end face are opposite and are perpendicular to each other; and A top strip adhered to the sealing surface and capable of covering the recessed portion.

11. A circuit board, characterized in that: include: The ceramic electronic component according to claim 1 or 2; and A mounting substrate having a mounting surface perpendicular to a first direction, and a pair of connecting electrodes arranged on the mounting surface and connected to the pair of external electrodes of the ceramic electronic component via solder, respectively, wherein the first direction is the first direction of the first direction and the second direction that are orthogonal to the direction relative to the first end face and the second end face and are orthogonal to each other.

12. A method for manufacturing a ceramic electronic component, characterized in that: include: A step of firing a laminated body obtained by laminating a plurality of laminated units, wherein an internal electrode pattern having Ni as a main component and a low-melting-point metal having a lower melting point than Cu is formed on a dielectric green sheet; and A step of forming a layer having Cu as a main component and containing the low melting point metal on a first end face and a second end face of the stacked body that are opposite to each other during or after the stacked body is fired, In one or more of the internal electrode patterns from the outermost layer among the plurality of internal electrode patterns, a width of a connection portion connected to a layer including the low melting point metal is narrower than a width of other regions.

13. A ceramic electronic component, characterized in that: The dimension of the ceramic electronic component in a first direction is 1.3 times or more of the dimension in a second direction perpendicular to the first direction. The ceramic electronic component comprises: A laminated sheet having a substantially rectangular parallelepiped shape in which a plurality of dielectric layers and a plurality of internal electrode layers having Ni as a main component are alternately laminated in the second direction, wherein the plurality of internal electrode layers are alternately exposed at a first end face and a second end face that are opposite to each other in a third direction that is orthogonal to the first direction and the second direction; and A pair of external electrodes provided on the first end surface and the second end surface, wherein the main component of the portion of the external electrodes in contact with the first end surface and the second end surface is Cu, A low melting point metal having a melting point lower than that of Cu is present in at least any one of the interiors of the plurality of internal electrode layers and the interfaces between the plurality of internal electrode layers and the plurality of dielectric layers.

14. The ceramic electronic component according to claim 13, characterized in that: The low melting point metal includes any one of Ga, In, Sn, Bi, Pb, and Zn.

15. The ceramic electronic component according to claim 13 or 14, characterized in that: In one or more internal electrode layers from the outermost layer among the plurality of internal electrode layers, a width in the first direction of a connection portion connected to the external electrode is narrower than a width of other regions.

16. The ceramic electronic component according to claim 15, characterized in that: The number of the one or more internal electrode layers from the outermost layer is 10% to 50% of the total number of the plurality of internal electrode layers stacked.

17. The ceramic electronic component according to claim 15 or 16, characterized in that: The width of the connection portion in the first direction is not less than 1 / 2 and not more than 4 / 5 of the width of the internal electrode layers in the first direction in a region where the internal electrode layers connected to different external electrodes face each other.

18. The ceramic electronic component according to claim 13 or 14, characterized in that: The thickness of each of the plurality of internal electrode layers is not less than 0.1 μm and not more than 2 μm.

19. The ceramic electronic component according to claim 13 or 14, characterized in that: The thickness of each of the plurality of dielectric layers is not less than 0.3 μm and not more than 3 μm.

20. A packaging body, characterized in that: include: The ceramic electronic component according to claim 13 or 14; a carrier tape having a sealing surface perpendicular to the first direction and a recessed portion recessed from the sealing surface in the first direction for accommodating the ceramic electronic component; and A top strip adhered to the sealing surface and capable of covering the recessed portion.

21. A circuit board, characterized in that: include: The ceramic electronic component according to claim 13 or 14; and The mounting substrate includes a mounting surface perpendicular to the first direction and a pair of connection electrodes provided on the mounting surface and connected to the pair of external electrodes of the ceramic electronic component via solder, respectively.

22. A method for manufacturing a ceramic electronic component, wherein a dimension of the ceramic electronic component in a first direction is 1.3 times or more of a dimension of the ceramic electronic component in a second direction orthogonal to the first direction, the method comprising: A step of firing a laminated body, wherein the laminated body is obtained by laminating a plurality of laminated units in the second direction, wherein the laminated units are formed on a dielectric green sheet with an internal electrode pattern having Ni as a main component and to which a low melting point metal having a lower melting point than Cu is added; and A step of forming a layer having Cu as a main component on a first end face and a second end face of the stacked body that are opposite to each other in a third direction orthogonal to the first direction and the second direction when or after the stacked body is fired.

Images