Multi-die flip chip package with heat sink
Through the combined design of flexible multi-layer support substrate and heat sink, the problems of large packaging space and poor heat dissipation in existing packaging solutions are solved, and a compact and efficient packaging solution is achieved.
Patent Information
- Application Number
- CN202411524815.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-10-07
- Filing Date
- 2024-10-30
- Publication Date
- 2025-05-16
AI Technical Summary
The existing integrated circuit die packaging solutions have problems such as large packaging space and poor heat dissipation, especially in multiple die configurations.
A flexible multi-layer support substrate is employed, including the central portion and the peripheral portion connected by a flexible coupling region, in combination with the design of the heat sink, wherein the tabs of the heat sink are mounted to the upper surface of the central portion of the support substrate and provide heat dissipation through the heat sink and the tabs.
The compactness of the package and efficient heat dissipation are achieved, reducing the space occupied by the package, while improving the rigidity and heat dissipation capabilities of the package.
Smart Images
Figure CN120015714A_ABST
Abstract
Description
[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Patent Application No. 63 / 599,651, filed on November 16, 2023, the disclosure of which is incorporated herein by reference. Technical Field
[0002] The present invention relates to three-dimensional (3D) packaging of multiple integrated circuit dies. Background Art
[0003] Advanced packaging of integrated circuit dies can provide Figure 1 , wherein a plurality of integrated circuit dies 10 (in a flip chip orientation) are mounted to the upper surface of a supporting substrate 12 (including a power / signal routing network 14) and share an upper heat sink 16 thermally coupled to each die and mounted to the substrate, or provided as Figure 2 , in which a plurality of integrated circuit dies 10 are stacked one on top of the other (in a flip-chip orientation with through silicon vias (TSVs) in thermally and electrically coupled relationship), supported by an underlying support substrate 12 (including a power / signal routing network 14), and capped with a heat sink 16 thermally coupled to an uppermost one of the dies.
[0004] Figure 1 The packaging solution shown in suffers from disadvantages associated with requiring longer interconnects between the dies and having a side-by-side die configuration that occupies a package footprint that is too large. Figure 2 The packaging solution shown in suffers from the disadvantages associated with a stacked die configuration that is overly complex, expensive, and limited in terms of heat dissipation.
[0005] There is a need in the art for a better packaging solution for multiple integrated circuit dies. Figure 1 and Figure 2 The present packaging solution will provide both reduced packaging footprint and improved heat dissipation compared to the packaging solution shown in . Summary of the invention
[0006] In an embodiment, a package includes: a supporting substrate including a wiring network; wherein the supporting substrate includes a central portion and at least one peripheral portion, and the at least one peripheral portion is connected to the central portion via a flexible coupling area; a first circuit device having an upper surface mounted to the supporting substrate at the central portion and electrically coupled to the front side of the wiring network; a second circuit device having an upper surface mounted to the supporting substrate at the at least one peripheral portion and electrically coupled to the front side of the wiring network; a heat sink including a base plate, a plurality of heat sinks extending from the upper surface of the base plate, and a plurality of tabs extending from the lower surface of the base plate; wherein the tabs of the heat sink are mounted to the upper surface of the supporting substrate at the central portion, and the lower surface of the base plate is thermally coupled to the back side of the first circuit device; wherein the at least one peripheral portion is folded relative to the central portion at the flexible coupling area; and wherein the outer surface of at least one heat sink of the heat sink is thermally coupled to the back side of the second circuit device.
[0007] In an embodiment, a package includes: a supporting substrate including a wiring network; wherein the supporting substrate includes a central portion and at least one peripheral portion, and the at least one peripheral portion is connected to the central portion via a flexible coupling area; a first circuit device having an upper surface mounted to the supporting substrate at the central portion and electrically coupled to the front side of the wiring network; a second circuit device having an upper surface mounted to the supporting substrate at the at least one peripheral portion and electrically coupled to the front side of the wiring network; a heat sink including a base plate and a plurality of tabs extending from the lower surface of the base plate; wherein the tabs of the heat sink are mounted to the upper surface of the supporting substrate at the central portion, and the lower surface of the base plate is thermally coupled to the back side of the first circuit device; wherein the at least one peripheral portion is folded relative to the central portion at the flexible coupling area; and wherein the outer surface of at least one tab of the heat sink is thermally coupled to the back side of the second circuit device. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] For the purpose of understanding the invention, embodiments of the invention will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which: Figure 1 The packaging of multiple integrated circuit dies is illustrated; Figure 2 The packaging of multiple integrated circuit dies is illustrated; Figure 3 The packaging of multiple integrated circuit dies is illustrated; Figure 4 Picture shows Figure 3 an expanded plan (top) view of a support substrate used in a package of; and Figure 5 An integrated circuit die is shown mounted to a supporting substrate. DETAILED DESCRIPTION
[0009] The following description refers to the arrangements shown in the accompanying drawings; therefore, expressions such as "above", "below", "upper", "lower", "top", "bottom", "right", "left", etc. are relative to the accompanying drawings and should not be interpreted in a limiting manner.
[0010] The illustrations in the accompanying drawings are not necessarily drawn to scale, and certain features are exaggerated in size, shape, degree, etc., in order to more clearly illustrate the subject matter.
[0011] Figure 3 A package 100 for a plurality of integrated circuit dies 102 is illustrated. A flexible multi-layer support substrate 104 includes a power / signal routing network 106. The support substrate 104 includes a central portion 104C and at least one peripheral portion 104P. The peripheral portion 104P can be folded relative to the central portion 104C at a flexible folding region 104F (including, for example, a flexible coupling region of the support substrate 104). In a preferred but non-limiting embodiment, the peripheral portion 104P is folded relative to the central portion 104C at 90°. o Corner fold.
[0012] In an embodiment, the flexible multi-layer support substrate 104 may be rigid (or substantially rigid) at the peripheral portion 104P and the central portion 104C, and flexible at the flexible folding region 104F.
[0013] Figure 4 The figure shows an expanded plan (top) view of the support substrate 104. The upper surface of the support substrate 104 includes an array of interconnect pads 110 at each of the peripheral portion 104P and the central portion 104C. These interconnect pads are electrically connected to the power / signal routing network 106. Figure 5 As shown in FIG, the integrated circuit die 102 is mounted to the upper surface of the support substrate 104 in a flip chip orientation (i.e., the front side of the die faces the support substrate 104). The interconnect balls 112 (or pillars) of the integrated circuit die 102 are soldered to the interconnect pad array 110. A suitable adhesive filler may be provided to encapsulate the interconnect balls 112 and secure the integrated circuit die 102 to the support substrate 104.
[0014] In an embodiment, the central portion 104C of the support substrate 104 may have a quadrilateral (square or rectangular) shape, wherein each of the peripheral portions 104P also has a quadrilateral (square or rectangular) shape. Each peripheral portion 104P coupled by a flexible coupling region at the flexible folding region 104F extends vertically away from one side of the quadrilateral shape. Although the quadrilateral shape of the central portion 104C of the support substrate 104 is a preferred embodiment, it should be understood that the central portion 104C may instead have some other geometric shapes (such as a triangular shape, a pentagonal shape, or a hexagonal shape), which is determined, for example, by the number of integrated circuit dies 102 to be included in the package 10.
[0015] Reference again Figure 3 , the package 100 also includes a heat sink 120. The heat sink 120 includes a base plate 120B having a plurality of fins 120F extending from an upper surface of the base plate 120B. The heat sink 120 also includes a plurality of tabs 120T extending from a lower surface of the base plate 120B. The base plate 120B, the fins 120F, and the tabs 120T form a single entity (e.g., made of aluminum or copper), for example, which is manufactured as a single piece of material using a suitable manufacturing technique such as milling, casting, extrusion, or molding.
[0016] The lower surface of the base plate 120B is positioned in thermal contact with the backside of the integrated circuit die 102 mounted to the central portion 104C of the support substrate 104. A thermally conductive adhesive layer 122 is used between the lower surface of the base plate 120B and the backside of the integrated circuit die 102. The distal end 121 of the tab 120T is positioned in contact with the upper surface of the support substrate 104 at the central portion 104C. The tab 120T of the heat sink 120 is fixed to the upper surface of the central portion 104C of the support substrate 104 using a suitable adhesive 124 (e.g., epoxy).
[0017] The integrated circuit die 102 is then mounted to its peripheral portion 104P at the flexible folding region 104F at 90° relative to the central portion 104C. o Corner fold. The back side of each integrated circuit die 102 mounted to the peripheral portion 104P is fixed to the outer surface(s) of the (one or more) heat sink 120F of the heat sink 120 using a thermally conductive adhesive layer 126. It should also be noted that each tab 120T is aligned with a corresponding one of the heat sinks 120F. With this configuration, the back side of each integrated circuit die 102 mounted to the peripheral portion 104P is also fixed to the outer surface(s) of the tab 120T of the heat sink 120 by the thermally conductive adhesive layer 126. This helps to provide a larger heat dissipation area of the heat sink in thermal contact with the die 102.
[0018] Although Figure 4-Figure 5 An embodiment of a package supporting five integrated circuit dies 102 is shown, but it will be understood that this is merely an example and the package may instead be made with two, three, or four integrated circuit dies 102 by adjusting the number of peripheral portions 104P included in the support substrate 104 .
[0019] In an embodiment, the integrated circuit die 102 are components of an electronic system, for example, one of the dies may be a processor or controller integrated circuit, another of the dies may be a memory integrated circuit, another of the dies may be a communication integrated circuit, and another of the dies may be a power management circuit.
[0020] In an embodiment, one or more of the dies may instead include a packaged circuit component. Such a circuit component may be an active or passive component. The packaged circuit component may include a packaged integrated circuit, such as provided with a quad flat no-leads (QFN) type package or other surface mount packaging configuration.
[0021] To allow the package to be electrically connected to other circuitry and further mounted to a printed circuit board (PCB), the bottom of the support substrate 104 includes a plurality of contact balls 140 (e.g., in a ball grid array (BGA) format) at a central portion 104C that are electrically connected to a power / signal routing network 106.
[0022] Figure 3 The package has several advantages over the prior art: a) the package is compact and occupies a small space; b) the heat sink is shared by all integrated circuit tube cores, thereby providing improved and efficient heat dissipation; c) in combination with the surface adhesive fixing of the heat sink to the back side of each tube core, the tab is adhesively mounted to the upper surface of the supporting substrate, which improves the rigidity of the package and does not require additional fixing structures such as clamps, tapes or covers.
[0023] Although the present invention has been illustrated and described in detail in the drawings and the above description, these illustrations and descriptions are to be regarded as illustrative or exemplary rather than restrictive; the present invention is not limited to the disclosed embodiments. Other variations of the disclosed embodiments can be understood and implemented by those skilled in the art in practicing the claimed invention by studying the drawings, the disclosure, and the appended claims.
Claims
1. A package comprising: A supporting substrate including a wiring network; wherein the support substrate comprises a central portion and at least one peripheral portion, the at least one peripheral portion being connected to the central portion via a flexible coupling region; a first circuit device having a front surface mounted to an upper surface at a central portion of the support substrate and electrically coupled to the wiring network; a second circuit device having a front surface mounted to the upper surface of the support substrate at the at least one peripheral portion and electrically coupled to the wiring network; a heat sink comprising a base plate, a plurality of fins extending from an upper surface of the base plate, and a plurality of tabs extending from a lower surface of the base plate; wherein a tab of the heat sink is mounted to an upper surface of the support substrate at a central portion, and a lower surface of the base plate is thermally coupled to a back surface of the first circuit device; wherein the at least one peripheral portion is folded relative to the central portion at a flexible coupling region; and An outer surface of at least one heat sink fin of the heat sink is thermally coupled to a back surface of the second circuit device. 2 . The package of claim 1 , wherein each tab of the heat sink has a distal end positioned to contact an upper surface of the support substrate at a central portion. 3 . The package of claim 2 , further comprising an adhesive material securing the at least one tab of the heat sink to an upper surface of the support substrate at a central portion.
4. The package of claim 1, wherein an outer surface of at least one tab of the heat sink is also thermally coupled to a back side of the second circuit device.
5. The package of claim 1, further comprising a ball grid array at a lower surface of the support substrate at a central portion, wherein the ball grid array is electrically coupled to the wiring network.
6. The package of claim 1, wherein the first circuit device and the second circuit device are integrated circuit dies mounted to the support substrate in a flip chip orientation.
7. The package of claim 1, wherein at least one of the first circuit device and the second circuit device is a packaged integrated circuit.
8. The package of claim 7, wherein a package for the integrated circuit of the package is a quad flat no-lead (QFN) package.
9. A package comprising: A supporting substrate including a wiring network; wherein the support substrate comprises a central portion and at least one peripheral portion, the at least one peripheral portion being connected to the central portion via a flexible coupling region; a first circuit device having a front surface mounted to an upper surface at a central portion of the support substrate and electrically coupled to the wiring network; a second circuit device having a front surface mounted to the upper surface of the support substrate at the at least one peripheral portion and electrically coupled to the wiring network; a heat sink including a base plate and a plurality of tabs extending from a lower surface of the base plate; wherein a tab of the heat sink is mounted to an upper surface of the support substrate at a central portion, and a lower surface of the base plate is thermally coupled to a back surface of the first circuit device; wherein the at least one peripheral portion is folded relative to the central portion at a flexible coupling region; and An outer surface of at least one tab of the heat sink is thermally coupled to a back surface of the second circuit component. 10 . The package of claim 9 , wherein each tab of the heat sink has a distal end positioned to contact an upper surface of the support substrate at the central portion.
11. The package of claim 10, further comprising an adhesive material securing the at least one tab of the heat sink to an upper surface of the support substrate at a central portion.
12. The package of claim 9, further comprising a ball grid array at a lower surface of the support substrate at the central portion, wherein the ball grid array is electrically coupled to the wiring network.
13. The package of claim 9, wherein the first circuit device and the second circuit device are integrated circuit dies mounted to the support substrate in a flip chip orientation.
14. The package of claim 9, wherein at least one of the first circuit device and the second circuit device is a packaged integrated circuit.
15. The package of claim 14, wherein a package for the integrated circuit of the package is a quad flat no-lead (QFN) package.