Chemical mechanical polishing slurry and method of forming same

Abstract

In an embodiment, a method includes forming an opening in a dielectric layer; filling the opening with a conductive material; and performing a chemical mechanical polishing process on the conductive material and the dielectric layer, the chemical mechanical polishing process comprising a slurry comprising: an abrasive comprising titanium dioxide-silica mixed particles; and an oxidizing agent. The embodiment of the invention also relates to a chemical mechanical polishing slurry and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to chemical mechanical polishing slurry and a method for forming the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) In most cases, this improvement in integration density comes from repeated reductions in minimum feature size, which allows more components to be integrated into a given area.

[0003] Fin field effect transistor (FinFET) devices are increasingly being used in integrated circuits. FinFET devices have a three-dimensional structure including a semiconductor fin protruding from a substrate. A gate structure configured to control the flow of charge carriers within a conductive channel of the FinFET device wraps around the semiconductor fin. For example, in a tri-gate FinFET device, the gate structure wraps around three sides of the semiconductor fin, thereby forming a conductive channel on the three sides of the semiconductor fin. Summary of the invention

[0004] Some embodiments of the present application provide a method for forming a chemical mechanical polishing slurry, comprising: forming an opening in a dielectric layer; filling the opening with a conductive material; and performing a chemical mechanical polishing process on the conductive material and the dielectric layer, the chemical mechanical polishing process comprising a slurry, the slurry comprising: an abrasive, the abrasive comprising titanium dioxide-silicon dioxide mixed particles; and an oxidizer.

[0005] Other embodiments of the present application provide a chemical mechanical polishing slurry, comprising: a solvent; mixed abrasive particles dispersed in the solvent, wherein each of the mixed abrasive particles comprises a silicon dioxide portion and a titanium dioxide portion; an oxidizer; a pH adjuster; a pH buffer; and a surfactant.

[0006] Still other embodiments of the present application provide a chemical mechanical polishing slurry, comprising: a solvent; an oxidizer; first mixed abrasive particles, the first mixed abrasive particles comprising silicon dioxide and a first material, the first material being different from silicon dioxide; and second mixed abrasive particles, the second mixed abrasive particles comprising titanium dioxide and a second material, the second material being different from titanium dioxide, the second mixed abrasive particles having a structure different from that of the first mixed abrasive particles. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figure 1 A perspective view of a fin field effect transistor (FinFET) device is shown in accordance with some embodiments.

[0009] Figures 2 to 6 , 7A to 7C , Figures 8 to 16 and Fig.19 Various cross-sectional views of a FinFET device at various stages of fabrication are shown in accordance with some embodiments.

[0010] FIG. 17A to FIG. 17E Components of a chemical mechanical polishing system are shown in accordance with some embodiments.

[0011] 18A to 18D A process for forming a chemical mechanical polishing abrasive is shown according to some embodiments. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for realizing different features of the disclosed embodiments. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact.

[0013] In addition, for ease of description, spatially relative terms such as "under," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or component to another (or other) elements or components as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Throughout the discussion herein, unless otherwise indicated, the same reference numerals in different figures refer to the same or similar components formed by the same or similar methods using the same or similar materials.

[0014] Embodiments of the present disclosure are discussed in the context of forming a FinFET device, and in particular, in the context of forming a contact plug for a FinFET device. Although the disclosed embodiments are discussed using a FinFET device as an example, the disclosed methods may also be used for other types of devices, such as a planar device, a gate-all-around (GAA) device, or a CFET device. Furthermore, although the disclosed embodiments are discussed in detail using a contact plug as an example, the disclosed methods may also be used for other conductive components, such as metallization layers of an interconnect structure.

[0015] The disclosed embodiments provide for forming semiconductor devices (e.g., transistors) over a semiconductor substrate and forming interconnect structures (e.g., contacts and metallization layers) electrically connected to the semiconductor devices. For example, a contact to the semiconductor device may be formed through an interlayer dielectric (ILD) layer by: first forming a dielectric layer (e.g., an oxide material) over an ILD layer; patterning openings through the dielectric layer and the ILD layer to expose components of the semiconductor device; filling the openings with a conductive material; and performing one or more chemical mechanical polishing (CMP) processes to remove portions of the conductive material and the dielectric layer. The CMP process may be advantageously implemented using a slurry having a mixed abrasive comprising multiple materials.

[0016] For example, in an embodiment where the conductive material includes ruthenium, the abrasive may include titanium dioxide and silicon dioxide materials. In certain embodiments, the abrasive may include titanium dioxide-silicon dioxide mixed particles, wherein each titanium dioxide-silicon dioxide mixed particle has a titanium dioxide structure and a silicon dioxide structure. In addition, the titanium dioxide-silicon dioxide mixed particles may have an optional structure (e.g., a material different from titanium dioxide and silicon dioxide) and a titanium dioxide structure or an optional structure and a silicon dioxide structure. By implementing the CMP process with an abrasive having a titanium dioxide material very close to the silicon dioxide material, ruthenium and dielectric materials (e.g., silicon dioxide) can be removed effectively and at a rate proportional to each other. Therefore, the CMP process may be implemented with increased efficiency, effectiveness, and yield.

[0017] Figure 1 An example of a FinFET 30 in a perspective view is shown. The FinFET 30 includes a substrate 50 and a fin 64 that protrudes above the substrate 50. An isolation region 62 is formed on opposite sides of the fin 64, wherein the fin 64 protrudes above the isolation region 62. A gate dielectric 66 is along the sidewalls of the fin 64 and is located above the top surface of the fin 64, and a gate electrode 68 is located above the gate dielectric 66. Source / drain regions 80 are located in the fin 64 and on opposite sides of the gate dielectric 66 and the gate electrode 68. Figure 1Reference cross sections used in later figures are also shown. Cross section BB extends along the longitudinal axis of gate electrode 68 of FinFET 30. Cross section AA is perpendicular to cross section BB and along the longitudinal axis of fin 64 and in the direction of current flow, for example, between source / drain regions 80. Cross section CC is parallel to cross section BB and crosses source / drain regions 80. For clarity, subsequent figures refer to these reference cross sections.

[0018] Figures 2 to 6 , 7A to 7C , Figures 8 to 16 and Fig.19 is a cross-sectional view of a FinFET device 100 at various stages of manufacture according to an embodiment. The FinFET device 100 is similar to Figure 1 The FinFET 30 in FIG. 1 is similar to the FinFET 30 in FIG. 1 , but has multiple fins and multiple gate structures. Figures 2 to 5 A cross-sectional view of the FinFET device 100 along section BB is shown. Figure 6 , Fig. 7A , Figures 8 to 16 and Fig.19 A cross-sectional view of the FinFET device 100 along section AA is shown. Figure 7B and Figure 7C An embodiment cross-sectional view of the FinFET device 100 along section CC is shown.

[0019] Figure 2 A cross-sectional view of a substrate 50 is shown. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate includes a semiconductor material layer formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. An insulating layer is provided on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0020] refer to Figure 3 , Figure 2The substrate 50 shown in FIG. 5 is patterned using, for example, photolithography and etching techniques. For example, a mask layer 58, such as a pad oxide layer 52 and a pad nitride layer 56 thereon, is formed over the substrate 50. The pad oxide layer 52 may be, for example, a thin film including silicon oxide formed using a thermal oxidation process. The pad oxide layer 52 may serve as an adhesion layer between the substrate 50 and the pad nitride layer 56 thereon. In some embodiments, as examples, the pad nitride layer 56 is formed of silicon nitride, silicon oxynitride, silicon carbonitride, etc., or a combination thereof, and may be formed using low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD).

[0021] The mask layer 58 can be patterned using photolithography techniques. In general, photolithography techniques utilize a photoresist material (not shown) that is deposited, irradiated (exposed), and developed to remove portions of the photoresist material. The remaining photoresist material protects the underlying material (such as the mask layer 58 in this example) from subsequent processing steps (such as etching). In this example, the photoresist material is used to pattern the pad oxide layer 52 and the pad nitride layer 56 to form a patterned mask 58, such as Figure 3 as shown in .

[0022] The patterned mask 58 is then used to pattern the exposed portions of the substrate 50 to form trenches 61, thereby defining semiconductor fins 64 (e.g., 64A and 64B) between adjacent trenches 61. In some embodiments, the semiconductor fins 64 are formed by etching trenches in the substrate 50 using, for example, reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching process may be anisotropic. In some embodiments, the trenches 61 may be strips that are parallel to each other and closely spaced relative to each other (as viewed from the top). In some embodiments, the trenches 61 may be continuous and surround the semiconductor fins 64. The semiconductor fins 64 may also be referred to as fins 64 hereinafter.

[0023] The fin 64 can be patterned by any suitable method. For example, the fin 64 can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, the double patterning or multiple patterning process combines photolithography and self-alignment processes, thereby allowing the creation of patterns having, for example, a pitch that is smaller than that obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and then the remaining spacers or mandrels can be used to pattern the fins.

[0024] Figure 4An insulating material is shown formed between adjacent semiconductor fins 64 to form isolation regions 62. The insulating material may be an oxide, such as silicon oxide, nitride, etc., or a combination thereof, and may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition and post-curing in a remote plasma system to convert it to another material, such as an oxide), etc., or a combination thereof. Other insulating materials and / or other formation processes may be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process may be performed. A planarization process, such as chemical mechanical polishing (CMP), may remove any excess insulating material and form coplanar top surfaces of the isolation regions 62 and top surfaces of the semiconductor fins 64 (not shown). The patterned mask 58 (see Figure 3 ) can also be removed by planarization process.

[0025] In some embodiments, the isolation region 62 includes a liner (not specifically shown), such as a liner oxide, at the interface between the isolation region 62 and the substrate 50 / semiconductor fin 64. In some embodiments, the liner oxide is formed to reduce crystal defects at the interface between the substrate 50 and the isolation region 62. Similarly, the liner oxide can also be used to reduce crystal defects at the interface between the semiconductor fin 64 and the isolation region 62. The liner oxide (e.g., silicon oxide) can be a thermal oxide formed by thermal oxidation of a surface layer of the substrate 50, but other suitable methods can also be used to form the liner oxide.

[0026] Next, the isolation region 62 is recessed to form a shallow trench isolation (STI) region 62. The isolation region 62 is recessed so that the upper portion of the semiconductor fin 64 protrudes from between adjacent STI regions 62. The top surface of the STI region 62 can have a flat surface (as shown), a convex surface, a concave surface (such as a depression), or a combination thereof. The top surface of the STI region 62 can be formed to be flat, convex and / or concave by appropriate etching. The isolation region 62 can be recessed using an acceptable etching process, such as an etching process that is selective to the material of the isolation region 62. For example, dry etching or wet etching using dilute hydrofluoric acid (dHF) acid can be implemented to recess the isolation region 62.

[0027] Figures 2 to 4 An embodiment of forming fins 64 is shown, but the fins can be formed in a variety of different processes. For example, the top portion of substrate 50 can be replaced by a suitable material, such as an epitaxial material suitable for the expected type (e.g., n-type or p-type) of semiconductor device to be formed. Thereafter, substrate 50 with the epitaxial material on top is patterned to form semiconductor fins 64 including the epitaxial material.

[0028] As another example, a dielectric layer may be formed over a top surface of the substrate; a trench may be etched through the dielectric layer; a homoepitaxial structure may be epitaxially grown in the trench; and the dielectric layer may be recessed such that the homoepitaxial structure protrudes from the dielectric layer to form a fin.

[0029] In yet another example, a dielectric layer can be formed over a top surface of a substrate; a trench can be etched through the dielectric layer; a heteroepitaxial structure can be epitaxially grown in the trench using a different material than the substrate; and the dielectric layer can be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form a fin.

[0030] In embodiments where epitaxial material or epitaxial structure (e.g., heteroepitaxial structure or homoepitaxial structure) is grown, the grown material or structure may be doped in situ during growth, which may avoid prior and subsequent implantation, but in situ and implantation doping may be used together. Further, it may be advantageous to epitaxially grow a different material in the NMOS region than in the PMOS region. In various embodiments, fin 64 may include silicon germanium (Si x Ge 1-x , where x can be between 0 and 1), silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, etc. For example, available materials for forming III-V compound semiconductors include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, etc.

[0031] Figure 5 A gate structure 75 is shown formed over the semiconductor fin 64. According to various embodiments, the gate structure 75 is a dummy gate structure and includes a gate dielectric 66 and a gate electrode 68. A mask 70 may be formed over the dummy gate structure 75. To form the dummy gate structure 75, a dielectric layer is formed on the semiconductor fin 64. The dielectric layer may be, for example, silicon oxide, silicon nitride, multilayers thereof, etc., and may be deposited or thermally grown.

[0032] A gate layer is formed over the dielectric layer, and a mask layer is formed over the gate layer. The gate layer may be deposited over the dielectric layer and then planarized, such as by CMP. The mask layer may be deposited over the gate layer. The gate layer may be formed, for example, of polysilicon, but other materials may also be used. The mask layer may be formed, for example, of silicon nitride, etc.

[0033] After forming those layers (e.g., dielectric layer, gate layer, and mask layer), the mask layer can be patterned using acceptable photolithography and etching techniques to form mask 70. The pattern of mask 70 can then be transferred to the gate layer and dielectric layer by acceptable etching techniques to form gate electrode 68 and gate dielectric 66, respectively. Gate electrode 68 and gate dielectric 66 cover the corresponding channel region of semiconductor fin 64. Gate electrode 68 can also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the corresponding semiconductor fin 64.

[0034] exist Figure 5 In the example of FIG. 5 , gate dielectric 66 is shown as being formed over fin 64 (e.g., over the top surface and sidewalls of fin 64) and over STI region 62. In other embodiments, gate dielectric 66 may be formed by, for example, thermal oxidation of the material of fin 64, and thus may be formed over fin 64, but not over STI region 62. These and other variations are fully intended to be included within the scope of the disclosed embodiments.

[0035] Figure 6 , Fig. 7A , Figures 8 to 16 and Fig.19 FIG. 4 shows a further processed cross-sectional view of the FinFET device 100 along section AA (eg, along the longitudinal axis of the fin 64 ). Figure 6 , Fig. 7A and Figure 8 In the embodiment, three dummy gate structures 75 (eg, 75A, 75B, and 75C) are formed over the fin 64. Those skilled in the art will appreciate that more or less than three gate structures 75 may be formed over the fin 64, and these and other variations are fully intended to be included within the scope of the disclosed embodiments.

[0036] Figure 6A lightly doped drain (LDD) region 65 is shown formed in the fin 64. The LDD region 65 may be formed by a plasma doping process. The plasma doping process may include forming and patterning a mask such as a photoresist to cover the region of the FinFET that will be protected from the plasma doping process. The plasma doping process may implant n-type or p-type impurities in the fin 64 to form the LDD region 65. For example, a p-type impurity such as boron may be implanted in the fin 64 to form an LDD region 65 for a p-type device. As another example, an n-type impurity such as phosphorus may be implanted in the fin 64 to form an LDD region 65 for an n-type device. In some embodiments, the LDD region 65 is adjacent to the channel region of the FinFET device 100. Portions of the LDD region 65 may extend below the gate electrode 68 and into the channel region of the FinFET device 100. It should be noted that other configurations, shapes, and formation methods of the LDD region 65 are also possible and are fully intended to be included within the scope of the disclosed embodiments. For example, the LDD region 65 may be formed after the gate spacer 87 is formed. In some embodiments, the LDD region 65 is omitted. For simplicity, the LDD region 65 is not shown in subsequent figures, and it should be understood that the LDD region 65 can be formed in the fin 64.

[0037] Still reference Figure 6 , after forming the LDD region 65, a gate spacer 87 is formed around the dummy gate structure 75. The gate spacer 87 may include a first gate spacer 72 and a second gate spacer 86. It should be noted that the gate spacer 87 may be considered as a part of the gate structure 75. For example, the first gate spacer 72 may be a gate sealing spacer and is formed on opposite sidewalls of the gate electrode 68 and on opposite sidewalls of the gate dielectric 66. The second gate spacer 86 is formed on the first gate spacer 72. The first gate spacer 72 may be formed of a nitride, such as silicon nitride, silicon oxynitride, silicon carbonitride, etc., or a combination thereof, and may be formed using, for example, thermal oxidation, CVD, or other suitable deposition processes. The second gate spacer 86 may be formed of silicon nitride, silicon carbonitride, a combination thereof, etc., using a suitable deposition method. In an embodiment, the first gate spacer 72 is formed of silicon nitride, and the atomic ratio between silicon and nitride (e.g., the ratio between the atomic percentages of silicon and nitride) is between about 0.7 and about 1.3.

[0038] In an embodiment, the gate spacer 87 is formed by: first conformally depositing a first gate spacer layer over the FinFET device 100; and then conformally depositing a second gate spacer layer over the deposited first gate spacer layer. Next, an anisotropic etching process, such as a dry etching process, is performed to remove a first portion of the second gate spacer layer disposed on an upper surface of the FinFET device 100 (e.g., an upper surface of the mask 70), while retaining a second portion of the second gate spacer layer disposed along a sidewall of the gate structure 75. The second portion of the second gate spacer layer remaining after the anisotropic etching process forms the second gate spacer 86. The anisotropic etching process also removes a portion of the first gate spacer layer disposed outside of the sidewall of the second gate spacer 86, and the remaining portion of the first gate spacer layer forms the first gate spacer 72.

[0039] like Figure 6 The shapes and formation methods of the gate spacers 87 shown in are merely non-limiting examples, and other shapes and formation methods are possible. These and other variations are fully intended to be included within the scope of the disclosed embodiments.

[0040] exist Fig. 7A In the embodiment of the present invention, a groove is formed in the fin 64 adjacent to the dummy gate structure 75, for example, between adjacent dummy gate structures 75 and / or adjacent to the dummy gate structure 75. Then, a source / drain region 80 is formed in the groove. In some embodiments, the groove is formed by, for example, an anisotropic etching process using the dummy gate structure 75 and the gate spacer 87 as an etching mask, but any other suitable etching process may also be used.

[0041] Next, source / drain regions 80 are formed in the recesses. The source / drain regions 80 are formed by epitaxially growing a material in the recesses using a suitable method such as metal organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), etc., or a combination thereof.

[0042] As shown, the epitaxial source / drain regions 80 may have surfaces that are raised from the corresponding surfaces of the fins 64 (e.g., raised above the non-recessed upper surface 64U of the fins 64), and may have facets. The source / drain regions 80 of adjacent fins 64 may merge to form a continuous epitaxial source / drain region 80 (see FIG. Figure 7B In some embodiments, the source / drain regions 80 of adjacent fins 64 are not merged together and separate source / drain regions 80 are maintained (see Figure 7C). In some embodiments, the resulting FinFET is an n-type FinFET, and the source / drain region 80 includes silicon carbide (SiC), silicon phosphorus (SiP), phosphorus-doped silicon carbide (SiCP), etc. In some embodiments, the resulting FinFET is a p-type FinFET, and the source / drain region 80 includes SiGe and a p-type impurity, such as boron or indium.

[0043] The epitaxial source / drain regions 80 may be implanted with dopants to form the source / drain regions 80, followed by an annealing process. The implantation process may include forming and patterning a mask, such as a photoresist, to cover areas of the FinFET device 100 that are to be protected from the implantation process. The source / drain regions 80 may have a thickness from about 1E19 cm -3 to about 1E21 cm -3 The impurity (e.g., dopant) concentration may be within a range of . A p-type impurity, such as boron or indium, may be implanted in the source / drain region 80 of a p-type transistor. An n-type impurity, such as phosphorus or arsenide, may be implanted in the source / drain region 80 of an n-type transistor. In some embodiments, the epitaxial source / drain region 80 may be doped in situ during growth.

[0044] exist Figure 8 in Fig. 7A A contact etch stop layer (CESL) 89 is formed over the structure shown in FIG. CESL 89 is used as an etch stop layer in a subsequent etching process and may include a suitable material such as silicon oxide, silicon nitride, silicon oxynitride, a combination thereof, etc., and may be formed by a suitable formation method such as CVD, PVD, a combination thereof, etc.

[0045] Next, a first interlayer dielectric (ILD) 90 is formed over the CESL 89 and over the dummy gate structures 75 (e.g., 75A, 75B, and 75C). In some embodiments, the first ILD 90 is formed of a dielectric material such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc., and may be deposited by any suitable method, such as CVD, PECVD, or FCVD. A planarization process, such as CMP, may be performed to remove the mask 70 (if present) and to remove the portion of the CESL 89 disposed over the gate electrode 68. After the planarization process, the top surface of the first ILD 90 is flush with the top surface of the gate electrode 68.

[0046] exist Fig. 9In the embodiment of the present invention, a gate-last process (e.g., a replacement gate process) is performed to replace the gate electrode 68 and the gate dielectric 66 (e.g., a dummy gate structure 75) with an active gate (e.g., a replacement gate or a metal gate) and an active gate dielectric material, respectively. Therefore, in the gate-last process, the gate electrode 68 and the gate dielectric 66 can be referred to as a dummy gate electrode and a dummy gate dielectric, respectively.

[0047] As shown, the dummy gate structures 75A, 75B and 75C are replaced by replacement gate structures 97A, 97B and 97C, respectively. The replacement gate structures 97 (e.g., 97A, 97B and 97C) may also be referred to as metal gate structures. According to some embodiments, in order to form the replacement gate structure 97 (e.g., 97A, 97B or 97C), the gate electrode 68 and the gate dielectric 66 directly below the gate electrode 68 are removed in an etching step so that grooves (not shown) are formed between the gate spacers 87. Each groove exposes the channel region of the corresponding fin 64. During the removal of the dummy gate, the gate dielectric 66 can be used as an etch stop layer when etching the gate electrode 68. Then, after removing the gate electrode 68, the gate dielectric 66 can be removed.

[0048] Next, a gate dielectric layer 94, a barrier layer 96, a work function layer 98, and a gate electrode 99 are formed in the recess for replacing the gate structure 97. The gate dielectric layer 94 is conformally deposited in the recess, such as on the top surface and sidewalls of the fin 64 and on the sidewalls of the gate spacer 87 and on the top surface of the first ILD 90 (not shown). According to some embodiments, the gate dielectric layer 94 includes silicon oxide, silicon nitride, or a multilayer thereof. In some embodiments, the gate dielectric layer 94 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 94 may have a k value greater than about 7.0 and may include a metal oxide or silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, or a combination thereof. The formation method of the gate dielectric layer 94 may include molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, etc.

[0049] Barrier layer 96 is conformally formed over gate dielectric layer 94. Barrier layer 96 may include a conductive material such as titanium nitride, but other materials such as tantalum nitride, titanium, tantalum, etc. may alternatively be utilized. Barrier layer 96 may be formed using a CVD process, such as PECVD. However, other alternative processes such as sputtering, metal organic chemical vapor deposition (MOCVD), or ALD may alternatively be used.

[0050] According to some embodiments, a work function layer 98, such as a p-type work function layer or an N-type work function layer, may be formed in a recess above the barrier layer 96 and formed before forming the gate electrode 99. Exemplary p-type work function metals that may be included in a gate structure for a p-type device include TiN, TaN, Ru, Mo, Al, WN, ZrSi 2 、MoSi 2 、TaSi 2 、NiSi 2 , WN, other suitable p-type work function materials, or combinations thereof. Exemplary n-type work function metals that may be included in a gate structure for an n-type device include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. The work function value is related to the material composition of the work function layer, and therefore, the material of the work function layer is selected to adjust its work function value so that a desired threshold voltage Vt is achieved in the device to be formed. The work function layer may be deposited by CVD, physical vapor deposition (PVD), and / or other suitable processes.

[0051] In some embodiments, a seed layer (not shown) is conformally formed over the work function layer 98. The seed layer may include copper, titanium, tantalum, titanium nitride, tantalum nitride, etc., or a combination thereof, and may be deposited by ALD, sputtering, PVD, etc. The seed layer is a metal layer that may be a single layer or a composite layer including multiple sublayers formed of different materials. For example, the seed layer includes a titanium layer and a copper layer over the titanium layer.

[0052] Then, a gate electrode 99 is deposited over the seed layer and fills the remaining portion of the recess. The gate electrode 99 may be made of a metal-containing material, such as Cu, Al, W, etc., a combination thereof, or a multilayer thereof, and may be formed by, for example, electroplating, chemical plating, or other suitable methods. After forming the gate electrode 99, a planarization process, such as CMP, may be performed to remove the gate dielectric layer 94, the barrier layer 96, the work function layer 98, the seed layer, and the excess portion of the gate electrode 99, which is located above the top surface of the first ILD 90. Therefore, the resulting remaining portion of the gate dielectric layer 94, the barrier layer 96, the work function layer 98, the seed layer, and the gate electrode 99 forms a replacement gate structure 97 of the resulting FinFET device 100.

[0053] exist Fig.10In the embodiment of the present invention, an etch stop layer 105 is formed (e.g., selectively) on an upper surface of the first ILD 90. The etch stop layer 105 may be a suitable dielectric material, such as silicon nitride or silicon oxynitride formed on an upper surface of the first ILD 90 by, for example, CVD, ALD, a combination thereof, or the like. For example, a patterned mask layer may be formed to cover the replacement gate structure 97 and the gate spacer 87 while exposing the first ILD 90, and then the etch stop layer 105 is formed over the exposed first ILD 90. After the etch stop layer 105 is formed, the patterned mask layer is removed. As another example, an upper layer of the first ILD 90 may be converted into the etch stop layer 105, for example, by a nitridation process using a nitride-containing gas or a nitride-containing plasma.

[0054] Next, the replacement gate structure 97 is recessed to form grooves 103 between the corresponding gate spacers 87. In some embodiments, a metal gate etch-back process is performed to remove an upper portion of the replacement gate structure 97, and thus, after the metal gate etch-back process, grooves 103 are formed between the gate spacers 87. A suitable etching process, such as dry etching, wet etching, or a combination thereof, may be performed as the metal gate etch-back process.

[0055] Still reference Fig.10 After forming the recess 103, a capping layer 101 is formed on the recessed replacement gate structure 97. In some embodiments, the capping layer 101 is formed of a conductive material (such as tungsten) using a suitable deposition method (such as ALD, CVD, PVD, etc.). Fig.10 In the example of FIG. 1 , the capping layer 101 continuously extends along the upper surface of the replacement gate structure 97 from the inner sidewall of the gate spacer 87 to the opposite inner sidewall of the corresponding gate spacer 87. In other words, in the illustrated embodiment, the capping layer 101 completely covers the upper surface of the replacement gate structure 97. In some embodiments, the capping layer 101 is omitted.

[0056] exist Fig.11 , recess 103 is filled with mask structure 108. As shown, semiconductor material 107 (also referred to as semiconductor liner) is conformally formed along the sidewalls and bottom of recess 103 and along the upper surface of etch stop layer 105. Next, dielectric material 109 is formed over semiconductor material 107 to fill recess 103. Dielectric material 109 may also be formed outside recess 103 over portions of semiconductor material 107 between replacement gate structures 97. Semiconductor material 107 and dielectric material 109 are collectively referred to as mask structure 108.

[0057] In an exemplary embodiment, the semiconductor material 107 is made of a material such as SiH 4 、Si 2 H 6 、SiH2 Cl 2 , combinations thereof, etc., by a suitable deposition process such as LPCVD, PECVD, ALD, etc. In some embodiments, a treatment process may be performed to amorphize any polycrystalline structure that may have been formed in the semiconductor material 107. In the discussion herein, the conformal semiconductor material 107 may also be referred to as a silicon liner, and it should be understood that other suitable materials may also be used as the semiconductor material 107.

[0058] In addition, the dielectric material 109 may be silicon nitride formed by a suitable formation method such as ALD, PECVD, LPCVD, etc. In addition to silicon nitride (e.g., SiN), other suitable dielectric materials such as silicon carbon nitride (SiCN), silicon carbon nitride oxide (SiCON), and silicon carbide oxide (SiCO) may also be used as the dielectric material 109. In some embodiments, the dielectric material 109 is selected to be different from the material of the gate spacer 87 to provide etching selectivity in a subsequent etching process.

[0059] Still reference Fig.11 , a planarization process, such as CMP, is performed to remove excess portions of the semiconductor material 107 and excess portions of the dielectric material 109, which are located above the upper surface of the first ILD 90. As shown, the planarization process may also remove the etch stop layer 105 and the top portions of the gate spacers 87. After the planarization process, the remaining portions of the semiconductor material 107 and the dielectric material 109 disposed between (the remaining portions of) the corresponding gate spacers 87 are referred to as a mask structure 108.

[0060] exist Fig.12 , a second ILD 111 is formed over the first ILD 90, the gate spacers 87, and the mask structure 108. The second ILD 111 may be formed of the same or similar material using the same or similar formation method as the first ILD 90, and therefore the details are not repeated. In some embodiments, the second ILD 111 is formed similarly to that described above in conjunction with the first ILD 90. For example, the second ILD 111 may be a dielectric material such as silicon oxide, PSG, BSG, BPSG, USG, etc., and may be deposited by any suitable method, such as CVD, PECVD, or FCVD. In a subsequent etching process, the second ILD 111 may be used as an etch stop layer over the gate structure 97 (e.g., over the mask structure 108).

[0061] As shown, an etch stop layer stack 112 is formed and patterned over the second ILD 111 to have an opening 120 in the etch stop layer stack 112. In some embodiments, the etch stop layer stack 112 includes a plurality of layers (also referred to as sub-layers), wherein each of the plurality of layers is formed of a different material. In the illustrated example, the etch stop layer stack 112 includes a first layer 113, a second layer 115, and a third layer 117 that are successively formed over the second ILD 111. The first layer 113 is formed of tungsten-doped carbide (WDC, also referred to as tungsten-doped silicon carbide), the second layer 115 is formed of an oxide (e.g., silicon oxide), and the third layer 117 is formed of silicon (e.g., Si). The different materials of the sub-layers of the etch stop layer stack 112 are combined to provide a target level of etching selectivity for, for example, a subsequent etching process.

[0062] Next, the etch stop layer stack 112 is patterned to form openings 120 in the etch stop layer stack 112. For example, a patterned mask layer 119 (e.g., a patterned photoresist layer) is formed over the etch stop layer stack 112, and then an anisotropic etching process is performed using the patterned mask layer 119 as an etching mask to pattern the patterned mask layer 119. The number and location of the openings 120 shown provide non-limiting examples. Those skilled in the art will readily appreciate that other numbers of openings 120 may be formed at other locations. In some embodiments, the anisotropic etching process includes a plurality of etching steps, wherein each of the etching steps uses a different etchant to selectively remove a sublayer of the etch stop layer stack 112. The anisotropic etching process may stop when the second ILD 111 is exposed.

[0063] Next, in Fig.13 In the embodiment, an etching process is performed to remove a portion of the second ILD 111 and a portion of the first ILD 90 located below the opening 120. Optionally, the patterned mask layer 119 (e.g., the patterned photoresist layer) may be removed first, for example, by an ashing process. According to various embodiments, the etching process is used to extend the opening 120 so that an opening 121 exposing the underlying source / drain region 80 is formed in the first ILD 90. The etching process may be any suitable etching process, such as dry etching (e.g., a plasma etching process), wet etching, a combination thereof, or the like. The etching process may use an etchant that is selective to (e.g., has a higher etching rate for) a material (e.g., an oxide) of the first ILD 90 and the second ILD 111, so that the first ILD 90 and the second ILD 111 are removed without substantially attacking other layers of the FinFET device 100. For example, the etching process may be performed using C x F y , H 2, Ar, a combination thereof, etc., to remove the exposed portions of the first ILD 90 and the second ILD 111. In some embodiments, after the etching process to remove the exposed portions of the first ILD 90 and the second ILD 111, another etching process using an etchant selective to the material of the CESL 89 is performed to remove the CESL 89 exposed by the opening 121 and to expose the source / drain region 80.

[0064] Next, in Fig.14 In the embodiment of the present invention, a conductive material 122 is formed in the opening 121 to fill the opening 121 at least above the second ILD 111. The conductive material 122 can be ruthenium, copper, cobalt, tungsten, molybdenum, iridium, a combination thereof, etc., and can be formed by a suitable formation method such as PVD, CVD, PECVD, ALD, etc. In some embodiments (not specifically shown), a barrier layer can be conformally deposited before depositing the materials listed above. For example, the barrier layer can be a metal nitride, such as tantalum nitride, titanium nitride, etc., and is formed by, for example, PVD, ALD, or any suitable method. In various embodiments, the conductive material 122 includes ruthenium and may or may not include an underlying tantalum nitride barrier layer.

[0065] exist Fig.15 In the embodiment of the present invention, a first removal process is performed to remove the etch stop layer stack 112 and any portion of the conductive material 122 that may protrude above the second ILD 111. In some embodiments, the first removal process includes a first CMP process. The first CMP process may be an overall CMP process to remove the conductive material 122 and the etch stop layer stack 112 at a high polishing rate. Planarizing the structure to quickly remove the etch stop layer stack 112 may exceed the requirement for high planarity, which will be addressed in subsequent steps discussed below.

[0066] exist Fig.16 In the embodiment of the present invention, a second removal process is performed to remove the second ILD 111 and the portion of the conductive material 122 protruding above the first ILD 90. The remaining portion of the conductive material 122 in the opening 121 forms a contact 123. As shown, after the planarization process, the first ILD 90, the mask structure 108, the gate spacer 87 and the contact 123 have a coplanar upper surface. In some embodiments, the second removal process includes a second CMP process. The second CMP process can be a polishing CMP process to remove the conductive material 122 and the second ILD 111 at a slower and uniform polishing rate (e.g., a low polishing rate).

[0067] The first CMP process and the second CMP process utilize several additional process parameters as discussed in more detail below (see FIG. 17A to FIG. 17E). In an embodiment, the first CMP process and the second CMP process can be performed continuously with similar process parameters, although there is a reduced polishing rate from the first CMP process to the second CMP process. In another embodiment, several other process parameters can also be changed.

[0068] FIG. 17A to FIG. 18D The second CMP process (see Fig.16 ) related process components, which can also be applied to the first CMP process (see Fig.15 ). In particular, the figures illustrate an exemplary CMP system 200 and various types of abrasives 311 that may be included in a CMP slurry 305 to achieve several advantages. Although the CMP slurry 305 is generally described in connection with polishing ruthenium as the conductive material 122, it should be understood that embodiments of the CMP slurry 305 (e.g., various types of abrasives 311 and other components) may also be applicable to other conductive materials 122, such as tungsten, molybdenum, iridium, etc.

[0069] Fig.17A and Fig. 17B The CMP system 200 is shown. The CMP system 200 can be used to remove excess conductive material 122 and to remove excess material of the second ILD 111, as described above in conjunction with Figure 15 to Figure 16 References Fig.17A , the CMP system 200 may include a load lock 201, a cleaning station 205, a high rate platen 207, and a polishing platen 211. The load lock 201 may be used to load a workpiece 400 (see Fig. 17B ) is loaded into the CMP system 200, and then once the CMP process has been completed, the workpiece 400 is unloaded. In some embodiments, the high rate platen 207 can be used for the first CMP process (see Fig.15 ) to polish and remove portions of the conductive material 122 and the etch stop layer stack 112 with a relatively high polishing rate (eg, an overall polishing rate). In addition, the polishing platen 211 may be used for a second CMP process (see Fig.16 ) to polish and remove additional portions of the conductive material 122 and the second ILD 111. The polishing platen 211 may also be used to repair defects and scratches that may occur during the removal of the conductive material 122.

[0070] In an embodiment, workpiece 400 may be loaded into CMP system 200 via load lock 201 and transferred to high rate platen 207 for bulk removal of conductive material 122 during, for example, a first CMP process. Once at high rate platen 207, workpiece 400 may be attached to carrier 301 (see Fig. 17B ), the carrier 301 faces the conductive material 122 toward the surface of the polishing pad 303 connected to the high-rate platen 207 (eg, the outer surface of the workpiece 400).

[0071] Fig. 17B A CMP apparatus 300 of the CMP system 200 is shown. The CMP apparatus can generally be adapted for use in any one of a first CMP process (e.g., using a high rate platen 207) and a second CMP process (e.g., using a polishing platen 211). The polishing pad 303 shown can be a hard polishing pad, which can be used to remove the conductive material 122 relatively quickly, or the polishing pad 303 shown can be a soft polishing pad, which can be used to remove the conductive material 122 more slowly and in a more controlled manner, while also polishing and eliminating defects and scratches that may be caused by the first CMP process. However, any other suitable polishing pad 303 can be used for each of the first CMP process and the second CMP process.

[0072] During the CMP process, the carrier 301 can press the surface of the conductive material 122 against the polishing pad 303. The workpiece 400 and the polishing pad 303 each rotate relative to each other, either in the same direction or counter-rotating in opposite directions. By rotating the polishing pad 303 and the workpiece 400 relative to each other, the polishing pad 303 mechanically grinds away the conductive material 122 and the dielectric material (e.g., the etch stop layer stack 112 or the second ILD 111) for removal. In addition, in some embodiments, the carrier 301 can move the workpiece 400 back and forth along the radius of the polishing pad 303.

[0073] According to various embodiments, mechanical grinding of the polishing pad 303 is assisted by using a CMP slurry 305, which can be dispensed onto the polishing pad 303 by a slurry dispensing system 307. In various embodiments, the CMP slurry 305 includes one or more types of abrasives and reactants. In addition, the CMP slurry 305 can include one or more pH adjusters (e.g., pH adjusters and / or pH buffers). In addition, the CMP slurry 305 can include additives for protecting the conductive material 122 (e.g., corrosion inhibitors), additives for morphology control (e.g., dishing and corrosion reduction), etc., wherein the additives can include molecules, surfactants, and polymers.

[0074] The reactant in the CMP slurry 305 may be a chemical substance that chemically reacts with the conductive material 122 to assist the polishing pad 303 in grinding away the conductive material 122. In some embodiments, the reactant may be an oxidant. For example, the reactant may be a peroxide, such as hydrogen peroxide (H 2 O 2 ), but any other suitable reactant (e.g., oxidant) that will facilitate removal of the conductive material 122 may also be utilized, including other peroxides such as dicumyl peroxide, di-tert-butyl peroxide, cumene hydroperoxide, etc., or combinations thereof. In some embodiments, the oxidant (e.g., H2 O 2 ) is present in a concentration ranging from about 0.01% to about 10% by weight, such as from about 1% to about 2% by weight.

[0075] In some embodiments, CMP slurry 305 may include a surfactant for helping to disperse first reactant 313 and abrasive 311 within CMP slurry 305 and also preventing abrasive 311 from agglomerating during the CMP process. For example, the surfactant may include sodium salts of polyacrylic acid, potassium oleate, sulfosuccinates, sulfosuccinate derivatives, sulfonated amines, sulfonated amides, sulfates of alcohols, alkyl sulfonates, carboxylated alcohols, alkyl aminopropionic acid, alkyl iminodipropionic acid, combinations of these, etc. However, these embodiments are not intended to be limited to these surfactants, as any suitable surfactant may be utilized.

[0076] As discussed above, the CMP slurry 305 includes one or more pH adjusters (e.g., pH adjusters and pH buffers). The pH adjusters help bring the CMP slurry 305 to a desired pH (e.g., between pH 1 and pH 12), while the pH buffers (e.g., pH buffers) help maintain the CMP slurry 305 substantially at the desired pH. In some embodiments, the pH adjusters set and maintain the pH in the range of 4-9. It should be understood that a pH of 4 or above prevents or reduces the generation of toxic ruthenium oxide during the CMP process. Conversely, a pH of 9 or below ensures a sufficiently fast oxidation reaction rate of ruthenium during the CMP process.

[0077] For example, the pH adjuster may include an acidic pH adjuster such as hydrochloric acid, nitric acid, acetic acid, sulfuric acid, phosphoric acid, phthalic acid, etc., other inorganic or organic acids, and mixtures thereof. In addition, the pH adjuster may include an alkaline pH adjuster such as ammonium hydroxide, potassium hydroxide, sodium hydride, tetraalkyl hydroxides (e.g., tetraethylammonium hydroxide or tetrabutylammonium hydroxide), organic amines, and other chemical agents that can be used to adjust the pH toward a more alkaline direction. It should be noted that any suitable combination of these pH adjusters may be utilized.

[0078] The pH buffer stabilizes the CMP slurry 305 at a desired pH range, whether the pH is in the range of 1-4, in the range of 4-9, or in the range of 9-12. For example, a pH buffer for a pH range of 1-4 may include a carboxylic acid, etc. A pH buffer for a pH range of 4-9 may include bis-tri-methane, MES, PIPES, MOPS, (4-(2-hydroxyethyl)-1-piperazineethanesulfonic acid) (HEPES), trimethylglycine (tricine), N,N-dihydroxyethylglycine, phosphate, N-[tris(hydroxymethyl)methyl]-3-aminopropanesulfonic acid) (TAPS), etc. A pH buffer for a pH range of 9-12 may include amines, ammonium hydroxide, etc. It should be noted that any suitable pH buffer (or any suitable combination of pH adjusters) may be utilized.

[0079] As discussed above, the CMP slurry 305 can include other additives. For example, the CMP slurry 305 can include a corrosion inhibitor (e.g., ruthenium corrosion protection). The corrosion inhibitor can include a chemical substance having a functional group that can interact with ruthenium to prevent chemical attack. For example, the corrosion inhibitor can be a surfactant (as described above) and a polymer or other molecule having a functional group, such as an amino acid, an amine, an azole, a pyridine, an imine, a sulfonate, a phosphate, etc. In addition, the CMP slurry 305 can include chemicals for morphology control (e.g., pitting and corrosion reduction). Similarly, the morphology control chemical can be a surfactant or a polymer, including non-ionic, anionic and cationic types, such as polyacrylic acid, polyethylene glycol, polyethyleneimine (PEI), alkyl sulfonates, alkyl ether phosphates, lauryl ether, lauryl amine, quaternary ammonium salts, etc. However, any other suitable additive can be utilized.

[0080] The remainder of the CMP slurry 305 may be a solvent (e.g., a liquid carrier) that may be used to combine the first reactant 313, the abrasive 311, the surfactant, the pH adjuster, and other additives and to allow the mixture to move and disperse onto the polishing pad 303. For example, the solvent of the CMP slurry 305 may be deionized water or alcohol. However, any other suitable solvent may be utilized.

[0081] FIG. 17C to FIG. 17E 305. The abrasive 311 includes particles that facilitate removal of the conductive material 122 and the corresponding dielectric material (in combination with the polishing pad 303). According to various embodiments, the abrasive 311 of the CMP slurry 305 includes titanium dioxide (e.g., titanium oxide or TiO 2 ) and silicon dioxide (e.g., silicon oxide or SiO 2 ). Fig. 17CAn abrasive 311 having a simple structure (eg, a simple abrasive 321 ) is shown such that the abrasive 311 includes a mixture of silica abrasive 321A and titanium dioxide abrasive 321B.

[0082] Fig.17D and Fig.17E An abrasive material 311 having at least a hybrid structure is shown. In particular, Fig.17D An abrasive 311 having a core-shell structure (e.g., core-shell abrasive 322) is shown, such that the abrasive 311 includes one or both of a silica core abrasive 322A and a titanium dioxide core abrasive 322B. As shown, the core-shell abrasive 322 includes a core 322X (e.g., a core structure) and a shell 322Y (e.g., a shell structure). For example, the silica core abrasive 322A has a silica core 322X and a titanium dioxide shell 322Y, while the titanium dioxide core abrasive 322B has a titanium dioxide core 322X and a silica shell 322Y. In addition, Fig.17E An abrasive 311 having a composite structure (e.g., composite abrasive 323) is shown, so that the abrasive 311 includes one or more of a silica carrier abrasive 323A, a titanium dioxide carrier abrasive 323B, or an optional carrier abrasive 323C. As shown, the composite abrasive 323 includes a core 323X (e.g., a carrier structure) in which particles 323Y are dispersed (e.g., decorated or modified) on the outer surface of the core 323X (e.g., a particle structure). For example, the silica carrier abrasive 323A has a silica core 323X, the titanium dioxide carrier abrasive 323B has a titanium dioxide core 323X, and the optional carrier abrasive 323C has a different material core 323X, wherein each type of the composite abrasive 323 is dispersed (e.g., decorated) by silica particles 323Y and / or titanium dioxide particles 323Y.

[0083] By using a material comprising titanium dioxide (e.g., TiO 2 ) and silicon dioxide (e.g., SiO 2 ) abrasive 311. In particular, in the presence of certain oxidizing agents (e.g., peroxides such as hydrogen peroxide), the metal polishing rate (e.g., removal rate) by titanium dioxide abrasives is increased. In embodiments where the conductive material 122 includes ruthenium, the removal rate of the metal by such oxidizing agents (e.g., hydrogen peroxide) is increased. 2 O 2 ) The titanium dioxide abrasive supplemented with the polishing pad 303 can also prevent or reduce contamination of the polishing pad 303, for example, by ruthenium oxide formed during the CMP process. In addition, the absence of an oxidizing agent (e.g., H 2 O 2) has a high silicon oxide removal rate, and when the titanium dioxide abrasive is present with an oxidant, the silicon oxide removal rate decreases. However, the silicon oxide removal rate increases with the titanium dioxide abrasive and the oxidant further supplemented by the silicon dioxide abrasive. Therefore, the titanium dioxide and silicon dioxide abrasive (e.g., the abrasive 311 including the titanium dioxide material and the silicon dioxide material) can be used with a weak oxidant (e.g., a peroxide such as H 2 O 2 ) effectively polishes ruthenium (Ru).

[0084] In addition, the disclosed embodiments achieve the additional advantage of preventing or reducing tool corrosion (e.g., equipment of the CMP system 200). Furthermore, CMP byproducts using such weak oxidants are safer for the environment and users of the CMP system 200 because some weak oxidants tend to react with ruthenium to produce non-toxic gases (e.g., ruthenium hydroxide (Ru(OH) 3 ) rather than toxic gases (e.g., ruthenium tetroxide (RuO 4 )). As shown, the abrasive 311 can include a combination of titanium dioxide and silicon dioxide particles or particles containing titanium dioxide and silicon dioxide portions (or a combination thereof).

[0085] Reference again Fig. 17C , the simple abrasive 321 may include a mixture of a silica abrasive 321A and a titanium dioxide abrasive 321B. Each type of the simple abrasive 321 may have a particle size (e.g., diameter) ranging between about 10nm and about 300nm, such as 150nm. In some embodiments, the ratio of the silica abrasive 321A to the titanium dioxide abrasive 321B may be selected and adjusted to achieve the desired specifications for the CMP process. For example, the silica abrasive 321A may be included in an amount larger, smaller, or substantially the same as the titanium dioxide abrasive 321B. In addition, the particle size of the silica abrasive 321A and the titanium dioxide abrasive 321B may be selected and adjusted. For example, the silica abrasive may have a particle size larger, smaller, or substantially the same as the titanium dioxide abrasive 321B. In some embodiments, the silica abrasive 321A may have a larger amount and a smaller particle size than the titanium dioxide abrasive 321B, and vice versa. For example, the parameters can be selected so that the total exposed surface area of ​​silica abrasive 321A is greater than, less than, or substantially the same as the total exposed surface area of ​​titania abrasive 321B. However, it should be understood that any suitable combination of the parameters described above can be utilized.

[0086] Reference again Fig.17D, the core-shell abrasive 322 may include one or both of a silica core abrasive 322A and a titanium dioxide core abrasive 322B. For example, each of the core-shell abrasive 322 includes a core 322X (e.g., a core structure) and a shell 322Y (e.g., a shell structure). The silica core abrasive 322A has a silica core 322X and a titanium dioxide shell 322Y, while the titanium dioxide core abrasive 322B has a titanium dioxide core 322X and a silica shell 322Y. According to various embodiments, the shell 322Y is chemically bonded to the core 322X. The shell 322Y may cover a small portion, a large portion, or substantially all of the outer surface of the core 322X. In some embodiments, the coverage of the shell 322Y may be in the range of from about 10% to about 90%. As discussed above, each of the abrasive 311 (e.g., the core-shell abrasive 322) may have a particle size between about 10nm and about 300nm, such as 150nm. For example, the core 322X may have a particle size between about 10 nm and about 300 nm, while the shell 322Y may have a particle size between about 10 nm and about 300 nm. (eg, a monolayer) to a thickness of about 10 nm (eg, having a significantly small or substantially negligible effect on the overall particle size of the core-shell abrasive 322). In some embodiments, the shell 322Y can be a monolayer over the core 322X.

[0087] Similar to the above description in conjunction with simple abrasive 321, various parameters of silica core abrasive 322A and titanium dioxide core abrasive 322B can be selected and adjusted to achieve the desired specifications for the CMP process. In addition to changing the amount and particle size of core-shell abrasive 322, the coverage of shell 322Y to core 322X can be selected and adjusted to further achieve the desired specifications. In some embodiments, the shell coverage of silica core abrasive 322A can be greater than, less than, or substantially the same as the shell coverage of titanium dioxide core abrasive 322B. In embodiments where CMP slurry 305 utilizes only one type of core-shell abrasive 322, the shell coverage can be selected to achieve the desired ratio of the surface area between silica and titanium dioxide materials. In addition, any suitable combination of simple abrasive 321 and core-shell abrasive 322 can be utilized. Thus, combinations of the disclosed embodiments may be selected to achieve a desired ratio of surface area between silica and titania materials, and such ratio may range from about 10% to about 90%.

[0088] Reference again Fig.17E, the composite abrasive 323 may include one or more of a silica carrier abrasive 323A, a titania carrier abrasive 323B, or an optional carrier abrasive 323C. In the illustrated embodiment, the silica carrier abrasive 323A has a silica core 323X dispersed by titania particles 323Y, while the titania carrier abrasive 323B has a titania core 323X dispersed by silica particles 323Y. In addition, the optional carrier abrasive 323C has an optional material as the core 323X dispersed by particles 323Y (for example, instead of silica or titania), and the particles 323Y may include one or both of silica and titania particles. In addition, the optional material of the core 323X may include various metals, non-metals (for example, including polymeric materials), or metal oxides, such as gold (Au), silver (Ag), aluminum oxide (Al 2 O 3 )、ZrO 2 ), cesium oxide (CeO 2 ), zinc oxide (ZnO), etc. Any suitable combination of composite abrasives 323 may be utilized in the CMP slurry 305 .

[0089] As discussed above, each of the composite abrasive 323 can have a particle size between about 10nm and about 300nm, such as 150nm. For example, the core 323X can have a particle size between about 30nm and about 300nm, and the microparticles 323Y can have a particle size between about 1nm and about 30nm (e.g., having a significantly smaller or substantially negligible effect on the overall particle size of the composite abrasive 323). According to various embodiments, the microparticles 323Y are chemically bonded to the core 323X and can cover a small portion or a large portion of the outer surface of the core 322X. For example, the coverage of the microparticles 323Y can be in the range of from about 0.05% to about 50%, such as about 10% to about 50%.

[0090] Similar to the above description in conjunction with simple abrasive 321 and core-shell abrasive 322, various parameters of composite abrasive 323 can be selected and adjusted to achieve the desired specifications for CMP process. In addition to changing the amount and particle size of the corresponding type of composite abrasive 323, the coverage of microparticles 323Y to core 323X can be selected and adjusted to further achieve the desired specifications. Similar to the previous embodiment, the microparticle coverage can be selected to achieve the desired ratio of the surface area between silica and titania materials. Parameters related to the size of core 323X and microparticles 323Y can also be selected and adjusted to achieve the desired ratio of the surface area. As noted above, any suitable combination and ratio of exemplary composite abrasive 323 can be utilized. In addition, any suitable combination of simple abrasive 321, core-shell abrasive 322 and composite abrasive 323 can be utilized. Therefore, the desired ratio of the surface area between silica and titania materials can be in the range of from about 10% to about 90%.

[0091] In addition, the first CMP process and the second CMP process can utilize different combinations of embodiments of the abrasive 311. For example, the first CMP process (e.g., a bulk polishing process) can include larger particles than the second CMP process (e.g., a lapping process). In addition, the first CMP process can utilize a simple abrasive 321 while the second CMP process utilizes a hybrid abrasive (e.g., a core-shell abrasive 322 and / or a composite abrasive 323). Because the hybrid abrasive 322 / 323 includes silicon dioxide and titanium dioxide materials in close proximity, the hybrid abrasive 322 / 323 can provide improved control, which may be more important during the second CMP process.

[0092] Overall reference FIG. 17A to FIG. 17E As noted above, embodiments of CMP slurry 305 disclosed herein refer to any suitable combination of reactants, abrasives, surfactants, solvents, and / or corrosion inhibitors described above in conjunction with various embodiments. Once mixed, CMP slurry 305 can be dispensed onto polishing pad 303 via slurry dispensing system 307. In some embodiments, workpiece 400 can be forced into contact with polishing pad 303 by pressing the surface of workpiece 400 against polishing pad 303 via carrier 301. As high-rate platen 207 rotates polishing pad 303 beneath workpiece 400, CMP slurry 305 is applied to the exposed surface of conductive material 122 and second ILD 111 of workpiece 400 to assist in removing conductive material 122.

[0093] By rotating the polishing pad 303 and the workpiece 400 relative to each other using the CMP slurry 305, the polishing pad 303 mechanically grinds away the conductive material 122 and the second ILD 111 with the aid of the abrasive 311 in the CMP slurry 305, thereby achieving the removal of the conductive material 122 and the second ILD 111 at substantially the same removal rate. As shown in the figure, in some embodiments, after the CMP process is performed, the second ILD 111 is removed.

[0094] 18A to 18D An exemplary method of synthesizing abrasives according to some embodiments is shown. As an initial matter, simple abrasive 321 can be formed using any suitable method. For example, simple abrasive 321 can be formed using gas phase synthesis, liquid phase synthesis, sol-gel synthesis, hydrothermal method, etc. or a combination thereof. In addition, these or any suitable methods can be used to synthesize core 322X / 323X and microparticles 323Y that are then used in the process described below.

[0095] refer to Fig.18A , the core-shell abrasive 322 can be formed by synthesizing a core 322X, similar to that described above. In some embodiments, a deposition process is performed to form a shell 322Y over the outer surface of the core 322X. The deposition process includes flowing a precursor over the core 322X to form a film (which becomes the shell 322Y).

[0096] For example, the precursor may include a titanium oxide precursor (e.g., to form a titanium dioxide shell 322Y) or a silicon oxide precursor (e.g., to form a silicon dioxide shell 322Y). The titanium oxide precursor may include tetrakis(dimethylamino)titanium (TDMA-Ti) and titanium tetrachloride (TiCl 4 ) or any suitable organic titanium compound (e.g., TiR 1 R 2 R 3 R 4 , wherein each R is hydrogen, an alkyl group or an alkoxide), and the silicon oxide precursor may include a silane, such as tetrachlorosilane (SiCl 4 ), tris(dimethylamino)silane (TDMAS), bis(ethylmethylamino)silane (BEMAS), bis(diethylamino)silane (BDEAS), etc., or any suitable organosilicon compound (e.g., SiR 1 R 2 R 3 R 4, where each R is hydrogen, an alkyl group, or an alkoxide). As discussed above, the precursor chemically bonds with the core 322X. Thus, Ti-O-Si bonds may form an initial sublayer of the shell 322Y, and then a film of titanium dioxide (e.g., for silica core abrasive 322A) or a film of silicon dioxide (e.g., for titanium dioxide core abrasive 322B) may be formed over the core 322X.

[0097] refer to FIG. 18B to FIG. 18D , composite abrasive 323 can be formed by synthesizing core 323X and microparticle 323Y respectively, similar to described above.In certain embodiments, treatment process is implemented to increase the reactivity of the outer surface of core 323X and / or microparticle 323Y, and application process is implemented to spread microparticle 323Y over the outer surface of core 323X.Similar to core-shell abrasive 322, treatment process includes functional group attached to core 323X and / or microparticle 323Y.It should be understood that the treatment process (for example, in the embodiment implementing both of them) for core 323X and microparticle 323Y is implemented respectively.The functional group attached to core 323X can be considered as core coating 503X, and the functional group attached to microparticle 323Y can be considered as microparticle coating 503Y.Application process includes mixing core 323X with microparticle 323Y, so that microparticle 323Y is joined to core 323X.Mixing can be implemented under dry conditions, in liquid solvent or any suitable method. Optionally, after the application process, a post-treatment process may be performed to remove any unreacted functional groups remaining on the outer surfaces of the core 323X and / or the microparticles 323Y.

[0098] According to some embodiments, the treatment process includes flowing a precursor over core 323X to form core coating 503X and / or flowing over particles 323Y to form particle coating 503Y. For example, the precursor may be selected to form functional groups such as hydroxyl (—OH), amino (—NH 2 ), acyl (-OCR), carboxylate (-COOH), phosphate (-PO 4 ), phosphoryl (-PO 3 ), ether group (-OR), ester group (-COOR), amide group (-NRR), silanol group (-SiOH), thiol group (-SH), azide alkyne (-N 3 R), etc. In some embodiments, the precursors may be ionized to form ions and / or plasmas of those precursors prior to flowing the corresponding precursors over the particles. It should be noted that hydroxyl groups are shown, but any of the above functional groups may constitute coating 503X / 503Y.

[0099] Fig.18BThe treatment process performed on the core 323X and the particles 323Y is shown before the treated particles 323Y are applied to the treated core 323X to form the composite abrasive 323 . Fig. 18C It is shown that a treatment process is performed on the particles 323Y before the treated particles 323Y are applied to the core 323X. Fig.18D The treatment process is shown being performed on the core 323X before the particles 323Y are applied to the treated core 323X.

[0100] exist Fig.19 In the embodiment of the present invention, an interconnect structure 148 is formed over the first ILD 90 to interconnect the underlying electronic components (e.g., FinFETs) to form a functional circuit. The interconnect structure 148 includes a plurality of dielectric layers (e.g., 125, 129, 133) and conductive components (e.g., 141, 143, 145, 147) formed in the plurality of dielectric layers. It should be noted that in the description herein, unless otherwise specified, conductive components and conductive materials refer to conductive components and conductive materials, respectively.

[0101] The dielectric layers 125 / 129 / 133 may also be referred to as intermetallic dielectric (IMD) layers. The IMD layers 125 / 129 / 133 may be formed of one or more suitable dielectric materials such as silicon oxide, silicon nitride, low-k dielectrics such as carbon-doped oxides, ultra-low-k dielectrics such as porous carbon-doped silicon dioxide, combinations of these materials, and the like. The IMD layers 125 / 129 / 133 may be formed by processes such as chemical vapor deposition (CVD), but any suitable process may be utilized. Etch stop layers 127 and 131 may be formed between adjacent IMD layers. The etch stop layers 127 and 131 may be formed of silicon nitride using PECVD, but other dielectric materials such as nitrides, carbides, borides, combinations thereof, and the like may alternatively be used, as well as alternative techniques for forming etch stop layers such as LPCVD, PVD, and the like.

[0102] exist Fig.191, a gate contact 141 is formed to extend through the IMD layer 125, the dielectric material 109, and the semiconductor material 107 to electrically couple to the replacement gate structure 97, for example, through the capping layer 101. As shown, the lower surface of the gate contact 141 physically contacts the upper surface of the underlying capping layer 101 and extends along the upper surface of the underlying capping layer 101. In addition, an upper source / drain contact 143 is formed to extend through the IMD layer 125 to electrically couple to the contact 123. In addition, a conductive line 145 and a via 147 are formed in the IMD layers 129 and 133, respectively. The gate contact 141, the upper source / drain contact 143, the conductive line 145, and the via 147 are formed of one or more conductive materials (e.g., copper, tungsten, cobalt, ruthenium, molybdenum, iridium), and can be formed using any suitable method, such as damascene, dual damascene, etc. It should be noted that the number and location of the conductive features in the interconnect structure 148 are for illustration purposes only and are not limiting. Other conductive features may be formed at other locations. In addition, some of the conductive features formed may not be Fig.19 In the cross section, therefore Fig.19 Not visible in (eg, shown).

[0103] According to some embodiments, gate contact 141 can be formed similarly to that described above in conjunction with contact 123. In particular, a sacrificial oxide (not shown) can be deposited over dielectric layer 125, and a gate contact opening can be formed through the sacrificial oxide, dielectric layer 125, dielectric material 109, and semiconductor material 107 to expose replacement gate structure 97 (e.g., capping layer 101). In embodiments where capping layer 101 is non-conductive (or has a low conductivity), the gate contact opening can be formed through capping layer 101 to expose gate electrode 99. A conductive material can then be deposited to fill the gate contact opening. The conductive material can be a material similar to that described above in conjunction with contact 123 (e.g., ruthenium). After depositing the conductive material, a removal process is performed to remove the conductive material and the portion of the sacrificial oxide located above dielectric layer 125. The remaining conductive material forms gate contact 141.

[0104] For example, the removal process may include a CMP process similar to that described above. In some embodiments, the CMP process utilizes a slurry including any suitable abrasive 311 (or a combination thereof) discussed above. However, the abrasive used in the CMP process for the gate contact 141 may be different from the abrasive used for the contact 123. The selection of the abrasive and its specific parameters may be based in part on the ratio of the sacrificial oxide to the conductive material along the exposed surface of the gate contact 141. When the ratio is relatively high, the abrasive may include an increased total exposed surface area of ​​silicon dioxide. When the ratio is relatively low, the abrasive may include a reduced total exposed surface area of ​​silicon dioxide. Therefore, the abrasive may be synthesized and selected so as to implement the CMP process according to the desired specifications.

[0105] In addition, similar CMP processes utilizing slurries of suitable abrasives 311 may be implemented in forming other conductive features. For example, other portions of the interconnect structure 148 (e.g., conductive features 143, 145, 147) may be formed of similar materials (e.g., ruthenium) and subsequently planarized using a selection of abrasives 311 to remove the respective conductive and dielectric materials at a desired rate. It should be understood that the abrasives 311 used in the respective CMP slurries 305 for each of the applicable CMP processes may also be selected based on the ratio of conductive material (e.g., ruthenium) and dielectric material (e.g., silicon oxide) being planarized. For example, if increased ruthenium polishing is desired, the CMP process may include an abrasive 311 having a high titanium dioxide to silicon dioxide ratio. Conversely, if less ruthenium polishing is desired, the CMP process may include an abrasive 311 having a low titanium dioxide to silicon dioxide ratio.

[0106] Embodiments can achieve advantages. According to various embodiments, the conductive components (e.g., the lower source / drain contacts 123, the gate contacts 141, or other components of the interconnect structure 148) can include ruthenium. After depositing the ruthenium, a CMP process is used to remove excess ruthenium and dielectric material, and the conductive components are planarized with the remaining dielectric material. The CMP process can utilize a CMP slurry 305, which includes an abrasive 311 including titanium dioxide (e.g., effectively removing excess ruthenium) and a hydrogen peroxide oxidizing agent (e.g., as a supplement, effectively preventing contamination of the polishing pad 303). In order to improve the efficiency of removing dielectric materials (e.g., silicon oxide), the abrasive 311 also includes silicon dioxide. Therefore, the CMP process can be more efficient, more effective and implemented with an increased yield.

[0107] In an embodiment, a method includes: forming an opening in a dielectric layer; filling the opening with a conductive material; and performing a chemical mechanical polishing process on the conductive material and the dielectric layer, the chemical mechanical polishing process including a slurry, the slurry including: an abrasive, the abrasive including titanium dioxide-silicon dioxide mixed particles; and an oxidizing agent. In another embodiment, the first core-shell particles of the titanium dioxide-silicon dioxide mixed particles include a titanium dioxide core and a silicon dioxide shell, and wherein the second core-shell particles of the titanium dioxide-silicon dioxide mixed particles include a silicon dioxide core and a titanium dioxide shell. In another embodiment, the first composite particles of the titanium dioxide-silicon dioxide mixed particles include a plurality of silicon dioxide particles bonded to a titanium dioxide carrier particle, and wherein the second composite particles of the titanium dioxide-silicon dioxide mixed particles include a plurality of titanium dioxide particles bonded to a silicon dioxide carrier particle. In another embodiment, the dielectric layer includes silicon oxide, and wherein the conductive material includes ruthenium. In another embodiment, performing the chemical mechanical polishing process includes removing silicon oxide and ruthenium at the same removal rate. In another embodiment, the composite particles of titanium dioxide-silicon dioxide hybrid particles include a plurality of silicon dioxide particles and a plurality of titanium dioxide particles bonded to metal oxide particles. In another embodiment, the metal oxide particles include at least one of aluminum oxide, zirconium oxide, cesium oxide, or zinc oxide. In another embodiment, the opening extends through the dielectric layer and the underlying dielectric layer, and wherein performing the chemical mechanical polishing process includes removing the entire dielectric layer.

[0108] In an embodiment, a chemical mechanical polishing slurry includes: a solvent; mixed abrasive particles dispersed in the solvent, wherein each of the mixed abrasive particles includes a silica portion and a titania portion; an oxidizing agent; a pH adjuster; a pH buffer; and a surfactant. In another embodiment, the first type of mixed abrasive particles includes first silica particles decorated on the outer surface of a first titania carrier particle, and wherein the second type of mixed abrasive particles includes second titania particles decorated on the outer surface of a second silica carrier particle. In another embodiment, each of the mixed abrasive particles includes a silica portion chemically bonded to the titania portion. In another embodiment, the silica portion includes a silica film, wherein the titania portion includes a titania particle, and wherein the silica film covers at least a portion of the outer surface of the titania particle. In another embodiment, the titania portion includes a titania film, wherein the silica portion includes a silica particle, and wherein the titania film covers at least a portion of the outer surface of the silica particle. In another embodiment, the oxidizing agent comprises a peroxide; wherein the pH adjusting agent comprises at least one of hydrogen chloride, nitric acid, ammonium hydroxide, or potassium hydroxide; wherein the pH buffer comprises at least one of a carboxylic acid, bis-trimethylammonium, or an amine; and wherein the surfactant comprises a polymer, the polymer comprising at least one of an amino acid, an amine, an azole, a pyridine, an imine, a sulfonate, or a phosphate.

[0109] In an embodiment, the chemical mechanical polishing slurry includes: a solvent; an oxidizing agent; a first mixed abrasive particle, the first mixed abrasive particle includes silica and a first material, the first material is different from silica; and a second mixed abrasive particle, the second mixed abrasive particle includes titanium dioxide and a second material, the second material is different from titanium dioxide, and the second mixed abrasive particle has a different structure from the first mixed abrasive particle. In another embodiment, the first material is titanium dioxide, and wherein the second material is silica. In another embodiment, the first mixed abrasive particle includes a silica core and a titanium dioxide shell, and wherein the second mixed abrasive particle includes a titanium dioxide core and a silica shell. In another embodiment, the first mixed abrasive particle includes a silica core and discrete titanium dioxide particles, and wherein the second mixed abrasive particle includes a titanium dioxide core and discrete silica particles. In another embodiment, the first material is a metal oxide, and wherein the second material is a metal oxide. In another embodiment, the first hybrid abrasive particle comprises a first core and discrete silica particles, wherein the first core comprises a metal oxide, wherein the second hybrid abrasive particle comprises a second core and discrete titania particles, and wherein the second core comprises a metal oxide.

[0110] Some embodiments of the present application provide a method for forming a chemical mechanical polishing slurry, comprising: forming an opening in a dielectric layer; filling the opening with a conductive material; and performing a chemical mechanical polishing process on the conductive material and the dielectric layer, the chemical mechanical polishing process comprising a slurry, the slurry comprising: an abrasive, the abrasive comprising titanium dioxide-silicon dioxide mixed particles; and an oxidizer.

[0111] In some embodiments, the first core-shell particles of the titanium dioxide-silicon dioxide hybrid particles include a titanium dioxide core and a silica shell, and wherein the second core-shell particles of the titanium dioxide-silicon dioxide hybrid particles include a silica core and a titanium dioxide shell. In some embodiments, the first composite particles of the titanium dioxide-silicon dioxide hybrid particles include a plurality of silica particles bonded to a titanium dioxide carrier particle, and wherein the second composite particles of the titanium dioxide-silicon dioxide hybrid particles include a plurality of titanium dioxide particles bonded to a silica carrier particle. In some embodiments, the dielectric layer includes silicon oxide, and wherein the conductive material includes ruthenium. In some embodiments, performing the chemical mechanical polishing process includes removing the silicon oxide and the ruthenium at the same removal rate. In some embodiments, the composite particles of the titanium dioxide-silicon dioxide hybrid particles include a plurality of silica particles and a plurality of titanium dioxide particles bonded to metal oxide particles. In some embodiments, the metal oxide particles include at least one of aluminum oxide, zirconium oxide, cesium oxide, or zinc oxide. In some embodiments, the opening extends through the dielectric layer and the underlying dielectric layer, and wherein performing the chemical mechanical polishing process includes removing the entire dielectric layer.

[0112] Other embodiments of the present application provide a chemical mechanical polishing slurry, comprising: a solvent; mixed abrasive particles dispersed in the solvent, wherein each of the mixed abrasive particles comprises a silicon dioxide portion and a titanium dioxide portion; an oxidizer; a pH adjuster; a pH buffer; and a surfactant.

[0113] In some embodiments, the first type of hybrid abrasive particles comprises first silica particles decorated on the outer surface of a first titanium dioxide carrier particle, and wherein the second type of hybrid abrasive particles comprises second titanium dioxide particles decorated on the outer surface of a second silica carrier particle. In some embodiments, each of the hybrid abrasive particles comprises the silica portion chemically bonded to the titanium dioxide portion. In some embodiments, the silica portion comprises a silica film, wherein the titanium dioxide portion comprises titanium dioxide particles, and wherein the silica film covers at least a portion of the outer surface of the titanium dioxide particles. In some embodiments, the titanium dioxide portion comprises a titanium dioxide film, wherein the silica portion comprises silica particles, and wherein the titanium dioxide film covers at least a portion of the outer surface of the silica particles. In some embodiments, wherein the oxidant comprises a peroxide; wherein the pH adjuster comprises at least one of hydrogen chloride, nitric acid, ammonium hydroxide or potassium hydroxide; wherein the pH buffer comprises at least one of a carboxylic acid, bis-trimethylammonium or an amine; and wherein the surfactant comprises a polymer comprising at least one of an amino acid, an amine, an azole, a pyridine, an imine, a sulfonate or a phosphate.

[0114] Still other embodiments of the present application provide a chemical mechanical polishing slurry, comprising: a solvent; an oxidizer; first mixed abrasive particles, the first mixed abrasive particles comprising silicon dioxide and a first material, the first material being different from silicon dioxide; and second mixed abrasive particles, the second mixed abrasive particles comprising titanium dioxide and a second material, the second material being different from titanium dioxide, the second mixed abrasive particles having a structure different from that of the first mixed abrasive particles.

[0115] In some embodiments, the first material is titanium dioxide, and wherein the second material is silicon dioxide. In some embodiments, the first hybrid abrasive particles include a silicon dioxide core and a titanium dioxide shell, and wherein the second hybrid abrasive particles include a titanium dioxide core and a silicon dioxide shell. In some embodiments, the first hybrid abrasive particles include a silicon dioxide core and discrete titanium dioxide particles, and wherein the second hybrid abrasive particles include a titanium dioxide core and discrete silicon dioxide particles. In some embodiments, the first material is a metal oxide, and wherein the second material is the metal oxide. In some embodiments, the first hybrid abrasive particles include a first core and discrete silicon dioxide particles, wherein the first core includes the metal oxide, wherein the second hybrid abrasive particles include a second core and discrete titanium dioxide particles, and wherein the second core includes the metal oxide.

[0116] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method for forming a chemical mechanical polishing slurry, comprising: forming an opening in the dielectric layer; filling the opening with a conductive material; as well as A chemical mechanical polishing process is performed on the conductive material and the dielectric layer, wherein the chemical mechanical polishing process includes a slurry, and the slurry includes: an abrasive, the abrasive comprising titanium dioxide-silicon dioxide mixed particles; as well as Oxidants.

2. The method according to claim 1, wherein: The first core-shell particles of the titania-silica hybrid particles include a titania core and a silica shell, and wherein the second core-shell particles of the titania-silica hybrid particles include a silica core and a titania shell.

3. The method according to claim 1, wherein: The first composite particle of the titania-silica hybrid particle includes a plurality of silica particles bonded to a titania support particle, and wherein the second composite particle of the titania-silica hybrid particle includes a plurality of titania particles bonded to a silica support particle.

4. The method according to claim 1, wherein: The dielectric layer comprises silicon oxide, and wherein the conductive material comprises ruthenium.

5. The method according to claim 4, wherein: Performing the chemical mechanical polishing process includes removing the silicon oxide and the ruthenium at the same removal rate.

6. The method according to claim 1, wherein: The composite particles of the titania-silicon dioxide mixed particles include a plurality of silicon dioxide particles and a plurality of titania particles bonded to metal oxide particles.

7. The method according to claim 6, wherein: The metal oxide particles include at least one of aluminum oxide, zirconium oxide, cesium oxide or zinc oxide.

8. The method according to claim 1, wherein: The opening extends through the dielectric layer and an underlying dielectric layer, and wherein performing the chemical mechanical polishing process includes removing the entire dielectric layer.

9. A chemical mechanical polishing slurry comprising: Solvents; mixed abrasive particles dispersed in the solvent, wherein each of the mixed abrasive particles includes a silicon dioxide portion and a titanium dioxide portion; Oxidants; pH adjuster; pH buffers; and Surfactant.

10. A chemical mechanical polishing slurry comprising: Solvents; Oxidants; first hybrid abrasive particles, the first hybrid abrasive particles comprising silicon dioxide and a first material, the first material being different from silicon dioxide; as well as The second mixed abrasive particles include titanium dioxide and a second material, the second material is different from titanium dioxide, and the second mixed abrasive particles have a different structure from the first mixed abrasive particles.

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