A method for detecting locked input-output logic

Abstract

The present invention discloses a method for detecting the locking input and output logic, belonging to the field of fault detection of electronic circuit systems, including: determining the logic unit that executes the locking function, constructing a logic judgment function, calculating the theoretical output signal and the clock coefficient of the logic judgment; setting the dynamic clock offset range of the input signal, and setting the dynamic clock offset threshold of the input signal based on the importance degree; calculating the clock coefficient after dynamic clock offset simulation and the average value of the clock coefficients simulated by dynamic clock offset; evaluating the response fault condition of the logic unit; calculating all the theoretical output signals output by the logic unit based on the logic judgment function, calculating the matching degree of the output response, and evaluating whether the output logic response of the logic unit is normal. The present invention significantly improves the detection efficiency of the locking logic, and can also be applied to chip design verification, hardware circuit fault diagnosis and embedded system reliability evaluation.

Description

Technical Field

[0001] The present invention relates to the field of fault detection of electronic circuit systems, and particularly to a method for detecting the locking input and output logic. Background Art

[0002] In a digital circuit system, the functional correctness of a locking logic unit (such as a latch, a register, a tri-state buffer, etc.) directly affects the system reliability; the delay detection of the output and output logic judgment and the accuracy detection of the output signal are very crucial for ensuring the normal use of the locking logic unit. In the prior art, the detection methods or systems for the locking logic unit mainly have the following defects:

[0003] 1. Insufficient static detection coverage: Traditional logic detection only verifies fixed input combinations, cannot cover dynamic clock deviations, and cannot verify the fault conditions of random dynamic clock deviations;

[0004] 2. Lack of a quantitative standard for response verification: Relying on manual interpretation of the output waveform, the misjudgment rate is high. Therefore, there is an urgent need for a new method for detecting the locking input and output logic. Summary of the Invention

[0005] In view of the above deficiencies of the prior art, the present invention provides a method for detecting the locking input and output logic, which evaluates the response faults of the logic unit and the output logic response faults by randomly dynamically simulating the clock offset of the logic unit.

[0006] To achieve the above invention purpose, the technical solution adopted by the present invention is as follows:

[0007] Provide a method for detecting the locking input and output logic, which includes:

[0008] Step S1: Determine the logic unit that performs the locking function, establish an input signal set and an output signal set, set the clock constraint of the logic unit, construct a logic judgment function, calculate the theoretical output signal and the clock coefficient of the logic judgment;

[0009] Step S2: Characterize the importance of the input signal according to the frequency of the input signal input to the logic unit, set the dynamic clock offset range of the input signal, and set the dynamic clock offset threshold of the input signal based on the importance;

[0010] Step S3: Randomly dynamically simulate the clock offset of the input signal based on the dynamic clock offset range, and calculate the clock coefficient after the dynamic clock offset simulation and the average value of the clock coefficients simulated by the dynamic clock offset;

[0011] Step S4: Evaluate the response fault condition of the logic unit according to the error value between the average value of the clock coefficients and the clock coefficient;

[0012] Step S5: Calculate all theoretical output signals output by the logic unit based on the logic judgment function, construct a matching degree function for the output response, calculate the matching degree of the output response, and evaluate whether the output logic response of the logic unit is normal.

[0013] Further, step S1 includes:

[0014] Step S11: Determine the logic unit that executes the locking function, and establish the input signal set and output signal set of the logic unit of the logic unit, where is the number of input signals, N is the number of output signals, M is the number of output signals, is the N th input signal, the M th output signal;

[0015] Step S12: Set the clock constraints of the logic unit, including the setup time , hold time and propagation delay . The setup time represents the minimum time for the input signal to remain stable before the active edge of the clock. The hold time represents the minimum time for the input signal to remain stable after the active edge of the clock. The propagation delay represents the time interval from the input change to the output stability;

[0016] Step S13: According to the clock constraints of the logic unit and the logic judgment function executed by the logic unit, establish the logic judgment function of each logic function, and calculate the theoretical output signal and the clock coefficient of the logic judgment.

[0017] Further, the logic judgment function is:

[0018] ;

[0019] where is the output signal function, is the theoretical output signal, m is the number of the theoretical output signal, is the set of input signals required for the logic judgment, is the input signal set the I th input signal in i is the number of the input signal in the input signal set is the number of the input signal in the input signal set is the input signal in the input signal set , I is the input signal set The number of input signals, is the clock coefficient for logical judgment, is the mapping function of the input signal, is the total mapping function, are respectively the setup time, hold time, and propagation delay of the input signal during the logical judgment process, is the natural logarithm function, are respectively the weight coefficients of the influence of the setup time, hold time, and propagation delay on the clock coefficient.

[0020] Furthermore, step S2 includes:

[0021] Step S21: Calculate the frequency of the input signals required when the logic unit outputs each output signal , is the number of times the output signal is used, and use the frequency as the importance degree coefficient of the input signal for the logic unit;

[0022] Step S22: Set the dynamic clock offset range of the input signal , and calculate the dynamic clock offset threshold of the input signal ; is the maximum allowable clock deviation amount.

[0023] Furthermore, step S3 includes:

[0024] Step S31: Randomly select a dynamic clock offset value from the dynamic clock offset range , compare the dynamic clock offset value with the dynamic clock offset threshold . If it satisfies , then use the dynamic clock offset value as the clock offset simulation value of the input signal , and execute step S32. Otherwise, randomly select a new dynamic clock offset value from the dynamic clock offset range ;

[0025] Step S32: Allocate the clock offset simulation value according to the weight coefficient to obtain the setup time simulation value , hold time simulation value , and propagation delay simulation value corresponding to the input signal ;

[0026] ;

[0027] Step S33: Repeat steps S31 - S32 to obtain the setup time simulation value, hold time simulation value, and propagation delay simulation value of each input signal under the dynamic clock skew simulation condition;

[0028] Step S34: Calculate the clock coefficient under the dynamic clock skew simulation condition ;

[0029] ;

[0030] wherein, are respectively the setup time simulation value, hold time simulation value, and propagation delay simulation value of the input signal under the dynamic clock skew simulation condition;

[0031] Step S35: Repeat steps S31 - S34 and conduct times of dynamic clock skew simulations within the dynamic clock skew range U to obtain the clock coefficients calculated after each dynamic clock skew simulation;

[0032] Step S36: Calculate the average value of the clock coefficients simulated by the dynamic clock skew;

[0033] ;

[0034] wherein, u is the simulation number of the dynamic clock skew, is the u th clock coefficient calculated by the dynamic clock skew simulation.

[0035] Furthermore, step S4 is specifically as follows:

[0036] Calculate the error value between the average value of the clock coefficients and the clock coefficient , and evaluate the response failure condition of the logic unit based on the allowable error threshold ;

[0037] If , it is determined that the logic unit has a response failure;

[0038] If , it is determined that the logic unit has no response failure.

[0039] Furthermore, step S5 specifically includes:

[0040] Step S51: Based on the logic judgment function for each logic judgment function implemented by the logic unit, calculate all the theoretical output signals output by the logic unit, construct a matching degree function for the output response, and according to the theoretical output signals With the true output signal Calculate the matching degree of the output response of the calculation logic unit ,

[0041] Step S52: Based on the set matching degree threshold , evaluate whether the output logic response of the evaluation logic unit is normal;

[0042] If , then the output logic response of the logic unit is normal. If , then the output logic response of the logic unit is abnormal.

[0043] Furthermore, the matching degree function of the output response is:

[0044] ;

[0045] Wherein, , is the weight coefficient of the clock deviation, is the weight coefficient of the output signal error.

[0046] The beneficial effects of the present invention are as follows: The present invention calculates the theoretical output signal and the clock coefficient of the logic judgment by establishing a logic judgment function that realizes the logic judgment function within the logic unit, constructs a matching degree function of the output response, and evaluates whether the output logic response of the logic unit fails. And, by randomly dynamically simulating the clock offset to characterize the possible clock deviation that may actually occur in the logic unit, it is used to evaluate whether the logic unit has a response failure, solving the problem of insufficient timing coverage of traditional static detection. The present invention significantly improves the detection efficiency of the locking logic and can also be applied to chip design verification, hardware circuit fault diagnosis, and embedded system reliability evaluation. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 It is a flowchart of the locking input and output logic detection method. DETAILED DESCRIPTION OF THE INVENTION

[0048] The following describes the specific embodiments of the present invention to facilitate those skilled in the art of the present technology to understand the present invention. However, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those of ordinary skill in the art of the present technology, as long as various changes are within the spirit and scope of the present invention defined and determined by the appended claims, these changes are obvious, and all inventions made using the inventive concept of the present invention are within the scope of protection.

[0049] As Figure 1 shown, a locking input and output logic detection method includes:

[0050] Step S1: Determine the logic unit that performs the locking function, establish the input signal set and output signal set, set the clock constraint of the logic unit, construct the logic judgment function, and calculate the theoretical output signal and the clock coefficient of the logic judgment. Step S1 specifically includes:

[0051] Step S11: Determine the logic unit that performs the locking function and establish the input signal set of the logic unit and the output signal set , where N is the number of input signals, M is the number of output signals, is the N th input signal, the M th output signal;

[0052] Step S12: Set the clock constraint of the logic unit, including the setup time , hold time and propagation delay . The setup time represents the minimum time for the input signal to remain stable before the active edge of the clock, and the hold time represents the minimum time for the input signal to remain stable after the active edge of the clock. The propagation delay represents the time interval from the input change to the output stability;

[0053] Step S13: According to the clock constraint of the logic unit and the logic judgment function performed by the logic unit, establish the logic judgment function of each logic function, and calculate the theoretical output signal and the clock coefficient of the logic judgment.

[0054] ;

[0055] where is the output signal function, is the theoretical output signal, m is the number of the theoretical output signal, is the set of input signals required for the logic judgment, is the input signal set the I th input signal in, i is the number of the input signal in the input signal set , is the input signal in the input signal set , I is the input signal set the number of input signals in, is the clock coefficient of the logic judgment, is the mapping function of the input signal, is the total mapping function, are respectively the setup time, hold time, and propagation delay of the input signal during the logic judgment process, is the natural logarithm function, are respectively the weight coefficients of the influence of the setup time, hold time, and propagation delay on the clock coefficient, and satisfy , generally take .

[0056] In this embodiment, the theoretical output signal of each logic judgment function executed by the logic unit is output through the logic judgment function, and the mapping function

[0057] maps each input signal to the corresponding logical operator. For example, 0 and 1, 0 represents false, and 1 represents true, and the total mapping function is used to integrate all logical operators and map them to the corresponding output signal function In, the output signal function generates the logical operation tags required for the output signal. In the substation automation system, the input signals of the embodiment include but are not limited to the signals accessed by the auxiliary contacts of equipment such as circuit breakers, disconnectors, and earthing switches in the circuit system. The logic unit realizes different anti-maloperation interlocking functions and forced interlocking functions through the judgment of the accessed signals; it can cover all aspects such as substation operation, operation, and maintenance. An independent logic judgment function unit can be built inside the logic unit to control and operate equipment such as circuit breakers and motor-operated disconnectors.

[0058] The input signal objects of the logic judgment function include: neutral point earthing disconnector of the main transformer, on-load tap-changer of the main transformer, motor-operated disconnector, signal restoration, commissioning and decommissioning of the microcomputer protection device, switching of the microcomputer protection setting group, etc.

[0059] During the logic judgment process, the clock coefficient when generating each output signal is calculated according to the clock error. The clock coefficient represents the clock offset degree during the logic judgment process, and the fault condition of the output response of the logic unit can be reflected through the clock coefficient.

[0060] Step S2: Characterize the importance degree of the input signal according to the frequency of the input signal input to the logic unit, set the dynamic clock offset range of the input signal, and set the dynamic clock offset threshold of the input signal based on the importance degree. Step S2 specifically includes:

[0061] Step S21: Calculate the frequency of the input signal required for the logic unit to output each output signal

[0062] , , is the number of times the output signal is used, and the frequency is used as the importance degree coefficient of the input signal for the logic unit;

[0063] When the logic unit executes different logic judgment functions, sometimes multiple input signals are required, and the input signals required between different logic judgment functions are neither independent nor unique. The higher the frequency of use of the input signal for the logic unit, the more important it is to the logic unit. The clock skew of the input signal often causes fluctuations and abnormalities in the signal output of the logic unit.

[0064] Step S22: Set the dynamic clock skew range of the input signal , and calculate the input signal 's dynamic clock skew threshold ; is the maximum allowable clock deviation.

[0065] The dynamic clock skew range is used as the ideal clock fluctuation range in the process of processing the input and output signals of the logic unit. By introducing the simulation of random dynamic clock skew, the clock skew caused by factors such as signal processing delay fluctuations in the actual logic unit during the signal processing process can be simulated, so as to more comprehensively detect the latch input and output logic. The simulation of random dynamic clock skew introduced in the present invention meets the randomness requirements of the signal transmission, processing, etc.

[0066] Step S3: Perform random dynamic simulation on the clock skew of the input signal based on the dynamic clock skew range, and calculate the clock coefficient after the dynamic clock skew simulation, and the average value of the clock coefficients simulated by the dynamic clock skew. Step S3 specifically includes:

[0067] Step S31: Randomly select a dynamic clock skew value from the dynamic clock skew range , compare the dynamic clock skew value with the dynamic clock skew threshold . If it meets , then use the dynamic clock skew value as the clock skew simulation value of the input signal , and execute step S32. Otherwise, randomly select a dynamic clock skew value again from the dynamic clock skew range ;

[0068] Step S32: Allocate the clock skew simulation value according to the weight coefficient to obtain the setup time simulation value , hold time simulation value , and propagation delay simulation value corresponding to the input signal ;

[0069] ;

[0070] Step S33: Repeat steps S31 - S32 to obtain the setup time simulation value, hold time simulation value, and propagation delay simulation value of each input signal under the dynamic clock skew simulation condition;

[0071] Step S34: Calculate the clock coefficient under the dynamic clock skew simulation condition ;

[0072] ;

[0073] wherein, are respectively the setup time simulation value, hold time simulation value, and propagation delay simulation value of the input signal under the dynamic clock skew simulation condition;

[0074] Step S35: Repeat steps S31 - S34 to perform times of dynamic clock skew simulations within the dynamic clock skew range U to obtain the clock coefficients calculated after each dynamic clock skew simulation;

[0075] Step S36: Calculate the average value of the clock coefficients simulated by the dynamic clock skew ;

[0076] ;

[0077] wherein, u is the simulation number of the dynamic clock skew, is the u th clock coefficient calculated by the dynamic clock skew simulation.

[0078] Step S4: Evaluate the response fault condition of the logic unit according to the error value between the average value of the clock coefficients and the clock coefficient. Specifically, it includes:

[0079] Calculate the error value between the average value of the clock coefficients and the clock coefficient , and evaluate the response fault condition of the logic unit based on the allowed error threshold ;

[0080] If , it is determined that the logic unit has a response fault;

[0081] If , it is determined that the logic unit has no response fault.

[0082] Step S5: Calculate all theoretical output signals output by the logic unit based on the logic judgment function, construct a matching degree function for the output response, calculate the matching degree of the output response, and evaluate whether the output logic response of the logic unit is normal. Step S5 specifically includes:

[0083] Step S51: Based on the logic judgment function for implementing each logic judgment function in the logic unit, calculate all theoretical output signals output by the logic unit, and calculate the matching degree of the output response of the logic unit according to the theoretical output signals and the actual output signals ; ;

[0084] ;

[0085] wherein, , is the weight coefficient of the clock deviation, indicating the influence degree of the clock deviation on the output response, and is taken according to the system's requirement for the output signal delay, generally taken as 0.6 - 0.8, is the weight coefficient of the output signal error, and is taken according to the influence degree of the output signal error on the system, generally taken as 0.7 - 0.95;

[0086] Step S52: Based on the set matching degree threshold , evaluate whether the output logic response of the logic unit is normal;

[0087] If , then the output logic response of the logic unit is normal. If , then the output logic response of the logic unit is abnormal.

[0088] The matching degree threshold is set according to the accuracy requirement for the logic unit in the system, generally taken as 0.85 - 0.95. The matching degree of the output response is quantified by constructing a membership degree function of the output response to provide the robustness of the detection result.

[0089] The present invention calculates the theoretical output signals and the clock coefficient of the logic judgment by establishing a logic judgment function for implementing the logic judgment function in the logic unit, constructs a matching degree function for the output response to evaluate whether there is a fault in the output logic response of the logic unit. Moreover, the clock deviation that may actually occur in the logic unit is characterized by randomly dynamically simulating the clock offset, which is used to evaluate whether the logic unit has a response fault, and solves the problem of insufficient timing coverage in traditional static detection. The present invention significantly improves the detection efficiency of the locking logic, and can also be applied to chip design verification, hardware circuit fault diagnosis, and reliability evaluation of embedded systems.

Claims

1. A method for detecting the locking input / output logic, characterized in that, Including: Step S1: Determine the logic unit that performs the locking function, establish the input signal set and output signal set, set the clock constraint of the logic unit, construct the logic judgment function, calculate the theoretical output signal and the clock coefficient of the logic judgment. Step S2: Characterize the importance of the input signal according to the frequency at which the input signal enters the logic unit, set the dynamic clock offset range of the input signal, and set the dynamic clock offset threshold based on the importance. Step S3: Perform random dynamic simulation on the clock offset of the input signal based on the dynamic clock offset range, and calculate the clock coefficient after the dynamic clock offset simulation and the average value of the clock coefficients simulated by the dynamic clock offset. Step S4: Evaluate the response failure condition of the logic unit according to the error value between the average clock coefficient and the clock coefficient. Step S5: Calculate all the theoretical output signals output by the logic unit based on the logic judgment function, construct the matching degree function of the output response, calculate the matching degree of the output response, and evaluate whether the output logic response of the logic unit is normal.

2. The latching input / output logic detection method according to claim 1, wherein The said step S1 includes: Step S11: Determine the logic unit that performs the locking function and establish the input signal set of the logic unit and the output signal set , where N is the number of input signals, M is the number of output signals, is the N th input signal, the M th output signal; Step S12: Set the clock constraints of the logic unit, including the setup time , hold time and propagation delay . The setup time represents the minimum time for the input signal to remain stable before the active edge of the clock. The hold time represents the minimum time for the input signal to remain stable after the active edge of the clock. The propagation delay represents the time interval from the input change to the output stability; Step S13: According to the clock constraint of the logic unit and the logic judgment function performed by the logic unit, establish the logic judgment function of each logic function, and calculate the theoretical output signal and the clock coefficient of the logic judgment.

3. The locking input / output logic detection method according to claim 2, characterized in that, The said logic judgment function is: ； Among them, is the output signal function, is the theoretical output signal, m is the number of the theoretical output signal, is the set of input signals required for logical judgment, is the set of input signals the I th input signal in i the set of input signals is the number of the input signal in the set of input signals is the set of input signals the input signal in I is the set of input signals is the number of input signals in the set of input signals is the clock coefficient of logical judgment, is the mapping function of the input signal, is the total mapping function, are respectively the setup time, hold time and propagation delay of the input signal in the logical judgment process, is the natural logarithm function, are respectively the weight coefficients of the influence of the setup time, hold time and propagation delay on the clock coefficient.

4. The locking input / output logic detection method according to claim 3, wherein The said step S2 includes: Step S21: Calculate the frequency of the input signals required for each output signal output by the logic unit , for the number of times the output signal is used, and use the frequency as the importance coefficient of the input signal for the logic unit; Step S22: Set the dynamic clock skew range of the input signal , and calculate the input signal 's dynamic clock skew threshold ; is the maximum allowable clock deviation amount.

5. The locking input / output logic detection method according to claim 4, wherein The said step S3 includes: Step S31: From the dynamic clock offset range A dynamic clock offset value is randomly selected within , compare the dynamic clock offset value With dynamic clock skew threshold If the size of , then the dynamic clock offset value As input signal The clock offset simulation value is, step S32 is executed, otherwise, the dynamic clock offset range is A dynamic clock offset value is randomly re-selected within the Step S32: According to the weight coefficient allocate the clock offset simulation value to obtain the setup time simulation value corresponding to the input signal , hold time simulation value and propagation delay simulation value ; ； Step S33: Repeat steps S31 - S32 to obtain the setup time simulation value, hold time simulation value, and propagation delay simulation value of each input signal under the condition of dynamic clock offset simulation. Step S34: Calculate the clock coefficient under the dynamic clock offset simulation condition ; ； Among them, are the input signal, the simulated setup time value, hold time value, and propagation delay value under dynamic clock skew simulation conditions, respectively; Step S35: Repeat steps S31 - S34 to perform dynamic clock offset simulations within the dynamic clock offset range U times, and obtain the clock coefficients calculated after each dynamic clock offset simulation ; Step S36: Calculate the average value of the clock coefficients simulated by the dynamic clock offset ; ； Among them, u is the serial number of the simulation times of the dynamic clock offset, is the u clock coefficient calculated by the u -th dynamic clock offset simulation.

6. The locking input / output logic detection method according to claim 5, wherein The said step S4 specifically is: Calculate the average value of the clock coefficient and the clock coefficient the error value between, based on the allowed error threshold evaluate the response failure condition of the logic unit; If , it is determined that there is a response failure in the determination logic unit; If , it is determined that the logic unit does not have a response failure.

7. The locking input / output logic detection method according to claim 6, wherein The said step S5 specifically includes: Step S51: Based on the logic functions that implement each logical judgment function in the logic unit, calculate all the theoretical output signals output by the logic unit, construct a matching degree function for the output response, and according to the theoretical output signals and the actual output signals calculate the matching degree of the output response of the logic unit , Step S52: Based on the set matching degree threshold , evaluate whether the output logic response of the logic unit is normal; If , the output logic response of the logic unit is normal. If , the output logic response of the logic unit is abnormal.

8. The locking input / output logic detection method according to claim 7, characterized in that The said matching degree function of the output response is: ； Among them, , is the weight coefficient of the clock deviation, is the weight coefficient of the output signal error.

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