Manufacturing method of package substrate

Abstract

A method for manufacturing a package substrate according to an example includes: a preparation step of preparing a substrate including a core layer and an insulating layer formed on the core layer; a patterning step of selectively performing plasma etching on the insulating layer by using an etching mask to form a patterned insulating layer; and a manufacturing step of manufacturing the package substrate from the substrate on which the patterned insulating layer is formed. The etching mask includes an organic compound. The atmosphere temperature in the patterning step is 120 DEG C or less. In this case, it is possible to manufacture a package substrate in which the convenience of the manufacturing process of the package substrate is improved and the electrical reliability is improved.

Description

Technical Field

[0001] The example relates to a method for manufacturing a packaged substrate. Background Art

[0002] In the manufacture of electronic products, the process of implementing a circuit on a semiconductor wafer is called the front-end process (FE), and the process of assembling the wafer into a state usable in an actual product is called the back-end process (BE). The subsequent processes include a packaging process.

[0003] Recently, the four core technologies in the semiconductor industry that can enable the rapid development of electronic products are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology is developing in various forms such as a line width in the nanometer unit below the micron, more than ten million units (Cells), high-speed operation, and a large amount of heat dissipation. However, there is no corresponding perfect packaging technology to support it. Therefore, the electrical performance of the semiconductor is determined more by the packaging technology and its electrical connection than by the performance of the semiconductor technology itself.

[0004] Recently, research has been carried out on applying ceramic materials to high-end packaged substrates. By forming a through-hole in the ceramic material substrate and applying a conductive substance to the through-hole, the wiring length between the device and the motherboard can be shortened, and excellent electrical characteristics can be obtained.

[0005] Prior Art Documents

[0006] Patent Documents

[0007] Patent Document 1: Korean Patent Publication No. 10-2022-0135842

[0008] Patent Document 2: Korean Patent Publication No. 10-2014-0085023 Summary of the Invention

[0009] Technical Problem

[0010] An object of the example is to provide a method for manufacturing a packaged substrate, in which the process convenience is improved and the electrical reliability is enhanced.

[0011] Solution to the Problem

[0012] A method for manufacturing a packaged substrate according to an embodiment of the present specification includes: a preparation step of preparing a substrate including a core layer and an insulating layer formed on the core layer; a patterning step of selectively performing plasma etching on the insulating layer using an etching mask to form a patterned insulating layer; and a manufacturing step of manufacturing a packaged substrate from the substrate on which the patterned insulating layer is formed.

[0013] The etching mask includes an organic compound.

[0014] The atmosphere temperature of the above patterning step is below 120°C.

[0015] In the above patterning step, the above etching mask can be arranged in contact with the upper surface of the above insulating layer.

[0016] The above insulating layer may include an area to be etched.

[0017] The above patterning step may include: an etching process of etching a part of the above insulating layer in the above area to be etched; and a stabilization process of reducing the atmosphere temperature of the above patterning step.

[0018] In the above patterning step, the above etching process and the above stabilization process can be taken as one cycle, and the cycle is implemented more than twice for each insulating layer.

[0019] Each time the above etching process can be carried out for 200 seconds to 700 seconds.

[0020] The above etching process can be carried out in an atmosphere including a first etching gas and a second etching gas.

[0021] The above first etching gas can be a fluorine-based gas.

[0022] The above second etching gas can be oxygen.

[0023] The plasma power of the above etching process can be 1.5 kW or more and 3 kW or less.

[0024] The thickness of the above etching mask can be 5 μm to 40 μm.

[0025] Before the above manufacturing step after the above patterning step, a cleaning step of ultrasonically cleaning the above substrate can also be included.

[0026] The vibration frequency of the above cleaning step can be 30 kHz to 200 kHz.

[0027] The above patterned insulating layer may include a through hole formed along the thickness direction of the above insulating layer.

[0028] The diameter of the above through hole can be 3 μm to 50 μm.

[0029] The above package substrate may include: the above core layer; and the above patterned insulating layer disposed on the above core layer.

[0030] The above package substrate may include a conductive layer formed in contact with at least a part of the upper surface of the above patterned insulating layer.

[0031] The peel strength of the conductive layer on the upper surface of the patterned insulating layer may be 200 gf / cm or more.

[0032] Effects of the Invention

[0033] The encapsulation substrate manufacturing method of the example can manufacture an encapsulation substrate with improved process convenience and enhanced electrical reliability. Description of the Drawings

[0034] Figure 1 Conceptual diagram for explaining the preparation step of the example.

[0035] Figure 2A and Figure 2B Conceptual diagrams for explaining the patterning step of the example, respectively.

[0036] Figure 3 Conceptual diagram for explaining the encapsulation substrate manufactured according to the manufacturing method of the example.

[0037] Description of Reference Numerals

[0038] 100: Substrate

[0039] 10: Core layer

[0040] 20: Insulating layer

[0041] 21: Patterned insulating layer

[0042] 22: Etching target area

[0043] 25: Through hole

[0044] 30: Etching mask

[0045] 40: Conductive layer

[0046] 50: First redistribution layer

[0047] 200: Encapsulation substrate Detailed Description of the Invention

[0048] Hereinafter, embodiments will be described in detail with reference to the drawings, which can be easily implemented by those of ordinary skill in the technical field to which the present invention pertains. However, the present invention can be implemented in various different forms and is not limited to the embodiments described herein. Throughout the specification, the same reference numerals are assigned to similar parts.

[0049] Throughout this specification, in a Markush-type expression, the term "combinations thereof" refers to one or more mixtures or combinations selected from the group consisting of multiple structural elements described in the Markush-type expression, and means including one or more selected from the group consisting of the above multiple structural elements.

[0050] Throughout this specification, terms such as "first", "second" or "A", "B" are used to distinguish the same terms. Also, unless there is a clearly different meaning in the context, a singular expression includes a plural expression.

[0051] In this specification, "~" may mean that the compound contains a compound equivalent to "~" or a derivative of "~".

[0052] In this specification, B being on A means that B is directly connected to A, or B is on A with other layers in between, and it is not limited to the interpretation that B is connected to the surface of A.

[0053] In this specification, B being connected to A means that A is directly connected to B, or A and B are connected through other structural elements. Unless otherwise specifically mentioned, it is not limited to the interpretation that A is directly connected to B.

[0054] In this specification, unless otherwise specified, a singular expression is interpreted to include the meaning of a singular or plural quantity as interpreted in the context.

[0055] In this specification, the shapes, relative sizes, angles, etc. of the various structures in the figures are illustrative and may be exaggerated for the purpose of illustration, and the claims are not limited to the figures for interpretation.

[0056] In this specification, A being adjacent to B means that A is in contact with B, or A and B are not in contact but are close. In this specification, unless otherwise specifically mentioned, the expression that A is adjacent to B is not limited to the interpretation that A is in contact with B.

[0057] In this specification, unless otherwise stated, a fine line means a line with a width of 5 μm or less. Exemplarily, a line with a width of 1 to 4 μm or less.

[0058] Hereinafter, examples will be described.

[0059] A method for manufacturing an encapsulation substrate of an example includes: a preparation step of preparing a substrate including a core layer and an insulating layer formed on the core layer; a patterning step of selectively performing plasma etching on the insulating layer using an etching mask to prepare a patterned insulating layer; and a manufacturing step of manufacturing an encapsulation substrate from the substrate on which the patterned insulating layer is formed.

[0060] Figure 1 A conceptual diagram for explaining the preparation step of the example. Referring to the above Figure 1 , a method for manufacturing an encapsulation substrate of the example will be described.

[0061] Preparation step

[0062] In the preparation step, a substrate 100 including a core layer 10 and an insulating layer 20 formed on the core layer 10 can be prepared.

[0063] The core layer 10 can have the shape of a substrate. The core layer 10 is not limited as long as it can be used as a substrate for electronic components.

[0064] The raw material of the core layer 10 can be an organic material, glass, alumina, aluminum nitride, silicon carbide, silicon nitride, etc.

[0065] The core layer 10 can be a glass core. Exemplarily, the core layer 10 can be an alkaline borosilicate flat glass, a non-alkaline borosilicate flat glass, a non-alkaline alkaline earth borosilicate flat glass, etc. The core layer 10 can be a glass substrate for electronic devices. Exemplarily, it can be manufactured by Schott, AGC, Corning, etc., but is not limited thereto.

[0066] The core layer 10 can include: an upper surface; and a side surface formed along the thickness direction of the core layer 10 connected to the upper surface. The surface of the core layer 10 can include a lower surface facing the upper surface.

[0067] The side surface is formed along the thickness direction of the core layer 10, including not only the case where the side surface is perpendicular to the upper surface of the core layer 10, but also the case where at least a part of the side surface forms a different angle (tilt angle) other than 90 degrees with the upper surface.

[0068] The side surface can be a plane or a curved surface.

[0069] The core layer 10 can include a cavity (not shown), which is a space formed by a part of the core layer 10 recessing inward.

[0070] The cavity can be formed by a part of the upper surface and / or the lower surface of the core layer 10 recessing along the thickness direction of the core layer 10, and can also penetrate along the thickness direction of the core layer 10.

[0071] The cavity can provide a space for mounting devices. The devices mounted in the cavity can be electrically connected to other structural elements in the package substrate. The devices are not only applicable to semiconductor devices such as CPUs, GPUs, memory chips, etc., but also applicable to capacitor devices, transistor devices, impedance devices, other modules, etc. That is, as long as they are devices mounted in semiconductor devices, they can be used as the above devices without limitation.

[0072] The core layer 10 can include a via hole portion (not shown) penetrating the core layer 10 along the thickness direction.

[0073] The via hole portion includes: a via hole space, which is a space for disposing a conductive layer; and a via hole inner diameter surface, which surrounds the via hole space. The via hole inner diameter surface means the surface of the core layer 10 formed inside the via hole portion.

[0074] The through-hole space may have a substantially uniform inner diameter in the thickness direction of the core layer 10. The through-hole space may have an inner diameter that varies in the thickness direction of the core layer 10.

[0075] In the preparation step, when a glass core is applied as the core layer 10, the glass core may be etched to prepare the through-hole portion. Specifically, defects may be formed at predetermined positions within the surface of the glass core. Methods for forming defects may include mechanical etching, laser irradiation, etc.

[0076] The region where defects are formed may be physically or chemically etched to form the through-hole portion. When chemical etching is applied, wet etching may be implemented through an etching solution. As the etching solution, as long as it can generally be applied to etching a glass substrate, there is no limitation. Exemplarily, the etching solution may include sulfuric acid solution, nitric acid solution, hydrofluoric acid solution, etc.

[0077] During the etching process, the remaining surface of the glass core other than the region where defects are formed may be masked, or etching may be performed without masking.

[0078] Defects may be formed at one location within the upper surface of the glass core, and defects may be formed at another location within the lower surface of the glass core opposite to the above-mentioned one location, and etching may be performed to prepare the core layer 10 having a through-hole portion formed therein.

[0079] The substrate 100 may include a conductive layer formed in the through-hole space. The conductive layer may fill at least a part of the through-hole space, or may be formed in a thin film form on the inner diameter surface of the through-hole. When the conductive layer is formed in a thin film form on the inner diameter surface of the through-hole, the remaining space in the through-hole space other than the space occupied by the conductive layer may be filled with an insulating layer.

[0080] The conductive layer disposed in the through-hole space may transmit an electrical signal in the thickness direction of the core layer 10, and may electrically connect the device to the main board, the redistribution layer, etc.

[0081] Descriptions of the raw materials of the insulating layer and the conductive layer, etc., are repeated in the following content, and thus are omitted.

[0082] The substrate 100 may further include an insulating layer 20 formed on the core layer 10. The insulating layer 20 may be formed in a manner that is in contact with the upper surface of the core layer 10. The substrate 100 may further include a conductive layer (not shown) disposed between the core layer 10 and the insulating layer 20. The insulating layer 20 is disposed on the conductive layer and may surround the above-mentioned conductive layer.

[0083] As the insulating layer 20, as long as it can be applied as the insulating layer 20 in a semiconductor device or a packaging substrate, there is no limitation. Exemplarily, the insulating layer 20 may include an epoxy resin containing a filler or the like. Exemplarily, the insulating layer 20 may be formed by a build-up layer material such as ABF (Ajinomoto Build-up Film) of Ajinomoto Co., Inc., an undercoat material, etc., but is not limited thereto.

[0084] The conductive layer is equivalent to a wire for transmitting an electrical signal. The conductive layer may include a conductive substance. Exemplarily, the conductive layer may include at least one of copper, nickel, aluminum, gold, or silver. The raw material of the conductive layer may be copper or the like.

[0085] In the preparation step, a substrate 100 having an insulating layer 20 pre-formed on the core layer 10 may be prepared. In the preparation step, the insulating layer 20 may be formed on the core layer 10 to prepare the substrate 100.

[0086] The insulating layer 20 may be formed by laminating an insulating resin in a film form on the core layer 10. Exemplarily, the insulating layer 20 in a film form may be pressure-laminated on the core layer 10 under reduced pressure to form the substrate 100. In this case, the surface of the conductive layer disposed below the insulating layer 20 may be surrounded in a void-free manner.

[0087] Patterning step

[0088] Figure 2A And Figure 2B FIGS. are conceptual diagrams for separately explaining the concept of the patterning step of the examples. Referring to the above Figure 2A And Figure 2B , the manufacturing method of the example packaging substrate is described.

[0089] The substrate 100 includes: a core layer 10; and an insulating layer 20 formed on the core layer 10. The specific structure of the substrate 100 directly applies to the description in the above Figure 1 . The following description is centered on the different parts.

[0090] In the patterning step, the insulating layer 20 may be selectively plasma-etched using an etching mask 30 to form a patterned insulating layer 21.

[0091] The etching mask 30 may contribute to forming a pattern of a pre-designed shape in the insulating layer 20 in the patterning step. The etching mask 30 may include a pattern having the same shape as the pattern to be formed in the insulating layer 20 in the patterning step. The etching mask 30 may include a hole pattern having the same shape as the hole pattern to be formed in the insulating layer 20 in the patterning step.

[0092] The etching mask 30 may include an organic compound. The etching mask 30 may be a patterned resist layer. Different from a metal etching mask 30, the exemplary etching mask 30 can be easily removed by lift-off without a separate etching process after the patterning of the insulating layer 20 is completed. Thus, the above etching mask 30 can cause no excessive damage to the insulating layer 20 during the removal process and leave no substantial residue on the insulating layer 20. Also, in this case, a decrease in the bonding force between the conductive layer formed on the insulating layer 20 and the insulating layer 20 can be suppressed.

[0093] As the above resist layer, as long as it is commonly used in the field of packaging substrates, there is no limitation. The above resist layer may include an amine-based resist. The above resist layer may include a positive resist. The above resist layer may include a negative resist.

[0094] The etching mask 30 may be disposed in contact with the upper surface of the insulating layer 20. Specifically, a resist composition may be coated and cured on the insulating layer 20 to form a resist layer, and the above resist layer may be patterned to form the etching mask 30.

[0095] When forming the resist layer, the resist composition may be coated in such a manner that the resist composition can cover the entire insulating layer 20. The thickness of the coated resist composition and the thickness of the cured resist layer may be adjusted in consideration of the thickness of the manufactured etching mask 30.

[0096] When patterning the resist layer, light may be selectively irradiated on the resist layer according to the shapes of all the patterns formed on the insulating layer 20, and then, the light-irradiated resist layer may be developed to form the etching mask 30. Exemplarily, the irradiation of the resist layer may be implemented by an electron beam.

[0097] The thickness of the etching mask 30 may be 5 μm to 40 μm. The above thickness may be 10 μm or more. The above thickness may be 15 μm or more. The above thickness may be 35 μm or less. The above thickness may be 30 μm or less. In this case, the etching mask 30 remains after the patterning step is completed, which can contribute to the selective etching of the insulating layer 20 and can contribute to achieving a delicate patterning of the insulating layer 20.

[0098] In the patterning step, the insulating layer 20 may be patterned by plasma etching. The atmosphere temperature of the patterning step may be 120 °C or less.

[0099] After the substrate 100 formed with the etching mask 30 is disposed in the etching chamber, an etching gas may be introduced into the chamber, and plasma power may be applied to perform plasma etching on the insulating layer.

[0100] In the patterning step, the insulating layer 20 can be selectively plasma-etched through the etching mask 30 to form a patterned insulating layer 21. Specifically, the etching target region 22 included in the insulating layer 20 can be plasma-etched to form the patterned insulating layer 21. The etching target region 22 is a region included in the insulating layer 20 and is a region removed by plasma etching in the patterning step. The etching target region 22 corresponds to a region where the upper surface of the insulating layer 20 is exposed to the outside in the insulating layer 20 with the etching mask 30 disposed on the upper side.

[0101] During the continuous execution of the plasma etching, the atmosphere temperature in the patterning step, specifically, the temperature inside the etching chamber, can continuously rise. In this case, the etching mask 30 can be modified by heat. The modified etching mask 30 has a sticky property, is difficult to remove from the surface of the insulating layer 20, and its shape is also deformed, resulting in problems when achieving a delicate pattern on the insulating layer 20. Thus, after removing the etching mask 30, there may be various foreign substances remaining on the insulating layer, and the electrical reliability of the manufactured package substrate may decrease.

[0102] Examples can help control the atmosphere temperature in the patterning step, that is, the temperature inside the chamber, within a preset range in the examples, so as to suppress the deterioration of the etching mask 30 and more delicately and stably achieve a high-integration redistribution layer on the core layer 10.

[0103] The atmosphere temperature in the patterning step can be 120 °C or lower. The above temperature can be 115 °C or lower. The above temperature can be 110 °C or lower. The above temperature can be 100 °C or lower. The above temperature can be 30 °C or higher. The above temperature can be 50 °C or higher. The above temperature can be 70 °C or higher. The above temperature can be 80 °C or higher. In this case, the modification of the etching mask 30 can be suppressed, and a stable plasma state can be maintained during the patterning step.

[0104] The patterning step can include: an etching process of etching a part of the insulating layer 20 in the etching target region 22; and a stabilization process of reducing the atmosphere temperature in the patterning step.

[0105] During one etching process, instead of continuously etching the entire insulating layer 20 in the etching target region 22, the insulating layer 20 disposed in the etching target region can be etched by dividing it multiple times along the thickness direction of the insulating layer 20. Thus, the etching mask 30 can be suppressed from being exposed to high temperatures for a long time.

[0106] The etching process can be carried out for 200 seconds to 700 seconds each time. The etching process can be carried out for more than 250 seconds each time. The etching process can be carried out for more than 300 seconds each time. The etching process can be carried out for more than 350 seconds each time. The etching process can be carried out for 650 seconds or less each time. The etching process can be carried out for 600 seconds or less each time. The etching process can be carried out for 550 seconds or less each time. In this case, a pattern with a micro pitch can be formed more precisely on the insulating layer 20, and during the process of removing the etching mask 30, the residue of the etching mask 30 can be inhibited from adsorbing on the insulating layer 20.

[0107] The etching process can be carried out in an atmosphere including a first etching gas and a second etching gas. The first etching gas can be a fluorine-based gas. The first etching gas can be one of carbon fluoride, nitrogen fluoride, sulfur fluoride, and combinations thereof.

[0108] Carbon fluoride can illustratively be CF 4 、CHF 3 、CH 2 F 2 、CH 3 F, and one of their combinations.

[0109] Nitrogen fluoride can be NF 3 . Sulfur fluoride can be SF 6 .

[0110] The first etching gas can be nitrogen fluoride.

[0111] The second etching gas can be oxygen.

[0112] In the example, the first etching gas and the second etching gas can be applied together as atmosphere gases during the etching process to further increase the etching speed of the insulating layer 20.

[0113] During the above etching process, the plasma power can be 1.5 kW or more and 3 kW or less. The above plasma power can be 1.7 kW or more. The above plasma power can be 2 kW or more. The above plasma power can be 2.7 kW or less. The above plasma power can be 2.5 kW or less. In this case, an etching speed above a specified level for the insulating layer 20 can be ensured, and over-etching damage to the insulating layer 20 by plasma can be prevented.

[0114] In the example, after an etching process is completed, overheating of the etching mask 30 can be inhibited through a stabilization process. Specifically, the supply of plasma power can be interrupted during the stabilization process, and the atmosphere temperature during the stabilization process can be adjusted to be lower than the atmosphere temperature during the etching process.

[0115] The stabilization process can be carried out until the atmosphere temperature, that is, the temperature inside the chamber reaches the target temperature. The target temperature can be a temperature that is more than 5°C lower than the maximum value of the atmosphere temperature during the etching process. The target temperature can be a temperature that is more than 10°C lower than the maximum value of the atmosphere temperature during the etching process. The target temperature can be a temperature that is more than 15°C lower than the maximum value of the atmosphere temperature during the etching process. Thus, it can help prevent deformation of the etching mask 30 and can easily peel off the etching mask 30 after the patterning is completed.

[0116] In the patterning step, the cooling fluid can be passed through the outside of the etching chamber, particularly, a partial periphery of the chamber where the substrate 100 is disposed, to lower the temperature of the etching mask 30. The cooling fluid can be passed through the partial periphery where the substrate 100 is disposed during the etching process and the stabilization process.

[0117] The cooling fluid can be a liquid or a gas. When the cooling fluid is a liquid, the pipe through which the cooling fluid flows can be disposed on the outer periphery of the etching chamber, and the cooling fluid can be made to flow in the above pipe to cool the inside of the chamber. The above cooling fluid can be water.

[0118] When the cooling fluid is a gas, similar to when the cooling fluid is a liquid, the gas can be made to flow in the pipe or the gas can be ejected to the outside of the chamber to cool the inside of the chamber. The above cooling fluid can be air or a gas with low reactivity such as helium or nitrogen.

[0119] In the patterning step, the above etching process and the above stabilization process can be taken as one cycle, and the cycle can be carried out more than twice for each layer of the insulating layer 20. In the patterning step, each layer of the insulating layer can be carried out more than three cycles. In the patterning step, each layer of the insulating layer can be carried out ten or less cycles. In this case, while adjusting the time required for the patterning step, it can help achieve delicate patterning of the insulating layer 20.

[0120] The patterned insulating layer 21 prepared by the etching process can include through holes 25 formed along the thickness direction of the insulating layer 20. The through holes 25 can spatially connect the upper surface and the lower surface of the insulating layer 20. A conductive layer (not shown) can be disposed in the through holes 25. The conductive layer disposed in the through holes 25 can electrically connect the conductive layer (not shown) disposed on the insulating layer 20 and the conductive layer (not shown) disposed under the insulating layer 20.

[0121] The diameter of the above through holes 25 can be 3μm to 50μm. The above diameter can be 5μm or more. The above diameter can be 7μm or more. The above diameter can be 40μm or less. The above diameter can be 30μm or less. The above diameter can be 20μm or less. The above diameter can be 15μm or less. In this case, a conductive layer with a higher integration degree can be stably formed.

[0122] In the patterning step, after the patterning of the insulating layer 20 is completed, the etching mask 30 can be removed. The etching mask 30 has an adjusted bonding force to the upper surface of the insulating layer 20, and the etching mask 30 can be physically easily peeled off and removed. Thus, in order to remove the etching mask 30, a separate complex process such as an etching process is not required, thereby improving the process convenience and reducing the damage to the insulating layer 20 to a certain level or below. Also, after the etching mask 30 is removed by the method described above, substantially no residue of the etching mask 30 remains on the upper surface of the insulating layer 20, and the surface is smooth. Therefore, the conductive layer formed on the upper surface of the insulating layer 20 can have an excellent bonding force to the insulating layer 20.

[0123] The etching mask 30 can be removed in an atmosphere temperature of 30°C to 60°C. The above atmosphere temperature can be 35°C or higher. The above atmosphere temperature can be 40°C or higher. The above atmosphere temperature can be 55°C or lower. The above atmosphere temperature can be 50°C or lower. In this case, the residue of the etching mask can be effectively suppressed from remaining in the insulating layer.

[0124] Cleaning step

[0125] In the method for manufacturing the packaged substrate of the example, after the patterning step is completed, a cleaning step of ultrasonically cleaning the substrate 100 can be further included before the manufacturing step.

[0126] During the plasma etching of the insulating layer 20, particles may be generated from the insulating layer 20. These particles may remain and be adsorbed in the through holes 25 with a small pitch in the insulating layer 20 and on the upper surface of the insulating layer 20, and may cause defects during the formation of the conductive layer on the through holes 25 and the upper surface of the insulating layer 20.

[0127] In the cleaning step of the example, the substrate 100 with the remaining particles can be immersed in a water tank, and ultrasonic vibration can be applied to the water tank to generate cavitation. Thus, the particles can be easily removed without overly damaging the substrate 100 in the cleaning step.

[0128] In the cleaning step of the example, the vibration frequency can be 30 kHz to 200 kHz. The above vibration frequency can be 50 kHz or higher. The above vibration frequency can be 70 kHz or higher. The above vibration frequency can be 100 kHz or higher. The above vibration frequency can be 150 kHz or lower. In this case, even if the insulating layer 20 has a fine and complex pattern structure, the substrate 100 can be effectively cleaned without causing significant damage.

[0129] Manufacturing step

[0130] Figure 3Conceptual diagram of a packaged substrate manufactured by the manufacturing method according to the example. Referring to the above Figure 3 , the method for manufacturing the packaged substrate of the example will be described.

[0131] In the manufacturing step, the packaged substrate 200 can be manufactured from the substrate 100 having the patterned insulating layer 21 formed thereon.

[0132] In the manufacturing step, the first rewiring layer 50 can be manufactured by forming a conductive layer 40 in the region where the insulating layer 20 is etched away by plasma etching, particularly in the through-holes.

[0133] The conductive layer 40 can be formed by a dry method or a wet method.

[0134] The dry method is a method of forming a seed layer by sputtering the region where the conductive layer 40 is to be disposed, and forming the conductive layer 40 by plating the region where the seed layer is formed. When forming the seed layer, metals such as titanium, chromium, and nickel can be sputtered, and the above metals and copper can be sputtered together. By sputtering, an anchoring effect in which the surface of the region where the conductive layer 40 is disposed and the deposited metal particles interact is generated, and the adhesion of the conductive layer 40 can be improved.

[0135] The wet method is a method of performing a primer treatment on the portion where the conductive layer 40 needs to be formed and then plating with a metal. The primer may include a compound having a functional group such as an amine. Depending on the desired degree of adhesion, the primer may simultaneously contain a compound having a functional group such as an amine and a silane coupling agent. When applying a silane coupling agent, the surface to be primer-treated can be pretreated with a silane coupling agent, and then a compound having an amine group can be applied to the pretreated region to form a primer layer.

[0136] After forming the seed layer or the primer layer, plating can be performed to form the conductive layer 40. When forming the conductive layer 40, copper plating can be applied, but it is not limited thereto. Before plating, the portion of the seed layer or the primer layer where the conductive layer 40 does not need to be formed can be inactivated, or the portion where the conductive layer 40 needs to be formed can be activated and then plating can be performed. As the activation or inactivation treatment method, light irradiation treatment such as irradiating a laser of a specific wavelength, chemical treatment, etc. can be applied. However, plating can be performed without applying the activation or inactivation treatment, and then the conductive layer 40 can be etched according to a pre-designed shape to be patterned.

[0137] When the patterned insulating layer 21 includes a hole pattern, the conductive layer 40 can be formed in the through-holes in the insulating layer 20. The above conductive layer 40 can electrically connect a conductive layer (not shown) located on the upper side and a conductive layer (not shown) located on the lower side with the conductive layer 40 as a reference.

[0138] When the structure of the pre-designed first redistribution layer 50 is a multi-layer structure, other patterned insulating layers (not shown) and conductive layers (not shown) may be formed on the above-mentioned patterned insulating layer 21 and conductive layer 40. The other patterned insulating layers and conductive layers disposed on the patterned insulating layer 21 and conductive layer 40 may be formed by the above method.

[0139] When the first redistribution layer 50 has a multi-layer structure, a conductive layer with a smaller width may be disposed as it goes upward from the first redistribution layer 50. A conductive layer with a thinner thickness may be disposed as it goes upward from the first redistribution layer 50. A conductive layer with a smaller pitch may be formed as it goes upward from the first redistribution layer 50. Thus, the first redistribution layer 50 can form a stable electrical connection with a semiconductor device having a micro-pattern.

[0140] According to requirements, the manufacturing process may further include a process of forming a second redistribution layer disposed below the core layer 10. The second redistribution layer may be a single-layer structure or a multi-layer structure. The redistribution layer formed below the core layer 10 can be formed by the same method as the above method.

[0141] The second redistribution layer may have a single-layer structure or a multi-layer structure.

[0142] When the second redistribution layer has a multi-layer structure, a conductive layer with a wider width may be disposed as it goes downward from the second redistribution layer. A conductive layer with a thicker thickness may be disposed as it goes downward from the second redistribution layer. A conductive layer with a larger pitch may be formed as it goes downward from the second redistribution layer. Thus, the second redistribution layer can form a stable electrical connection with a main board having a wide or thick conductive layer.

[0143] In the manufacturing process, the packaged substrate 200 can be prepared by completing the formation of the redistribution layer with a pre-designed structure on the upper side and / or lower side of the core layer 10.

[0144] According to requirements, in the manufacturing process, upper terminals and the like may also be formed on the upper part and / or side part of the packaged substrate 200, and bumps may also be formed on the lower part of the packaged substrate 200. The bumps can be disposed in a preset form below the redistribution layer disposed below the core layer 10. Exemplarily, the bumps may be disposed on a part of the lower surface of the packaged substrate 200 to facilitate connection with a main board or the like.

[0145] Manufactured packaged substrate

[0146] The packaged substrate 200 manufactured according to the manufacturing method of the packaged substrate of the example may include: the above-mentioned core layer 10; and the above-mentioned patterned insulating layer 21 disposed on the above-mentioned core layer 10.

[0147] The packaged substrate 200 may further include a conductive layer (not shown) formed in such a manner that at least a part thereof is in contact with the upper surface of the patterned insulating layer 21.

[0148] The description of the raw materials and structure of the core layer 10 and the patterned insulating layer 21 is repeated with the above content, and thus is omitted.

[0149] It may include through holes (not shown) that form the patterned insulating layer 21 along the thickness direction of the above insulating layer 20. A conductive layer 40 may be formed in the through holes.

[0150] The conductive layer formed in a manner that at least a part thereof is in contact with the upper surface of the patterned insulating layer 21 may be formed on the patterned insulating layer 21 and the conductive layer by the above dry or wet method.

[0151] In the package substrate 200 manufactured by the method for manufacturing a package substrate according to an example, the conductive layer formed in contact with the upper surface of the patterned insulating layer 21 may have excellent adhesion to the above insulating layer 20. This is because after the patterning of the insulating layer is completed, it is easy to remove the etching mask without substantially causing damage or modification to the patterned insulating layer 21, and the etching mask does not substantially leave residues on the surface of the patterned insulating layer 21. Thus, even after the etching mask is removed, it can help the upper surface of the above patterned insulating layer 21 to maintain a smooth surface.

[0152] The peel strength between the patterned insulating layer 21 and the conductive layer is measured by the method described below. After the conductive layer formed on the patterned insulating layer 21 is cut long into a width of 1 cm, the conductive layer is peeled from the above insulating layer 20 by 3 cm using a universal testing machine (UTM, Universal Testing Machine) at a peel speed of 847 μm / s, and the peel strength is measured. The average value of the peel strength in the saturation interval is calculated from the measured peel strength distribution, and this value is used as the peel strength between the patterned insulating layer 21 and the conductive layer.

[0153] The peel strength of the above conductive layer from the upper surface of the patterned insulating layer 21 may be 200 gf / cm or more. The above peel strength may be 250 gf / cm or more. The above peel strength may be 300 gf / cm or more. The above peel strength may be 320 gf / cm or more. The above peel strength may be 500 gf / cm or less. In this case, the above conductive layer can be stably fixed on the upper surface of the patterned insulating layer 21, and the manufactured package substrate 200 may have excellent electrical reliability.

[0154] The diameter of the through hole 25 in the patterned insulating layer 21 may be 3 μm to 50 μm. The above diameter may be 5 μm or more. The above diameter may be 7 μm or more. The above diameter may be 40 μm or less. The above diameter may be 30 μm or less. The above diameter may be 20 μm or less. The above diameter may be 15 μm or less. In this case, the through hole 25 pattern with a higher pattern density can be stably formed in the insulating layer.

[0155] Hereinafter, examples will be described in more detail with specific examples. The following examples are merely illustrative to facilitate understanding of the examples, and the scope of the examples is not limited thereto.

[0156] Manufacturing Example: Manufacturing of a Package Substrate

[0157] Example 1: An insulating layer was formed by vacuum lamination of an Ajinomoto Build-up Film (ABF) of Ajinomoto Co., Inc. on the upper surface of a Corning glass plate SG7.8 to prepare a substrate.

[0158] A resist composition, DRY FILM PHOTEC (RY series) of RESONAC Co., Ltd., was coated and cured on the above insulating layer to form a resist layer with a thickness of 5 to 40 μm. The above resist layer was exposed using an electron beam, and the exposed resist layer was developed to form an etching mask having a plurality of hole patterns with a diameter of 7 to 10 μm.

[0159] The substrate with the etching mask formed thereon was placed in an etching chamber, and the above insulating layer was plasma-etched to be patterned. When performing plasma etching, a plasma power of 1.5 kW was applied, and 150 sccm of NF 3 was supplied as the first etching gas in the chamber, and 150 sccm of O 2 was supplied as the second etching gas.

[0160] Plasma etching was performed three times, each time for 500 seconds. After performing plasma etching once, the etching was interrupted for 60 seconds. During the patterning of the insulating layer, helium gas was sprayed onto the lower side of the etching chamber to control the internal temperature of the chamber to be less than 120°C.

[0161] After completing the patterning of the insulating layer, the etching mask was peeled off in an atmosphere of 30°C to 55°C. The substrate with the etching mask peeled off was immersed in a water tank, and ultrasonic cleaning was performed at a vibration frequency of 100 kHz for 300 seconds.

[0162] After cleaning, sputtering was performed on the etched space in the insulating layer to form a titanium layer and a copper layer disposed on the above titanium layer, and electroplated copper was performed on the above copper layer to form a conductive layer, thereby completing the package substrate.

[0163] Example 2: A package substrate was manufactured under the same conditions as in Example 1, except that the vibration frequency during ultrasonic cleaning was 50 kHz.

[0164] Example 3: A package substrate was manufactured under the same conditions as in Example 1, except that the vibration frequency during ultrasonic cleaning was 130 kHz.

[0165] Comparative Example 1: A package substrate was manufactured under the same conditions as in Example 1, except that the cooling process by helium gas injection was not performed during the patterning process of the insulating layer.

[0166] Comparative Example 2: A package substrate was manufactured under the same conditions as in Example 1, except that ultrasonic cleaning was not performed after the patterning of the insulating layer was completed.

[0167] Evaluation Example: Etching Mask Stripping Evaluation

[0168] By visually observing the upper surface of the patterned insulating layer in each example and comparative example, check whether any remnants of the etching mask are found. The case where no such remnants are found is evaluated as Pass, and the case where such remnants are found is evaluated as Fail.

[0169] The measured values of each example and comparative example are shown in Table 1 below.

[0170] Evaluation Example: Cleaning Evaluation

[0171] In the package substrates of each example and comparative example, the through-holes in the patterned insulating layer were observed using an optical microscope to check whether any particles remained. The case where no such particles were found was evaluated as Pass, and the case where such particles were found was evaluated as Fail.

[0172] The measured values of each example and comparative example are shown in Table 1 below.

[0173] Evaluation Example: Adhesion Strength Evaluation of Conductive Layer

[0174] In Examples 1 to 3 and Comparative Example 2, a conductive layer was also formed on the patterned insulating layer. A titanium target was used for sputtering to form a titanium layer with a thickness of 50 nm. A copper target was used on the above titanium layer for sputtering to form a copper layer with a thickness of 100 nm. Electroplating of copper was also performed on the above copper layer to form a copper layer with a thickness of 20 μm.

[0175] The peel strength of the conductive layer on the patterned insulating layer is measured using the method described below. After cutting the conductive layer formed on the patterned insulating layer into a length of 1 cm in width, the conductive layer is peeled from the insulating layer by 3 cm using a UTM (Universal Testing Machine) at a peel speed of 847 μm / s, and the peel strength is measured. The average value of the peel strength in the saturation interval is calculated from the measured peel strength distribution, and this value is taken as the peel strength between the patterned insulating layer and the conductive layer.

[0176] The measured values of each example and comparative example are shown in Table 1 below.

[0177] Table 1

[0178] Peeling evaluation Cleaning evaluation Peeling strength (gf / cm) Example 1 Qualified Qualified 340 Example 2 Qualified Qualified 280 Example 3 Qualified Qualified 320 Comparative Example 1 Unqualified Qualified - Comparative Example 2 Qualified Unqualified 60

[0179] In the evaluation of peeling or not in Table 1 above, Examples 1 to 3 were evaluated as Pass, while Comparative Example 1 was evaluated as Fail. This means that when the atmosphere temperature is adjusted within the preset range in the patterning step, the etching mask can be easily removed.

[0180] In the cleaning evaluation, Examples 1 to 3 were evaluated as Pass, while Comparative Example 2 was evaluated as Fail. This means that particles adsorbed in the through-holes of the patterned insulating layer can be easily removed by ultrasonic cleaning.

[0181] In the peel strength evaluation, Examples 1 to 3 were evaluated as 250 gf / cm or more, while Comparative Example 2 was evaluated as 100 gf / cm or less. This is because the residue of the insulating layer caused by etching remains on the upper surface of the patterned insulating layer, preventing the bonding between the conductive layer and the patterned insulating layer.

[0182] As described above, the preferred embodiments of the present invention have been described in detail, but the scope of the rights of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art of the present invention using the basic concepts defined in the appended claims also fall within the scope of the rights of the present invention.

Claims

1. A method for manufacturing a packaging substrate, characterized in that: include: A preparation step is to prepare a base substrate including a core layer and an insulating layer formed on the core layer. a patterning step, selectively performing plasma etching on the insulating layer using an etching mask to form a patterned insulating layer, and A manufacturing step of manufacturing a packaging substrate from a base substrate having the patterned insulating layer; The etching mask comprises an organic compound, The atmosphere temperature in the patterning step is 120° C. or lower.

2. The method for manufacturing a packaging substrate according to claim 1, wherein: In the patterning step, the etching mask is arranged in contact with the upper surface of the insulating layer.

3. The method for manufacturing a packaging substrate according to claim 1, wherein: The insulating layer includes an etching target area. The patterning steps include: an etching process, etching a portion of the insulating layer in the etching target area, and A stabilization process to reduce the atmosphere temperature of the patterning step; In the patterning step, the etching process and the stabilization process are regarded as one cycle, and the cycle is performed twice or more for each insulating layer.

4. The method for manufacturing a packaging substrate according to claim 3, wherein: The above etching process is performed for 200 seconds to 700 seconds each time.

5. The method for manufacturing a packaging substrate according to claim 3, wherein: The etching process is carried out in an atmosphere including a first etching gas and a second etching gas. The first etching gas is a fluorine-based gas. The second etching gas is oxygen.

6. The method for manufacturing a packaging substrate according to claim 3, wherein: The plasma power of the above etching process is greater than or equal to 1.5 kW and less than or equal to 3 kW.

7. The method for manufacturing a packaging substrate according to claim 1, wherein: The etching mask has a thickness of 5 μm to 40 μm.

8. The method for manufacturing a packaging substrate according to claim 1, wherein: After the patterning step is completed and before the manufacturing step, a cleaning step of ultrasonically cleaning the substrate is also included. The vibration frequency of the above cleaning step is 30kHz to 200kHz.

9. The method for manufacturing a packaging substrate according to claim 1, wherein: The patterned insulating layer includes through holes formed along the thickness direction of the insulating layer. The through hole has a diameter of 3 μm to 50 μm.

10. The method for manufacturing a packaging substrate according to claim 1, wherein: The above-mentioned packaging substrate comprises: The core layer, and The patterned insulating layer is disposed on the core layer; The above-mentioned packaging substrate also includes: The conductive layer is formed in such a way that at least a portion of it is in contact with the upper surface of the patterned insulating layer. The peel strength of the conductive layer on the upper surface of the patterned insulating layer is 200 gf / cm or more.

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