Clock duty ratio and phase difference detection circuit for SERDESTX

Abstract

The invention aims to provide a clock duty ratio and phase difference detection circuit for SERDESTX. The circuit comprises a one-out-of-four multiplexer, a low-pass filtering module and a comparison module, the output end of the one-out-of-four multiplexer is connected with the input end of the low-pass filtering module; and the output end of the low-pass filtering module is connected with the control module. According to the invention, the area used in the prior art and additional error sources in front of a filter circuit can be reduced, and the circuit complexity is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and particularly relates to a circuit for detecting the duty cycle and phase difference of a clock for SERDES_TX. Background Art

[0002] SERDES_TX is a transmitter (TX) module in SerDes technology, and its main function is to convert parallel data into serial data for transmission. SerDes technology is a technology that converts parallel data into serial data for transmission and then converts the received serial data back into parallel data. In this way, SerDes can achieve high-speed data transmission while reducing the complexity and cost of wiring.

[0003] In recent years, in high-speed clock transmission, in order to meet the timing requirements in timing circuits, bilateral edge, four-phase clock or even higher sub-clock sampling schemes have been used for clock sampling. However, this has also led to higher requirements for the calibration of the duty cycle and phase error of the clock. In traditional technical solutions, a low-pass filter is often inserted before the final sampling clock to become a filtered level, and then a comparator is used to judge the size of the duty cycle (such as Figure 2 ). The system often completes calibration before transmitting data. At the same time, when implementing the layout, in order to ensure the noise requirements of the signal, a resistor is placed at the clock output point to reduce the interference of the trace capacitance on the signal duty cycle.

[0004] In high-speed design, when four-phase sampling clocks are used, there are two sets of differential clocks ICLK and QCLK. For high-speed clocks to filter them into low-frequency DC signals, a large area of RC filter circuits is required. When there are two or more sets of clocks in the system, their duty cycles and the phase differences between them need to be calibrated separately. At this time, three or more sets of calibration circuits are required. This occupies a large amount of chip area. If only one set of filters and comparators is used for calibration, a MUX needs to be inserted before filtering to select which set of signals to filter, and the error of the MUX device itself will also be added to the finally detected duty cycle, resulting in incorrect results. When performing phase difference calibration, ICLK / QCLK needs to be XORed first and then filtered. The circuit at the XOR level will have some phase errors due to the error in its own rise and fall times. This results in the finally detected result not being the true phase difference of I / QCLK. Summary of the Invention

[0005] The purpose of the present invention is to provide a circuit for detecting the duty cycle and phase difference of a clock for SERDES_TX, which can reduce the area used in the prior art and additional error sources before the filter circuit, and reduce the circuit complexity.

[0006] A circuit for detecting the clock duty cycle and phase difference of SERDES_TX, comprising: A 4-to-1 multiplexer, a low-pass filtering module, and a comparison module; The output end of the 4-to-1 multiplexer is connected to the input end of the low-pass filtering module; The output end of the low-pass filtering module is connected to the control module.

[0007] Preferably, it further comprises: a DCC module; The input end of the DCC module is connected to the phase-locked loop signal, and the output end is connected to the 4-to-1 multiplexer, for improving the signal transmission efficiency.

[0008] Preferably, it further comprises: a QEC module; The input end of the QEC module is connected to the output end of the DCC module, and the output end of the QEC module is connected to the 4-to-1 multiplexer, for ensuring the integrity of signal transmission.

[0009] Preferably, it further comprises: a control module; The control module is connected to the DCC module and the QEC module, for controlling the reliability and accuracy of the transmitted signal.

[0010] Preferably, the 4-to-1 multiplexer comprises: four identical branches; One branch comprises: a first NOR gate, a second NOR gate, a first NAND gate, a second NAND gate, a first PMOS transistor, and a first NMOS transistor; The output end of the first NOR gate is connected to the first input end of the first NAND gate; The output end of the second NAND gate is connected to the second input end of the second NOR gate; The second input end of the first NAND gate is connected to the first input end of the second NOR gate, and the output end is connected to the gate of the first PMOS transistor; The output end of the second NOR gate is connected to the gate of the first NMOS transistor; The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor as the output end of the branch; The output ends of the four branches are connected as the output end of the 4-to-1 multiplexer.

[0011] A circuit control method for detecting the clock duty cycle and phase difference of SERDES_TX, comprising: Obtaining a clock signal; Performing an exclusive OR operation on the clock signal to obtain a phase difference; Performing low-pass filtering on the clock signal to obtain a duty cycle.

[0012] Preferably, the obtaining of the phase difference by performing an exclusive OR operation on the clock signals includes: Input two clock signals into a 4-to-1 multiplexer; Adjust the control signal of the 4-to-1 multiplexer to 1100 or 0110; Judge the phase difference between the two clocks according to the output value of the 4-to-1 multiplexer.

[0013] Preferably, the obtaining of the duty cycle by performing low-pass filtering on the clock signals includes: Input the clock signal into a low-pass filtering module to obtain a constant level; Judge the duty cycle according to the constant level.

[0014] An electronic device includes: a chip, a processor, and a memory. The memory is used to store computer program code, and the computer program code includes computer instructions. When the chip executes the computer instructions, the electronic device executes a circuit control method for detecting the duty cycle and phase difference of a clock for SERDES_TX.

[0015] A computer-readable storage medium stores a computer program, and the computer program includes program instructions. When the program instructions are executed by a processor of an electronic device, the processor is caused to execute a circuit control method for detecting the duty cycle and phase difference of a clock for SERDES_TX.

[0016] The beneficial effects of the present invention are as follows: 1. The present invention replaces the exclusive OR gate in the prior art with a high-bandwidth 4-to-1 multiplexer, which can avoid the influence of the noise inherent in the exclusive OR gate on the circuit and can also improve the operating bandwidth of the circuit; 2. The controllability of the input signals of the 4-to-1 multiplexer in the present invention allows us to achieve multiple effects only by changing the pattern of the input signals without designing three sets of circuit layouts; 3. The detection circuit in the present invention is the circuit in the actual signal path, reducing the error caused by the difference between the detection circuit and the actual signal path. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings herein are incorporated into the specification and constitute a part of this specification, showing the embodiments that conform to the present invention, and are used together with the specification to explain the principles of the present invention.

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative efforts.

[0019] Figure 1 Circuit diagram for detecting clock duty cycle and phase difference of SERDES_TX according to the present invention; Figure 2 Circuit diagram of the prior art of the present invention; Figure 3 Schematic diagram of the 4-to-1 multiplexer structure according to the present invention; Figure 4 Schematic diagram for comparing the bandwidth of the prior art and the present invention of the present invention; Figure 5 Schematic diagram of the hardware structure of an electronic device according to the present invention. Specific embodiments

[0020] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0021] It should be noted that all directional indications (such as up, down, left, right, front, back...) in the embodiments of the present invention are only used to explain the relative positional relationship and movement conditions between components in a specific posture (as shown in the drawings). If the specific posture changes, the directional indications will also change accordingly.

[0022] In addition, the descriptions involving "first", "second", etc. in the present invention are only for descriptive purposes, and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between various embodiments can be combined with each other, but it must be based on the fact that those of ordinary skill in the art can implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope required by the present invention.

[0023] In the TX (transmitter) circuit of SerDes (serializer / deserializer), DCD (Duty Cycle Distortion) and QED (Quadrature Error Distortion) circuits are used to correct signal distortion and ensure signal integrity. In high-speed design, when four-phase sampling clocks are used, there are two sets of differential clocks ICLK and QCLK. For high-speed clocks, filtering them into low-frequency DC signals requires a larger RC filter circuit area. When the system has two or more sets of clocks, their duty cycles and phase differences between each other need to be calibrated separately. At this time, three sets of calibration circuits or more are required. A large amount of chip area is occupied. If only one set of filters and comparators are used for calibration, a MUX needs to be inserted before filtering to select which set of signals to filter. The error of the MUX device itself will also be added to the final detected duty cycle, resulting in incorrect results. When calibrating the phase difference, ICLK / QCLK needs to be XORed once before filtering. However, the XOR circuit will have some phase errors due to its own rise and fall time errors, which results in the final detection result not being the actual I / QCLK phase difference.

[0024] The present invention replaces the XOR gate in the prior art with a high-bandwidth 4-to-1 multiplexer, which can avoid the influence of the noise of the XOR gate itself on the circuit and improve the operating bandwidth of the circuit; the controllability of the input signal of the 4-to-1 multiplexer of the present invention does not require us to design three sets of circuit layouts, and we only need to change the pattern of the input signal to achieve multiple effects; the circuit detected in the present invention is the circuit in the actual signal path, which reduces the error caused by the difference between the detection circuit and the actual signal path.

[0025] Example 1 A circuit for detecting clock duty cycle and phase difference of SERDES_TX, referring to Figure 1 ,include: 4-to-1 multiplexer, low-pass filter module and comparison module; In the TX circuit of SerDes, the 4-to-1 MUX (4-way multiplexer) is a key component in the DCD (Duty Cycle Distortion) and QED (Quadrature Error Distortion) correction circuits, which is used to select or adjust the signal path to achieve the correction of duty cycle and quadrature error. The 4-to-1 MUX is a multiplexer that selects one of the 4 input signals as the output. In the DCD / QED circuit, its main functions are: Select the correction path: Select different signal paths according to the correction requirements. Adjust the signal timing: Correct the duty cycle or quadrature error by selecting signals with different delays or phases. In DCD correction, the 4-to-1 MUX is used to adjust the duty cycle of the signal: Input signals: 4 signals with different delays or duty cycles. Selection logic: Select the signal closest to the ideal duty cycle (50%) according to the duty cycle detection result. Output signal: The corrected signal with the minimum duty cycle distortion. In QED correction, the 4-to-1 MUX is used to adjust the phase of the I / Q signal: Input signals: 4 I / Q signals with different phases. Selection logic: Select the signal with the phase difference closest to 90 degrees according to the phase error detection result. Output signal: The corrected I / Q signal with the minimum quadrature error. In the embodiment of the present invention, the input signals of the 4-to-1 multiplexer are two clock signals, that is, two input ports have an input of 0. The 4-to-1 multiplexer performs an exclusive OR operation on the two clocks. Logically, this 4-to-1 multiplexer replaces the function of the exclusive OR gate and will have a faster speed and less noise, and then a filtering operation is performed.

[0026] In the embodiment of the present invention, referring to Figure 1 , the comparison module is COMP, which is used to compare two voltage signals and output high and low levels, and can also detect whether the input signal exceeds a preset threshold for overvoltage, undervoltage and other protection circuits. The COMP module can provide fast response and is suitable for high-speed signal processing such as pulse width modulation (PWM).

[0027] The output end of the 4-to-1 multiplexer is connected to the input end of the low-pass filter module; In an embodiment of the present invention, the low-pass filter module is an LPF. The main function of the low-pass filter module is to filter out the high-frequency components in the input signal and retain the low-frequency components. The working principle of the low-pass filter module is based on a specific filtering algorithm, and its design goal is to filter out the high-frequency components in the input signal so that only the low-frequency components are retained in the output signal. In this way, high-frequency components such as noise and interference can be effectively removed, thereby improving the quality and reliability of the signal. In duty cycle detection, the main function of low-pass filtering is to extract the average voltage or DC component from the PWM (pulse width modulation) signal, so as to accurately reflect the duty cycle information. The duty cycle of the PWM signal determines its average voltage. The low-pass filter filters out the high-frequency PWM carrier and retains the low-frequency average voltage component, which is convenient for detecting the duty cycle. The low-pass filter can smooth the PWM signal, eliminate high-frequency fluctuations, make the output signal more stable, and facilitate subsequent processing. Through low-pass filtering, the duty cycle can be directly read by a simple analog circuit (such as a voltmeter or ADC) without complex digital processing. The low-pass filter can effectively suppress high-frequency noise and improve the accuracy and reliability of duty cycle detection.

[0028] The output end of the low-pass filter module is connected to the control module.

[0029] When designing the SerDes TX circuit, in the 4-to-1 serializer design before the pre-driver stage, various schemes are added to increase the system bandwidth. For example, in Figure 2 the 4-to-1 mux, the tri-state gates use a two-stage structure, which makes the final slew rate of the 4-to-1 faster than that of the cascode structure by a factor of two. When we input the data pattern of 1010 to the optimized 4-to-1 serializer, the output result is equivalent to the waveform after XOR that needs to be used for filtering. Such a scheme has a higher bandwidth than a simple XOR ( Figure 2 ) and can better reflect the duty cycle of the clock in the actual signal path. Since this is the case, it can be directly used in the DCD / QED circuit.

[0030] DCD (Duty Cycle Distortion) circuit, function: correct duty cycle distortion to ensure equal high and low signal levels in terms of time. Reason: Duty cycle distortion can cause signal asymmetry, affecting clock recovery and data sampling at the receiving end. Detection: Detect duty cycle distortion by comparing high and low signal levels in terms of time. Correction: Adjust the signal edges to make the high and low signal levels consistent. QED (Quadrature Error Distortion) circuit, function: correct quadrature error distortion to ensure an exact 90-degree phase difference between I / Q signals. Reason: Quadrature error can lead to signal demodulation errors, affecting the performance of the receiving end. Detection: Measure the phase difference between I / Q signals. Correction: Adjust the phase of I / Q signals to ensure a 90-degree phase difference.

[0031] Preferably, it further includes: a DCC module; The input end of the DCC module is connected to the phase-locked loop, and the output end is connected to a 4-to-1 multiplexer, which is used to improve signal transmission efficiency.

[0032] In the embodiment of the present invention, the main function of the DCC module is to monitor the accuracy of the system clock, ensuring the stability and reliability of the system clock. The DCC module measures the frequency of the selectable clock source by using another input clock as a reference. The user can select two clock sources (such as PLLRAWCLK, INTOSC1, INTOSC2, etc.) according to the requirements of the application program and set the allowable error range. When the input clock frequency exceeds the set range, the DCC module will trigger an error, thereby realizing real-time monitoring of the input clock frequency.

[0033] Preferably, it further includes: a QEC module; The input end of the QEC module is connected to the output end of the DCC module, and the output end of the QEC module is connected to a 4-to-1 multiplexer, which is used to ensure the integrity of signal transmission.

[0034] In the embodiment of the present invention, the QEC (Quadrature Encoder Counter) module is mainly used to process quadrature encoder signals and also includes a noise filtering function to ensure stable and reliable signals.

[0035] Preferably, it further includes: a control module; The control module is connected to the DCC module and the QEC module, and is used to control the reliability and accuracy of the transmitted signal.

[0036] In the embodiment of the present invention, the control module is an FSM, which is driven by a clock signal, and state transitions and output updates are triggered at the clock edge. The control module can control the DCC module and the QEC module, and adjust the parameters of the DCC module and the QEC module according to the output of the comparison module to ensure the correct rate and stability of signal transmission.

[0037] Preferably, the 4-to-1 multiplexer includes: four identical branches; One branch includes: a first NOR gate, a second NOR gate, a first NAND gate, a second NAND gate, a first PMOS transistor, and a first NMOS transistor; The output terminal of the first NOR gate is connected to the first input terminal of the first NAND gate; The output terminal of the second NAND gate is connected to the second input terminal of the second NOR gate; The second input terminal of the first NAND gate is connected to the first input terminal of the second NOR gate, and the output terminal is connected to the gate of the first PMOS transistor; The output terminal of the second NOR gate is connected to the gate of the first NMOS transistor; The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor as the output terminal of the branch; The output terminals of the four branches are connected as the output terminal of the 4-to-1 multiplexer.

[0038] The 4-to-1 multiplexer is a device that can receive four input signals and select one of them as the output according to the control signal. The multiplexer usually contains a certain number of data inputs and a single output. A multiplexer (Multiplexer) is a device that can receive multiple input signals and multiplex one of the input signals to an output channel according to the selection of the control signal. Taking the 4-to-1 multiplexer as an example, it has four input terminals (D0, D1, D2, D3) and an output terminal (Out), and at the same time has two control terminals (S0 and S1), and selects one of the input signals as the output through the combination of these two control terminals.

[0039] Embodiment 2 A circuit control method for detecting the duty cycle and phase difference of a clock for SERDES_TX, including: S100, obtaining a clock signal; S200, performing an exclusive OR operation on the clock signal to obtain a phase difference; The exclusive OR operation is a binary operation, denoted by the symbol "⊕". The exclusive OR operation can be regarded as a logical operation of "true if different". When the values of the two operands are different, the result is 1; when the values of the two operands are the same, the result is 0. The clock signal phase difference refers to the time difference between two clock signals, which is usually used to measure the signal transmission delay, data synchronization, and the accuracy of clock synchronization. In a communication system, the clocks of the sender and the receiver need to be synchronized to ensure the accurate transmission of data. The existence of the clock phase difference may cause data transmission errors or losses. Therefore, accurately measuring and controlling the clock phase difference is crucial for ensuring the reliability and stability of the communication system. By measuring the clock phase difference, the stability and accuracy of the clock signal, as well as the performance of the communication system, can be evaluated.

[0040] S300, perform low-pass filtering on the clock signal to obtain the duty cycle.

[0041] The duty cycle refers to the ratio of the duration of the high-level signal to the period in a periodic signal. Calculation method: The duty cycle is usually expressed as a percentage, and the calculation formula is: Duty cycle = (High-level duration / Period time) × 100%. For example, if the high-level duration of a pulse signal is 1 μs and the signal period is 4 μs, then the duty cycle of this signal is 25%.

[0042] Preferably, S200, obtaining the phase difference by performing an exclusive OR operation on the clock signals includes: S210, input the two clock signals into a 4-to-1 multiplexer; S220, adjust the control signal of the 4-to-1 multiplexer to 1100 or 0110; S230, judge the phase difference between the two clocks according to the output value of the 4-to-1 multiplexer.

[0043] For the I / Q phase difference, it is necessary to detect the phase relationship between the two clocks. Generally, the two clocks need to be subjected to an exclusive OR operation first and then filtered. However, in high-speed clock applications, the bandwidth of the XOR module often cannot reach the bandwidth of such a high frequency as 28 GHz, and the noise inherent in the XOR module becomes non-negligible.

[0044] Although the 4to1mux module in the final driver often cannot reach the highest bandwidth in many cases, it will be optimized to the extreme to achieve the best performance. Therefore, copy a 4to1mux and provide fixed input data, then this 4to1mux logically replaces the function of the XOR. It will have a faster speed and noise similar to that of the driver. It is closer to the clock model used in the actual circuit.

[0045] Preferably, in S300, obtaining the duty cycle by performing low-pass filtering on the clock signal includes: S310, inputting the clock signal into a low-pass filtering module to obtain a constant level; The low-pass filter attenuates high-frequency components (including the high-frequency part of the clock signal), and only retains low-frequency or DC components. For the clock signal, the low-pass filter filters out its rapidly changing part and outputs a value close to its average value.

[0046] S320, judging the duty cycle according to the constant level.

[0047] If the duty cycle of the clock signal is 50%, its average value is the intermediate value between the high level and the low level. If the duty cycle is not 50%, the output level will be biased towards the high level or the low level, depending on the duty cycle.

[0048] At the final node during clock transmission, the duty cycle and I / Q phase difference of the clock are detected. The detection of the duty cycle mainly involves performing significant low-pass filtering on the clock. After filtering, it will basically become a constant level, and the voltage value of this level is closely related to the clock amplitude and duty cycle. (Vout = Vpp * Dutycycle) Then, comparing this level with a comparator can determine whether the duty cycle is too large or too small.

[0049] Embodiment 3 An electronic device includes: a chip, a processor, and a memory. The memory is used to store computer program code, and the computer program code includes computer instructions. When the chip executes the computer instructions, the electronic device executes a circuit control method for detecting the duty cycle and phase difference of a clock for SERDES_TX.

[0050] Reference Figure 5 , the electronic device 2 includes a processor 21, a memory 22, an input device 23, and an output device 24. The processor 21, the memory 22, the input device 23, and the output device 24 are coupled through a connector, and the connector includes various interfaces, transmission lines, or buses, etc., which are not limited in the embodiments of the present invention. It should be understood that in various embodiments of the present invention, coupling refers to mutual connection through a specific method, including direct connection or indirect connection through other devices. For example, they can be connected through various interfaces, transmission lines, buses, etc.

[0051] The processor 21 may be one or more graphics processing units (GPUs). When the processor 21 is a GPU, the GPU may be a single-core GPU or a multi-core GPU. Optionally, the processor 21 may be a processor group composed of multiple GPUs, and multiple processors are coupled to each other through one or more buses. Optionally, the processor may also be other types of processors, etc., which are not limited in the embodiments of the present invention.

[0052] The memory 22 can be used to store computer program instructions and various computer program codes including the program codes for executing the solution of the present invention. Optionally, the memory includes, but is not limited to, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), or a compact disc read-only memory (CD-ROM), and the memory is used for relevant instructions and data.

[0053] The input device 23 is used to input data and / or signals, and the output device 24 is used to output data and / or signals. The output device 24 and the input device 23 may be independent devices or an integrated device.

[0054] Embodiment 4 A computer-readable storage medium stores a computer program, and the computer program includes program instructions. When the program instructions are executed by a processor of an electronic device, the processor is caused to execute a circuit control method for detecting the duty cycle and phase difference of a clock for SERDES_TX.

[0055] In the present invention, the exclusive-OR gate in the prior art is replaced with a high-bandwidth 4-to-1 multiplexer, which can avoid the influence of the noise inherent in the exclusive-OR gate on the circuit and can also increase the operating bandwidth of the circuit; the controllability of the input signals of the 4-to-1 multiplexer in the present invention enables us to achieve multiple effects by only changing the pattern of the input signals without designing three sets of circuit layouts; the detection circuit in the present invention is the circuit in the actual signal path, reducing the error caused by the difference between the detection circuit and the actual signal path.

[0056] The above are only specific embodiments of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but rather to the broadest scope consistent with the principles and novel features claimed herein.

Claims

1. A circuit for detecting clock duty cycle and phase difference of SERDES_TX, characterized in that: include: 4-to-1 multiplexer, low-pass filter module and comparison module; The output end of the 4-to-1 multiplexer is connected to the input end of the low-pass filter module; The input end of the comparison module is connected to the output end of the low-pass filter module, and is used to compare the voltage of the input signal; The input end of the control module is connected to the output end of the comparison module, and is used to control the reliability and accuracy of the transmission signal; The input end of the DCC module is connected to the phase-locked loop signal, and the output end is connected to the 4-to-1 multiplexer, so as to improve the signal transmission efficiency; The input end of the QEC module is connected to the output end of the DCC module, and the output end of the QEC module is connected to the 4-to-1 multiplexer to ensure the integrity of signal transmission; Block connection, used to control the reliability and accuracy of the transmitted signal.

2. The circuit for detecting clock duty cycle and phase difference of SERDES_TX according to claim 1, characterized in that: The 4-to-1 multiplexer includes: four identical branches; One branch includes: a first NOR gate, a second NOR gate, a first NAND gate, a second NAND gate, a first PMOS transistor and a first NMOS transistor; The output terminal of the first NOR gate is connected to the first input terminal of the first NAND gate; The output terminal of the second NAND gate is connected to the second input terminal of the second NOR gate; The second input terminal of the first NAND gate is connected to the first input terminal of the second NOR gate, and the output terminal is connected to the gate of the first PMOS transistor; The output end of the second NOR gate is connected to the gate of the first NMOS tube; The drain of the first PMOS tube is connected to the drain of the first NMOS tube as an output end of the branch; The output ends of the four branches are connected as the output ends of a 4-to-1 multiplexer.

3. A circuit control method for detecting clock duty cycle and phase difference of SERDES_TX, characterized in that: include: Get the clock signal; Performing an XOR operation on the clock signal to obtain a phase difference; The clock signal is low-pass filtered to obtain a duty cycle.

4. The circuit control method for detecting clock duty cycle and phase difference of SERDES_TX according to claim 3, characterized in that: The performing an XOR operation on the clock signal to obtain a phase difference comprises: Input two clock signals into a 4-to-1 multiplexer; Adjust the control signal of the 4-to-1 multiplexer to 1100 or 0110; The phase difference between the two clocks is determined based on the output value of the 4-to-1 multiplexer.

5. The circuit control method for detecting clock duty cycle and phase difference of SERDES_TX according to claim 4, characterized in that: The low-pass filtering of the clock signal to obtain a duty cycle comprises: Inputting the clock signal into a low-pass filter module to obtain a constant level; The duty cycle is determined according to the constant level.

6. An electronic device, characterized in that: include: A chip, a processor and a memory, wherein the memory is used to store computer program code, wherein the computer program code includes computer instructions. When the chip executes the computer instructions, the electronic device executes a circuit control method for detecting clock duty cycle and phase difference for SERDES_TX as described in any one of claims 3 to 5.

7. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, which includes program instructions. When the program instructions are executed by a processor of an electronic device, the processor executes a circuit control method for detecting clock duty cycle and phase difference of SERDES_TX as described in any one of claims 3 to 5.

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