Three-dimensional memory device with through-stack contact

Abstract

A memory device includes a first alternating stack of first insulating layers and first conductive layers, a first dielectric material portion overlying a first step surface of the first alternating stack, a memory opening extending vertically through the first alternating stack, a memory opening fill structure in the memory opening and including a vertical stack of vertical semiconductor channels and memory elements, and a first contact via structure extending vertically through the first alternating stack and the first dielectric material portion. The first contact via structure includes a conductive pillar portion and a conductive fin portion laterally protruding from the conductive pillar portion and having a first annular bottom surface section contacting the annular top surface section of one of the first conductive layers.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of the entire contents of U.S. non-provisional application No. 18 / 361,629, filed on July 28, 2023, with the U.S. Patent and Trademark Office, entitled “THREE-DIMENSIONAL MEMORY DEVICE WITH THROUGH-STACK CONTACT VIA STRUCTURES AND METHOD OF MAKING THE SAME,” and is hereby incorporated by reference for all purposes, which non-provisional application claims priority to U.S. Provisional Application No. 63 / 499,819, filed on May 3, 2023. Technical Field

[0003] The present disclosure generally relates to the field of semiconductor devices, and more particularly to a three-dimensional memory device including a through-stack contact via structure and a method for manufacturing the same. Background Art

[0004] Three-dimensional vertical NAND strings with one bit per cell are disclosed in an article by T. Endoh et al. entitled "Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell", IEDM Proc. (2001) 33-36. Summary of the invention

[0005] According to one aspect of the present disclosure, a memory device is provided, the memory device comprising: a first alternating stack of a first insulating layer and a first conductive layer, wherein the first alternating stack comprises a first stepped surface in a contact region; a first dielectric material portion, the first dielectric material portion overlying the first stepped surface of the first alternating stack; a memory opening, the memory opening extending vertically at least through each layer within the first alternating stack; a memory opening filling structure, the memory opening filling structure being located in the memory opening and comprising a vertical semiconductor channel and a vertical stack of memory elements; and a first contact via structure, the first contact via structure extending vertically at least from the bottommost surface of the first alternating stack through the first dielectric material portion and extending to a horizontal plane located at or above the top surface of the memory opening filling structure, and the first contact via structure comprising a conductive pillar portion and a conductive fin portion, the conductive fin portion protruding laterally from the conductive pillar portion and having a first annular bottom surface segment of an annular top surface segment contacting one of the first conductive layers.

[0006] According to another aspect of the present disclosure, a method for forming a memory device is provided. The method includes: forming a first alternating stack of a first insulating layer and a first sacrificial material layer located above a substrate; forming a first stepped surface in a contact area by patterning the first alternating stack; forming a first dielectric material portion above the first stepped surface; forming a memory opening extending vertically through each layer within the first alternating stack; forming a memory opening filling structure including a vertical stack of vertical semiconductor channels and memory elements in the memory opening; replacing the first sacrificial material layer with a first conductive layer; and forming a first contact via structure, the first contact via structure extending vertically from at least the bottommost surface of the first alternating stack to a horizontal plane located at or above the top surface of the memory opening filling structure, wherein the first contact via structure includes a conductive pillar portion and a conductive fin portion, the conductive fin portion protruding laterally from the conductive pillar portion and having a first annular bottom surface section that contacts an annular top surface section of one layer in the first conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a vertical cross-sectional view of an exemplary structure after forming a first alternating stack of dielectric isolation layers, first insulating layers, and first sacrificial material layers, and a first stepped surface according to an embodiment of the present disclosure.

[0008] Figure 2 is a vertical cross-sectional view of an exemplary structure after forming a first insulating liner and a first sacrificial liner over a first stepped surface according to an embodiment of the present disclosure.

[0009] Figure 3 is a vertical cross-sectional view of an exemplary structure after forming a first stepped dielectric material portion according to an embodiment of the present disclosure.

[0010] Figure 4 is a vertical cross-sectional view of an exemplary structure after forming an interlayer dielectric layer and a first layer memory opening according to an embodiment of the present disclosure.

[0011] Figure 5A is a vertical cross-sectional view of an exemplary structure after forming a first layer support opening and a first layer contact opening according to an embodiment of the present disclosure.

[0012] Figure 5B yes Figure 5A A top-down view of an exemplary structure of FIG. The articulated vertical plane A-A' is Figure 5A A plane of a vertical section.

[0013] Figure 6is a vertical cross-sectional view of an exemplary structure after forming a first level sacrificial memory opening filling structure, a first level sacrificial support opening filling structure, and a first level sacrificial contact opening filling structure according to an embodiment of the present disclosure.

[0014] Figure 7 is a vertical cross-sectional view of an exemplary structure after forming a second alternating stack of second insulating layers and second sacrificial material layers, and a second stepped surface according to an embodiment of the present disclosure.

[0015] Figure 8 is a vertical cross-sectional view of an exemplary structure after forming a second insulating liner and a second sacrificial liner over the second stepped surface according to an embodiment of the present disclosure.

[0016] Fig. 9 is a vertical cross-sectional view of an exemplary structure after forming a second stepped dielectric material portion and an insulating cap layer according to an embodiment of the present disclosure.

[0017] Fig.10 is a vertical cross-sectional view of an exemplary structure after forming multi-layer support openings and multi-layer contact openings according to an embodiment of the present disclosure.

[0018] Fig.11 is a vertical cross-sectional view of an exemplary structure after forming a sacrificial support opening filling structure and a sacrificial contact opening filling structure according to an embodiment of the present disclosure.

[0019] Fig.12 is a vertical cross-sectional view of an exemplary structure after forming a support column structure according to an embodiment of the present disclosure.

[0020] Fig.13 is a vertical cross-sectional view of an exemplary structure after forming a dielectric cap layer according to an embodiment of the present disclosure.

[0021] Fig.14 is a vertical cross-sectional view of an exemplary structure after forming a memory opening according to an embodiment of the present disclosure.

[0022] Fig.15 is a vertical cross-sectional view of an exemplary structure after forming a memory opening filling structure according to an embodiment of the present disclosure.

[0023] Fig.16A is a vertical cross-sectional view of an exemplary structure after forming a contact-level dielectric layer and contact via cavities according to an embodiment of the present disclosure.

[0024] Fig. 16B yes Fig.16A A top-down view of an exemplary structure of FIG. The articulated vertical plane A-A' is Fig.16A A plane of a vertical section.

[0025] Fig.17 is a vertical cross-sectional view of an exemplary structure after forming a fin contact via cavity in a first stage process according to an embodiment of the present disclosure.

[0026] Fig.18 is a vertical cross-sectional view of an exemplary structure after conformally depositing a layer of conformal dielectric material according to an embodiment of the present disclosure.

[0027] Fig.19 is a vertical cross-sectional view of an exemplary structure after forming a vertical stack of annular insulating plates according to an embodiment of the present disclosure.

[0028] Fig. 20 is a vertical cross-sectional view of an exemplary structure after laterally expanding the fin contact via cavity in the second stage process to form the fin contact via cavity in the third stage process according to an embodiment of the present disclosure.

[0029] Fig.21 is a vertical cross-sectional view of an exemplary structure after forming a sacrificial fin-shaped cavity fill material structure according to an embodiment of the present disclosure.

[0030] Fig.22A is a vertical cross-sectional view of an exemplary structure after forming a sacrificial contact level dielectric layer and lateral isolation trenches according to an embodiment of the present disclosure.

[0031] Fig. 22B yes Fig.22A A top-down view of an exemplary structure of FIG. The articulated vertical plane A-A' is Fig.22A A plane of a vertical section.

[0032] Fig.23 is a vertical cross-sectional view of an exemplary structure after forming a laterally extending cavity according to an embodiment of the present disclosure.

[0033] Fig.24 is a vertical cross-sectional view of an exemplary structure after forming a backside blocking dielectric layer and a blocking dielectric liner according to an embodiment of the present disclosure.

[0034] Fig.25 is a vertical cross-sectional view of an exemplary structure after forming a conductive layer according to an embodiment of the present disclosure.

[0035] Fig.26 is a vertical cross-sectional view of an exemplary structure after forming source regions and insulating spacers according to an embodiment of the present disclosure.

[0036] Fig. 27 is a vertical cross-sectional view of an exemplary structure after forming a source contact via structure according to an embodiment of the present disclosure.

[0037] Fig.28 is a vertical cross-sectional view of an exemplary structure after removal of a sacrificial fin cavity fill material structure according to an embodiment of the present disclosure.

[0038] Fig.29 is a vertical cross-sectional view of an exemplary structure after expanding the fin contact via cavity according to an embodiment of the present disclosure.

[0039] Fig. 30A is a vertical cross-sectional view of an exemplary structure after forming a contact via structure according to an embodiment of the present disclosure.

[0040] Fig. 30B yes Fig. 30A A top-down view of an exemplary structure of FIG. The articulated vertical plane A-A' is Fig. 30A A plane of a vertical section. DETAILED DESCRIPTION

[0041] As discussed above, the present disclosure is directed to a three-dimensional memory device including a through-stack contact via structure and a method of manufacturing the same, various aspects of which are described below.

[0042] The drawings are not drawn to scale. Multiple instances of an element may be repeated where a single instance of an element is illustrated, unless explicitly described or otherwise clearly indicated that there is no repetition of an element. Ordinals such as "first," "second," and "third" are used only to identify similar elements, and different ordinals may be used in the specification and claims of the present disclosure. The term "at least one" element refers to all possibilities including the possibility of a single element and the possibility of multiple elements.

[0043] The same reference numerals represent the same elements or similar elements. Unless otherwise specified, elements with the same reference numerals are assumed to have the same composition and the same function. Unless otherwise specified, "contact" between elements refers to direct contact between elements providing an edge or surface shared by the elements. If two or more elements are not in direct contact with each other or with each other, the two elements are "separated" from each other or "separated" from each other. As used herein, the element "on" the second element may be located on the outside of the surface of the second element or the inside of the second element. As used herein, if there is physical contact between the surface of the element and the surface of the second element, the element is "directly located" on the second element. As used herein, if there is a conductive path composed of at least one conductive material between the element and the second element, the element is "electrically connected to" the second element. As used herein, a "prototype" structure or "in-process" structure refers to a transient structure that is subsequently modified in terms of the shape or composition of at least one component therein.

[0044] As used herein, "layer" refers to a portion of a material including a region having a thickness. A layer may extend over the entire underlying structure or overlying structure, or may have an extent that is smaller than the extent of the underlying structure or overlying structure. In addition, a layer may be a region of a uniform or non-uniform continuous structure having a thickness that is less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below.

[0045] Generally speaking, a semiconductor die or a semiconductor package may include a memory chip. Each semiconductor package contains one or more die (e.g., one, two, or four). A die is the smallest unit that can independently execute a command or report a status. Each die contains one or more planes (usually one or two). Although there are some limitations, the same concurrent operations can be performed on each plane. Each plane contains multiple blocks, which are the smallest units that can be erased by a single erase operation. Each block contains multiple pages, which are the smallest units that can be programmed, that is, the smallest units on which a read operation can be performed.

[0046] refer to Figure 1 , illustrates an exemplary structure according to an embodiment of the present disclosure, the exemplary structure comprising a substrate 8 including a semiconductor material layer 9 at least in its upper portion. The semiconductor material layer 9 may include a single crystal semiconductor material layer or a polycrystalline semiconductor material layer. Below the semiconductor material layer, the substrate 8 may or may not include additional layers (such as a dielectric material layer embedded in a metal interconnect structure) and / or semiconductor devices (such as peripheral circuits for controlling the operation of a three-dimensional memory array to be formed subsequently). In one embodiment, the substrate 8 may include a commercially available semiconductor wafer, such as a single crystal silicon wafer. The semiconductor material layer 9 may include an upper portion of a silicon wafer, a doped well in a silicon wafer, an epitaxial silicon layer on a silicon wafer, and the like.

[0047] The exemplary structure includes a memory array region 100 and a contact region 300. The memory array region 100 is a region in which a three-dimensional memory array is to be formed subsequently. The contact region 300 is a region in which a layer contact via structure that contacts a conductive line used as a word line of the three-dimensional memory array is to be formed subsequently. The contact region 300 may include a first contact region 301, in which a first contact via structure providing electrical connection to a first conductive layer is to be formed subsequently, and a second contact via structure providing electrical connection to a second conductive layer is to be formed subsequently in the second contact region 302. The memory array region 100 may be disposed adjacent to the contact region 300.

[0048] An optional dielectric isolation layer 6 may be formed in an upper portion of the substrate 8. The dielectric isolation layer 6 may include a silicon oxide layer that is located in the contact region 300 and may optionally extend into the memory array region 100.

[0049] A first alternating stack of first insulating layers 132 and first sacrificial material layers 142 may be formed over a substrate 8. The first insulating layer 132 includes an insulating material such as undoped silicate glass or doped silicate glass, and the first sacrificial material layer 142 includes a sacrificial material such as silicon nitride or a silicon-germanium alloy. The first alternating stack (132, 142) may include multiple repetitions of a unit layer stack including the first insulating layer 132 and the first sacrificial material layer 142. The total number of repetitions of the unit layer stack within the first alternating stack (132, 142) may be, for example, in the range of 8 to 1,024 (such as 32 to 256), but fewer and greater numbers of repetitions may also be employed. Each of the first insulating layers 132 may have a thickness in the range of 20 nm to 100 nm (such as 30 nm to 60 nm), but smaller and greater thicknesses may also be employed. Each of the first sacrificial material layers 142 may have a thickness in a range of 20 nm to 100 nm, such as 30 nm to 60 nm, although lesser and greater thicknesses may also be employed.

[0050] A first stepped surface is formed in the first contact region 301. As used herein, "stepped surface" refers to a set of surfaces including at least two horizontal surfaces and at least two vertical surfaces, such that each horizontal surface is adjacent to a first vertical surface extending upward from a first edge of the horizontal surface and adjacent to a second vertical surface extending downward from a second edge of the horizontal surface. A first stepped cavity is formed in a volume from which a portion of the first alternating stack (132, 142) is removed by the formation of the first stepped surface. A "stepped cavity" refers to a cavity having a stepped surface.

[0051] The first stepped cavity may have various first stepped surfaces such that the horizontal cross-sectional shape of the first stepped cavity changes stepwise as a function of the vertical distance from the top surface of the substrate 8. In one embodiment, the first stepped cavity may be formed by repeatedly performing a set of processing steps. The set of processing steps may include, for example, a first type of etching process that vertically increases the depth of the cavity by one or more levels, and a second type of etching process that laterally expands the area to be vertically etched in a subsequent first type of etching process. As used herein, a structure including an alternating plurality of "levels" is defined as the relative positions of a pair of first material layers and a second material layer within the structure.

[0052] Each first sacrificial material layer 142 in the first alternating stack (132, 142) except for the topmost first sacrificial material layer 142 extends laterally further than any overlying first sacrificial material layer 142 in the step region in the first alternating stack (132, 142). A first stepped surface of the first alternating stack (132, 142) extends continuously from a bottommost layer in the first alternating stack (132, 142) to a topmost layer in the first alternating stack (132, 142). Typically, the first stepped surface extends continuously from a bottommost layer in the first alternating stack (132, 142) to at least a topmost layer in the first alternating stack (132, 142).

[0053] refer to Figure 2 , a first insulating liner 152 and a first sacrificial liner 154 may be sequentially deposited over the first stepped surface. The first insulating liner 152 may be formed by a first conformal deposition process and may include an insulating material, such as undoped silicate glass (i.e., silicon oxide) or doped silicate glass. The thickness of the first insulating liner 152 may be in a range from 10nm to 50nm, such as from 15nm to 30nm, but smaller and larger thicknesses may also be used. The first sacrificial liner 154 may be formed by a second conformal deposition process and may include a sacrificial material that may be selectively removed from the material of the first insulating liner 152 subsequently. In one embodiment, the first sacrificial liner 154 may include silicon nitride. The thickness of the first sacrificial liner 154 is greater than the thickness of the first sacrificial material layer 142 and may be in a range from 40nm to 150nm, such as from 60nm to 100nm, but smaller and larger thicknesses may also be used.

[0054] refer to Figure 3 , a dielectric filling material, such as silicon oxide, may be deposited in the first stepped cavity. Excess portions of the deposited dielectric filling material may be removed, for example, by chemical mechanical planarization (CMP) from above a horizontal plane including the top surface of the first sacrificial liner 154. A recess etching process may be performed to vertically recess the remaining portion of the dielectric filling material by a vertical recess distance that is the same as the thickness of the first sacrificial liner 154. An isotropic etching process may then be performed to selectively remove the horizontally extending portion of the first sacrificial liner 154 with respect to the material of the first insulating liner 152. The remaining portion of the dielectric filling material that fills the first stepped cavity constitutes a first stepped dielectric material portion 165. The first stepped dielectric material portion 165 may be reverse stepped.

[0055] As used herein, a "reverse step" element refers to an element having a first step surface and a horizontal cross-sectional area that increases monotonically as a function of the vertical distance from the top surface of the substrate on which the element resides. If silicon dioxide is used for the first step dielectric material portion 165, the silicon dioxide of the first step dielectric material portion 165 may or may not be doped with dopants such as B, P, and / or F. In one embodiment, the first step dielectric material portion 165 covers and contacts the first step surface and has a top surface that is coplanar with a top surface of a horizontally extending portion of the first insulating liner 152 that covers the first alternating stack (132, 142) in the memory array region 100.

[0056] refer to Figure 4 , a dielectric material layer may be formed over the first insulating liner 152 and the first stepped dielectric material portion 165. The dielectric material layer is referred to herein as an interlayer dielectric layer 180. The interlayer dielectric layer 180 includes a dielectric material such as silicon oxide and may have a thickness in a range from 50 nm to 200 nm such as 80 nm to 160 nm, although smaller and larger thicknesses may also be employed.

[0057] A first photoresist layer (not shown) may be applied over the interlayer dielectric layer 180, and the first photoresist layer may be photolithographically patterned to form an array of openings in the memory array region 100. An anisotropic etching process may be performed to transfer the pattern of the openings in the first photoresist layer through the interlayer dielectric layer 180, the first insulating liner 152, and the first alternating stack (132, 142) and optionally into the upper portion of the semiconductor material layer 9. The first layer of memory openings 149 may be formed through the interlayer dielectric layer 180, the first insulating liner 152, and the first alternating stack (132, 142). The overetching depth of the first layer of memory openings 149 into the semiconductor material layer 9 may be in the range of from 0 nm to 50 nm, such as from 5 nm to 30 nm, but a greater overetching depth may also be employed. Subsequently, the first photoresist layer may be removed, for example, by ashing.

[0058] refer to Figure 5A and Figure 5B, a second photoresist layer (not shown) may be applied over the interlayer dielectric layer 180, and the second photoresist layer may be photolithographically patterned to form openings in the contact regions 300. An anisotropic etching process may be performed to transfer the pattern of the openings in the second photoresist layer through the interlayer dielectric layer 180, the first sacrificial liner 154, the first insulating liner 152, the first stepped dielectric material portion 165, and the portion of the first alternating stack (132, 142) underlying the first stepped dielectric material portion 165, and optionally into the upper portion of the dielectric isolation layer 6 (if present) or the semiconductor material layer 9 (if layer 6 is omitted). The first layer contact opening 139 may be formed in an area where a layer contact via structure will be subsequently formed. The layer contact via structure is a contact via structure that will contact a subsequently formed conductive layer. The first layer support opening 119 may be formed in an area laterally surrounding the first layer contact opening 139. A support post structure is then formed in the volume of the first layer support opening 119, and the support post structure serves as a structural support structure during replacement of the first sacrificial material layer 142 with the first conductive layer. Subsequently, the second photoresist layer may be removed, for example, by ashing. The first layer memory openings 149 may be arranged in rows extending along a first horizontal direction (e.g., a word line direction) hd1. The rows of the first layer memory openings 149 may be laterally spaced apart from each other along a second horizontal direction (e.g., a bit line direction) hd2, which may be perpendicular to the first horizontal direction. The first layer contact openings 139 may be arranged in rows extending laterally along the first horizontal direction hd1.

[0059] refer to Figure 6 , an optional etch stop liner (not shown) and a first sacrificial fill material may be deposited in the first layer memory opening 149, the first layer support opening 119, and the first layer contact opening 139. The optional etch stop liner, if present, comprises a thin silicon oxide layer having a thickness in the range of 1 nm to 6 nm. The first sacrificial fill material may comprise a carbon-based material such as amorphous carbon or diamond-like carbon, a semiconductor material such as amorphous silicon or polycrystalline silicon, a dielectric fill material such as borosilicate glass or organosilicate glass, or a polymer material.

[0060] A recess etching process may be performed to remove portions of the first sacrificial filling material from above a horizontal plane including the top surface of the interlayer dielectric layer 180. In one embodiment, each remaining portion of the first sacrificial filling material has a top surface within a horizontal plane including the top surface of the interlayer dielectric layer 180. The remaining portions of the first sacrificial filling material filling the first layer memory openings 149 constitute a first layer sacrificial memory opening filling structure 148. The remaining portions of the first sacrificial filling material filling the first layer support openings 119 constitute a first layer sacrificial support opening filling structure 118. The remaining portions of the first sacrificial filling material filling the first layer contact openings 139 constitute a first layer sacrificial contact opening filling structure 138.

[0061] refer to Figure 7 , a second alternating stack of a second insulating layer 232 and a second sacrificial material layer 242 may be formed over the first alternating stack (132, 142). The second insulating layer 232 includes an insulating material, such as undoped silicate glass (i.e., silicon oxide) or doped silicate glass, and the second sacrificial material layer 242 includes a sacrificial material, such as silicon nitride. The second alternating stack (232, 242) may include multiple repetitions of a unit layer stack, which includes the second insulating layer 232 and the second sacrificial material layer 242. The total number of repetitions of the unit layer stack within the second alternating stack (232, 242) may be, for example, in the range of 8 to 1,024 (such as, 32 to 256), but fewer and greater numbers of repetitions may also be used. Each of the second insulating layers 232 may have a thickness in the range of 20 nm to 100 nm (such as, 30 nm to 60 nm), but smaller and greater thicknesses may also be used. Each of the second sacrificial material layers 242 may have a thickness in the range of 20 nm to 100 nm (e.g., 30 nm to 60 nm), but smaller and larger thicknesses may also be employed. Although two alternating stacks are provided in this embodiment, in other embodiments, only one alternating stack or more than two alternating stacks (e.g., three alternating stacks) may be used.

[0062] A second stepped surface is formed in the second contact region 302. A second stepped cavity is formed in a volume from which a portion of the second alternating stack (232, 242) is removed by the formation of the second stepped surface. The second stepped cavity may have various second stepped surfaces so that the horizontal cross-sectional shape of the second stepped cavity changes stepwise as a function of the vertical distance from the top surface of the substrate 8. In one embodiment, the second stepped cavity may be formed by repeatedly performing a set of processing steps. The set of processing steps may include, for example, a second type of etching process that vertically increases the depth of the cavity by one or more levels, and a second type of etching process that laterally expands the area to be vertically etched in a subsequent second type of etching process.

[0063] Each second sacrificial material layer 242 in the second alternating stack (232, 242) except for the topmost second sacrificial material layer 242 extends laterally further than any overlying second sacrificial material layer 242 in the stepped region in the second alternating stack (232, 242). The second stepped surface of the second alternating stack (232, 242) extends continuously from the bottommost layer in the second alternating stack (232, 242) to the topmost layer in the second alternating stack (232, 242). Typically, the second stepped surface extends continuously from the bottommost layer in the second alternating stack (232, 242) to at least the topmost layer in the second alternating stack (232, 242).

[0064] refer to Figure 8 , a second insulating liner 252 and a second sacrificial liner 254 may be sequentially deposited over the second stepped surface. The second insulating liner 252 may be formed by a conformal deposition process and may include an insulating material such as undoped silicate glass or doped silicate glass. The thickness of the second insulating liner 252 may be the same as the thickness of the first insulating liner 152. The second sacrificial liner 254 may be formed by a conformal deposition process and may include a sacrificial material that may be selectively removed from the material of the second insulating liner 252 subsequently. In one embodiment, the second sacrificial liner 254 may include silicon nitride. The thickness of the second sacrificial liner 254 is greater than the thickness of the second sacrificial material layer 242 and may be the same as the thickness of the first sacrificial liner 154.

[0065] A resist layer (not shown) may be applied over the second sacrificial liner 254, and the resist layer may be photolithographically patterned so that the photoresist layer covers the memory array region 100 and the second contact region 302 and does not cover the first contact region 301. A first etching process may be performed to remove an unmasked portion of the second sacrificial liner 254 in the first contact region 301. A second etching process may be performed to remove an unmasked portion of the second insulating liner 252 in the first contact region 301. Subsequently, the photoresist layer may be removed, for example, by ashing.

[0066] refer to Fig. 9 , a dielectric filling material, such as silicon oxide, may be deposited in the second stepped cavity. Excess portions of the deposited dielectric filling material may be removed, for example, by chemical mechanical planarization (CMP) from above a horizontal plane including the top surface of the second sacrificial liner 254. A recess etching process may be performed to vertically recess the remaining portion of the dielectric filling material by a vertical recess distance that is the same as the thickness of the second sacrificial liner 254. An isotropic etching process may then be performed to selectively remove the horizontally extending portion of the second sacrificial liner 254 with respect to the material of the second insulating liner 252. The remaining portion of the dielectric filling material that fills the second stepped cavity constitutes a second stepped dielectric material portion 265.

[0067] If silicon dioxide is used for the second stepped dielectric material portion 265 , the silicon dioxide of the second stepped dielectric material portion 265 may or may not be doped with dopants such as B, P, and / or F. In one embodiment, the second stepped dielectric material portion 265 covers and contacts the second stepped surface and has a top surface that is coplanar with a top surface of a horizontally extending portion of the second insulating liner 252 that covers the second alternating stacks ( 232 , 242 ) in the memory array region 100 .

[0068] An insulating cap layer 270 may be formed over the second insulating liner 252 and the second stepped dielectric material portion 265. The insulating cap layer 270 includes a dielectric material such as silicon oxide and may have a thickness ranging from 50 nm to 200 nm such as 80 nm to 260 nm, although lesser and greater thicknesses may also be employed.

[0069] refer to Fig.10 , a photoresist layer (not shown) may be applied over the insulating cap layer 270, and the photoresist layer may be photolithographically patterned to form openings over the regions of the first layer sacrificial contact opening filling structures 138 and the first layer sacrificial support opening filling structures 118. An anisotropic etching process may be performed to transfer the pattern of the openings in the photoresist layer through the insulating cap layer 270, the second stepped dielectric material portion 265, the second sacrificial liner 254, the second insulating liner 252, and the portion of the second alternating stack (232, 242) underlying the second stepped dielectric material portion 265. Subsequently, the sacrificial filling material of the first layer sacrificial contact opening filling structures 138 and the first layer sacrificial support opening filling structures 118 may be removed selectively to the materials of the insulating cap layer, the first alternating stack (132, 232), the second alternating stack (232, 242), the interlayer dielectric layer 180, and the dielectric isolation layer 6. For example, a selective etching process or an ashing process (for carbon sacrificial material) may be performed to remove the sacrificial filling materials of the first layer sacrificial contact opening filling structure 138 and the first layer sacrificial support opening filling structure 118 .

[0070] Multilayer contact openings 39 (also referred to as contact openings 39) may be formed in the volume from which the first layer of sacrificial contact opening filling structures 138 are removed, and in the volume overlying the volume of the first layer of sacrificial contact opening filling structures 138 and vertically extending through the second alternating stacks (232, 242) and / or the second stepped dielectric material portion 265 and through the insulating cap layer 270. Multilayer support openings 19 (also referred to as support openings 39) may be formed in the volume from which the first layer of sacrificial support opening filling structures 118 are removed, and in the volume overlying the volume of the first layer of sacrificial support opening filling structures and vertically extending through the second alternating stacks (232, 242) and / or the second stepped dielectric material portion 265 and through the insulating cap layer 270. Subsequently, the photoresist layer may be removed, for example, by ashing.

[0071] refer to Fig.11 , an optional etch stop liner (not shown) and a second sacrificial fill material may be deposited in the multi-layer support opening 19 and the multi-layer contact opening 39. The optional etch stop liner, if present, comprises a thin silicon oxide layer having a thickness in the range of 2 nm to 6 nm. The first sacrificial fill material may comprise a carbon-based material (such as amorphous carbon or diamond-like carbon), a semiconductor material (such as amorphous silicon or polycrystalline silicon), a dielectric fill material (such as borosilicate glass or organosilicate glass), or a polymer material.

[0072] A recess etching process may be performed to remove portions of the second sacrificial filling material from above a horizontal plane including the top surface of the insulating cap layer 270. In one embodiment, each remaining portion of the second sacrificial filling material has a top surface within a horizontal plane including the top surface of the insulating cap layer 270. The remaining portions of the second sacrificial filling material filling the multi-layer support openings 19 constitute a sacrificial support opening filling structure 18. The remaining portions of the second sacrificial filling material filling the multi-layer contact openings 39 constitute a sacrificial contact opening filling structure 38. A capping insulating layer 270A is formed over the insulating cap layer 270, the sacrificial support opening filling structure 18, and the sacrificial contact opening filling structure 38. The capping insulating layer 270A may include silicon oxide and be incorporated into the insulating cap layer 270.

[0073] refer to Fig.12A photoresist layer (not shown) may be applied over the insulating cap layer 270, and the photoresist layer may be photolithographically patterned to form an opening in a region overlying the sacrificial support opening filling structure 18. The sacrificial support opening filling structure 18 may be selectively removed from the insulating cap layer 270, the alternating stack {(132, 142), (232, 242)}, the interlayer dielectric layer 180, and the dielectric isolation layer 6. An anisotropic etching process, an isotropic etching process, or an ashing process may be used. Subsequently, the photoresist layer may be removed, for example, by ashing. The cavity formed by removing the sacrificial support opening filling structure 18 includes a plurality of support openings 19, which are referred to as subsequent process support openings.

[0074] refer to Fig.13 , at least one dielectric spacer layer (272, 273) may be optionally formed in the support opening 19 and over the insulating cap layer 270. The at least one dielectric spacer layer (272, 273) may include an outer dielectric spacer layer 272 and an optional inner dielectric spacer layer 273. In an illustrative example, the outer dielectric spacer layer 272 may include a silicon nitride layer that is converted into a silicon oxide or silicon oxynitride layer by plasma oxidation. The inner dielectric spacer layer 273 may include a deposited silicon oxide layer. Alternatively, the inner dielectric spacer layer 273 may be omitted. The at least one dielectric spacer layer prevents the silicon nitride layer subsequently formed in the multi-layer support opening 19 from being exposed to the subsequently formed lateral isolation trenches, and thus prevents being removed together with other silicon nitride sacrificial material layers (142, 242) during replacement of the sacrificial material layer with a conductive layer.

[0075] refer to Fig.14 A photoresist layer (not shown) may be applied over the dielectric spacer layers (272, 274), and the photoresist layer may be photolithographically patterned to form openings in the region of the first layer sacrificial memory opening filling structure 148. An anisotropic etching process may be performed to form openings through the dielectric spacer layers (272, 274), the insulating cap layer 270, and the second alternating stack (232, 242) below the openings in the photoresist layer and above the first layer sacrificial memory opening filling structure 148. The first layer sacrificial memory opening filling structure 148 may then be removed selectively to the material of the dielectric spacer layers (272, 274), the insulating cap layer 270, the alternating stack {(132, 142), (232, 242)}, and the interlayer dielectric layer 180. Multi-layer memory opening 49 (also referred to as memory opening 49) is formed in the volume from which first layer of sacrificial memory opening filling structure 148 was removed and in the volume of the cavity overlying the volume from which first layer of sacrificial memory opening filling structure 148 was removed. Subsequently, the photoresist layer may be removed, for example, by ashing.

[0076] refer to Fig.15, a series of processing steps may be performed to form a memory opening filling structure 58 within each interlayer memory opening 49 and simultaneously form a support pillar structure 20 within each interlayer support opening 19. For example, a memory film 50 may be formed within each of the memory opening 49 and the support opening 19. The memory film 50 may include any memory material that can store information by charge trapping, a change in resistivity, a change in ferroelectric polarization direction (e.g., in a ferroelectric material), or any other material in which information can be stored. For example, each memory film 50 may include a layer stack that includes a blocking dielectric layer 52, a charge storage material layer 54, and a tunneling dielectric layer 56. In one embodiment, the memory film 50 may be formed by depositing a material layer and / or a material portion, and removing excess portions of the material layer and / or a material portion from the outside and bottom of the memory opening 49 and the support opening 19, for example, by performing an anisotropic etching process (e.g., a sidewall spacer etching process). In one embodiment, the blocking dielectric layer 52 may include a silicon oxide or aluminum oxide layer. The charge storage material layer 54 may include a silicon nitride layer. Tunneling dielectric layer 56 may include a silicon oxide layer or an “ONO” stack of silicon oxide / silicon nitride / silicon oxide layers.

[0077] A vertical semiconductor channel 60 may be formed in each of the memory opening 49 and the support opening 19 by conformally depositing a semiconductor channel material (e.g., amorphous silicon or polycrystalline silicon) doped with a first conductivity type. The semiconductor channel material may have a doping of the same conductivity type as a horizontal semiconductor channel (not explicitly shown) located in the substrate 9. A dielectric fill material may be deposited in the remaining volume of the memory opening 49 and the support opening 19, and the dielectric fill material may be vertically recessed to form a dielectric core 62. A semiconductor material (e.g., amorphous silicon or polycrystalline silicon) doped with a second conductivity type may be deposited above each dielectric core 62 at the top of each vertical semiconductor channel 60 to form a drain region 63 within each of the memory opening 49 and the support opening 19. The second conductivity type is opposite to the first conductivity type. Each adjacent combination of the memory film 50 and the vertical semiconductor channel 60 constitutes a memory stack structure 55. Each memory stack structure 55 includes a corresponding vertical stack of memory elements. For example, each vertical stack of memory elements may include portions of the charge storage layer 54 at the level of the sacrificial material layer (142, 242), which portions are subsequently replaced by a conductive layer.

[0078] Typically, the memory opening filling structures 58 are formed in the memory openings 49, and the support pillar structures 20 are formed in the support openings 19. Each of the memory opening filling structures 58 includes a corresponding vertical semiconductor channel 60, a corresponding vertical stack of memory elements (e.g., portions of the memory film 50), a drain region 63, and an optional dielectric core 62. Each of the support pillar structures 20 includes a dummy vertical semiconductor channel (which is not electrically connected to a bit line), a dummy memory film, a dummy drain region, and an optional dielectric core that include the same material as the memory opening filling structures 58. In one embodiment, each of the support pillar structures 20 also includes at least one dielectric spacer layer (272, 273) surrounding the dummy memory film, while the memory opening filling structures 58 lack at least one dielectric spacer layer (272, 274). In alternative embodiments, the support pillar structures may be formed separately from the memory opening filling structures 58 (e.g., formed before or after them). In alternative embodiments, the support pillar structures 20 may contain only insulating material, such as silicon oxide. The drain select level dielectric isolation structure 72 may be formed through the uppermost set of second sacrificial material layers 242 .

[0079] refer to Fig.16A and Fig. 16B, a contact level dielectric layer 280 may be optionally formed over the dielectric spacer layers (272, 274). A photoresist layer may be applied over the contact level dielectric layer 280, and the photoresist layer may be photolithographically patterned to form openings in areas overlying the sacrificial contact opening fill structures 38. An anisotropic etching process may be performed to transfer the pattern of the openings in the photoresist layer through the contact level dielectric layer 280 and the dielectric spacer layers (272, 274). A cavity may be formed over each sacrificial contact opening fill structure 38 through the contact level dielectric layer 280 and the dielectric spacer layers (272, 273). The sacrificial contact opening filling structure 38 may then be removed selectively to the materials of the contact level dielectric layer 280, the dielectric spacer layers (272, 274), the insulating cap layer 270, the alternating stack {(132, 142), (232, 242)}, the interlayer dielectric layer 180, and the optional dielectric isolation layer 6 (if present). A contact via cavity 81 is formed in the volume from which the sacrificial contact opening filling structure 38 was removed and in the volume of the cavity overlying the volume from which the sacrificial contact opening filling structure 38 was removed. The photoresist layer may then be removed, for example, by ashing. The contact via cavity 81 includes: a first contact via cavity 81A, which is formed in the first contact area 301 and extends through the first stepped dielectric material portion 165 and the first alternating stack (132, 142); and a second contact via cavity 81B, which is formed in the second contact area 302 and extends through the second stepped dielectric material portion 265, the first alternating stack (132, 142) and the second alternating stack (232, 242).

[0080] refer to Fig.17 A first isotropic etching process may be performed to isotropically recess the material of the sacrificial material layer (142, 242), the first sacrificial liner 154, and the second sacrificial liner 254 selectively to the material of the contact level dielectric layer 280, the dielectric spacer layer (272, 274), the insulating cap layer 270, the insulating layer (132, 232), the interlayer dielectric layer 180, and the dielectric isolation layer 6 (if present). For example, if the sacrificial material layer (142, 242), the first sacrificial liner 154, and the second sacrificial liner 254 include silicon nitride, a wet etching process using hot phosphoric acid may be performed to laterally recess the sacrificial material layer (142, 242).

[0081] Typically, the sidewalls of the sacrificial material layer (142, 242), the first sacrificial liner 154, and the second sacrificial liner 254 may be laterally recessed relative to the sidewalls of the insulating layer (132, 232) and the stepped dielectric material portion (165, 265) surrounding the contact via cavity 81. A lateral recess 41 is formed in the volume from which the material of the sacrificial material layer (142, 242) is removed. The lateral recess 41 may have a width of 50nm to 250nm (such as 100nm to 150nm) and may be configured to obtain a desired electric field between the word line and the layer contact via structure to be formed in a subsequent step, as will be described below. A first annular cavity 155 may be formed in each volume from which an annular portion of the first sacrificial liner 154 is removed around a corresponding one of the first contact via cavities 81A. A second annular cavity 255 may be formed in each volume from which an annular portion of the second sacrificial liner 254 is removed around a corresponding one of the second contact via cavities 81B.

[0082] Typically, the first isotropic etching process etches the first sacrificial liner 154 and the proximal portion of the first sacrificial material layer 142 from around each first contact via cavity 81A to form a corresponding fin-shaped cavity, which is referred to herein as the first first-stage process fin-shaped contact via cavity 82A. In addition, the first isotropic etching process etches the second sacrificial liner 154, the first sacrificial material layer 142, and the proximal portion of the second sacrificial material layer 242 from around each second contact via cavity 81B to form a corresponding fin-shaped cavity, which is referred to herein as the second first-stage process fin-shaped contact via cavity 82B. The first first-stage process fin-shaped contact via cavity 82A and the second first-stage process fin-shaped contact via cavity 82A include the first-stage process fin-shaped contact via cavity 82.

[0083] Each first first-stage process fin-shaped contact via cavity 82A includes a cylindrical cavity, a first annular cavity 155, and at least one lateral recess 41 formed by removing an annular portion of a corresponding first sacrificial material layer 142, wherein the cylindrical cavity includes the volume of the corresponding first contact via cavity 82A. Each second first-stage process fin-shaped contact via cavity 82B includes a cylindrical cavity, a second annular cavity 255, and a lateral recess 41 formed by removing annular portions of a first sacrificial material layer 142 and at least one second sacrificial material layer 242, wherein the cylindrical cavity includes the volume of the corresponding second contact via cavity 82B.

[0084] The physically exposed recessed surfaces of the sacrificial material layer (142, 242), the first sacrificial liner 154, and the second sacrificial liner 254 after the first isotropic etching process include sidewall segments that are laterally offset by a uniform lateral offset distance from the sidewalls of the insulating layer (132, 232) and the stepped dielectric material portion (165, 265) surrounding the cylindrical cavity of the fin-shaped contact via cavity 82 in the corresponding first stage process. The uniform lateral offset distance can be the same as the etching distance of the first isotropic etching process.

[0085] refer to Fig.18 , a conformal dielectric material layer 40L may be deposited in the fin contact via cavity 82 in the first stage process by a conformal deposition process (such as a low pressure chemical vapor deposition process or an atomic layer deposition process). The conformal dielectric material layer 40L may be conformally deposited to completely fill the volume of the lateral recess 41 without completely filling the volume of the first annular cavity 155 or the second annular cavity 255. The conformal dielectric material layer 40L includes a material different from that of the sacrificial material layer (142, 242). For example, the conformal dielectric material layer 40L includes silicon oxide.

[0086] As discussed above, the first sacrificial liner 154 and the second sacrificial liner 254 have a thickness greater than the thickness of the sacrificial material layer (142, 242). Therefore, the first annular cavity 155 or the second annular cavity 255 has a height greater than the height of the lateral recess 41. The thickness of the conformal dielectric material layer 40L may be greater than half of the height of the lateral recess 41, and may be less than half of the height of the first annular cavity 155 or the second annular cavity 255. Therefore, the volume of the first annular cavity 155 or the second annular cavity 255 may be partially filled with the conformal dielectric material layer 40L, while there is still an unfilled volume within each of the first annular cavity 155 or the second annular cavity 255.

[0087] refer to Fig.19 , an isotropic recess etching process may be performed to isotropically recess the conformal dielectric material layer 40L. For example, if the conformal dielectric material layer 40L includes silicon oxide, a wet etching process using dilute hydrofluoric acid may be performed to isotropically recess the conformal dielectric material layer 40L around the cavities passing through the alternating stack {(132, 142), (232, 242)}. The duration of the isotropic etching process may be selected so that the isotropic recess etching process completely removes material of the conformal dielectric material layer 40L from the interior of each of the first annular cavity 155 and the second annular cavity 255. The remaining portion of the conformal dielectric material layer 40L that fills the lateral recess 41 (i.e., the volume from which the portion of the sacrificial material layer (142, 242) is removed) constitutes an annular insulating plate 40 (e.g., an insulating fin).

[0088] The remaining volume of the first-stage process fin-shaped contact via cavity 82 is referred to herein as the second-stage process fin-shaped contact via cavity 83. The second-stage process fin-shaped contact via cavity 83 may include a first second-stage process fin-shaped contact via cavity 83A extending through the first stepped dielectric material portion 165 and a portion of the first alternating stack (132, 142), and a second second-stage process fin-shaped contact via cavity 83B extending through the second stepped dielectric material portion 265 and a portion of the second alternating stack (232, 242). Each second-stage process fin-shaped contact via cavity 83 includes a cylindrical cavity portion 83C and an annular cavity portion 83F, the cylindrical cavity portion having a cylindrical shape and extending vertically from the top surface of the contact level dielectric layer 280 to the dielectric isolation layer 6 (if present, or alternatively to the substrate 8), the annular cavity portion adjacent to and laterally surrounding the cylindrical cavity portion 83C. Each annular cavity portion 83F may be defined by an annular bottom surface of the stepped dielectric material portion (165, 265), a cylindrical sidewall of the sacrificial liner (154, 254), and an annular top surface segment of the insulating liner (152, 252).

[0089] At least one annular insulating plate 40 may be present around each second-stage process fin contact via cavity 83. Each of the plurality of first second-stage process fin contact via cavities 83A and second second-stage process fin contact via cavities 83B may be laterally surrounded by a corresponding vertical stack of annular insulating plates 40. The first second-stage process fin contact via cavity 83A may include a first cylindrical surface and a second cylindrical surface, the first cylindrical surface vertically extending through the first stepped dielectric material portion 165 and the second stepped dielectric material portion 265 and having a bottom periphery adjacent to the inner periphery of the annular top surface of the annular cavity portion 83F, and the second cylindrical surface vertically extending through a subset of the layers within the first alternating stack (132, 142) and having a top periphery adjacent to the annular bottom surface of the annular cavity portion 83F. The second second stage process fin contact via cavity 83B may include a first cylindrical surface and a second cylindrical surface, the first cylindrical surface extending vertically through the second stepped dielectric material portion 265 and having a bottom perimeter adjacent to the inner perimeter of the annular top surface of the annular cavity portion 83F, and the second cylindrical surface extending vertically through a subset of the layers within the second alternating stack (232, 242) and each layer within the first alternating stack (132, 142) and having a top perimeter adjacent to the annular bottom surface of the annular cavity portion 83F. Typically, each second second stage process fin contact via cavity 83 includes the entire volume of the corresponding contact via cavity 81 and the volume formed by removing a portion of the sacrificial liner (154, 254) during the first isotropic etching process.

[0090] refer to Fig. 20, a second isotropic etching process may be performed to selectively and isotropically recess the material of the sacrificial pad (154, 254) with respect to the material of the contact level dielectric layer 280, the dielectric spacer layer (272, 274), the insulating cap layer 270, the insulating layer (132, 232), the interlayer dielectric layer 180, the dielectric isolation layer 6 (if present), and the annular insulating plate 40. For example, if the sacrificial pad (154, 254) includes silicon nitride, a wet etching process using hot phosphoric acid may be performed to isotropically recess the sacrificial pad (154, 254). The volume of each annular cavity portion 83F may be laterally expanded by the second isotropic etching process. The second stage process fin contact via cavity 83 expanded by the second isotropic etching process is referred to herein as the third stage process fin contact via cavity 85.

[0091] Typically, the fin contact via cavity 85 in the third stage process can be formed by performing a second isotropic etching process to laterally recess the sidewalls of the sacrificial liner (154, 254) surrounding the fin contact via cavity 83 in the second stage process. The lateral recess distance of the second isotropic etching process can be in the range of from 20nm to 300nm, such as from 40nm to 150nm, but smaller and larger lateral etching distances can also be used. The fin contact via cavity 85 in the third stage process includes a first fin contact via cavity 85A in the third stage process formed in the first contact area 301 and a second fin contact via cavity 85B in the third stage process formed in the second contact area 302. Each of the fin contact via cavities 85 in the third stage process includes a cylindrical cavity portion 85C and an annular cavity portion 85F. In one embodiment, each annular cavity portion 85F may have: a stepped top surface, the stepped top surface comprising a first annular top surface segment, the first annular top surface segment being an annular bottom surface segment of the stepped dielectric material portion (165, 265); a cylindrical surface segment adjacent to the outer periphery of the first annular top surface segment; and a second annular top surface segment, the second annular top surface segment being another annular bottom surface segment of the stepped dielectric material portion (165, 265).

[0092] refer to Fig.21 , a sacrificial fill material may be deposited in the fin contact via cavity 85 in the third stage process. The sacrificial fill material may include a semiconductor material (such as amorphous silicon or polycrystalline silicon), a carbon-based material (such as amorphous carbon or diamond-like carbon), a dielectric fill material (such as borosilicate glass or organosilicate glass), or a polymer material. Optionally, a thin etch stop liner (not shown) may be deposited before filling the fin contact via cavity 85 in the third stage process with the sacrificial fill material. The thin etch stop liner may include silicon oxide or a dielectric metal oxide and may have a thickness in the range of 2 nm to 6 nm, although smaller and larger thicknesses may also be used.

[0093] The portion of the sacrificial filling material overlying the horizontal plane including the top surface of the contact level dielectric layer 280 may be removed by a planarization process, which may include a recess etching process or a chemical mechanical polishing process. Each remaining portion of a corresponding one of the fin-shaped contact via cavities 85 in the third stage of the filling process of the sacrificial filling material constitutes a sacrificial fin cavity filling material structure 84. Each sacrificial fin cavity filling material structure 84 includes a corresponding cylindrical filling material portion 84C and at least one fin-shaped filling material portion 84F. Each fin-shaped filling material portion 84F has a corresponding annular shape.

[0094] refer to Fig.22A and Fig. 22B , a sacrificial contact level dielectric layer 282 may be formed over the contact level dielectric layer 280. The sacrificial contact level dielectric layer 282 includes a dielectric material, such as undoped silicate glass or doped silicate glass, and may have a thickness in a range from 10 nm to 200 nm, such as from 20 nm to 100 nm, although lesser and greater thicknesses may also be employed.

[0095] A photoresist layer (not shown) may be applied over the sacrificial contact level dielectric layer 282, and the photoresist layer may be photolithographically patterned to form openings in an area extending across the memory array region 100 and the contact region 300. The openings in the photoresist layer may extend laterally along the first horizontal direction hd1 between each adjacent cluster of memory opening fill structures 58. Lateral isolation trenches 79 may be formed by transferring the pattern in the photoresist layer through the sacrificial contact level dielectric layer 282, the contact level dielectric layer 280, the second alternating stack (232, 242) and the first alternating stack (132, 142), the stepped dielectric material portions (165, 265), and into the substrate 8. Portions of the sacrificial contact level dielectric layer 282, the contact level dielectric layer 280, the second alternating stacks (232, 242) and the first alternating stacks (132, 142), and the stepped dielectric material portions (165, 265) underlying the openings in the photoresist layer may be removed to form lateral isolation trenches 79. In one embodiment, lateral isolation trenches 79 may be formed between clusters (e.g., blocks) of memory opening filling structures 58. Clusters of memory opening filling structures 58 may be laterally spaced apart along a second horizontal direction hd2 by lateral isolation trenches 79. In one embodiment, the isolation trenches 79 form sidewalls of a memory block.

[0096] refer to Fig.23, an etchant that selectively etches the first and second sacrificial material layers (142, 242), the first and second sacrificial liners 154, 254 relative to the materials of the first and second insulating layers (132, 232), the materials of the outermost layer of the memory film 50 of the memory opening filling structure 58, and the materials of the at least one dielectric spacer layer (272, 273) of the support pillar structure 20 may be introduced into the lateral isolation trench 79, for example, using an isotropic etching process. The first laterally extending cavity 143 is formed in the volume from which the first sacrificial material layer 142 is removed. The second laterally extending cavity 143 is formed in the volume from which the second sacrificial material layer 242 is removed. The first stepped cavity 153 is formed in the volume from which the first sacrificial liner 154 is removed. The second stepped cavity 253 is formed in the volume from which the second sacrificial liner 254 is removed.

[0097] The isotropic etching process may be a wet etching process using a wet etching solution, or may be a vapor phase (dry) etching process in which an etchant is introduced in a vapor phase into the lateral isolation trench 79. For example, if the first and second sacrificial material layers (142, 242), the first and second sacrificial liners 154, 254 include silicon nitride, the etching process may be a wet etching process in which the exemplary structure is immersed in a wet etching bath including phosphoric acid, which selectively etches silicon nitride to silicon oxide and silicon.

[0098] The annular insulating plate 40 and the sacrificial fin-shaped cavity filling material structure 84 extend vertically from the dielectric isolation layer 6 (if present, or from the substrate 8) to the contact level dielectric layer 280, and provide structural support for the portion of the insulating layer (132, 232) and the stepped dielectric material portion (165, 265) present in the contact area 300 after the sacrificial material layer is removed. The annular insulating plate 40 can enhance the structural support for the insulating layer (132, 232) and the stepped dielectric material portion (165, 265). The memory opening filling structure 58 provides structural support to the insulating layer (132, 232) in the memory array area 100.

[0099] Each of the first and second lateral extension cavities (143, 243) may be a lateral extension cavity having a lateral dimension greater than the vertical extent of the cavity. In other words, the lateral dimension of each of the first and second lateral extension cavities (143, 243) may be greater than the height of the corresponding lateral extension cavity. A plurality of first lateral extension cavities may be formed in a volume of material from which the first sacrificial material layer 142 is removed. A plurality of second lateral extension cavities may be formed in a volume of material from which the second sacrificial material layer 242 is removed. Each of the first and second lateral extension cavities may extend substantially parallel to the top surface of the substrate 8. The lateral extension cavities (143, 243) may be vertically defined by the top surface of the underlying insulating layer (132 or 232) and the bottom surface of the overlying insulating layer (132 or 232). In one embodiment, each of the first and second lateral extension cavities (143, 243) may always have a uniform height.

[0100] The first stepped cavity 153 may be formed over the first stepped surface and the first insulating liner 152. As discussed above, the first sacrificial liner 154 may be formed by a conformal deposition process and have a uniform thickness greater than the thickness of each first sacrificial material layer 142.

[0101] Therefore, after removing the first sacrificial liner 154, each horizontally extending portion of the first stepped cavity 153 has a uniform height, which is the same as the uniform width of each vertically extending portion of the first stepped cavity 153. Each horizontally extending portion of the second stepped cavity 253 has a uniform height, which is the same as the uniform width of each vertically extending portion of the second stepped cavity 253. The uniform width and uniform height of the first stepped cavity 153 and the second stepped cavity 253 are greater than the thickness of the sacrificial material layer (142, 242).

[0102] refer to Fig.24 , an optional blocking dielectric material (i.e., a dielectric material that can be used to block electron tunneling) can be conformally deposited in the laterally extended cavity (143, 243), the first stepped cavity 153, and the second stepped cavity 253. In one embodiment, the blocking dielectric material includes a dielectric metal oxide material, such as aluminum oxide, hafnium oxide, tantalum oxide, titanium oxide, yttrium oxide, etc. Alternatively or additionally, the blocking dielectric material may include silicon oxide, silicon nitride, silicon oxynitride, and / or silicon carbonitride. The thickness of the blocking dielectric material can be in the range of 2nm to 20nm, such as 6nm to 12nm, but smaller and larger thicknesses can also be used.

[0103] A backside blocking dielectric layer 44 may be formed in each of the laterally extending cavities (143, 243). A blocking dielectric liner 144 may be formed in each of the first stepped cavity 153 and the second stepped cavity 253. Each outer sidewall of the annular insulating plate 40 may contact the backside blocking dielectric layer 44. Each fin-shaped filling material portion 84F of the sacrificial fin-shaped cavity filling material structure 84 may contact a corresponding blocking dielectric liner 144. The first blocking dielectric liner 144 formed in the first stepped cavity 153 may contact each of the first sacrificial fin-shaped cavity filling material structures 84A. The second blocking dielectric liner 144 formed in the second stepped cavity 253 may contact each of the second sacrificial fin-shaped cavity filling material structures 84B.

[0104] refer to Fig.25 At least one conductive material may be conformally deposited in the plurality of laterally extending cavities (143, 243), in the stepped cavities (153, 253), on the sidewalls of the lateral isolation trenches 79, and over the contact level dielectric layer 280. The at least one conductive material may include at least one metallic material, i.e., a conductive material including at least one metallic element.

[0105] The at least one metal material may be deposited by a conformal deposition method, which may be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), chemical plating, electroplating, and / or a combination thereof. The at least one metal material may be an elemental metal, an intermetallic alloy of at least two elemental metals, a conductive nitride of at least one elemental metal, a conductive metal oxide, a conductive doped semiconductor material, a conductive metal semiconductor alloy (such as a metal silicide), an alloy thereof, and a combination or stack thereof. Non-limiting exemplary metal materials that may be deposited in the laterally extended cavity include tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, and / or ruthenium. In one embodiment, the at least one metal material may include a combination of a metal barrier liner material and a metal filling material. The metal barrier liner material may include titanium nitride, tantalum nitride, tungsten nitride, molybdenum nitride, or a combination thereof. The metal filling material may include titanium, tantalum, tungsten, cobalt, molybdenum, ruthenium, copper, and the like. In one embodiment, the at least one metal material may be deposited by chemical vapor deposition or atomic layer deposition.

[0106] According to one aspect of the present disclosure, the total thickness of the at least one conformally deposited conductive material may be greater than half the height of the laterally extending cavity (143, 243), and may be less than half the height of the horizontally extending portion of the stepped cavity (153, 253) (the height of the horizontally extending portion is the same as the width of the vertically extending portion of the stepped cavity (153, 253)). Therefore, each of the laterally extending cavities (143, 243) may be completely filled with the at least one conformally deposited conductive material, while the stepped cavity (153, 253) is only partially filled and contains unfilled voids.

[0107] The at least one conformally deposited conductive material can be isotropically etched back from inside the stepped cavity (153, 253), from the sidewalls of the lateral isolation trench 79, and from above the sacrificial contact level dielectric layer 282 by performing an isotropic etch back process. The etching distance of the isotropic etch back process can be the same as or greater than the total thickness of the deposited at least one conductive material. Each remaining portion of the deposited metal material in the first laterally extending cavity constitutes a conductive layer 146. Each remaining portion of the deposited metal material in the second laterally extending cavity constitutes a second conductive layer 246. Each conductive layer (146, 246) can be a conductive line structure (e.g., a word line or a select gate electrode). The at least one conductive material can be completely removed from inside the stepped cavity (153, 253), and the blocking dielectric liner 144 can be physically exposed around each stepped cavity (153, 253).

[0108] A plurality of conductive layers 146 may be formed in the plurality of first laterally extending cavities 143, and a plurality of second conductive layers 246 may be formed in the plurality of second laterally extending cavities 243. Thus, the first sacrificial material layer and the second sacrificial material layer (142, 242) may be replaced with the first conductive material layer and the second conductive material layer (146, 246), respectively. Specifically, each first sacrificial material layer 142 may be replaced with a backside blocking dielectric layer 44 and a first conductive layer 146, and each second sacrificial material layer 242 may be replaced with a backside blocking dielectric layer 44 and a second conductive layer 246. The backside cavity exists in the portion of each lateral isolation trench 79 that is not filled with a continuous metal material layer.

[0109] Each of the memory opening filling structures 58 (which includes the corresponding memory stack structure 55) includes a vertical stack of memory elements at each level of the conductive layers (146, 246). A subset of the intermediate conductive layers (146, 246) may include word lines for the memory elements. At least one uppermost conductive layer 246 may include a drain side select gate electrode. At least one bottommost conductive layer 146 may include a source side select gate electrode.

[0110] The backside blocking dielectric layer 44 may be interposed between each adjacent pair of the first conductive layer 146 and the first insulating layer 132 within the first alternating stack (132, 146), and may be interposed between each adjacent pair of the second conductive layer 246 and the second insulating layer 232. In one embodiment, a subset of the backside blocking dielectric layers 44 is embedded in a corresponding one of the first conductive layers 146 and interposed between a corresponding one of the first conductive layers 146 and a corresponding one of the first insulating layers 132. A subset of the backside blocking dielectric layers 44 is embedded in a corresponding one of the first conductive layers 246 and interposed between a corresponding one of the first conductive layers 246 and a corresponding one of the first insulating layers 232. In one embodiment, each annular insulating plate 40 may contact the sidewall of a corresponding one of the backside blocking dielectric layers 44. Each fin-shaped filling material portion 84F of the sacrificial fin-shaped cavity filling material structure 84 may contact the sidewall of a corresponding blocking dielectric liner 144. The blocking dielectric liner 144 and the backside blocking dielectric layer 44 may have the same material composition and the same thickness. A first alternating stack of first insulating layers 132 and first conductive layers 146 may be formed below interlayer dielectric layer 180 , and a second alternating stack of second insulating layers 232 and second conductive layers 246 may be formed above interlayer dielectric layer 180 .

[0111] refer to Fig.26 , a second conductivity type dopant may optionally be implanted into a surface portion of the semiconductor material layer 9 underlying the lateral isolation trench 79 to form a source region 61. The source region 61 may include a second conductivity type dopant at an atomic concentration in the range of 5.0×1018 / cm3 to 2.0×1021 / cm3. Alternatively, the formation of the source region 61 may be omitted at this time, and instead a top source contact may be formed above the bottom tip of the vertical semiconductor channel after removing the substrate 8.

[0112] A dielectric filling material may be conformally deposited in the stepped cavity (153, 253) and in the peripheral portion of the lateral isolation trench 79 by a conformal deposition process. The dielectric filling material may include silicon oxide or silicon nitride. The thickness of the deposited dielectric filling material may be greater than half the height of the horizontal extension of the stepped cavity (153, 253), so that the stepped cavity (153, 253) is filled in the dielectric filling material. The portion of the dielectric filling material filling the first stepped cavity 153 constitutes a first dielectric filling material layer 174. The portion of the dielectric filling material filling the second stepped cavity 253 constitutes a second dielectric filling material layer 274. The adjacent combination of the first dielectric filling material layer 174 and the blocking dielectric liner 144 constitutes a first composite dielectric layer (144, 174). The adjacent combination of the second dielectric filling material layer 274 and the blocking dielectric layer 144 constitutes a second composite dielectric layer (144, 274).

[0113] An anisotropic etching process may be performed to remove horizontally extending portions of the dielectric fill material from above the top surface of the sacrificial contact level dielectric layer 282 and from the bottom of each of the lateral isolation trenches 79. Each remaining tubular portion of the dielectric fill material that remains in the respective lateral isolation trench 79 constitutes an insulating spacer 74. A laterally extending cavity 79' may be present within each unfilled volume of the lateral isolation trenches 79 that is laterally surrounded by a respective one of the insulating spacers 74.

[0114] Typically, the first composite dielectric layer (144, 174) may be interposed between the first stepped surface and the first stepped dielectric material portion 165, and include a first blocking dielectric liner 144 and a first dielectric fill material layer 174 embedded within the first blocking dielectric liner 144. The first blocking dielectric liner 144 contacts each top surface of the first dielectric fill material layer 174, each bottom surface of the first dielectric fill material layer 174, and a subset of the sidewalls of the first dielectric fill material layer 174. The second composite dielectric layer (144, 274) may be interposed between the second stepped surface and the second stepped dielectric material portion 265, and include a second blocking dielectric liner 144 and a second dielectric fill material layer 274 embedded within the blocking dielectric liner 144. The second blocking dielectric liner 144 contacts each top surface of the second dielectric fill material layer 274, each bottom surface of the second dielectric fill material layer 274, and a subset of the sidewalls of the second dielectric fill material layer 274.

[0115] Each composite dielectric layer {(144, (174 or 274)} includes horizontally extending portions and vertically extending portions interconnected above the stepped surface. The vertical thickness of the horizontally extending portions and the lateral thickness of the vertically extending portions are the same for each composite dielectric layer {(144, (174 or 274)} and are greater than the interlayer gaps between vertically adjacent pairs of first insulating layers 132 within the first alternating stack (232, 246) and greater than the interlayer gaps between vertically adjacent pairs of second insulating layers 232 within the second alternating stack (132, 146).

[0116] refer to Fig. 27 , at least one conductive filling material may be optionally deposited in the laterally extending cavity 79'. Portions of the at least one conductive material overlying a horizontal plane including a top surface of the sacrificial contact level dielectric layer 282 may be removed by a planarization process such as a recess etching process and / or a chemical mechanical polishing process. Each remaining portion of the at least one conductive filling material filling a respective laterally extending cavity 79' constitutes a source contact via structure 76. Alternatively, if the source region 61 is omitted, the source contact via structure 76 may also be omitted at this step. Alternatively, the lateral isolation trench 79 may be completely filled with the insulating spacer 74.

[0117] refer to Fig.28 , a photoresist layer (not shown) may be applied on the sacrificial contact level dielectric layer 282, and the photoresist layer may be photolithographically patterned to form an opening in an area overlapping the top surface of the sacrificial fin cavity filling material structure 84. An anisotropic etching process may be performed to form an etch through the unmasked portion of the sacrificial contact level dielectric layer 282 to physically expose the top surface of the sacrificial fin cavity filling material structure 84. A selective etching process may be performed to selectively remove the sacrificial filling material of the sacrificial fin cavity filling material structure 84 with respect to the material of the annular insulating plate 40, the stepped dielectric material portion (165, 265), and the dielectric isolation layer 6 (if present). The fin contact via cavity 87 is formed in the volume from which the sacrificial fin cavity filling material structure 84 is removed. The fin contact via cavity 87 includes a first fin contact via cavity 87A and a second fin contact via cavity 87B, the first step dielectric material portion 165 is exposed to the first fin contact via cavity and the first step dielectric material portion 165 is not exposed to the second fin contact via cavity. Each fin contact via cavity 87 includes a cylindrical cavity portion 87C and a fin cavity portion 87F.

[0118] refer to Fig.29 , an optional isotropic etching process may be performed to isotropically etch the material of the first insulating liner 152 and the second insulating liner 252. The duration of the isotropic etching may be selected so that the etching distance of the material of the first insulating liner 152 and the second insulating liner 252 is greater than the thickness of the first insulating liner 152 and the second insulating liner 252. Therefore, each physically exposed portion of the first insulating liner 152 and the second insulating liner 252 underlying the fin-shaped cavity portion 87F is etched through. Each of the conductive layers (146, 246) has a corresponding annular top surface section that is physically exposed to a corresponding one of the fin-shaped cavity portions 87F of the fin-shaped contact via cavity 87. The annular conical concave surface of the insulating liner (152, 252) may be physically exposed around each fin-shaped cavity portion 87F. The isotropic etching for the first insulating liner 152 and the second insulating liner 252 may include dilute hydrofluoric acid etching.

[0119] Optionally, the isotropic etch may be continued to remove exposed portions of the respective blocking dielectric liner 144 and the respective blocking dielectric layer 44. If the respective blocking dielectric liner 144 and the blocking dielectric layer 44 comprise aluminum oxide, the isotropic etch may comprise a hot phosphoric acid etch.

[0120] In one embodiment, surface portions of the stepped dielectric material layer ( 165 , 265 ), the annular insulating plate 40 , the contact level dielectric layer 280 , the interlayer dielectric layer 180 , and the dielectric isolation layer 6 may be isotropically recessed in parallel during the isotropic etching process.

[0121] Common Reference FIG. 16A to FIG. 29In the processing step, the proximal portion of the first sacrificial liner 154 and the proximal portion of the first insulating liner 152 may be removed around the volume of each first contact via cavity 81A to form a first fin contact via cavity 87A, and the proximal portion of the second sacrificial liner 254 and the proximal portion of the second insulating liner 252 may be removed around the volume of each second contact via cavity 81B to form a second fin contact via cavity 87B. After removing the first sacrificial fin cavity filling material structure 84A that forms the first fin contact via cavity 87A, an annular top surface section of the first conductive layer 146 may be physically exposed by removing at least the proximal portion of the first insulating liner 152. After removing the second sacrificial fin cavity filling material structure 84B that forms the second fin contact via cavity 87B, an annular top surface section of the second conductive layer 246 may be physically exposed by removing at least the proximal portion of the second insulating liner 252.

[0122] refer to Fig. 30A and Fig. 30B At least one conductive material, such as at least one metal material, may be deposited in the fin contact via cavity 87. The at least one conductive material may include a combination of a metal barrier liner material (such as TiN, TaN, WN, MoN, or a combination thereof) and a metal fill material (such as W, Ti, Ta, Mo, Ru, Co, Cu, etc.). Excess portions of the at least one conductive material may be removed from above a horizontal plane including the top surface of the contact level dielectric layer 280 by a planarization process (such as a chemical mechanical polishing process). In one embodiment, portions of the sacrificial contact level dielectric layer 282 and the insulating spacers 74 and the source contact via structure 76 overlying the horizontal plane including the top surface of the contact level dielectric layer 280 may be removed in parallel during the planarization process. Each remaining portion of the at least one conductive material filling the corresponding fin contact via cavity 87 constitutes a contact via structure, which is referred to herein as a layer contact via structure 86.

[0123] The layer contact via structure 86 includes a first contact via structure 86A formed in a first fin contact via cavity 87A and a second contact via structure 86B formed in a second fin contact via cavity 87B. Each of the layer contact via structures 86 extends vertically from at least the bottommost surface of the first alternating stack (132, 146) to a horizontal plane located at or above the top surface of the memory opening filling structure 58. Each layer contact via structure 86 includes a corresponding conductive column portion 86C and a corresponding conductive fin portion 86F, which protrudes laterally from the corresponding conductive column portion 86C and has a first annular bottom surface section ABSS1 of an annular top surface section contacting one of the conductive layers (146, 246). Each conductive fin portion 86F may also have a second annular bottom surface section ABSS2 of an annular top surface section contacting an annular insulating plate 40, which may be the topmost annular insulating plate 40 in the vertical stack of annular insulating plates 40 underlying the corresponding conductive fin portion 86F. Segments ABSS1 and ABSS2 may be horizontally coplanar.Each conductive fin portion 86F may have an annular top surface ATS contacting an annular bottom surface segment of one of the stepped dielectric material portions (165, 265).

[0124] A plurality of first contact via structures 86A extend vertically through the first stepped dielectric material portion 165 and the second stepped dielectric material portion 265. A plurality of second contact via structures 86B extend vertically through the second stepped dielectric material portion 265. In one embodiment, each annular insulating plate 40 within the vertical stack of annular insulating plates 40 has a lateral width that causes the corresponding conductive layer (146, 246) to be laterally offset from the conductive pillar portion 86C by a uniform lateral offset distance, which is referred to herein as the first lateral offset distance lod1. Each conductive fin portion 86F of the layer contact via structure 86 may have an outer sidewall that is laterally spaced from the sidewall of the conductive pillar portion 86C of the layer contact via structure 86 by a second lateral offset distance lod2.

[0125] Common Reference Figures 1 to 30BAnd according to various embodiments of the present disclosure, a memory device includes: a first alternating stack (132, 146) of a first insulating layer 132 and a first conductive layer 146, wherein the first alternating stack (132, 146) includes a first stepped surface in a contact area 300; a first stepped dielectric material portion 165 overlying the first stepped surface of the first alternating stack (132, 146); a memory opening 49 extending vertically at least through each layer within the first alternating stack (132, 146); a memory opening filling structure 58 located in the memory opening 49 and including a vertical stack of a vertical semiconductor channel 60 and a memory element (e.g., a portion of a memory film 50); and a first contact via structure 86A extending vertically from at least the bottommost surface of the first alternating stack (132, 146) through the first stepped dielectric material portion 165 and extending to a horizontal plane located at or above the top surface of the memory opening filling structure 58. The first contact via structure 86A includes a conductive pillar portion 86C and a conductive fin portion 86F that laterally protrudes from the conductive pillar portion 86C and has a first annular bottom surface section ABSS1 that contacts an annular top surface section of one of the first conductive layers 146 .

[0126] In one embodiment, the memory device includes a vertical stack of annular insulating plates 40 that laterally surround and contact the conductive pillar portion 86C and underlie the conductive fin portion 86F. The annular insulating plates (e.g., insulating fins) 40 isolate the conductive layer (146, 246) under the conductive fin portion 86F from the conductive pillar portion 86C. This prevents short circuits of conductive layers at different vertical levels caused by the conductive pillar portion 86C.

[0127] In one embodiment, the topmost annular insulating plate 40 within the vertical stack of annular insulating plates 40 is in contact with the second annular bottom surface section of the conductive fin portion 86F.

[0128] In one embodiment, the memory device includes backside blocking dielectric layers 44, wherein each of the backside blocking dielectric layers 44 is embedded in a corresponding one of the first conductive layers 146 and interposed between a corresponding one of the first conductive layers 146 and a corresponding one of the first insulating layers 132. In one embodiment, each annular insulating plate 40 within the vertical stack of annular insulating plates 40 contacts a sidewall of a corresponding one of the backside blocking dielectric layers 44.

[0129] In one embodiment, each annular insulating plate 40 within the vertical stack of annular insulating plates 40 has a lateral width that causes a corresponding one of the conductive layers (146, 246) located at the same vertical level (as the plate 40) to be laterally offset from the conductive column portion 86C by a uniform lateral offset distance lod1.

[0130] In one embodiment, the conductive fin portion 86F includes an annular top surface in contact with the annular planar surface segment of the first stepped dielectric material portion 165. In one embodiment, the conductive pillar portion 86C includes: a first cylindrical surface extending vertically through the first stepped dielectric material portion 165 and having a bottom perimeter adjacent to the inner perimeter of the annular top surface of the conductive fin portion 86F; and a second cylindrical surface extending vertically through a subset of the layers within the first alternating stack (132, 146) and having a top perimeter adjacent to the bottom surface of the conductive fin portion 86F.

[0131] In one embodiment, the memory device includes a composite dielectric layer (144, 174) interposed between the first stepped surface and the first stepped dielectric material portion 165, and includes a blocking dielectric liner 144 and a dielectric filling material layer 174 embedded in the blocking dielectric liner 144, wherein the blocking dielectric liner 144 contacts each top surface of the dielectric filling material layer 174 and each bottom surface of the dielectric filling material layer 174. In one embodiment, the conductive fin portion 86F contacts the sidewall of the dielectric filling material layer 174.

[0132] In one embodiment, the memory device further includes a backside blocking dielectric layer 44 interposed between each adjacent pair of the first conductive layer 146 and the first insulating layer 132 within the first alternating stack (132, 146) and having the same material composition and the same thickness as the blocking dielectric liner 144. In one embodiment, the composite dielectric layer (144, 174) includes a horizontally extending portion and a vertically extending portion interconnected above the first stepped surface; and the vertical thickness of the horizontally extending portion and the lateral thickness of the vertically extending portion are the same and are greater than the interlayer gap between the vertically adjacent pairs of the first insulating layer 132 within the first alternating stack (132, 146).

[0133] In one embodiment, the memory device also includes: a second alternating stack (232, 246) of a second insulating layer 232 and a second conductive layer 246 located in the first alternating stack (232, 246), wherein the second alternating stack (132, 146) includes a second stepped surface in the contact area 300, and wherein the memory opening filling structure 58 extends vertically through the second alternating stack (232, 246); a second stepped dielectric material portion 265 overlying the second stepped surface of the second alternating stack (232, 246); a second contact via structure 86B extending vertically from at least the bottommost surface of the first alternating stack (132, 146) to a horizontal plane located at or above the top surface of the memory opening filling structure 58, and including an additional conductive column portion 86C and an additional conductive fin portion 86F, which additional conductive fin portion protrudes laterally from the additional conductive column portion 86C and has an additional annular bottom surface segment having an annular top surface segment that contacts one layer of the second conductive layer 246.

[0134] The above method provides a more accurate method for forming the contact via structure 86. Therefore, the formation of the contact via cavity 87 that penetrates or fails to reach the corresponding conductive layer (146, 246) due to etching non-uniformity can be avoided. The conductive fin portion 86F of the layer contact via structure 86 provides a reliable electrical contact between the conductive layer (146, 246) and the layer contact via structure 86, and the layer contact via structure can be used as a word line contact via structure.

[0135] Although specific preferred embodiments are mentioned above, it should be understood that the present disclosure is not limited thereto. It will be appreciated by those of ordinary skill in the art that various modifications may be made to the disclosed embodiments and that these modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of..." or the words "consisting of..." replace the words "comprising" or "including". Where embodiments employing specific structures and / or configurations are exemplified in the present disclosure, it should be understood that the present disclosure may be practiced with any other compatible structures and / or configurations that are functionally equivalent, as long as such substitutions are not expressly prohibited or are not otherwise impossible for those of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A memory device, comprising: a first alternating stack of first insulating layers and first conductive layers, wherein the first alternating stack comprises a first stepped surface in a contact region; a first dielectric material portion, the first dielectric material portion overlying the first stepped surface of the first alternating stack; a reservoir opening extending vertically through at least each layer in the first alternating stack; a memory opening filling structure located in the memory opening and comprising a vertical stack of memory elements and a vertical semiconductor channel; and A first contact via structure extending vertically from at least the bottommost surface of the first alternating stack through the first dielectric material portion and to a horizontal plane located at or above the top surface of the memory opening filling structure, wherein the first contact via structure includes a conductive pillar portion and a conductive fin portion, the conductive fin portion protruding laterally from the conductive pillar portion and having a first annular bottom surface segment that contacts an annular top surface segment of one of the first conductive layers. 2 . The memory device of claim 1 , further comprising a vertical stack of annular insulating plates laterally surrounding and contacting the conductive pillar portion and underlying the conductive fin portion. 3 . The memory device of claim 2 , wherein a topmost annular insulating plate within the vertical stack of annular insulating plates contacts the second annular bottom surface section of the conductive fin portion.

4. The memory device of claim 2, further comprising a backside blocking dielectric layer, wherein each of the backside blocking dielectric layers is embedded in a corresponding one of the first conductive layers and interposed between the corresponding one of the first conductive layers and a corresponding one of the first insulating layers. 5 . The memory device of claim 4 , wherein each annular insulating plate within the vertical stack of annular insulating plates contacts a sidewall of a corresponding one of the backside blocking dielectric layers.

6. The memory device of claim 2 , wherein each annular insulating plate within the vertical stack of annular insulating plates has a lateral width that causes a corresponding one of the conductive layers at the same vertical level to be laterally offset from the conductive pillar portion by a uniform lateral offset distance. 7 . The memory device of claim 1 , wherein the conductive fin portion comprises an annular top surface in contact with an annular planar surface segment of the first dielectric material portion.

8. The memory device of claim 7, wherein the conductive pillar portion comprises: a first cylindrical surface extending vertically through the first dielectric material portion and having a bottom perimeter abutting an inner perimeter of the annular top surface of the conductive fin portion; and A second cylindrical surface extends vertically through a subset of the layers within the first alternating stack and has a top perimeter abutting a bottom surface of the conductive fin portion.

9. The memory device according to claim 1 further includes a composite dielectric layer, which is interposed between the first stepped surface and the first dielectric material portion, and includes a blocking dielectric liner and a dielectric filling material layer embedded in the blocking dielectric liner, wherein the blocking dielectric liner contacts each top surface of the dielectric filling material layer and each bottom surface of the dielectric filling material layer. 10 . The memory device of claim 9 , wherein the conductive fin portion contacts a sidewall of the dielectric filling material layer.

11. The memory device of claim 9, further comprising a backside blocking dielectric layer interposed between each adjacent pair of first conductive layers and first insulating layers within the first alternating stack and having the same material composition and the same thickness as the blocking dielectric liner.

12. The memory device according to claim 9, wherein: The composite dielectric layer includes horizontally extending portions and vertically extending portions interconnected above the first stepped surface; and A vertical thickness of the horizontally extending portion and a lateral thickness of the vertically extending portion are the same and are greater than an interlayer gap between vertically adjacent pairs of the first insulating layers within the first alternating stack.

13. The memory device according to claim 1, further comprising: a second alternating stack of second insulating layers and second conductive layers located in the first alternating stack, wherein the second alternating stack includes a second stepped surface in the contact region, and wherein the memory opening fill structure extends vertically through the second alternating stack; and A second dielectric material portion overlies the second stepped surface of the second alternating stack.

14. The memory device according to claim 13 further includes a second contact via structure, which extends vertically from at least the bottommost surface of the first alternating stack to the horizontal plane located at or above the top surface of the memory opening filling structure, and includes an additional conductive column portion and an additional conductive fin portion, which protrudes laterally from the additional conductive column portion and has an additional annular bottom surface segment having an annular top surface segment that contacts one of the second conductive layers.

15. A method of forming a memory device, the method comprising: forming a first alternating stack of first insulating layers and first sacrificial material layers over the substrate; forming a first stepped surface in a contact region by patterning the first alternating stack; forming a first dielectric material portion over the first stepped surface; forming a memory opening extending vertically through each layer in said first alternating stack; forming a memory opening filling structure including a vertical semiconductor channel and a vertical stack of memory elements in the memory opening; replacing the first sacrificial material layer with a first conductive layer; as well as A first contact via structure is formed, the first contact via structure extending vertically from at least the bottom-most surface of the first alternating stack to a horizontal plane located at or above the top surface of the memory opening filling structure, wherein the first contact via structure includes a conductive column portion and a conductive fin portion, the conductive fin portion protruding laterally from the conductive column portion and having a first annular bottom surface segment that contacts an annular top surface segment of one of the first conductive layers.

16. The method according to claim 15, further comprising: forming a first insulating liner and a first sacrificial liner over the first stepped surface; forming a first contact via cavity through the first dielectric material portion, the first insulating liner, the first sacrificial liner, and a subset of the layers within the first alternating stack; as well as A proximal portion of the first sacrificial liner and a proximal portion of the first insulating liner are removed around a volume of the first contact via cavity to form a first fin contact via cavity, wherein the first contact via structure is formed in the first fin contact via cavity.

17. The method according to claim 16, further comprising: performing a first isotropic etching process, wherein the first isotropic etching process etches the first sacrificial liner and a proximal portion of the first sacrificial material layer from around the first contact via cavity to form a fin-shaped contact via cavity in a first stage process; Conformally depositing a conformal dielectric material layer in the fin contact via cavity in the first stage process; as well as An isotropic recess etch process is performed to isotropically recess the conformal dielectric material layer, wherein a remaining portion of the conformal dielectric material layer filling the volume from which the portion of the first sacrificial material layer was removed constitutes a vertical stack of annular insulating plates.

18. The method of claim 17, wherein: the isotropic recess etch process completely removing material of the conformal dielectric material layer from within a volume formed by removing a portion of the first sacrificial liner during the first isotropic etch process; and A second-stage in-process fin contact via cavity is formed after the isotropic recess etching process, wherein the second-stage in-process fin contact via cavity includes an entire volume of the first contact via cavity and the volume formed by removing the portion of the first sacrificial liner during the first isotropic etching process.

19. The method according to claim 18, further comprising: forming a third-stage process fin contact via cavity by further laterally recessing the sidewalls of the first sacrificial liner around the second-stage process fin contact via cavity; forming a sacrificial fin cavity filling material structure in the fin contact cavity in the third stage process, wherein after forming the sacrificial fin cavity filling material structure, replacing the first sacrificial material layer with the first conductive layer; as well as The sacrificial fin cavity filling material structure is removed after forming the first conductive layer.

20. The method according to claim 19, further comprising: The annular top surface section of the one of the first conductive layers is physically exposed by removing at least the proximal portion of the first insulating liner after removing the sacrificial fin cavity filling material structure to form the first fin contact via cavity.

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