Duty cycle correction circuit calibration method, system and memory

Abstract

The duty cycle correction circuit calibration method, system, and memory provided by the embodiments of the present disclosure include: obtaining an internal clock signal output by a DLL circuit and a feedback clock signal output by a DCC circuit, and determining a duty cycle difference signal based on the internal clock signal and the feedback clock signal; obtaining first actual temperature information and first actual voltage information of the DCC circuit at a target sampling moment, as well as actual process corner level information of a DRAM; determining an initial DCC coding signal based on the first actual temperature information, the first actual voltage signal, and the actual process corner level information; and adjusting the initial DCC coding signal based on the duty cycle difference signal to obtain a target DCC coding signal, so as to control the conduction state of the DCC circuit via the target DCC coding signal, thereby avoiding the DCC circuit calibration requiring a large amount of time to correct duty cycle imbalances of the clock signal caused by temperature and voltage changes.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of memory technology and related technologies, and in particular, to a DCC circuit calibration method, system, and memory. Background Art

[0002] Dynamic Random Access Memory (DRAM), also known as main memory, is internal memory that exchanges data directly with the CPU. It offers fast read / write speeds and is typically used as temporary data storage for operating systems and other running programs.

[0003] When the internal circuitry of a dynamic random access memory (DRAM) uses an external clock signal as its input, the internal clock signal is delayed due to internal circuit delays. To ensure that the phase of the DRAM's internal clock signal is equal to that of the external clock signal and to ensure data transmission reliability, a synchronization control circuit, such as a delay-locked loop (DLL), is embedded within the DRAM's internal circuitry to synchronize the DRAM's internal clock signal with the external clock signal. Furthermore, to ensure that the high-level and low-level duty cycles of the internal clock signal are the same, a duty cycle corrector (DCC) circuit is embedded within the DRAM's internal circuitry to eliminate duty cycle distortion (e.g., 60% high and 40% low) caused by process variations, noise, or temperature changes.

[0004] In existing technology, the coordinated operation of the DCC circuit and the DLL circuit typically involves the following stages: Upon startup of the DLL circuit, the DCC circuit first performs a coarse duty cycle adjustment on the DLL circuit's output clock signal, ensuring the initial waveform is close to 50%. The DLL circuit then performs an initial phase lock, aligning the rising edges of the DRAM's internal clock signal with the external clock signal. Therefore, the DCC circuit must promptly calibrate the DLL circuit's output clock signal; otherwise, errors can easily accumulate, ultimately leading to functional failure. When DRAMs operate at high frequencies and short clock cycles, conventional digital DCC circuits are no longer sufficient for design requirements. Furthermore, the performance of the logic devices in the DCC circuit is significantly affected by PVT. Therefore, DCC circuit calibration requires significant time to correct for signal duty cycle imbalances caused by temperature and voltage fluctuations. Summary of the Invention

[0005] The embodiments described herein provide a DCC circuit calibration method, system, and memory to prevent the DCC from requiring a large amount of time to correct signal duty cycle imbalances caused by temperature and voltage changes.

[0006] In a first aspect, according to the present disclosure, a DCC circuit calibration method is provided, comprising:

[0007] Obtaining an internal clock signal output by the DLL circuit and a feedback clock signal output by the DCC circuit, and determining a duty cycle difference signal based on the internal clock signal and the feedback clock signal;

[0008] Acquire first actual temperature information and first actual voltage information of the DCC circuit at a target sampling moment, and actual process corner grade information of the DRAM;

[0009] determining an initial DCC coding signal according to the first actual temperature information, the first actual voltage signal, and the actual process angle level information;

[0010] The initial DCC coding signal is adjusted according to the duty cycle difference signal to obtain a target DCC coding signal, so as to control the conduction state of the DCC circuit through the target DCC coding signal.

[0011] In some embodiments of the present disclosure, before determining the initial DCC coding signal according to the first actual temperature information, the first actual voltage signal, and the actual process corner level information, the method further includes:

[0012] Determining a clock phase difference signal according to the internal clock signal and the feedback clock signal;

[0013] Acquire second actual temperature information and second actual voltage information of the DLL circuit at a target sampling time, and determine a target step size control signal according to the second actual temperature information, the second actual voltage information, and the actual process corner level information;

[0014] determining a target DLL encoding signal according to the clock phase difference signal and the target step size control signal;

[0015] The determining an initial DCC coding signal according to the first actual temperature information, the first actual voltage signal, and the actual process angle level information includes:

[0016] An initial DCC coding signal is determined according to the target DLL coding signal, the first actual temperature information, the first actual voltage signal, and the actual process corner level information.

[0017] In some embodiments of the present disclosure, determining the initial DCC coding signal according to the target DLL coding signal, the first actual temperature information, the first actual voltage signal, and the actual process corner level information includes:

[0018] Determine a first actual temperature encoding signal, a first actual voltage encoding signal, and an actual process angle encoding signal according to the first actual temperature information, the first actual voltage information, and the actual process angle level information;

[0019] An initial DCC encoding signal is determined according to the target DLL encoding signal, the first actual temperature encoding signal, the first actual voltage encoding signal, and the actual process angle encoding signal.

[0020] In some embodiments of the present disclosure, determining a first actual temperature encoding signal, a first actual voltage encoding signal, and an actual process angle encoding signal according to the first actual temperature information, the first actual voltage information, and the actual process angle level information includes:

[0021] Determining a first actual temperature encoding signal according to a temperature interval within which the first actual temperature information is located at a target sampling moment;

[0022] Determining a first actual voltage encoding signal according to a voltage interval in which the first actual voltage information is located at a target sampling time;

[0023] An actual process angle coding signal is determined according to the actual process angle level information submitted by the test module.

[0024] In some embodiments of the present disclosure, determining an initial DCC coding signal according to the target DLL coding signal, the first actual temperature coding signal, the first actual voltage coding signal, and the actual process angle coding signal includes:

[0025] Acquire a test DCC coding signal corresponding to a test DLL coding signal, a test temperature coding signal, a test voltage coding signal, and a test process angle coding signal of each target bit during a test phase;

[0026] An initial DCC coding signal is determined according to the correspondence between the target bit target DLL coding signal and the target bit test DLL coding signal, the correspondence between the first actual temperature coding signal and the test temperature coding signal, the correspondence between the first actual voltage coding signal and the test voltage coding signal, and the correspondence between the actual process angle coding signal and the test process angle coding signal.

[0027] In some embodiments of the present disclosure, determining the target DLL encoding signal according to the clock phase difference signal and the target step size control signal includes:

[0028] Determining a target number of delay units required to be delayed in the adjustable delay chain according to the clock phase difference signal and the target step size control signal;

[0029] The target DLL coding signal is determined according to the target number of delay units required to be delayed by the adjustable delay chain and the initial DLL coding signal of the adjustable delay chain.

[0030] In some embodiments of the present disclosure, determining the target number of delay units required to be delayed in the adjustable delay chain according to the clock phase difference signal and the target step size control signal includes:

[0031] Determining the number of unit delay units required to be delayed in the adjustable delay chain according to the clock phase difference signal;

[0032] The target number of delay units required for the adjustable delay chain to be delayed is determined according to the number of unit delay units and the target step length control signal.

[0033] In some embodiments of the present disclosure, acquiring an internal clock signal output by a DLL circuit and a feedback clock signal output by a DCC circuit, and determining a duty cycle difference signal based on the internal clock signal and the feedback clock signal, includes:

[0034] Obtain the internal clock signal output by the DLL circuit and the feedback clock signal output by the DCC circuit;

[0035] A duty cycle difference signal is determined according to a duration corresponding to a high level of the internal clock signal and a duration corresponding to a high level of the feedback clock signal.

[0036] In a second aspect, according to the present disclosure, a DCC circuit calibration system is provided, comprising:

[0037] a duty cycle difference signal determination module, configured to obtain an internal clock signal output by the DLL circuit and a feedback clock signal output by the DCC circuit, and determine a duty cycle difference signal based on the internal clock signal and the feedback clock signal;

[0038] An information acquisition module, configured to acquire first actual temperature information and first actual voltage information of a DCC circuit at a target sampling moment, and actual process corner grade information of a DRAM;

[0039] an initial DCC coding signal determining module, configured to determine an initial DCC coding signal according to the first actual temperature information, the first actual voltage signal, and the actual process angle level information;

[0040] The target DCC coding signal determination module is used to adjust the initial DCC coding signal according to the duty cycle difference signal to obtain a target DCC coding signal, so as to control the conduction state of the DCC circuit through the target DCC coding signal.

[0041] In a third aspect, according to the contents of the present disclosure, a memory is provided, comprising the DCC circuit calibration system described in the second aspect.

[0042] The DCC circuit calibration method, system, and memory provided by the embodiments of the present disclosure first obtain an internal clock signal output by the DLL circuit and a feedback clock signal output by the DCC circuit, and determine a duty cycle difference signal based on the internal clock signal and the feedback clock signal. Then, first actual temperature information and first actual voltage information of the DCC circuit at a target sampling moment, as well as actual process corner level information of the DRAM, are obtained. An initial DCC coding signal is determined based on the first actual temperature information, the first actual voltage signal, and the actual process corner level information. Finally, the initial DCC coding signal is adjusted based on the duty cycle difference signal to obtain a target DCC coding signal, thereby avoiding the need for DCC circuit calibration to require a significant amount of time to correct clock signal duty cycle imbalances caused by temperature and voltage changes. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure and are not intended to limit the present disclosure.

[0044] Figure 1 1 is a flow chart of a DCC circuit calibration method provided by an embodiment of the present disclosure;

[0045] Figure 2 1 is a schematic diagram of a circuit structure for determining an initial DCC coding signal provided by an embodiment of the present disclosure;

[0046] Figure 3 is a flow chart of another DCC circuit calibration method provided by an embodiment of the present disclosure;

[0047] Figure 4 Schematic diagram of the structure of a DCC circuit calibration system provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0049] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the subject matter of the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal manner unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together either directly or through one or more intermediate components.

[0050] In all embodiments of the present disclosure, terms such as “first” and “second” are used only to distinguish one component (or a part of a component) from another component (or another part of a component).

[0051] Unless the context clearly indicates otherwise, as used herein and in the appended claims, the singular includes the plural, and vice versa. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the words "include" and "comprising" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0052] Based on the problems existing in the prior art, the present disclosure provides a DCC circuit calibration method. Figure 1 FIG. 1 is a flow chart of a DCC circuit calibration method provided by an embodiment of the present disclosure, such as Figure 1 As shown, the DCC circuit calibration method includes:

[0053] S110 , obtaining an internal clock signal output by the DLL circuit and a feedback clock signal output by the DCC circuit, and determining a duty cycle difference signal according to the internal clock signal and the feedback clock signal.

[0054] In a specific embodiment, the DCC circuit receives an internal clock signal output by the DLL circuit. After receiving the internal clock signal output by the DLL circuit, the DCC circuit inverts the phase of the internal clock signal and outputs a feedback clock signal. At this time, a duty cycle difference signal can be determined based on the internal clock signal output by the DLL circuit and the feedback clock signal output by the DLL circuit.

[0055] Specifically, the internal clock signal output by the DLL circuit and the feedback clock signal output by the DCC circuit are obtained, and a duty cycle difference signal is determined based on the internal clock signal and the feedback clock signal, including: obtaining the internal clock signal output by the DLL circuit and the feedback clock signal output by the DCC circuit; and determining the duty cycle difference signal based on the duration corresponding to the high level of the internal clock signal and the duration corresponding to the high level of the feedback clock signal.

[0056] As another specific implementable manner, the duty cycle difference signal may be determined according to the duration corresponding to the low level of the internal clock signal and the duration corresponding to the low level of the feedback clock signal.

[0057] S120 , obtaining first actual temperature information and first actual voltage information of the DCC circuit at the target sampling moment, and actual process corner grade information of the DRAM.

[0058] In the prior art, a DCC code signal is determined based on the relationship between the durations corresponding to the same level in the internal clock signal output by the DLL and the feedback clock signal output by the DCC. This determined DCC code signal is then applied to the DCC circuit to control the conduction state of switches within the DCC circuit, thereby adjusting the duty cycle of the clock signal acting on the DLL circuit. Due to interference from external factors such as PVT (actual temperature and voltage information of the DCC, as well as information about the actual process corner grade of the DRAM), DCC circuit calibration requires a significant amount of time to correct for clock signal duty cycle imbalances caused by temperature and voltage changes.

[0059] In view of the problems existing in the prior art, the embodiment of the present disclosure obtains the internal clock signal output by the DLL circuit and the feedback clock signal output by the DCC circuit before calibrating the DCC circuit, and determines the duty cycle difference signal based on the internal clock signal and the feedback clock signal. On the other hand, the first actual temperature information and the first actual voltage information of the DCC circuit and the actual process angle level information of the DRAM are obtained at the target sampling moment, and the initial DCC coding signal is determined based on the first actual temperature information, the first actual voltage information and the actual process angle level information. The initial DCC coding signal is then adjusted through the duty cycle difference signal to obtain a target DCC coding signal acting on the DCC circuit, so as to control the conduction state of the switch in the DCC circuit through the target DCC coding signal and realize the adjustment of the clock signal duty cycle.

[0060] In a specific embodiment, since the temperature information corresponding to the DCC circuit at different times is different, and due to the influence of the voltage drop of each module in the DRAM, the voltage information corresponding to the DCC circuit at different times is different. Therefore, in order to avoid the DCC circuit calibration requiring a large amount of time to correct the duty cycle imbalance of the clock signal caused by temperature and voltage changes, the embodiment of the present disclosure first determines the initial DCC coding signal based on the first actual temperature information, the first actual voltage signal and the actual process corner level information before adjusting the duty cycle of the clock signal, and then adjusts the initial DCC coding signal according to the duty cycle difference signal, thereby improving the efficiency of the DCC circuit in calibrating the clock signal duty cycle.

[0061] It should be noted that the actual process corner level information of the DRAM is determined based on the test module test in the test phase, that is, the process corner of the DRAM is affected by the DRAM preparation process. When the DRAM preparation is completed, the process corner level information of the DRAM can be determined.

[0062] S140: Determine an initial DCC coding signal according to the first actual temperature information, the first actual voltage signal, and the actual process corner level information.

[0063] In a specific embodiment, specifically, determining the initial DCC coding signal based on the first actual temperature information, the first actual voltage information and the actual process angle level information includes: determining the first actual temperature coding signal, the first actual voltage coding signal and the actual process angle coding signal based on the first actual temperature information, the first actual voltage information and the actual process angle level information; determining the initial DCC coding signal based on the first actual temperature coding signal, the first actual voltage coding signal and the actual process angle coding signal.

[0064] Among them, the first actual temperature encoding signal, the first actual voltage encoding signal and the actual process angle encoding signal are determined according to the first actual temperature information, the first actual voltage information and the actual process angle level information, including: determining the first actual temperature encoding signal according to the temperature range where the first actual temperature information is located at the target sampling moment; determining the first actual voltage encoding signal according to the voltage range where the first actual voltage information is located at the target sampling moment; and determining the actual process angle encoding signal according to the actual process angle level information submitted by the test module.

[0065] Specifically, in DRAM design, the process corner level is simply divided into three levels: SS, TT, and FF. During the product testing phase, the test module can confirm which process corner level the DRAM chip belongs to. The process corner level of the DRAM is only affected by the DRAM manufacturing process. The DRAM parameters will not change after the DRAM is tape-out, which means that the actual process corner level of the DRAM will not change after tape-out. As an example, when the actual process corner level information of the DRAM submitted by the test module is SS, the actual process corner encoding signal is Code<2:0>=001. When the actual process corner level information of the DRAM submitted by the test module is TT, the actual process corner encoding signal is Code<2:0>=010. When the actual process corner level information of the DRAM submitted by the test module is FF, the actual process corner encoding signal is Code<2:0>=100.

[0066] Specifically, the temperature information is divided into the following three intervals: -40℃-10℃, 11℃-70℃, and 71℃-120℃. When the first actual temperature information is in the -40℃-10℃ interval, the first actual temperature encoding signal is Code<5:3>=001. When the first actual temperature information is in the 11℃-70℃ interval, the first actual temperature encoding signal is Code<5:3>=010. When the first actual temperature information is in the 71℃-120℃ interval, the first actual temperature encoding signal is Code<5:3>=100.

[0067] Specifically, the voltage information is divided into the following three intervals: 1.08V-1.16V, 1.17V-1.24V, and 1.25V-1.32V. When the first actual voltage information is in the 1.08V-1.16V interval, the first actual voltage coding signal is Code<8:6>=001. When the first actual voltage information is in the 1.17V-1.24V interval, the first actual voltage coding signal is Code<8:6>=010. When the first actual voltage information is in the 1.25V-1.32V interval, the first actual voltage coding signal is Code<8:6>=100.

[0068] In addition, an initial DCC coding signal is determined based on the first actual temperature coding signal, the first actual voltage coding signal, and the actual process angle coding signal, including: obtaining a test DCC coding signal corresponding to each test temperature coding signal, test voltage coding signal, and test process angle coding signal during a test phase; and determining the initial DCC coding signal based on a correspondence between the first actual temperature coding signal and the test temperature coding signal, a correspondence between the first actual voltage coding signal and the test voltage coding signal, and a correspondence between the actual process angle coding signal and the test process angle coding signal.

[0069] In order to determine the initial DCC coding signal corresponding to the first actual temperature coding signal, the first actual voltage coding signal and the actual process angle coding signal, it is first necessary to obtain the test DCC coding signals corresponding to each test temperature coding signal, test voltage coding signal and test process angle coding signal in the test phase, and then based on the correspondence between the first actual temperature coding signal and the test temperature coding signal, the correspondence between the first actual voltage coding signal and the test voltage coding signal, and the correspondence between the actual process angle coding signal and the test process angle coding signal, the initial DCC coding signal is determined from the test DCC coding signals.

[0070] In a specific embodiment, the range of the DCC coding signal is first determined, and then the number of fuse groups is set according to the range of the DCC coding signal. Specifically, each group of fuse groups corresponds to an output of a test DCC coding signal. For example, the DCC coding signal output by the first group of fuse groups is 00010000, the DCC coding signal output by the second group of fuse groups is 00110000, the DCC coding signal output by the third group of fuse groups is 01010000, the DCC coding signal output by the fourth group of fuse groups is 01110000, and the DCC coding signal output by the fifth group of fuse groups is 01010000. The DCC coding signal output by the first fuse group is 10010000, the DCC coding signal output by the sixth fuse group is 10110000, the DCC coding signal output by the seventh fuse group is 11010000, and the DCC coding signal output by the eighth fuse group is 11110000. Each fuse group includes 27 fuses. The first test temperature coding signal, the first test voltage coding signal and the test process angle coding signal are arranged and combined to obtain 27 test coding signals. The test DCC coding signals corresponding to the 27 test coding signals are tested respectively, as shown in FIG. Figure 2 After determining the test DCC coding signals corresponding to the 27 test coding signals during the test phase, an initial DCC coding signal is determined based on the actual coding signal composed of the first actual temperature coding signal, the first actual voltage coding signal, and the actual process angle coding signal during duty cycle adjustment of the clock signal by the DCC circuit.

[0071] In a specific exemplary embodiment, if the test coding signal is TestCode<8:0>=000000000, wherein TestCode<2:0>=000 is a test process angle coding signal, TestCode<5:3>=000 is a first test temperature coding signal, and TestCode<8:6>=000 is a first test voltage coding signal, it is determined in the test phase that the test DCC coding signal of the test coding signal TestCode<8:0>=000000000 is 00010000. In the actual adjustment phase, if the actual coding signal composed of the first actual temperature coding signal, the first actual voltage coding signal, and the actual process angle coding signal is Code<8:0>=000000000, at this time, the first fuse of the first fuse group is controlled to be blown, and the initial DCC coding signal 00010 is output through the first fuse group. 000; if the test coding signal is TestCode<8:0>=000000001, where TestCode<2:0>=001 is the test process angle coding signal, TestCode<5:3>=000 is the first test temperature coding signal, and TestCode<8:6>=000 is the first test voltage coding signal, the test DCC coding signal of the test coding signal TestCode<8:0>=000000001 is determined to be 00110000 in the test phase. In the actual adjustment phase, if the actual coding signal determined based on the first actual temperature coding signal, the first actual voltage coding signal and the actual process angle coding signal is Code<8:0>=000000001, at this time, the second fuse of the second fuse group is controlled to be blown, and the initial DCC coding signal 00110000 is output through the second fuse group.

[0072] S150 , adjusting the initial DCC coding signal according to the duty cycle difference signal to obtain a target DCC coding signal, so as to control the conduction state of the DCC circuit through the target DCC coding signal.

[0073] After determining the initial DCC coding signal and the duty cycle difference signal, the DCC coding signal is adjusted according to the duty cycle difference signal to determine the target DCC coding signal. The target DCC coding is used to control the conduction state of each switch in the DCC circuit, thereby changing the driving capability of the inverter and the transmission line capacitance in the DCC circuit to correct the delay of the rising edge or falling edge.

[0074] The DCC circuit calibration method provided by the embodiment of the present disclosure first obtains the internal clock signal output by the DLL circuit and the feedback clock signal output by the DCC circuit, and determines a duty cycle difference signal based on the internal clock signal and the feedback clock signal. Then, first actual temperature information and first actual voltage information of the DCC circuit at the target sampling moment, as well as actual process corner level information of the DRAM, are obtained. An initial DCC coding signal is determined based on the first actual temperature information, the first actual voltage signal, and the actual process corner level information. Finally, the initial DCC coding signal is adjusted based on the duty cycle difference signal to obtain a target DCC coding signal, thereby avoiding the DCC circuit calibration requiring a large amount of time to correct duty cycle imbalances of the clock signal caused by temperature and voltage changes.

[0075] As a preferred embodiment, Figure 3 FIG. 1 is a flow chart of another DCC circuit calibration method provided by an embodiment of the present disclosure, such as Figure 3 As shown, when executing Figure 1 The step S140 shown in the figure also includes:

[0076] S130: Determine a clock phase difference signal according to the internal clock signal and the feedback clock signal.

[0077] In a specific embodiment, the internal clock signal output by the DLL circuit to the DCC circuit and the feedback clock signal after passing through the DCC circuit are collected, and the clock phase difference signal between the feedback clock signal and the internal clock signal is determined through the internal and external clock signals and the feedback clock signal, that is, the number of unit clock cycles that differ between the feedback clock signal and the internal clock signal is determined.

[0078] S131 , obtaining second actual temperature information and second actual voltage information of the DLL circuit at a target sampling time, and determining a target step size control signal according to the second actual temperature information, the second actual voltage information, and the actual process corner level information.

[0079] Because the DCC circuit adjusts the clock signal's duty cycle after the DLL circuit adjusts the clock signal's phase, if the number of delay cells adjusted by the DLL circuit is uncertain, varying performance of the delay cells under different PVT conditions can lead to asymmetry in the clock signal's rise and fall delays, resulting in clock signal duty cycle distortion. As a preferred embodiment, an initial DCC code signal is determined based on a target DLL code signal acting on the DLL circuit, first actual temperature information and first actual voltage information of the DCC circuit at a target sampling time, and actual DRAM process corner level information, ensuring the validity of the determined initial DCC code signal.

[0080] In the specific implementation process of determining the target DLL encoding signal acting on the DLL circuit, it is first necessary to determine the clock phase difference signal based on the internal clock signal and the feedback clock signal, and obtain the second actual temperature information and second actual voltage information of the DLL circuit at the target sampling time. Then, based on the second actual temperature information, the second actual voltage information and the actual process angle level information, the target step size control signal is determined.

[0081] It should be noted that, in the above embodiment, the specific process of determining the target step control signal based on the second actual temperature information, the second actual voltage information and the actual process angle level information is the same as the method of determining the initial DCC coding signal based on the first actual temperature information, the first actual voltage information and the actual process angle level information, and no further examples are given here.

[0082] S132: Determine a target DLL encoding signal according to the clock phase difference signal and the target step size control signal.

[0083] In a specific embodiment, a target DLL encoding signal is determined based on a clock phase difference signal and a target step size control signal, including: determining a target number of delay units that the adjustable delay chain needs to delay based on the clock phase difference signal and the target step size control signal; and determining the target DLL encoding signal based on the target number of delay units that the adjustable delay chain needs to delay and an initial DLL encoding signal of the adjustable delay chain.

[0084] In a specific example, if the clock phase difference signal between the internal clock signal and the feedback clock signal is 4 unit clock cycles, then the number of unit delay cells required to be delayed in the adjustable delay chain is determined to be 4. After determining the number of unit delay cells required to be delayed in the adjustable delay chain, the target number of delay cells required to be delayed in the adjustable delay chain can be determined based on the target step size control signal and the target number of delay cells required to be delayed in the adjustable delay chain. Finally, the target DLL code signal is determined based on the target number of delay cells required to be delayed in the adjustable delay chain and the initial DLL code signal of the adjustable delay chain.

[0085] at this time Figure 1 The implementation of step S140 is as follows:

[0086] S1401: Determine an initial DCC coding signal according to a target DLL coding signal, first actual temperature information, a first actual voltage signal, and the actual process corner level information.

[0087] In a specific implementation, determining an initial DCC coding signal based on a target DLL coding signal, first actual temperature information, first actual voltage signal, and actual process angle level information includes: determining a first actual temperature coding signal, a first actual voltage coding signal, and an actual process angle coding signal based on the first actual temperature information, the first actual voltage information, and the actual process angle level information; and determining an initial DCC coding signal based on the target DLL coding signal, the first actual temperature coding signal, the first actual voltage coding signal, and the actual process angle coding signal.

[0088] Among them, the first actual temperature encoding signal, the first actual voltage encoding signal and the actual process angle encoding signal are determined according to the first actual temperature information, the first actual voltage information and the actual process angle level information, including: determining the first actual temperature encoding signal according to the temperature range where the first actual temperature information is located at the target sampling moment; determining the first actual voltage encoding signal according to the voltage range where the first actual voltage information is located at the target sampling moment; and determining the actual process angle encoding signal according to the actual process angle level information submitted by the test module.

[0089] Determining an initial DCC coding signal based on a target DLL coding signal, a first actual temperature coding signal, a first actual voltage coding signal, and an actual process angle coding signal includes: obtaining a test DCC coding signal corresponding to the test DLL coding signal, the test temperature coding signal, the test voltage coding signal, and the test process angle coding signal of each target bit during a test phase; and determining the initial DCC coding signal based on a correspondence between the target bit target DLL coding signal and the target bit test DLL coding signal, a correspondence between the first actual temperature coding signal and the test temperature coding signal, a correspondence between the first actual voltage coding signal and the test voltage coding signal, and a correspondence between the actual process angle coding signal and the test process angle coding signal.

[0090] In the process of determining the initial DCC coding signal based on the target DLL coding signal, the first actual temperature coding signal, the first actual voltage coding signal and the actual process angle coding signal of the DRAM, since the DLL coding signal is at least 8 bits, at this time, the actual coding signal composed of the target DLL coding signal, the first actual temperature coding signal, the first actual voltage coding signal and the actual process angle coding of the DRAM has at least 18 bits. At this time, the number of fuses included in each fuse group is 256. Since the fuse group cannot accommodate a larger number of fuses, the actual coding signal is composed of the coding signal of the highest three bits of the target DLL coding signal (the highest three bits of the target DLL coding signal are the target bits of the target DLL coding signal) and the first actual temperature coding signal, the first actual voltage coding signal and the actual process angle coding signal of the DRAM. The initial DCC coding signal is determined based on the actual coding signal.

[0091] It should be noted that the specific process of determining the initial DCC coding signal based on the correspondence between the target bit target DLL coding signal and the target bit test DLL coding signal, the correspondence between the first actual temperature coding signal and the test temperature coding signal, the correspondence between the first actual voltage coding signal and the test voltage coding signal, and the correspondence between the actual process angle coding signal and the test process angle coding signal is the same as the process of determining the initial DCC coding signal based on the correspondence between the first actual temperature coding signal and the test temperature coding signal, the correspondence with the test voltage coding signal, and the correspondence between the actual process angle coding signal and the test process angle coding signal. The difference is that, in the embodiment of the present disclosure, the number of fuses included in each fuse group is 81, and the specific implementation process is not specifically limited in the embodiment of the present disclosure.

[0092] The DCC circuit calibration method provided by the embodiments of the present disclosure obtains a target DLL coding signal acting on the DLL circuit and then determines an initial DCC coding signal based on the target DLL coding signal, a first actual temperature coding signal, a first actual voltage coding signal, and an actual process angle coding signal. This method solves the problem of asymmetric clock signal rise and fall delays, which can occur when the number of delay cells to be adjusted in the DLL circuit cannot be determined. This can lead to clock signal duty cycle distortion due to varying performance of delay cells under different PVT conditions. This method ensures the validity of the determined initial DCC coding signal.

[0093] Based on the above embodiments, the present disclosure further provides a DCC circuit calibration system. Figure 4 FIG. 1 is a structural diagram of a DCC circuit calibration system provided by an embodiment of the present disclosure. Figure 4 As shown, the DCC circuit calibration system includes:

[0094] A duty cycle difference signal determination module 410 is configured to obtain an internal clock signal output by the DLL circuit and a feedback clock signal output by the DCC circuit, and determine a duty cycle difference signal based on the internal clock signal and the feedback clock signal;

[0095] An information acquisition module 420 is configured to acquire first actual temperature information and first actual voltage information of a DCC circuit at a target sampling moment, as well as actual process corner grade information of a DRAM;

[0096] An initial DCC coding signal determining module 430 is configured to determine an initial DCC coding signal according to the first actual temperature information, the first actual voltage signal, and the actual process corner level information;

[0097] The target DCC coding signal determination module 440 is used to adjust the initial DCC coding signal according to the duty cycle difference signal to obtain a target DCC coding signal, so as to control the conduction state of the DCC circuit through the target DCC coding signal.

[0098] The DCC circuit calibration system provided by the embodiment of the present disclosure first obtains the internal clock signal output by the DLL circuit and the feedback clock signal output by the DCC circuit, and determines a duty cycle difference signal based on the internal clock signal and the feedback clock signal. Then, the system obtains the first actual temperature information and the first actual voltage information of the DCC circuit at the target sampling moment, as well as the actual process corner level information of the DRAM. The system determines the initial DCC coding signal based on the first actual temperature information, the first actual voltage signal, and the actual process corner level information. Finally, the system adjusts the initial DCC coding signal based on the duty cycle difference signal to obtain the target DCC coding signal, thereby avoiding the DCC circuit calibration requiring a large amount of time to correct the duty cycle imbalance of the clock signal caused by temperature and voltage changes.

[0099] In a specific embodiment, before determining the initial DCC coding signal according to the first actual temperature information, the first actual voltage signal, and the actual process angle level information, the method further includes:

[0100] Determining a clock phase difference signal according to the internal clock signal and the feedback clock signal;

[0101] Acquire second actual temperature information and second actual voltage information of the DLL circuit at a target sampling time, and determine a target step size control signal according to the second actual temperature information, the second actual voltage information, and the actual process corner level information;

[0102] determining a target DLL encoding signal according to the clock phase difference signal and the target step size control signal;

[0103] The determining an initial DCC coding signal according to the first actual temperature information, the first actual voltage signal, and the actual process angle level information includes:

[0104] An initial DCC coding signal is determined according to the target DLL coding signal, the first actual temperature information, the first actual voltage signal, and the actual process corner level information.

[0105] In a specific embodiment, determining the initial DCC coding signal according to the target DLL coding signal, the first actual temperature information, the first actual voltage signal, and the actual process corner level information includes:

[0106] Determine a first actual temperature encoding signal, a first actual voltage encoding signal, and an actual process angle encoding signal according to the first actual temperature information, the first actual voltage information, and the actual process angle level information;

[0107] An initial DCC encoding signal is determined according to the target DLL encoding signal, the first actual temperature encoding signal, the first actual voltage encoding signal, and the actual process angle encoding signal.

[0108] In a specific embodiment, determining a first actual temperature encoding signal, a first actual voltage encoding signal, and an actual process angle encoding signal according to the first actual temperature information, the first actual voltage information, and the actual process angle level information includes:

[0109] Determining a first actual temperature encoding signal according to a temperature interval within which the first actual temperature information is located at a target sampling moment;

[0110] Determining a first actual voltage encoding signal according to a voltage interval in which the first actual voltage information is located at a target sampling time;

[0111] An actual process angle coding signal is determined according to the actual process angle level information submitted by the test module.

[0112] In a specific embodiment, determining the initial DCC coding signal according to the target DLL coding signal, the first actual temperature coding signal, the first actual voltage coding signal, and the actual process angle coding signal includes:

[0113] Acquire a test DCC coding signal corresponding to a test DLL coding signal, a test temperature coding signal, a test voltage coding signal, and a test process angle coding signal of each target bit during a test phase;

[0114] An initial DCC coding signal is determined according to the correspondence between the target bit target DLL coding signal and the target bit test DLL coding signal, the correspondence between the first actual temperature coding signal and the test temperature coding signal, the correspondence between the first actual voltage coding signal and the test voltage coding signal, and the correspondence between the actual process angle coding signal and the test process angle coding signal.

[0115] In a specific embodiment, determining the target DLL encoding signal according to the clock phase difference signal and the target step size control signal includes:

[0116] Determining a target number of delay units required to be delayed in the adjustable delay chain according to the clock phase difference signal and the target step size control signal;

[0117] The target DLL coding signal is determined according to the target number of delay units required to be delayed by the adjustable delay chain and the initial DLL coding signal of the adjustable delay chain.

[0118] In a specific embodiment, determining the target number of delay units required to be delayed in the adjustable delay chain according to the clock phase difference signal and the target step size control signal includes:

[0119] Determining the number of unit delay units required to be delayed in the adjustable delay chain according to the clock phase difference signal;

[0120] The target number of delay units required for the adjustable delay chain to be delayed is determined according to the number of unit delay units and the target step length control signal.

[0121] In a specific embodiment, acquiring an internal clock signal output by the DLL circuit and a feedback clock signal output by the DCC circuit, and determining a duty cycle difference signal based on the internal clock signal and the feedback clock signal, includes:

[0122] Obtain the internal clock signal output by the DLL circuit and the feedback clock signal output by the DCC circuit;

[0123] A duty cycle difference signal is determined according to a duration corresponding to a high level of the internal clock signal and a duration corresponding to a high level of the feedback clock signal.

[0124] Based on the above embodiments, an embodiment of the present disclosure further provides a memory, which includes a DCC circuit calibration system. The DCC circuit calibration system controls the DCC circuit based on the DCC circuit calibration method, and has the beneficial effects described in any of the above embodiments.

[0125] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0126] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned steps / processes does not mean the order of execution, and the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. In addition, the serial numbers of the embodiments of the present application mentioned above are only for description and do not represent the advantages and disadvantages of the embodiments.

[0127] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can, for example, be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0128] The foregoing description is merely a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Those skilled in the art will readily appreciate that various modifications and variations are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present disclosure shall be included within the scope of protection of the present disclosure.

Claims

1. A DCC circuit calibration method, characterized in that: include: Obtaining an internal clock signal output by the DLL circuit and a feedback clock signal output by the DCC circuit, and determining a duty cycle difference signal based on the internal clock signal and the feedback clock signal; Acquire first actual temperature information and first actual voltage information of the DCC circuit at a target sampling moment, and actual process corner grade information of the DRAM; determining an initial DCC coding signal according to the first actual temperature information, the first actual voltage information, and the actual process angle level information; adjusting the initial DCC coding signal according to the duty cycle difference signal to obtain a target DCC coding signal, so as to control the conduction state of the DCC circuit through the target DCC coding signal; The determining of the initial DCC coding signal according to the first actual temperature information, the first actual voltage information, and the actual process angle level information includes: Determining a first actual temperature encoding signal, a first actual voltage encoding signal, and an actual process angle encoding signal according to the first actual temperature information, the first actual voltage information, and the actual process angle level information; Determining an initial DCC coding signal according to the first actual temperature coding signal, the first actual voltage coding signal, and the actual process angle coding signal; The determining, according to the first actual temperature information, the first actual voltage information and the actual process angle level information, a first actual temperature encoding signal, a first actual voltage encoding signal and an actual process angle encoding signal comprises: Determining a first actual temperature encoding signal according to a temperature interval within which the first actual temperature information is located at a target sampling moment; Determining a first actual voltage encoding signal according to a voltage interval in which the first actual voltage information is located at a target sampling time; Determining an actual process angle coding signal according to the actual process angle level information submitted by the test module; The determining of the initial DCC coding signal according to the first actual temperature coding signal, the first actual voltage coding signal and the actual process angle coding signal comprises: Acquire a test DCC coding signal corresponding to each test temperature coding signal, test voltage coding signal, and test process angle coding signal during a test phase; An initial DCC coding signal is determined according to the correspondence between the first actual temperature coding signal and the test temperature coding signal, the correspondence between the first actual voltage coding signal and the test voltage coding signal, and the correspondence between the actual process angle coding signal and the test process angle coding signal.

2. The method according to claim 1, characterized in that Before determining the initial DCC coding signal according to the first actual temperature information, the first actual voltage information, and the actual process angle level information, the method further includes: Determining a clock phase difference signal according to the internal clock signal and the feedback clock signal; Acquire second actual temperature information and second actual voltage information of the DLL circuit at a target sampling time, and determine a target step size control signal according to the second actual temperature information, the second actual voltage information, and the actual process corner level information; determining a target DLL encoding signal according to the clock phase difference signal and the target step size control signal; The determining an initial DCC coding signal according to the first actual temperature information, the first actual voltage information, and the actual process angle level information includes: An initial DCC encoding signal is determined according to the target DLL encoding signal, the first actual temperature information, the first actual voltage information, and the actual process corner level information.

3. The method according to claim 2, characterized in that The determining an initial DCC coding signal according to the target DLL coding signal, the first actual temperature information, the first actual voltage information, and the actual process corner level information includes: Determine a first actual temperature encoding signal, a first actual voltage encoding signal, and an actual process angle encoding signal according to the first actual temperature information, the first actual voltage information, and the actual process angle level information; An initial DCC encoding signal is determined according to the target DLL encoding signal, the first actual temperature encoding signal, the first actual voltage encoding signal, and the actual process angle encoding signal.

4. The method according to claim 3, characterized in that The determining an initial DCC coding signal according to the target DLL coding signal, the first actual temperature coding signal, the first actual voltage coding signal, and the actual process angle coding signal includes: Acquire a test DCC coding signal corresponding to a test DLL coding signal, a test temperature coding signal, a test voltage coding signal, and a test process angle coding signal of each target bit during a test phase; An initial DCC coding signal is determined according to the correspondence between the target bit target DLL coding signal and the target bit test DLL coding signal, the correspondence between the first actual temperature coding signal and the test temperature coding signal, the correspondence between the first actual voltage coding signal and the test voltage coding signal, and the correspondence between the actual process angle coding signal and the test process angle coding signal.

5. The method according to claim 2, characterized in that The step of determining a target DLL encoding signal according to the clock phase difference signal and the target step size control signal includes: Determining a target number of delay units required to be delayed in the adjustable delay chain according to the clock phase difference signal and the target step size control signal; The target DLL coding signal is determined according to the target number of delay units required to be delayed by the adjustable delay chain and the initial DLL coding signal of the adjustable delay chain.

6. The method according to claim 5, characterized in that The step of determining the target number of delay units required to be delayed in the adjustable delay chain according to the clock phase difference signal and the target step size control signal includes: Determining the number of unit delay units required to be delayed in the adjustable delay chain according to the clock phase difference signal; The target number of delay units required for the adjustable delay chain to be delayed is determined according to the number of unit delay units and the target step length control signal.

7. The method according to claim 1, characterized in that The acquiring the internal clock signal output by the DLL circuit and the feedback clock signal output by the DCC circuit, and determining the duty cycle difference signal according to the internal clock signal and the feedback clock signal, includes: Obtain the internal clock signal output by the DLL circuit and the feedback clock signal output by the DCC circuit; A duty cycle difference signal is determined according to a duration corresponding to a high level of the internal clock signal and a duration corresponding to a high level of the feedback clock signal.

8. A DCC circuit calibration system, characterized in that: include: a duty cycle difference signal determination module, configured to obtain an internal clock signal output by the DLL circuit and a feedback clock signal output by the DCC circuit, and determine a duty cycle difference signal based on the internal clock signal and the feedback clock signal; An information acquisition module, configured to acquire first actual temperature information and first actual voltage information of a DCC circuit at a target sampling moment, and actual process corner grade information of a DRAM; an initial DCC coding signal determining module, configured to determine an initial DCC coding signal according to the first actual temperature information, the first actual voltage information, and the actual process angle level information; a target DCC coding signal determination module, configured to adjust the initial DCC coding signal according to the duty cycle difference signal to obtain a target DCC coding signal, so as to control the conduction state of the DCC circuit through the target DCC coding signal; The determining of the initial DCC coding signal according to the first actual temperature information, the first actual voltage information, and the actual process angle level information includes: Determining a first actual temperature encoding signal, a first actual voltage encoding signal, and an actual process angle encoding signal according to the first actual temperature information, the first actual voltage information, and the actual process angle level information; Determining an initial DCC coding signal according to the first actual temperature coding signal, the first actual voltage coding signal, and the actual process angle coding signal; The determining, according to the first actual temperature information, the first actual voltage information and the actual process angle level information, a first actual temperature encoding signal, a first actual voltage encoding signal and an actual process angle encoding signal comprises: Determining a first actual temperature encoding signal according to a temperature interval within which the first actual temperature information is located at a target sampling moment; Determining a first actual voltage encoding signal according to a voltage interval in which the first actual voltage information is located at a target sampling time; Determining an actual process angle encoding signal according to the actual process angle level information submitted by the test module; The determining of the initial DCC coding signal according to the first actual temperature coding signal, the first actual voltage coding signal and the actual process angle coding signal comprises: Acquire a test DCC coding signal corresponding to each test temperature coding signal, test voltage coding signal, and test process angle coding signal during a test phase; An initial DCC coding signal is determined according to the correspondence between the first actual temperature coding signal and the test temperature coding signal, the correspondence between the first actual voltage coding signal and the test voltage coding signal, and the correspondence between the actual process angle coding signal and the test process angle coding signal.

9. A memory, characterized in that: Including the DCC circuit calibration system as described in claim 8.

Images