Analog-to-digital converter circuit, electronic device including the same, and method of controlling the same

Abstract

An ADC circuit comprises: an ADC for performing a conversion operation in a time-interleaved manner; and a control logic circuit connected to the ADC, where the control logic circuit is configured to: calculate a correlation value between the data at a first number of times using a first number of bits in each of the data output from the ADC; calibrating the sampling timing of at least some of the ADCs based on a first accumulated correlation value obtained by accumulating correlation values calculated at a first number of times; calculating a correlation value between the data at a second number of times by using a second number of bits in each data; and calibrating the sampling timing of at least some of the ADCs based on a second accumulated correlation value obtained by accumulating the correlation values calculated by the second number of times.

Description

Cross - reference to related applications

[0001] This application claims priority to Korean Patent Application No. 10 - 2023 - 0178954, filed with the Korean Intellectual Property Office on December 11, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0002] Embodiments of the present disclosure described herein relate to an analog - to - digital converter circuit, an electronic device including the analog - to - digital converter circuit, and a method of controlling the analog - to - digital converter circuit. Background art

[0003] An analog signal can be converted into a digital signal to make it easier to process with modern digital systems. For example, a radio - frequency (RF) signal in analog form can be received through an antenna in an electronic device and converted into a digital signal for processing by the internal system of the device.

[0004] The circuit that performs this conversion is called an analog - to - digital converter (ADC). The output of the ADC can be used to drive components within a digital system.

[0005] Recently, to increase the speed of these ADC circuits, a high - speed analog - to - digital conversion method that uses multiple ADCs in a time - interleaved manner has been used.

[0006] However, this method may cause data distortion due to time - deviation errors between multiple ADCs, which may degrade the performance of the ADC circuit.

[0007] To solve this problem, calibration methods have been developed that use correlation calculations based on their respective outputs to calibrate the sampling timing of multiple ADCs. Summary of the invention

[0008] Embodiments of the present disclosure provide an analog - to - digital converter (ADC) circuit that minimizes both the power consumption and time required to calculate the correlation value between data output from multiple ADCs, thereby enabling efficient calibration of their sampling timing.

[0009] According to an embodiment of the present disclosure, an ADC circuit is provided. The ADC circuit includes: a plurality of ADCs configured to perform conversion operations in a time-interleaved manner; and a control logic circuit connected to the plurality of ADCs. The control logic circuit is configured to: calculate a correlation value between the data using a first number of bits in each of the data output from the plurality of ADCs at a first number of times; calibrate the sampling timing of at least some of the plurality of ADCs based on a first cumulative correlation value obtained by accumulating the correlation values calculated at the first number of times; calculate the correlation value between the data using a second number of bits in each of the data at a second number of times, where the second number of times is greater than the first number of times, and the second number of bits is greater than the first number of bits; and calibrate the sampling timing of at least some of the plurality of ADCs based on a second cumulative correlation value obtained by accumulating the correlation values calculated at the second number of times.

[0010] According to an embodiment of the present disclosure, a method for controlling an ADC circuit is provided. The method includes: calculating a correlation value between the data using a first number of bits in each of the data output from a plurality of ADCs at a first number of times; calibrating the sampling timing of at least some of the plurality of ADCs based on a first cumulative correlation value obtained by accumulating the correlation values calculated at the first number of times; calculating the correlation value between the data using a second number of bits in each of the data at a second number of times, where the second number of times is greater than the first number of times, and the second number of bits is greater than the first number of bits; and calibrating the sampling timing of at least some of the plurality of ADCs based on a second cumulative correlation value obtained by accumulating the correlation values calculated at the second number of times.

[0011] According to an embodiment of the present disclosure, there is provided an electronic device for transmitting and receiving radio frequency (RF) signals, the electronic device including: an antenna configured to receive an RF signal; and an ADC circuit configured to convert the RF signal into a digital signal, wherein the ADC circuit includes: a first ADC and a second ADC that perform a conversion operation in a time-interleaved manner; and a control logic circuit connected to the first ADC and the second ADC, wherein the control logic circuit is configured to: calculate a correlation value between the first data output from the first ADC and the second data output from the second ADC using a first number of bits in each of the first data and the second data; calibrate a sampling timing of at least some of the first ADC and the second ADC based on a first cumulative correlation value including the calculated correlation value; calculate a correlation value between the first data and the second data using a second number of bits in each of the first data and the second data, the second number of bits being greater than the first number of bits; and calibrate a sampling timing of at least some of the first ADC and the second ADC based on a second cumulative correlation value including the calculated correlation value. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other features of the present disclosure will become apparent by describing embodiments of the present disclosure in detail with reference to the drawings.

[0013] Figure 1 is a block diagram showing an analog-to-digital converter (ADC) circuit according to an embodiment.

[0014] Figure 2A is a diagram showing a first number of bits used by a control logic circuit according to an embodiment to calculate a correlation value between data output from an ADC.

[0015] Figure 2B is a diagram showing a second number of bits used by a control logic circuit according to an embodiment to calculate a correlation value between data output from an ADC.

[0016] Figure 3 is a diagram showing a configuration in which a control logic circuit according to an embodiment calculates a correlation value between data output from an ADC a different number of times.

[0017] Figure 4A is a block diagram showing a configuration of an ADC circuit according to an embodiment further including a clock generation circuit and a delay circuit.

[0018] Figure 4B is a diagram showing a configuration in which a control logic circuit according to an embodiment controls a phase of a first clock signal through a delay circuit.

[0019] Figure 4CFIG. is a diagram showing a configuration in which a control logic circuit controls a phase of a second clock signal through a delay circuit according to an embodiment.

[0020] Figure 5 FIG. is a block diagram showing an ADC circuit including a control logic circuit including associated circuits according to an embodiment.

[0021] Figure 6 FIG. is a flowchart showing a method in which a control logic circuit calibrates phases of at least some of a plurality of ADCs according to an embodiment.

[0022] Figure 7 FIG. is a flowchart showing a method in which a control logic circuit calculates a correlation value between data output from a plurality of ADCs a different number of times using a different number of bits depending on the number of calibration times according to an embodiment.

[0023] Figure 8A FIG. is a flowchart showing a method in which a control logic circuit controls a phase of a clock signal along a calibration direction based on a sign of a first cumulative correlation value according to an embodiment.

[0024] Figure 8B FIG. is a flowchart showing a method in which a control logic circuit controls a phase of a clock signal according to a calibration amount based on an amount of a first cumulative correlation value according to an embodiment.

[0025] Figure 9 FIG. is a flowchart showing a method in which a control logic circuit calibrates sampling timings of at least some of a plurality of ADCs based on a third cumulative correlation value according to an embodiment.

[0026] Figure 10A FIG. is a diagram showing a first number of bits used by a control logic circuit according to an embodiment to calculate a correlation value between data output from an ADC.

[0027] Figure 10B FIG. is a diagram showing a second number of bits used by a control logic circuit according to an embodiment to calculate a correlation value between data output from an ADC.

[0028] Figure 10C FIG. is a diagram showing a third number of bits used by a control logic circuit according to an embodiment to calculate a correlation value between data output from an ADC.

[0029] Figure 11 FIG. is a block diagram showing an electronic device including an antenna and an ADC circuit according to an embodiment.

[0030] Figure 12 FIG. is a block diagram showing an Internet of Things (IoT) device including an ADC circuit according to an embodiment.

[0031] Figure 13 is a block diagram showing a mobile terminal applying an ADC circuit according to an embodiment. Detailed implementation

[0032] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0033] Figure 1 is a block diagram showing an analog-to-digital converter (ADC) circuit according to an embodiment. Figure 2A is a diagram showing a first number of bits used by a control logic circuit according to an embodiment to calculate a correlation value between data output from the ADC. Figure 2B is a diagram showing a second number of bits used by a control logic circuit according to an embodiment to calculate a correlation value between data output from the ADC. Figure 3 is a diagram showing a configuration in which a control logic circuit according to an embodiment calculates a correlation value between data output from the ADC a different number of times.

[0034] Refer to Figure 1 According to an embodiment, the ADC circuit 100 may include a plurality of ADCs 120 and a control logic circuit 110.

[0035] For example, the ADC circuit 100 may include a plurality of ADCs 120 that convert analog data AD into digital data DO for output. The plurality of ADCs 120 may include a first ADC ADC1 to an nth ADC ADCn connected in parallel with each other.

[0036] According to an embodiment, the plurality of ADCs 120 may operate in a time-interleaved manner to convert analog data AD into digital data DO for output.

[0037] More specifically, each ADC among the plurality of ADCs 120 may sample the analog data AD received from the outside based on a clock signal having a different phase. In other words, each ADC among the plurality of ADCs 120 may sample the analog data AD received from the outside based on a clock signal having a different phase. In addition, each ADC among the plurality of ADCs 120 may output data DO1 to DOn including sampled data samples.

[0038] The digital data DO may include data DO1 to DOn output from each of the plurality of ADCs 120. For example, the digital data DO may include data DO1 to DOn sequentially output from the plurality of ADCs 120.

[0039] Therefore, multiple ADCs 120 can be referred to as time-interleaved (TI) ADCs. Additionally, each of the multiple ADCs 120 (e.g., ADC1 to ADCn) can be referred to as a sub-ADC.

[0040] Furthermore, the ADC circuit 100 can include control logic circuitry 110 connected to the multiple ADCs 120.

[0041] The control logic circuitry 110 can, for example, execute software (or a program) to control at least one other component of the ADC circuit 100 (e.g., the multiple ADCs 120), and can process or calculate various data. The control logic circuitry 110 can include a central processing unit or a microprocessor, and can control the overall operation of the ADC circuit 100. Thus, the operations performed by the ADC circuit 100 can be executed under the control of the control logic circuitry 110.

[0042] According to an embodiment, the control logic circuitry 110 can include an algorithm for controlling the multiple ADCs 120. For example, the algorithm can be software code programmed inside the control logic circuitry 110. As another example, the algorithm can be hard code obtained through hard coding inside the control logic circuitry 110, but is not limited thereto.

[0043] The control logic circuitry 110 can control the sampling timing of each of the multiple ADCs 120 according to the algorithm. More specifically, the control logic circuitry 110 can output a control signal CMD for controlling the sampling timing of each of the multiple ADCs 120. The control signal CMD can be provided to the multiple ADCs 120.

[0044] According to an embodiment, the control logic circuitry 110 can calibrate the sampling timing of at least some of the multiple ADCs 120 based on the digital data DO output from the multiple ADCs 120.

[0045] More specifically, the control logic circuitry 110 can calculate the correlation values between the data DO1 to DOn output from the multiple ADCs 120 based on the digital data DO output from the multiple ADCs 120.

[0046] For example, the control logic circuitry 110 can calculate the correlation values between the data DO1 to DOn by inputting at least some bits of each of the data DO1 to DOn into a correlation function. In this case, the correlation value can be referred to as a correlation coefficient, which indicates the degree of correlation of each of the data DO1 to DOn.

[0047] Furthermore, the control logic circuitry 110 can calibrate the sampling timing of at least some of the multiple ADCs 120 based on the calculated correlation values.

[0048] In addition, the control logic circuit 110 according to an embodiment may increase a calibration count in response to calibrating the sampling timing of at least some of the plurality of ADCs 120.

[0049] For example, the control logic circuit 110 may increase the calibration count by "1" in response to calibrating the sampling timing of at least some of the plurality of ADCs 120.

[0050] In this case, the calibration count may refer to the number of times the control logic circuit 110 calibrates the sampling timing of at least some of the plurality of ADCs 120.

[0051] Referring together Figure 1 , Figure 2A and Figure 2B , the control logic circuit 110 may calculate a correlation value between the data DO1 to DOn using at least some bits in each of the data DO1 to DOn output from the plurality of ADCs 120.

[0052] For example, the control logic circuit 110 may calculate the correlation value between the data DO1 to DOn using different numbers of bits in each of the data DO1 to DOn depending on the number of times of calibration performed on the sampling timing of the plurality of ADCs 120.

[0053] According to an embodiment, when the calibration count is less than or equal to a threshold number, the control logic circuit 110 may calculate the correlation value between the data DO1 to DOn using a first number n1 of bits in each of the data DO1 to DOn.

[0054] For example, referring to Figure 2A , the control logic circuit 110 may calculate the correlation value between the first data DO1 output from the first ADC1 and the second data DO2 output from the second ADC2 using a first number n1 of bits in each of the data DO1 and DO2.

[0055] In this case, the control logic circuit 110 may calculate the correlation value between the data DO1 to DOn using the first number n1 of bits starting from the most significant bit (MSB) in each of the first data DO1 and the second data DO2.

[0056] Specifically, when the number of times of calibration of the sampling timing for the plurality of ADCs 120 is less than or equal to the threshold number, the control logic circuit 110 may calculate the correlation value between the data DO1 to DOn using the first number n1 of bits including the most significant bit (MSB) in each of the data DO1 to DOn.

[0057] In addition, referring together to Figure 2A and Figure 3 , when the calibration count is less than or equal to the threshold quantity Tn1, the control logic circuit 110 may calculate the correlation value between the data DO1 to DOn at a first count k1.

[0058] More specifically, when the calibration count is less than or equal to the threshold quantity Tn1, the control logic circuit 110 may use the first quantity n1 of bits in each of the data DO1 to DOn and calculate the correlation value between the data DO1 to DOn by accumulating the correlation value between the data DO1 to DOn at a first count k1.

[0059] For example, when the calibration count is less than or equal to the threshold quantity Tn1, the control logic circuit 110 may use the first quantity n1 of bits in each of the first data DO1 and the second data DO2 and calculate the correlation value between the first data DO1 and the second data DO2 at a first count k1. In another example, when the calibration count is less than or equal to the threshold quantity Tn1, the control logic circuit 110 may use the first quantity n1 of bits in each of the second data DO2 and the third data DO3 and calculate the correlation value between the second data DO2 and the third data DO3 at a first count k1.

[0060] For example, when the calibration count is less than or equal to the threshold quantity Tn1, the portion where the control logic circuit 110 uses the first quantity n1 of bits in each of the data DO1 to DOn and calculates the correlation value between the data DO1 to DOn at a first count k1 may be referred to as the coarse calibration portion.

[0061] In addition, the control logic circuit 110 may calibrate the sampling timing of at least some of the plurality of ADCs 120 based on the first accumulated correlation value, where the correlation value calculated at a first count k1 is accumulated.

[0062] According to an embodiment, when the calibration count exceeds the threshold quantity Tn1, the control logic circuit 110 may use the second quantity n2 of bits in each of the data DO1 to DOn to calculate the correlation value between the data DO1 to DOn.

[0063] For example, referring to Figure 2B , the control logic circuit 110 may use the second quantity n2 of bits in each of the first data DO1 and the second data DO2 to calculate the correlation value between the first data DO1 and the second data DO2.

[0064] In this case, the second quantity n2 may be greater than the first quantity n1.

[0065] Therefore, when the calibration count exceeds the threshold number Tn1, the control logic circuit 110 can calculate the correlation value between the data DO1 to DOn using the second number n2 of bits in each of the data DO1 to DOn, where the second number n2 of bits is greater than the first number n1 of bits.

[0066] In addition, for example, each of the data DO1 to DOn output from the multiple ADCs 120 can be output with the second number n2 of bits.

[0067] Therefore, when the number of calibration times for the sampling timing of the multiple ADCs 120 exceeds the threshold number Tn1, the control logic circuit 110 can calculate the correlation value between the data DO1 to DOn using all the bits in each of the data DO1 to DOn.

[0068] Specifically, when the calibration count exceeds the threshold number Tn1, the control logic circuit 110 can calculate the correlation value between the data DO1 to DOn using the second number n2 of bits including the most significant bit (MSB) to the least significant bit (LSB) in each of the data DO1 to DOn.

[0069] In addition, referring together to Figure 2B and Figure 3 , when the calibration count exceeds the threshold number Tn1, the control logic circuit 110 can calculate the correlation value between the data DO1 to DOn at the second number k2 of times.

[0070] In this case, the second number k2 of times can be greater than the first number k1 of times.

[0071] More specifically, when the calibration count exceeds the threshold number Tn1, the control logic circuit 110 can calculate the correlation value between the data DO1 to DOn by accumulating the correlation value between the data DO1 to DOn at the second number k2 of times using the second number n2 of bits in each of the data DO1 to DOn.

[0072] For example, the control logic circuit 110 can calculate the correlation value between the first data DO1 and the second data DO2 at the second number k2 of times using the second number n2 of bits in each of the first data DO1 and the second data DO2. As another example, the control logic circuit 110 can calculate the correlation value between the second data DO2 and the third data DO3 at the second number k2 of times using the second number n2 of bits in each of the second data DO2 and the third data DO3.

[0073] For example, when the calibration count exceeds a threshold number Tn1, the portion of the control logic circuit 110 that calculates a correlation value between the data DO1 to DOn using a second number n2 of bits in each of the data DO1 to DOn a second number of times k2 can be referred to as a fine calibration portion.

[0074] In addition, the control logic circuit 110 can calibrate the sampling timing of at least some of the plurality of ADCs 120 based on the second cumulative correlation value, where the correlation values calculated a second number of times k2 are accumulated.

[0075] Referring to the above configuration, when the calibration count is less than or equal to the threshold number Tn1, compared to the case where the calibration count exceeds the threshold number Tn1, the control logic circuit 110 can use a relatively smaller number of bits in each of the data DO1 to DOn to calculate the correlation value between the data DO1 to DOn.

[0076] In this way, the ADC circuit 100 according to an embodiment of the present disclosure can minimize power while calculating the correlation value between the data DO1 to DOn, thereby calibrating the sampling timing of at least some of the plurality of ADCs 120.

[0077] In addition, when the calibration count is less than or equal to the threshold number Tn1, compared to when the calibration count exceeds the threshold number Tn1, the control logic circuit 110 can calculate the correlation value between the data DO1 to DOn by accumulating the correlation values between the data DO1 to DOn a relatively smaller number of times.

[0078] Therefore, when the calibration count is less than or equal to the threshold number Tn1, compared to when the calibration count exceeds the threshold number Tn1, the control logic circuit 110 can calculate the correlation value between the data DO1 to DOn at a relatively faster rate.

[0079] In this way, the ADC circuit 100 according to an embodiment of the present disclosure can minimize the time and / or power required to calculate the correlation value between the data DO1 to DOn, thereby calibrating the sampling timing of at least some of the plurality of ADCs 120.

[0080] Conversely, when the calibration count exceeds the threshold number Tn1, the control logic circuit 110 can increase the number of bits used to calculate the correlation value between the data DO1 to DOn.

[0081] In addition, when the calibration count exceeds the threshold number Tn1, the control logic circuit 110 can increase the number of calculation times performed by accumulating the correlation values between the data DO1 to DOn.

[0082] In addition, the control logic circuit 110 may calibrate the sampling timings of at least some of the plurality of ADCs 120 based on the accumulated correlation values, where an increasing number of bits are used to accumulate the correlation values calculated a increasing number of times.

[0083] Thus, the ADC circuit 100 according to an embodiment of the present disclosure can improve the calibration accuracy of the sampling timings for the plurality of ADCs 120.

[0084] Specifically, the control logic circuit 110 may calculate the correlation values between the data DO1 to DOn using different numbers of bits depending on the number of calibration times performed for the sampling timings of at least some of the plurality of ADCs 120.

[0085] In addition, the control logic circuit 110 may calculate the correlation values between the data DO1 to DOn by accumulating the correlation values between the data DO1 to DOn a different number of times based on the number of calibration times performed for the sampling timings of at least some of the plurality of ADCs 120.

[0086] Thus, the ADC circuit 100 can minimize the time and power required to calculate the correlation values for calibrating the sampling timings of the plurality of ADCs 120 while maintaining the calibration accuracy.

[0087] Figure 4A is a block diagram showing a configuration of an ADC circuit according to an embodiment further including a clock generation circuit and a delay circuit. Figure 4B is a diagram showing a configuration in which a control logic circuit controls a phase of a first clock signal through a delay circuit according to an embodiment. Figure 4C is a diagram showing a configuration in which a control logic circuit controls a phase of a second clock signal through a delay circuit according to an embodiment.

[0088] Refer to Figure 4A , the ADC circuit 100A according to an embodiment may include a plurality of ADCs 120, a control logic circuit 110, a clock generation circuit 140, and a delay circuit 130.

[0089] Figure 4A The ADC circuit 100A shown in Figure 1 is an example of the ADC circuit 100 shown in

[0090] According to an embodiment, the ADC circuit 100A may include a clock generation circuit 140 that generates a reference clock signal CKref.

[0091] The clock generation circuit 140 may generate a reference clock signal CKref with a preset target frequency based on the frequency and phase of an input signal.

[0092] For example, the clock generation circuit 140 may be a phase-locked loop (PLL) circuit that includes a phase detector, an oscillator, and a loop filter to generate a reference clock signal CKref with a specific target frequency.

[0093] As another example, the clock generation circuit 140 may be a delay-locked loop (DLL) circuit that delays an input voltage signal by a preset phase and generates a reference clock signal CKref with a specific target frequency.

[0094] However, the configuration of the clock generation circuit 140 is not limited to the above examples.

[0095] In addition, the ADC circuit 100A may include a delay circuit 130 that controls the phase of the reference clock signal CKref and outputs a plurality of clock signals CK with different phases.

[0096] According to an embodiment, the delay circuit 130 may delay the phase of the reference clock signal CKref received from the clock generation circuit 140 by different degrees, thereby providing a plurality of clock signals CK with different phases to the plurality of ADCs 120.

[0097] For example, the delay circuit 130 may include a plurality of delay units for controlling the phase of the reference clock signal CKref. Therefore, the delay circuit 130 may control the phase of the reference clock signal CKref using the plurality of delay units based on a control signal CMD received from the control logic circuit 110.

[0098] In addition, the ADC circuit 100A may include a multiplexer MUX connected to the plurality of ADCs 120.

[0099] According to an embodiment, the multiplexer MUX may output digital data DO including some of the data DO1 to DOn output from the plurality of ADCs 120.

[0100] The multiplexer MUX may sequentially output the data DO1 to DOn output from the plurality of ADCs 120. Therefore, the digital data DO output by the multiplexer MUX may include the data DO1 to DOn output sequentially from the plurality of ADCs 120.

[0101] According to an embodiment, the control logic circuit 110 may calculate a correlation value between the data DO1 to DOn included in the digital data DO.

[0102] More specifically, the control logic circuit 110 may calculate a correlation value between the data DO1 to DOn using at least some bits in each of the data DO1 to DOn.

[0103] In addition, the control logic circuit 110 may use at least some bits in each of the data DO1 to DOn to calculate a correlation value between the data DO1 to DOn by accumulating the correlation value between the data DO1 to DOn a specific number of times.

[0104] In addition, the control logic circuit 110 may calibrate the phase of at least some of the multiple clock signals CK output by the delay circuit 130 based on the accumulated correlation value calculated by accumulating the correlation value a specific number of times.

[0105] According to an embodiment, when the number of calibration times for the phase of at least some of the multiple clock signals CK is less than or equal to a threshold number Tn1, the control logic circuit 110 may use a first number n1 of bits in each of the data DO1 to DOn to calculate a correlation value between the data DO1 to DOn.

[0106] In addition, when the number of calibration times for the phase of at least some of the multiple clock signals CK is less than or equal to a threshold number Tn1, the control logic circuit 110 may calculate a correlation value between the data DO1 to DOn a first number of times k1.

[0107] According to another embodiment, when the number of calibration times for the phase of at least some of the multiple clock signals CK exceeds a threshold number Tn1, the control logic circuit 110 may use a second number n2 of bits in each of the data DO1 to DOn to calculate a correlation value between the data DO1 to DOn. In this case, the second number n2 may be greater than the first number n1.

[0108] In addition, when the number of calibration times for the phase of at least some of the multiple clock signals CK exceeds a threshold number Tn1, the control logic circuit 110 may calculate a correlation value between the data DO1 to DOn a second number of times k2. In this case, the second number of times k2 may be greater than the first number of times k1.

[0109] In addition, the control logic circuit 110 may calibrate the phase of at least some of the multiple clock signals CK output by the delay circuit 130 based on the calculated correlation value.

[0110] Referring to the above configuration, when the number of calibration times for the phases of multiple clock signals CK is less than or equal to the threshold number Tn1, compared with the case where the number of calibration times exceeds the threshold number Tn1, the control logic circuit 110 can use a relatively small number of bits to calculate the correlation value between the data DO1 to DOn.

[0111] In this way, the ADC circuit 100A can minimize the power consumed when calculating the correlation value between the data DO1 to DOn, thereby calibrating the sampling timing of at least some of the multiple ADCs 120.

[0112] In addition, when the number of calibration times for the phases of multiple clock signals CK is less than or equal to the threshold number Tn1, compared with the case where the number of calibration times exceeds the threshold number Tn1, the control logic circuit 110 can calculate the correlation value between the data DO1 to DOn by accumulating the correlation value between the data DO1 to DOn a relatively small number of times.

[0113] In this way, the ADC circuit 100A according to the embodiment of the present disclosure can minimize the time and / or power required to calculate the correlation value between the data DO1 to DOn, thereby calibrating the sampling timing of at least some of the multiple ADCs 120.

[0114] In the following Figure 4B and Figure 4C description, for ease of description, it is assumed that the control logic circuit 110 controls the delay circuit 130 based on the first cumulative correlation value.

[0115] In this case, the first cumulative correlation value can be a value accumulated by the control logic circuit 110 calculating the correlation value between the data DO1 to DOn using the first number n1 of bits in each of the data DO1 to DOn for the first number k1 of times.

[0116] According to an embodiment, the control logic circuit 110 can determine the calibration direction for the phases of at least some of the multiple clock signals CK based on the sign of the first cumulative correlation value.

[0117] In addition, the control logic circuit 110 can calibrate the phases of at least some of the multiple clock signals CK along the calibration direction determined by the sign of the first cumulative correlation value.

[0118] For example, referring to Figure 4B , the control logic circuit 110 can calibrate the phase of the first clock signal CK1 along the first calibration direction D1 based on the sign of the first cumulative correlation value to output the first calibrated clock signal CK1'.

[0119] In this case, the operation of the control logic circuit 110 to calibrate the phase of the first clock signal CK1 along the first calibration direction D1 can be referred to as the control logic circuit 110 lagging the phase of the first clock signal CK1.

[0120] For example, referring to Figure 4C , the control logic circuit 110 can calibrate the phase of the second clock signal CK2 along the second calibration direction D2 based on the sign of the first cumulative correlation value to output the second calibrated clock signal CK2'.

[0121] In this case, the operation of the control logic circuit 110 to calibrate the phase of the second clock signal CK2 along the second calibration direction D2 can be referred to as the control logic circuit 110 leading the phase of the second clock signal CK2.

[0122] In addition, the control logic circuit 110 can determine the calibration amount of the phase of at least some of the plurality of clock signals CK based on the amount of the first cumulative correlation value.

[0123] The control logic circuit 110 can control the phase of at least some of the plurality of clock signals CK according to the calibration amount based on the amount of the first cumulative correlation value.

[0124] For example, referring to Figure 4B , the control logic circuit 110 can calibrate the phase of the first clock signal CK1 according to the first calibration amount A1 based on the amount of the first cumulative correlation value to output the first calibrated clock signal CK1'.

[0125] As another example, referring to Figure 4C , the control logic circuit 110 can calibrate the phase of the second clock signal CK2 according to the second calibration amount A2 based on the amount of the first cumulative correlation value to output the second calibrated clock signal CK2'.

[0126] According to an embodiment, each ADC among the plurality of ADCs 120 can sample the analog data AD in response to the calibrated and received clock signals.

[0127] More specifically, each ADC among the plurality of ADCs 120 can sample the analog data AD in response to the rising edge of the calibrated and received clock signals.

[0128] For example, referring to Figure 4B , the first ADC ADC1 can sample the analog data AD in response to the rising edge of the first calibrated clock signal CK1'.

[0129] In addition, referring to Figure 4C, the second ADC ADC2 may sample the analog data AD in response to the rising edge of the second calibration clock signal CK2'.

[0130] Referring to the above configuration, the control logic circuit 110 according to the embodiment may calculate the correlation value between the data DO1 to DOn using different numbers of bits in portions divided according to the number of calibration times for the plurality of clock signals CK.

[0131] In addition, the control logic circuit 110 may calculate the correlation value between the data DO1 to DOn by accumulating the correlation value between the data DO1 to DOn different numbers of times in portions divided according to the number of calibration times for the plurality of clock signals CK.

[0132] In addition, the control logic circuit 110 may determine the phase of at least some of the plurality of clock signals CK output by the delay circuit 130 based on the cumulative correlation value of the correlation values calculated different numbers of times.

[0133] In this way, the control logic circuit 110 may calibrate the sampling timing of the clock signals of at least some of the plurality of ADCs 120.

[0134] Therefore, the ADC circuit 100A according to the embodiment of the present disclosure may minimize the time and power required to calculate the correlation value for calibrating the plurality of ADCs 120 while maintaining the calibration accuracy of the sampling timing for the plurality of ADCs 120.

[0135] Figure 5 is a block diagram showing an ADC circuit including a control logic circuit including a correlation circuit according to an embodiment.

[0136] Referring to Figure 5 , the ADC circuit 100B according to the embodiment may include a control logic circuit 110A, and the control logic circuit 110A includes a correlation circuit 201.

[0137] More specifically, the control logic circuit 110A according to the embodiment may include a correlation circuit 201 that calculates the correlation value between the plurality of ADCs 120.

[0138] In this case, Figure 5 the ADC circuit 100B and the control logic circuit 110A shown in Figure 1 are examples of the ADC circuit 100 and the control logic circuit 110 shown in

[0139] According to an embodiment, the correlation circuit 201 may calculate a correlation value between data DO1 to DOn output from a plurality of ADCs 120.

[0140] The first calculation circuit 611 may multiply the first data DO1 by the second data DO2 delayed by the second register 642.

[0141] In addition, the second calculation circuit 612 may multiply the second data DO2 by the first data DO1 delayed by the first register 641.

[0142] In this case, for example, when the number of times the control logic circuit 110A calibrates the sampling timing of the plurality of ADCs 120 is less than or equal to a threshold number Tn1, the correlation circuit 201 may calculate using the first number n1 of bits in each of the first data DO1 and the second data DO2.

[0143] As another example, when the number of times the control logic circuit 110A calibrates the sampling timing of the plurality of ADCs 120 exceeds the threshold number Tn1, the correlation circuit 201 may calculate using the second number n2 of bits in each of the first data DO1 and the second data DO2, where the second number n2 of bits is greater than the first number n1 of bits.

[0144] In addition, the third calculation circuit 613 may perform a subtraction calculation (or deduction) between the value output from the first calculation circuit 611 and the value output from the second calculation circuit 612. In this way, the third calculation circuit 613 may output a first correlation value CV1 between the first data DO1 and the second data DO2.

[0145] In addition, the correlation circuit 201 may calculate by accumulating the first correlation value CV1 between the first data DO1 and the second data DO2 based on the first data DO1 and the second data DO2 a specific number of times.

[0146] For example, when the number of times the control logic circuit 110A calibrates the sampling timing of the plurality of ADCs 120 is less than or equal to the threshold number Tn1, the correlation circuit 201 may calculate the first correlation value CV1 between the first data DO1 and the second data DO2 a first number of times k1.

[0147] As another example, when the number of times the control logic circuit 110A calibrates the sampling timing of the plurality of ADCs 120 exceeds the threshold number Tn1, the correlation circuit 201 may calculate the first correlation value CV1 between the first data DO1 and the second data DO2 a second number of times k2 greater than the first number of times k1.

[0148] Referring to the above configuration, when the number of times of calibrating the sampling timing of multiple ADCs 120 is less than or equal to the threshold number Tn1, compared with the case where the number of calibration times exceeds the threshold number Tn1, the control logic circuit 110A can use a relatively small number of bits to calculate the correlation value between the data DO1 to DOn.

[0149] In this way, the ADC circuit 100B can minimize the power consumed when calculating the correlation value between the data DO1 to DOn, so as to calibrate the sampling timing of at least some of the multiple ADCs 120.

[0150] In addition, when the number of times of calibrating the sampling timing of multiple ADCs 120 is less than or equal to the threshold number Tn1, compared with the case where the number of calibration times exceeds the threshold number Tn1, the control logic circuit 110A can perform the calculation by accumulating the correlation value between the data DO1 to DOn a relatively small number of times.

[0151] Therefore, when the number of times of calibrating the sampling timing of multiple ADCs 120 is less than or equal to the threshold number Tn1, compared with the case where the number of calibration times exceeds the threshold number Tn1, the control logic circuit 110A can calculate the correlation value between the data DO1 to DOn at a relatively faster rate.

[0152] In this way, the ADC circuit 100B according to the embodiment of the present disclosure can minimize the time and / or power required to calculate the correlation value between the data DO1 to DOn, so as to calibrate the sampling timing of at least some of the multiple ADCs 120.

[0153] In addition, when the number of times of calibrating the sampling timing of multiple ADCs 120 exceeds the threshold number Tn1, the control logic circuit 110A can increase the number of bits used to calculate the correlation value between the data DO1 to DOn.

[0154] In addition, when the number of times of calibrating the sampling timing of multiple ADCs 120 exceeds the threshold number Tn1, the control logic circuit 110A can increase the number of calculation times by accumulating the correlation value between the data DO1 to DOn.

[0155] In this way, the ADC circuit 100B according to the embodiment of the present disclosure can improve the calibration accuracy of the sampling timing of multiple ADCs 120.

[0156] Figure 6 It is a flowchart showing a method for calibrating the phase of at least some of multiple ADCs by a control logic circuit according to an embodiment.

[0157] Referring to Figure 6, according to an embodiment, the control logic circuit 110 may calculate a correlation value between data output from multiple ADCs 120 to calibrate the sampling timings of at least some of the multiple ADCs 120.

[0158] More specifically, the control logic circuit 110 may use different numbers of bits in each data within a portion divided based on the sampling timings of the multiple ADCs 120, and calculate the correlation value between the data a different number of times.

[0159] In addition, the control logic circuit 110 may use a cumulative correlation value determined based on the accumulation of correlation values calculated a different number of times to calibrate the sampling timings of at least some of the multiple ADCs 120.

[0160] In operation S10, according to an embodiment, the control logic circuit 110 may calculate the correlation value between data DO1 to DOn output from multiple ADCs 120 using a first number n1 of bits in each of the data DO1 to DOn a first number k1 of times.

[0161] More specifically, the control logic circuit 110 may use a first number n1 of bits in each of the data DO1 to DOn output from multiple ADCs 120 to calculate the correlation value between the data DO1 to DOn.

[0162] In addition, the control logic circuit 110 may calculate the correlation value between data DO1 to DOn output from multiple ADCs 120 a first number k1 of times.

[0163] In this way, the control logic circuit 110 may generate a first cumulative correlation value that includes the correlation value between data DO1 to DOn calculated a first number k1 of times.

[0164] In operation S20, according to an embodiment, the control logic circuit 110 may calibrate the sampling timings of at least some of the multiple ADCs 120 based on the first cumulative correlation value.

[0165] More specifically, the control logic circuit 110 may calibrate the phases of at least some of the multiple clock signals CK input to the multiple ADCs 120 based on the first cumulative correlation value.

[0166] For example, the control logic circuit 110 may calibrate the phases of at least some of the multiple clock signals CK input to the multiple ADCs 120 based on the calibration direction identified by the sign of the first cumulative correlation value.

[0167] In addition, the control logic circuit 110 may calibrate the phases of at least some of the clock signals CK input to the plurality of ADCs 120 according to the calibration amount determined from the first cumulative correlation value.

[0168] In this way, the control logic circuit 110 can control the timing at which each of the plurality of ADCs 120 samples the analog data AD.

[0169] In operation S30, the control logic circuit 110 according to an embodiment may calculate the correlation values between the data DO1 to DOn using the second number n2 of bits in each of the data DO1 to DOn output from the plurality of ADCs 120 for the second number of times k2.

[0170] More specifically, the control logic circuit 110 may calculate the correlation values between the data DO1 to DOn using the second number n2 of bits in each of the data DO1 to DOn output from the plurality of ADCs 120. In this case, the second number n2 may be greater than the first number n1.

[0171] In addition, for example, each of the data DO1 to DOn output from the plurality of ADCs 120 may be output with the second number n2 of bits.

[0172] Specifically, the control logic circuit 110 may calculate the correlation values between the data DO1 to DOn using all the bits in each of the data DO1 to DOn output from the plurality of ADCs 120.

[0173] In addition, the control logic circuit 110 may calculate the correlation values between the data DO1 to DOn output from the plurality of ADCs 120 for the second number of times k2. In this case, the second number of times k2 may be greater than the first number of times k1.

[0174] In this way, the control logic circuit 110 can generate a second cumulative correlation value that includes the correlation values between the data DO1 to DOn calculated for the second number of times k2.

[0175] In operation S40, the control logic circuit 110 according to an embodiment may calibrate the sampling timing of at least some of the plurality of ADCs 120 based on the second cumulative correlation value.

[0176] More specifically, the control logic circuit 110 may calibrate the phases of at least some of the plurality of clock signals CK input to the plurality of ADCs 120 based on the second cumulative correlation value.

[0177] For example, the control logic circuit 110 may calibrate the phases of at least some of the multiple clock signals CK input to the multiple ADCs 120 based on the calibration direction identified by the sign of the second cumulative correlation value.

[0178] In addition, the control logic circuit 110 may calibrate the phases of at least some of the clock signals CK input to the multiple ADCs 120 according to the calibration amount determined by the second cumulative correlation value.

[0179] In this way, the control logic circuit 110 may control the timing at which each of the multiple ADCs 120 samples the analog data AD.

[0180] Referring to the above configuration, the control logic circuit 110 may use different numbers of bits to calculate the correlation values between the data DO1 to DOn in different operations (e.g., operations S10 and S30).

[0181] The ADC circuit 100 uses a relatively small number of bits to calculate the correlation values between the data DO1 to DOn, thereby minimizing the power consumed when calculating the correlation values between the data DO1 to DOn.

[0182] In addition, the control logic circuit 110 may calculate the correlation values between the data DO1 to DOn different numbers of times in different operations (e.g., operations S10 and S30).

[0183] The ADC circuit 100 calculates the correlation values between the data DO1 to DOn a relatively small number of times, thereby minimizing the time and / or power required in the process of calculating the correlation values between the data DO1 to DOn.

[0184] In addition, the control logic circuit 110 may increase the number of bits used to calculate the correlation values between the data DO1 to DOn. In addition, the control logic circuit 110 may increase the number of times of calculating the correlation values between the data DO1 to DOn.

[0185] In addition, the control logic circuit 110 may use the cumulative correlation value to calibrate the sampling timing of at least some of the multiple ADCs 120, where a larger number of bits are used to accumulate the correlation values calculated a greater number of times.

[0186] In this way, the ADC circuit 100 according to the embodiments of the present disclosure can improve the calibration accuracy of the sampling timing of the multiple ADCs 120.

[0187] Specifically, the ADC circuit 100 according to an embodiment of the present disclosure can minimize the time and / or power required to calculate the relevant values for calibrating the sampling timings of multiple ADCs 120, while maintaining the calibration accuracy of the sampling timings of the multiple ADCs 120.

[0188] Figure 7 FIG. is a flowchart showing a method in which a control logic circuit according to an embodiment calculates the correlation value between data output from multiple ADCs a different number of times using a different number of bits depending on the number of calibration times.

[0189] Referring to Figure 7 , the control logic circuit 110 according to an embodiment can calculate the correlation value between data DO1 to DOn a different number of times using a different number of bits depending on whether the number of calibration times for the sampling timings of the multiple ADCs 120 exceeds a threshold number.

[0190] In this case, Figure 7 the operations S10 and S20 shown in Figure 6 may be the same operations as the operations S10 and S20 shown in

[0191] Therefore, descriptions overlapping with the above will be omitted to avoid redundancy.

[0192] In operation S21, the control logic circuit 110 according to an embodiment can increase the calibration count.

[0193] More specifically, the control logic circuit 110 can increase the calibration count in response to calibrating the sampling timings of at least some of the multiple ADCs 120 based on the first cumulative correlation value.

[0194] For example, the control logic circuit 110 can increase the calibration count by "1" in response to calibrating the sampling timings of at least some of the multiple ADCs 120.

[0195] In operation S23, the control logic circuit 110 according to an embodiment can determine whether the calibration count exceeds a first threshold number.

[0196] More specifically, when the calibration count increases, the control logic circuit 110 can determine whether the calibration count exceeds a first threshold number.

[0197] According to an embodiment, when the calibration count is less than or equal to the first threshold number, the control logic circuit 110 may calculate the correlation value between the data DO1 to DOn using the first number n1 of bits in each of the data DO1 to DOn.

[0198] In addition, when the calibration count is less than or equal to the first threshold number, the control logic circuit 110 may calculate the correlation value between the data DO1 to DOn at the first number of times k1.

[0199] In addition, the control logic circuit 110 may calibrate the sampling timing of at least some of the plurality of ADCs 120 based on the first cumulative correlation value, which is obtained by accumulating the correlation values calculated at the first number of times k1.

[0200] Specifically, the control logic circuit 110 may calibrate the sampling timing of at least some of the plurality of ADCs 120 based on the first cumulative correlation value according to the preset first threshold number.

[0201] According to another embodiment, when the calibration count exceeds the first threshold number, the control logic circuit 110 may calculate the correlation value between the data DO1 to DOn using the second number n2 of bits in each of the data DO1 to DOn.

[0202] In this case, the second number n2 may be greater than the first number n1.

[0203] In addition, for example, each of the data DO1 to DOn output from the plurality of ADCs 120 may be output with the second number n2 of bits.

[0204] Specifically, when the calibration count exceeds the first threshold number, the control logic circuit 110 may calculate the correlation value between the data DO1 to DOn using all the bits in each of the data DO1 to DOn.

[0205] In addition, when the calibration count exceeds the first threshold number, the control logic circuit 110 may calculate the correlation value between the data DO1 to DOn at a second number of times k2 greater than the first number of times k1.

[0206] In addition, the control logic circuit 110 may calibrate the sampling timing of at least some of the plurality of ADCs 120 based on the second cumulative correlation value, which is obtained by accumulating the correlation values calculated at the second number of times k2.

[0207] Referring to the above configuration, the control logic circuit 110 may use different numbers of bits to calculate the correlation value between the data DO1 to DOn depending on the number of calibration times for the sampling timing of the plurality of ADCs 120.

[0208] When the number of calibration times for the sampling timings of multiple ADCs 120 is less than or equal to a first threshold number, the control logic circuit 110 can use a relatively small number of bits to calculate the correlation value between DO1 to DOn as compared to when the number of calibration times exceeds the first threshold number.

[0209] In this way, the ADC circuit 100 according to an embodiment of the present disclosure can minimize the power consumed in the process of calculating the correlation value between data DO1 to DOn, thereby calibrating the sampling timings of at least some of the multiple ADCs 120.

[0210] In addition, the control logic circuit 110 can calculate the correlation value between data DO1 to DOn by accumulating the correlation value between data DO1 to DOn a different number of times depending on the number of calibration times for the sampling timings of multiple ADCs 120.

[0211] In this way, the ADC circuit 100 according to an embodiment of the present disclosure can minimize the time and / or power required in the process of calculating the correlation value between data DO1 to DOn, thereby calibrating the sampling timings of at least some of the multiple ADCs 120.

[0212] When the number of calibration times for the sampling timings of multiple ADCs 120 exceeds the first threshold number, the control logic circuit 110 can increase the number of bits used to calculate the correlation value between data DO1 to DOn.

[0213] In addition, when the number of calibration times for the sampling timings of multiple ADCs 120 exceeds the first threshold number, the control logic circuit 110 can increase the number of calculation times performed by accumulating the correlation value between data DO1 to DOn.

[0214] In this way, the ADC circuit 100 according to an embodiment of the present disclosure can improve the calibration accuracy of the sampling timings of multiple ADCs 120.

[0215] In addition, the ADC circuit 100 according to an embodiment of the present disclosure can minimize the time and power required to calculate the correlation value for calibrating at least some of the multiple ADCs 120 while maintaining the calibration accuracy of the multiple ADCs 120.

[0216] Figure 8A is a flowchart showing a method in which a control logic circuit according to an embodiment controls the phase of a clock signal along a calibration direction depending on the sign of a first accumulated correlation value. Figure 8B is a flowchart showing a method in which a control logic circuit according to an embodiment controls the phase of a clock signal by a calibration amount depending on the amount of a first accumulated correlation value.

[0217] Reference Figure 8A and Figure 8B According to the control logic circuit 110 of the embodiment, at least some of the plurality of clock signals CK can be controlled (or calibrated or adjusted) based on the first cumulative correlation value in terms of phase.

[0218] More specifically, with reference to Figure 8A at least some of the plurality of clock signals CK can be calibrated in terms of phase based on the sign of the first cumulative correlation value.

[0219] In operation S211, the control logic circuit 110 can determine the calibration direction for the phase of at least some of the plurality of clock signals CK based on the sign of the first cumulative correlation value.

[0220] For example, the control logic circuit 110 can determine the calibration direction for the phase of the first clock signal CK1 by using the sign of the cumulative correlation value between the first data DO1 and the other data DO2 to DOn.

[0221] For example, the control logic circuit 110 can determine whether to advance or delay the phase of the first clock signal CK1 based on the sign of the cumulative correlation value between the first data DO1 and the other data DO2 to DOn.

[0222] In operation S212, the control logic circuit 110 can calibrate the phase of at least some of the plurality of clock signals CK along the calibration direction determined by the sign of the first cumulative correlation value.

[0223] For example, the control logic circuit 110 can calibrate the phase of the first clock signal CK1 along the calibration direction determined by the sign of the cumulative correlation value between the first data DO1 and the other data DO2 to DOn.

[0224] In addition, with reference to Figure 8B the control logic circuit 110 can calibrate the phase of at least some of the plurality of clock signals CK based on the magnitude of the first cumulative correlation value.

[0225] In operation S221, the control logic circuit 110 can determine the calibration amount for the phase of at least some of the plurality of clock signals CK based on the magnitude of the first cumulative correlation value.

[0226] For example, the control logic circuit 110 can determine the calibration amount for the phase of the first clock signal CK1 based on the sign of the cumulative correlation value between the first data DO1 and the other data DO2 to DOn.

[0227] In operation S222, the control logic circuit 110 may calibrate the phases of at least some of the plurality of clock signals CK according to a calibration amount determined based on the amount of the first cumulative correlation value.

[0228] For example, the control logic circuit 110 may calibrate the phase of the first clock signal CK1 according to a calibration amount determined based on the amount of the cumulative correlation value between the first data DO1 and the other data DO2 to DOn.

[0229] Referring to the above configuration, the control logic circuit 110 according to an embodiment may calibrate the phases of at least some of the plurality of clock signals CK input to the plurality of ADCs 120 based on the cumulative correlation value calculated a specific number of times.

[0230] In this way, the control logic circuit 110 may calibrate the timing at which each of the plurality of ADCs 120 samples the input analog data AD.

[0231] In addition, the ADC circuit 100 according to an embodiment of the present disclosure may improve the accuracy of calibrating the sampling timing of the plurality of ADCs 120.

[0232] Figure 9 is a flowchart showing a method in which a control logic circuit according to an embodiment calibrates the sampling timing of at least some of the plurality of ADCs based on a third cumulative correlation value. Figure 10A is a diagram showing a first number of bits used by a control logic circuit according to an embodiment to calculate the correlation value between the data output from the ADCs. Figure 10B is a diagram showing a second number of bits used by a control logic circuit according to an embodiment to calculate the correlation value between the data output from the ADCs. Figure 10C is a diagram showing a third number of bits used by a control logic circuit according to an embodiment to calculate the correlation value between the data output from the ADCs.

[0233] Refer together Figures 9 to 10C , the control logic circuit 110 according to an embodiment may use different numbers of bits to calculate the correlation value between the data DO1 to DOn a different number of times depending on whether the number of calibration times for the sampling timing of the plurality of ADCs 120 exceeds a threshold number Tn1.

[0234] In operation S30, the control logic circuit 110 according to an embodiment may use a second number n2 of bits in each of the data DO1 to DOn output from the plurality of ADCs 120 to calculate the correlation value between the data DO1 to DOn.

[0235] The control logic circuit 110 can calculate the correlation value between the data DO1 to DOn using the second number n2 of bits in each of the data DO1 to DOn output from the multiple ADCs 120, where the second number n2 of bits is greater than the first number n1 of bits.

[0236] For example, referring to Figure 10A and Figure 10B , the control logic circuit 110 can calculate the correlation value between the first data DO1 and the second data DO2 using the second number n2 of bits in each of the first data DO1 and the second data DO2, where the second number n2 of bits is greater than the first number n1 of bits.

[0237] In this case, the second number n2 of bits can be some of the bits in each of the first data DO1 and the second data DO2 including the most significant bit (MSB).

[0238] In addition, the control logic circuit 110 can cumulatively calculate the correlation value between the data DO1 to DOn using the second number n2 of bits in each of the data DO1 to DOn output from the multiple ADCs 120 for the second number of times k2.

[0239] In this case, the second number of times k2 can be greater than the first number of times k1.

[0240] In this way, the control logic circuit 110 can generate a second cumulative correlation value that includes the correlation value between the data DO1 to DOn cumulatively calculated for the second number of times k2.

[0241] In operation S40, the control logic circuit 110 according to the embodiment can calibrate the sampling timing of at least some of the multiple ADCs 120 based on the second cumulative correlation value.

[0242] More specifically, the control logic circuit 110 can calibrate the phase of at least some of the multiple clock signals CK input to the multiple ADCs 120 based on the second cumulative correlation value.

[0243] For example, the control logic circuit 110 can calibrate the phase of at least some of the multiple clock signals CK input to the multiple ADCs 120 based on the calibration direction identified by the sign of the second cumulative correlation value.

[0244] In addition, the control logic circuit 110 can calibrate the phase of at least some of the clock signals CK input to the multiple ADCs 120 according to the calibration amount determined based on the second cumulative correlation value.

[0245] In this way, the control logic circuit 110 can control the timing at which each of the plurality of ADCs 120 samples the analog data AD.

[0246] In addition, in operation S41, the control logic circuit 110 according to the embodiment can increment a calibration count.

[0247] More specifically, the control logic circuit 110 can increment the calibration count in response to calibrating the sampling timing of at least some of the plurality of ADCs 120 based on a second cumulative correlation value.

[0248] For example, the control logic circuit 110 can increment the calibration count by "1" in response to calibrating the sampling timing of at least some of the plurality of ADCs 120.

[0249] In this case, the calibration count can be referred to as the number of times the control logic circuit 110 calibrates the sampling timing of at least some of the plurality of ADCs 120.

[0250] In operation S43, the control logic circuit 110 according to the embodiment can determine whether the calibration count exceeds a second threshold number.

[0251] More specifically, the control logic circuit 110 can determine whether the calibration count exceeds a second threshold number that is greater than the first threshold number.

[0252] In operation S50, the control logic circuit 110 can calculate a correlation value between the data DO1 to DOn output from the plurality of ADCs 120 using a third number n3 of bits in each of the data DO1 to DOn a third number of times k3.

[0253] More specifically, when the calibration count exceeds the second threshold number, the control logic circuit 110 can calculate a correlation value between the data DO1 to DOn using a third number n3 of bits in each of the data DO1 to DOn a third number of times k3.

[0254] According to the embodiment, the control logic circuit 110 can calculate a correlation value between the data DO1 to DOn using a third number n3 of bits in each of the data DO1 to DOn output from the plurality of ADCs 120, where the third number n3 of bits is greater than the second number n2 of bits.

[0255] For example, referring to Figure 10C , the control logic circuit 110 can calculate a correlation value between the first data DO1 and the second data DO2 using a third number n3 of bits in each of the first data DO1 and the second data DO2, where the third number n3 of bits is greater than the second number n2 of bits.

[0256] In addition, for example, each of the data DO1 to DOn output from the plurality of ADCs 120 may be output in a third number n3 of bits.

[0257] Specifically, the control logic circuit 110 may calculate the correlation value between the data DO1 to DOn using all the bits in each of the data DO1 to DOn output from the plurality of ADCs 120.

[0258] In addition, the control logic circuit 110 may calculate the correlation value between the data DO1 to DOn output from the plurality of ADCs 120 a third number of times k3.

[0259] In this case, the third number of times k3 may be greater than the second number of times k2.

[0260] In this way, the control logic circuit 110 may generate a third cumulative correlation value that includes the correlation values between the data DO1 to DOn calculated a third number of times k3.

[0261] In operation S60, the control logic circuit 110 according to an embodiment may calibrate the sampling timing of at least some of the plurality of ADCs 120 based on the third cumulative correlation value.

[0262] More specifically, the control logic circuit 110 may calibrate the phase of at least some of the plurality of clock signals CK input to the plurality of ADCs 120 based on the third cumulative correlation value.

[0263] For example, the control logic circuit 110 may calibrate the phase of at least some of the plurality of clock signals CK input to the plurality of ADCs 120 based on the calibration direction identified by the sign of the third cumulative correlation value.

[0264] In addition, the control logic circuit 110 may calibrate the phase of at least some of the clock signals CK input to the plurality of ADCs 120 according to the calibration amount determined based on the third cumulative correlation value.

[0265] In this way, the control logic circuit 110 may control the sampling timing of each of the plurality of ADCs 120 to sample the analog data AD.

[0266] Referring to the above configuration, the control logic circuit 110 may calibrate the sampling timing of the plurality of ADCs 120 a specific number of times while calculating the correlation value between the data DO1 to DOn using a relatively small number of bits.

[0267] In this way, the ADC circuit 100 can minimize the power consumed during the process of calculating the correlation values between the calculated data DO1 to DOn, thereby calibrating the sampling timing of at least some of the multiple ADCs 120.

[0268] In addition, the control logic circuit 110 can calculate the correlation values between the data DO1 to DOn a relatively small number of times while calibrating the sampling timing of the multiple ADCs 120 a specific number of times.

[0269] In this way, the ADC circuit 100 can minimize the time and / or power required during the process of calculating the correlation values between the data DO1 to DOn, thereby calibrating the sampling timing of at least some of the multiple ADCs 120.

[0270] In addition, the control logic circuit 110 can increase the number of bits used to calculate the correlation values between the data DO1 to DOn.

[0271] In addition, the control logic circuit 110 can increase the number of times of calculating the correlation values between the data DO1 to DOn.

[0272] In addition, the control logic circuit 110 can calibrate the sampling timing of at least some of the multiple ADCs 120 based on the cumulative correlation value, which is obtained by accumulating the correlation values calculated a increased number of times using an increased number of bits.

[0273] In this way, the ADC circuit 100 according to the embodiments of the present disclosure can improve the calibration accuracy of the sampling timing for the multiple ADCs 120.

[0274] In addition, the ADC circuit 100 according to the embodiments of the present disclosure can minimize the time and / or power required to calculate the correlation values for calibrating at least some of the multiple ADCs 120 while maintaining the calibration accuracy for the multiple ADCs 120.

[0275] Figure 11 is a block diagram showing an electronic device including an antenna and an ADC circuit according to an embodiment.

[0276] Referring to Figure 11 , the electronic device 10 may include an ADC circuit 100C and an antenna 1110.

[0277] In this case, Figure 11 the ADC circuit 100C shown in Figure 1 is an example of the ADC circuit 100 shown in

[0278] More specifically, the electronic device 10 may include an ADC circuit 100C configured to convert analog data AD into digital data DO.

[0279] According to an embodiment, the electronic device 10 may include an antenna 1110 that receives a radio frequency (RF) signal and transmits the analog data AD to the ADC circuit 100C.

[0280] In addition, the electronic device 10 may include an analog front end (AFE) that receives an RF signal of a predetermined frequency and converts the RF signal into analog data AD. In this case, the AFE may be disposed between the antenna 1110 and the ADC circuit 100C.

[0281] According to an embodiment, the antenna 1110 may receive an RF signal transmitted from an external source and may transmit the analog data AD generated according to the RF signal to the ADC circuit 100C.

[0282] According to another embodiment, the antenna 1110 may convert an analog signal transmitted from the ADC circuit into an RF signal having a specified frequency and transmit it to the outside.

[0283] According to an embodiment, the ADC circuit 100C may convert the analog data AD received through the antenna 1110 into digital data DO to be output.

[0284] More specifically, the control logic circuit 110 may control a plurality of ADCs 120 to convert the analog data AD received through the antenna 1110 into digital data DO to be output.

[0285] In this case, each ADC of the plurality of ADCs 120 may sample the analog data AD received from the outside based on clock signals having different phases, enabling it to be output as digital data DO.

[0286] Therefore, the plurality of ADCs 120 may be referred to as time-interleaved (TI) ADCs. In addition, each ADC of the plurality of ADCs 120 (e.g., ADC1 to ADCn) may be referred to as a sub-ADC.

[0287] In addition, according to an embodiment, the control logic circuit 110 may calibrate the sampling timing of at least some of the plurality of ADCs 120 based on the digital data DO output from the plurality of ADCs 120.

[0288] More specifically, the control logic circuit 110 may calculate a correlation value between the data DO1 to DOn output from the plurality of ADCs 120 based on the digital data DO output from the plurality of ADCs 120.

[0289] In addition, the control logic circuit 110 may calibrate the sampling timing of at least some of the plurality of ADCs 120 based on the calculated correlation value.

[0290] In addition, the control logic circuit 110 may increment a calibration count in response to calibrating the sampling timing of at least some of the plurality of ADCs 120. In this case, the calibration count may be the number of times the control logic circuit 110 calibrates the sampling timing of at least some of the plurality of ADCs 120.

[0291] According to an embodiment, when the calibration count is less than or equal to a threshold number Tn1, the control logic circuit 110 may calculate a correlation value between the data DO1 to DOn using a first number n1 of bits in each of the data DO1 to DOn.

[0292] In this case, the first number n1 of bits may be a number less than the number of bits in each of the data DO1 to DOn.

[0293] In addition, the control logic circuit 110 may calculate a correlation value between the data using a first number n1 of bits starting from the most significant bit (MSB) in each of the data DO1 to DOn.

[0294] Specifically, when the number of calibration times for at least some of the plurality of ADCs 120 is less than or equal to the threshold number Tn1, the control logic circuit 110 may calculate a correlation value between the data DO1 to DOn using some bits including the most significant bit (MSB) in each of the data DO1 to DOn.

[0295] In addition, when the calibration count is less than or equal to the threshold number Tn1, the control logic circuit 110 may calculate a correlation value between the data DO1 to DOn at a first number of times k1.

[0296] In addition, the control logic circuit 110 may calibrate the sampling timing of at least some of the plurality of ADCs 120 based on a first cumulative correlation value, where the correlation values calculated at the first number of times k1 are accumulated.

[0297] Conversely, when the calibration count exceeds the threshold number Tn1, the control logic circuit 110 may calculate a correlation value between DO1 to DOn using a second number n2 of bits in each of the data DO1 to DOn, where the second number n2 of bits is greater than the first number n1 of bits.

[0298] In addition, when the calibration count exceeds the threshold number Tn1, the control logic circuit 110 may calculate a correlation value between the data DO1 to DOn at a second number of times k2 greater than the first number of times k1.

[0299] In addition, the control logic circuit 110 may calibrate the sampling timing of at least some of the plurality of ADCs 120 based on the second cumulative correlation value, where the correlation value calculated at the second number k2 is accumulated.

[0300] Referring to the above configuration, when the calibration count is less than or equal to the threshold number Tn1, compared with the case where the calibration count exceeds the threshold number Tn1, the control logic circuit 110 may use a relatively small number of bits to calculate the correlation value between the data DO1 to DOn.

[0301] Thus, the ADC circuit 100 according to an embodiment of the present disclosure may minimize the power consumed in the process of calculating the correlation value between the data DO1 to DOn, thereby calibrating the sampling timing of at least some of the plurality of ADCs 120.

[0302] In addition, when the calibration count is less than or equal to the threshold number Tn1, compared with when the calibration count exceeds the threshold number Tn1, the control logic circuit 110 may calculate the correlation value between the data DO1 to DOn a relatively small number of times.

[0303] Thus, the ADC circuit 100 according to an embodiment of the present disclosure may minimize the time and / or power required in the process of calculating the correlation value between the data DO1 to DOn, thereby calibrating the sampling timing of at least some of the plurality of ADCs 120.

[0304] In addition, when the calibration count exceeds the threshold number Tn1, the control logic circuit 110 may increase the number of bits used to calculate the correlation value between the data DO1 to DOn and / or the number of calculations performed by accumulating the correlation value between the data DO1 to DOn.

[0305] In addition, the control logic circuit 110 may calibrate the sampling timing of at least some of the plurality of ADCs 120 based on the second cumulative correlation value, where the correlation value calculated at an increased number of times is accumulated using an increased number of bits.

[0306] Thus, the ADC circuit 100 according to an embodiment of the present disclosure may improve the calibration accuracy of the sampling timing for the plurality of ADCs 120.

[0307] In addition, the ADC circuit 100 may minimize the time and power required to calculate the correlation value for calibrating at least some of the plurality of ADCs 120 while maintaining the calibration accuracy for the plurality of ADCs 120.

[0308] Figure 12 is a block diagram showing an Internet of Things (IoT) device including an ADC circuit according to an embodiment.

[0309] Referring to Figure 12 , IoT can refer to a network between things using wired and / or wireless communication. IoT devices can include accessible wired or / and wireless interfaces and can include devices that communicate with at least one or more other devices via a wired or / and wireless interface to send or receive data. The accessible interfaces included in IoT devices can include a modem communication interface that can access a local area network (LAN), a wireless local area network (WLAN) (such as Wi-Fi), a wireless personal area network (WPAN) (such as Bluetooth, wireless universal serial bus (USB), Zigbee, near field communication (NFC), radio frequency identification (RFID)), power line communication (PLC), or a mobile cellular network (such as 3G, Long Term Evolution (LTE), 4G, or 5G). The Bluetooth interface can support Bluetooth Low Energy (BLE).

[0310] Specifically, the IoT device 1200 can include a communication interface 1220 for communicating with the outside. The communication interface 1220 can be, for example, a modem communication interface that can access a local area network (LAN), a wireless local area network communication interface (such as Bluetooth, Wi-Fi, or Zigbee), or a mobile communication network (such as PLC, 3G, LTE, 4G, or 5G).

[0311] The communication interface 1220 can include a transmitter and a receiver. In this case, Figure 12 the communication interface 1220 shown in Figure 11 can include the antenna 1110 in

[0312] The IoT device 1200 can send and / or receive information from an access point or gateway via the antenna 1110. In addition, the IoT device 1200 can communicate with a user device or any other IoT device to send and / or receive control information or data of the IoT device 1200.

[0313] The IoT device 1200 can include a processor 1210 for performing calculations. In this case, Figure 12 the processor 1210 shown in Figure 1 or Figure 11 can have the same or a similar configuration as the control logic circuit 110 shown in

[0314] According to an embodiment, the processor 1210 can control a plurality of ADCs 120 included in the ADC circuit 100 to convert the analog data AD into digital data DO to be output.

[0315] In this case, the processor 1210 may calculate the correlation values between the data DO1 to DOn using different numbers of bits depending on the number of calibration times of the sampling timing for at least some of the plurality of ADCs 120.

[0316] In addition, the processor 1210 may calculate the correlation values between the data DO1 to DOn a different number of times depending on the number of calibration times of the sampling timing for at least some of the plurality of ADCs 120.

[0317] In addition, the processor 1210 may calibrate the sampling timing of at least some of the plurality of ADCs 120 based on the cumulative correlation value including the calculated correlation values.

[0318] In this way, the processor 1210 (or the ADC circuit 100) may minimize the time and power required to calculate the correlation values for calibrating at least some of the plurality of ADCs 120.

[0319] The IoT device 1200 may have a built-in battery to provide internal power, or may also include a power supply unit that receives power from an external source. In addition, the IoT device 1200 may include a display 1240 for displaying the internal state or data. The user may control the IoT device 1200 through a user interface (UI) of the display 1240 of the IoT device 1200.

[0320] The memory 1230 may store control instruction codes, control data, or user data for controlling the IoT device 1200. The memory 1230 may include at least one of a volatile memory and a non-volatile memory. The non-volatile memory may include at least one of various memories, such as read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase change random access memory (RAM) (PRAM), magnetic RAM (MRAM), resistive RAM (ReRAM), and ferroelectric RAM (FRAM). The volatile memory may include at least one of various memories, such as dynamic RAM (DRAM), static RAM (SRAM), and synchronous DRAM (SDRAM).

[0321] The IoT device 1200 may also include a storage device. The storage device may include at least one of non-volatile media, such as a hard disk drive (HDD), a solid state drive (SSD), an embedded multimedia card (eMMC), and a universal flash storage (USF). The storage device may store user information provided through the input / output (I / O) unit 1250 and sensed information collected through the sensor 1260.

[0322] Figure 13 is a block diagram showing a mobile terminal applying an ADC circuit according to an embodiment.

[0323] Referring to Figure 13 , the mobile terminal 1000 may include a processor 1300, a memory 1400, a display 1500, and a radio frequency module (RF module) 1510. In addition, the mobile terminal 1000 may further include various components such as a lens, a sensor, and an audio module.

[0324] The processor 1300 may be implemented as a system on a chip (SoC), and may include a central processing unit (CPU) 1310, a RAM 1320, a power management unit (PMU) 1330, a memory interface 1340, a display controller (DCON) 1350, a MODEM 1360, and a bus 1370. In addition, the processor 1300 may further include various intellectual properties. Since the function of a MODEM chip can be integrated in the processor 1300, it may be referred to as a "ModAP".

[0325] In this case, Figure 13 the illustrated processor 1300 may have the same or a similar configuration as Figure 1 or Figure 11 the control logic circuit 110 shown.

[0326] The CPU 1310 may control the overall operations of the processor 1300 and the mobile terminal 1000. The CPU 1310 may control the operations of each component of the processor 1300. In addition, the CPU 1310 may be implemented with multiple cores. A multi-core may be a computing component having two or more independent cores.

[0327] The RAM 1320 may temporarily store programs, data, or instructions. For example, the programs and / or data stored in the memory 1400 may be temporarily stored in the RAM 1320 under the control of the CPU 1310 or according to the boot code. The RAM 1320 may be implemented with DRAM or SRAM.

[0328] The PMU 1330 may manage the power of each component of the processor 1300. The PMU 1330 may also determine the operating conditions of each component of the processor 1300 and control its operations.

[0329] The memory interface 1340 may control the overall operations of the memory 1400 and control the data exchange between the memory 1400 and each component of the processor 1300. According to the request of the CPU 1310, the memory interface 1340 may write data to the memory 1400 or may read data from the memory 1400.

[0330] The display controller 1350 may provide image data to the display 1500 for display thereon. The display 1500 may be implemented as a flat panel display (such as a liquid crystal display (LCD) or an organic light emitting diode (OLED)) or a flexible display.

[0331] For wireless communication, the MODEM 1360 may modulate data to be transmitted to suit the wireless environment and may recover received data. The MODEM 1360 may perform digital communication with the RF module 1510.

[0332] Specifically, the MODEM 1360 may include Figure 1 the ADC circuit 100 shown in

[0333] Accordingly, the MODEM 1360 may use a plurality of ADCs 120 to convert the analog data AD of the RF signal received from the RF module 1510 into digital data DO to be output.

[0334] The RF module 1510 may convert a high-frequency signal received through an antenna into a low-frequency signal and may transmit the converted low-frequency signal to the MODEM 1360. In addition, the RF module 1510 may convert the low-frequency signal received from the MODEM 1360 into a high-frequency signal and may transmit the converted high-frequency signal to the outside of the mobile terminal 1000 through the antenna. The RF module 1510 may amplify or filter the signal.

[0335] In this case, Figure 13 the RF module 1510 shown in Figure 11 may include the antenna 1110 shown in

[0336] According to an embodiment, the processor 1300 may calculate the correlation values between the data DO1 to DOn using different numbers of bits depending on the number of calibration times of the sampling timing of at least some of the plurality of ADCs 120 included in the MODEM 1360.

[0337] In addition, the processor 1300 may accumulate the calculation of the correlation values between the data DO1 to DOn different numbers of times depending on the number of calibration times of the sampling timing of at least some of the plurality of ADCs 120.

[0338] In this way, the processor 1300 may minimize the time and power required to calculate the correlation values for calibrating at least some of the plurality of ADCs 120 while maintaining the calibration accuracy for the plurality of ADCs 120.

[0339] As described above, when the calibration count is less than or equal to the threshold number Tn1, compared with when the calibration count exceeds the threshold number Tn1, the control logic circuit 110 according to an embodiment of the present disclosure may use a relatively small number of bits in each data to calculate the correlation value between the data DO1 to DOn.

[0340] In this way, the ADC circuit 100 according to an embodiment of the present disclosure may minimize the power consumed in the process of calculating the correlation value between the data DO1 to DOn, thereby calibrating the sampling timing of at least some of the plurality of ADCs 120.

[0341] In addition, when the calibration count is less than or equal to the threshold number Tn1, compared with when the calibration count exceeds the threshold number Tn1, the control logic circuit 110 may calculate the correlation value between the data DO1 to DOn by accumulating a relatively small number of times.

[0342] Therefore, when the calibration count is less than or equal to the threshold number Tn1, compared with when the calibration count exceeds the threshold number Tn1, the control logic circuit 110 may calculate the correlation value between the data DO1 to DOn at a relatively fast rate.

[0343] In this way, the ADC circuit 100 according to an embodiment of the present disclosure may minimize the time and / or power required in the process of calculating the correlation value between the data DO1 to DOn, thereby calibrating the sampling timing of at least some of the plurality of ADCs 120.

[0344] On the contrary, when the calibration count exceeds the threshold number Tn1, the control logic circuit 110 may increase the number of bits used to calculate the correlation value between the data DO1 to DOn.

[0345] In addition, when the calibration count exceeds the threshold number Tn1, the control logic circuit 110 may increase the number of calculation times performed by accumulating the correlation value between the data DO1 to DOn.

[0346] In addition, the control logic circuit 110 may calibrate the sampling timing of at least some of the plurality of ADCs 120 based on the accumulated correlation value, where the correlation value calculated by increasing the number of times is accumulated using an increased number of bits.

[0347] In this way, the ADC circuit 100 according to an embodiment of the present disclosure may improve the calibration accuracy of the sampling timing for the plurality of ADCs 120.

[0348] Specifically, the control logic circuit 110 may use different numbers of bits to calculate the correlation value between the data DO1 to DOn depending on the number of calibration times of the sampling timing of at least some of the plurality of ADCs 120.

[0349] In addition, the control logic circuit 110 can calculate the correlation value between the data DO1 to DOn by accumulating the correlation value between the data DO1 to DOn a different number of times depending on the number of calibration times for the sampling timing of at least some of the plurality of ADCs 120.

[0350] In this way, the ADC circuit 100 can minimize the time and power required to calculate the correlation value for calibrating the sampling timing of the plurality of ADCs 120 while maintaining the calibration accuracy of the sampling timing of the plurality of ADCs 120.

[0351] According to an embodiment of the present disclosure, the ADC circuit can minimize the power and time required to calibrate the sampling timing of a plurality of ADCs.

[0352] Although the present disclosure has been described with reference to embodiments of the present disclosure, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. An analog-to-digital converter (ADC) circuit, the ADC circuit comprising: A plurality of ADCs configured to perform conversion operations in a time-interleaved manner; as well as A control logic circuit is connected to the plurality of ADCs, wherein the control logic circuit is configured to: calculating a correlation value between the data output from the plurality of ADCs using a first number of bits in each of the data; calibrating sampling timings of at least some of the plurality of ADCs based on a first cumulative correlation value obtained by accumulating correlation values ​​calculated the first number of times; calculating a correlation value between the data with a second number of times by using a second number of bits in each of the data, wherein the second number of times is greater than the first number of times and the second number of bits is greater than the first number of bits; and The sampling timings of the at least some of the plurality of ADCs are calibrated based on a second cumulative correlation value obtained by accumulating the correlation values ​​calculated the second number of times.

2. The ADC circuit according to claim 1, wherein: The control logic circuit is configured to: In response to calibrating the sampling timing of the at least some ADCs based on the first accumulated correlation value, incrementing a calibration count; as well as In response to the calibration count exceeding a first threshold number, a correlation value between the data is calculated the second number of times using the second number of bits in each of the data.

3. The ADC circuit according to claim 1, further comprising: A clock generation circuit configured to generate a reference clock signal; as well as a delay circuit configured to control the phase of the reference clock signal and send a plurality of clock signals having different phases to each of the plurality of ADCs, and The control logic circuit controls the phases of at least some of the multiple clock signals along a calibration direction based on the sign of the first accumulated correlation value through the delay circuit to calibrate the sampling timing of at least some of the multiple ADCs.

4. The ADC circuit according to claim 3, wherein: The control logic circuit calibrates the phases of the at least some of the plurality of clock signals in a calibration direction based on the sign of the second accumulated correlation value through the delay circuit to calibrate sampling timings of the at least some of the plurality of ADCs.

5. The ADC circuit according to claim 3, wherein: The control logic circuit calibrates the phases of the at least some of the plurality of clock signals by the delay circuit by a calibration amount based on an amount of the first accumulated correlation value to calibrate sampling timings of the at least some of the plurality of ADCs.

6. The ADC circuit according to claim 1, wherein: The control logic circuit calculates the correlation value between the data the first number of times using the first number of bits starting from the most significant bit MSB in each of the data.

7. The ADC circuit according to claim 1, wherein: Each of the plurality of ADCs performs a conversion operation on an analog input in the time-interleaved manner to output digital data comprising the second number of bits.

8. The ADC circuit according to claim 2, wherein: The control logic circuit is configured to: In response to calibrating the sampling timing of the at least some ADCs based on the second accumulated correlation value, incrementing the calibration count; and In response to the calibration count exceeding a second threshold number that is greater than the first threshold number, a correlation value between the data is calculated using a third number of bits in each of the data as a third number, wherein the third number is greater than the second number and the third number of bits is greater than the second number of bits.

9. The ADC circuit according to claim 8, wherein: The control logic circuit calibrates sampling timings of the at least some of the plurality of ADCs based on a third cumulative correlation value obtained by accumulating correlation values ​​calculated at the third accumulative value.

10. The ADC circuit according to claim 1, further comprising: a multiplexer configured to output some of the data, and Wherein, the control logic circuit controls the multiplexer to output the data sequentially.

11. A method for controlling an analog-to-digital converter (ADC) circuit, the method comprising: calculating a correlation value between the data output from the plurality of ADCs using a first number of bits in each of the data; calibrating sampling timings of at least some of the plurality of ADCs based on a first cumulative correlation value obtained by accumulating correlation values ​​calculated the first number of times; Calculating a correlation value between the data using a second number of bits in each of the data with a second number of times, wherein the second number of times is greater than the first number of times, and the second number of bits is greater than the first number of bits; as well as The sampling timings of the at least some of the plurality of ADCs are calibrated based on a second cumulative correlation value obtained by accumulating the correlation values ​​calculated the second number of times.

12. The method according to claim 11, further comprising: In response to calibrating the sampling timing of the at least some ADCs based on the first accumulated correlation value, incrementing a calibration count; as well as In response to the calibration count exceeding a first threshold number, a correlation value between the data is calculated the second number of times using the second number of bits in each of the data.

13. The method according to claim 11, wherein: Calibrating the sampling timing of at least some of the plurality of ADCs based on the first accumulated correlation value comprises: determining a calibration direction for sampling timing of the at least some of the plurality of ADCs based on a sign of the first accumulated correlation value; and Phases of at least some of a plurality of clock signals input to the plurality of ADCs are controlled along the calibration direction.

14. The method according to claim 13, wherein: Calibrating the sampling timing of at least some of the plurality of ADCs based on the first accumulated correlation value comprises: determining an amount of calibration for sampling timing of the at least some of the plurality of ADCs based on the amount of the first accumulated correlation values; and The phases of the at least some of the plurality of clock signals are controlled according to the calibration amount.

15. The method according to claim 11, wherein: Calculating the correlation value between the data using the first number of bits in each of the data includes calculating the correlation value between the data the first number of times by using the first number of bits starting from a most significant bit MSB among the bits of the data.

16. An electronic device for sending and receiving radio frequency (RF) signals, the electronic device comprising: an antenna configured to receive the RF signal; as well as an analog-to-digital converter (ADC) circuit configured to convert the RF signal into a digital signal, Wherein, the ADC circuit comprises: The first ADC and the second ADC perform conversion operations in a time-interleaved manner, and a control logic circuit connected to the first ADC and the second ADC, Wherein, the control logic circuit is configured as follows: calculating a correlation value between the first data output from the first ADC and the second data output from the second ADC using a first number of bits in each of the first data output from the first ADC and the second data; calibrating sampling timing of at least some of the first ADC and the second ADC based on first accumulated correlation values ​​including the calculated correlation value; calculating a correlation value between the first data and the second data using a second number of bits in each of the first data and the second data, wherein the second number of bits is greater than the first number of bits; and Sampling timings of the at least some of the first ADC and the second ADC are calibrated based on second accumulated correlation values ​​including the calculated correlation values.

17. The electronic device according to claim 16, wherein: The control logic circuit is configured to: In response to calibrating sampling timing of the at least some of the first ADC and the second ADC based on the first accumulated correlation value, incrementing a calibration count; as well as In response to the calibration count exceeding a first threshold number, a correlation value between the first data and the second data is calculated using the second number of bits in each of the first data and the second data.

18. The electronic device according to claim 16, further comprising: A clock generation circuit configured to generate a reference clock signal; as well as a delay circuit configured to control the phase of the reference clock signal and send a clock signal having a different phase to each of the first ADC and the second ADC, and The control logic circuit controls the phases of at least some of the clock signals along a calibration direction based on the sign of the first accumulated correlation value through the delay circuit to calibrate the sampling timing of at least some of the first ADC and the second ADC.

19. The electronic device according to claim 16, wherein: The control logic circuit accumulates and calculates a correlation value between the first data and the second data in a first order using the first number of bits in each of the first data and the second data, and The first cumulative correlation value is obtained by accumulating a plurality of correlation values ​​calculated the first number of times.

20. The electronic device according to claim 19, wherein: The control logic circuit accumulates and calculates a correlation value between the first data and the second data a second number of times greater than the first number of times using the second number of bits in each of the first data and the second data, and The second cumulative correlation value is obtained by accumulating a plurality of correlation values ​​calculated the second number of times.

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