High-temperature ohmic GaN HEMT vertical structure chip and preparation method thereof

Abstract

The invention discloses a high-temperature ohmic GaN HEMT vertical structure chip and a preparation method thereof, and belongs to the technical field of high-temperature ohmic contact preparation, and the method comprises the steps: firstly carrying out the pretreatment of a substrate, and sequentially growing a GaN drift region, a channel layer, an AlN insertion layer, an AlXGa (1-X) N barrier layer and a SiN dielectric cap layer, and forming a GaN HEMT vertical structure epitaxial wafer; and then, preparing a mark through photoetching and evaporation processes, photoetching a source electrode window region and forming ohmic contact, performing ion implantation to form a chip isolation region, and photoetching a gate electrode. Then, growing a passivation layer, etching out the field plate, performing deep etching trepanning on the epitaxial wafer, photoetching out a drain electrode, and growing a bottom passivation layer; and finally, photoetching a gate electrode and a source electrode leading-out region to obtain the high-temperature ohmic GaN HEMT vertical structure chip. The prepared chip has excellent electrical properties and high-temperature reliability, is suitable for high-frequency, high-power and other application scenes, and provides a new technical approach for development and application of GaN-based power devices.

Description

Technical Field

[0001] The present invention belongs to the technical field of high-temperature ohmic contact preparation, and particularly relates to a high-temperature ohmic GaN HEMT vertical structure chip and a preparation method thereof. Background Art

[0002] With the continuous progress of information technology, especially the rapid development of fields such as 5G communication, Internet of Things, and new energy vehicles, the demand for high-performance and high-reliability semiconductor power devices is increasing day by day. As a wide-bandgap semiconductor material, GaN shows great potential in the preparation of high-efficiency and high-power-density semiconductor devices. High-temperature ohmic contact technology, as one of the key technologies to achieve high performance of GaN HEMT devices, is of great significance for improving the conductivity and stability of devices.

[0003] High-temperature ohmic contact technology realizes low-resistance and high-efficiency current transmission by forming a good contact between metal and semiconductor under high-temperature conditions. At present, certain progress has been made in the research on high-temperature ohmic GaN HEMT vertical structure chips, including optimizing the metallization layer material, improving the deposition process, and exploring high-temperature annealing conditions, etc. These researches aim to improve the conductivity, thermal stability, and reliability of devices.

[0004] Although certain achievements have been made in the research on high-temperature ohmic GaN HEMT vertical structure chips, there are still some challenges. The reaction activity between metal and semiconductor under high-temperature conditions is relatively high, which easily leads to interface reaction and diffusion, thus affecting the performance and stability of devices. In addition, high-temperature ohmic contact technology has strict requirements for process condition control, and parameters such as temperature, time, and atmosphere need to be precisely controlled to ensure the consistency and reliability of devices. Summary of the Invention

[0005] In order to overcome the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a high-temperature ohmic GaN HEMT vertical structure chip and a preparation method thereof, so as to solve the technical problem of how to effectively cope with the interface reaction and diffusion caused by the high reaction activity between metal and semiconductor under high-temperature conditions.

[0006] In order to achieve the above purpose, the present invention adopts the following technical solutions: The present invention discloses a preparation method of a high-temperature ohmic GaN HEMT vertical structure chip, including the following steps: 1) After pre-treating the substrate, successively carry out GaN drift region growth, ion implantation, channel layer growth, AlN insertion layer growth, Al X Ga (1-X) N barrier layer growth and SiN dielectric cap layer growth to obtain a GaN HEMT vertical structure epitaxial wafer; wherein, AlX Ga (1-X) In the GaN barrier layer, X is 0.2 to 0.25; 2) Clean the GaN HEMT vertical structure epitaxial wafer, and after drying, prepare markings; 3) Photolithograph the window area of the source electrode at the top, with a photolithography angle of 55 - 65°, and remove the SiN dielectric capping layer in the window area; 4) Photolithograph the electrode contact area of the source electrode at the top, evaporate the electrode metal, and after stripping, form the source electrode; after rapid thermal annealing treatment at 780 - 820 °C, an ohmic contact is formed in the source area; 5) Form a chip isolation area at the top through photolithography and ion implantation; 6) Photolithograph the electrode contact area of the gate electrode at the top, evaporate the electrode metal, and after stripping, form the gate electrode; 7) Grow a passivation layer at the top by plasma-enhanced chemical vapor deposition, etch out the conductive channels of the source and the gate, and obtain a field plate; 8) Perform deep etching and opening on the GaN HEMT vertical structure epitaxial wafer; 9) Photolithograph the electrode contact area of the drain electrode at the bottom, with a photolithography angle of 55 - 65°, evaporate the electrode metal, and after stripping, form the drain electrode; 10) Grow a passivation layer at the bottom, and photolithograph the drain electrode lead-out area; 11) Photolithograph the gate electrode and the source electrode lead-out areas at the top to obtain a high-temperature ohmic GaN HEMT vertical structure chip.

[0007] Preferably, in step 1), an n-type doped GaN with a thickness of 300 - 1000 μm is selected as the substrate; the pretreatment conditions of the substrate include: pretreating the GaN substrate at 1000 - 1150 °C, while introducing N2 at a rate of 0 - 100 L / min, H2 at a rate of 50 - 200 L / min, and NH3 at a rate of 1 - 100 L / min.

[0008] Preferably, the growth conditions of the GaN drift region in step 1) include: at 1000 - 1150 °C and a growth pressure of 200 torr, by controlling the flow rates of trimethylgallium, N2, H2, NH3, and monosilane, grow a GaN drift region with a thickness of 0.5 - 50 μm, the growth temperature is 1000 - 1150 °C, and the growth rotation speed is 800 - 1200 rpm; among them, the flow rate of trimethylgallium is 200 - 1000 sccm / min, the flow rate of N2 is 0 - 100 L / min, the flow rate of H2 is 50 - 200 L / min, the flow rate of NH3 is 1 - 100 L / min, and the flow rate of monosilane is 0 - 500 sccm / min.

[0009] Preferably, in step 1), the temperature for growing the channel layer is 1000 - 1150 °C, the rotation speed is 800 - 1200 rpm, the growth pressure is 200 torr, and trimethylgallium, N2, H2, and NH3 are simultaneously introduced to grow undoped GaN with a thickness controlled within 150 - 400 nm. Among them, the introduction rate of trimethylgallium is 200 - 1000 sccm / min, the introduction rate of N2 is 0 - 100 L / min, the introduction rate of H2 is 0 - 200 L / min, and the introduction rate of NH3 is 0 - 100 L / min.

[0010] Preferably, in step 1), the conditions for growing the AlN insertion layer include: at a temperature of 800 - 1100 °C and a growth pressure of 75 torr, trimethylaluminum, H2, and NH3 are simultaneously introduced to grow an extremely thin AlN insertion layer with a thickness of 0 - 2 nm; among them, the introduction rate of trimethylaluminum is 0 - 500 sccm / min, the introduction rate of H2 is 50 - 200 L / min, and the introduction rate of NH3 is 1 - 100 L / min.

[0011] Preferably, in step 1), Al X Ga (1-X) The conditions for growing the N barrier layer include: at a temperature of 800 - 1100 °C, a rotation speed of 800 - 1200 rpm, and a growth pressure of 100 torr, by adjusting the flow rates of trimethylgallium, trimethylaluminum, N2, H2, and NH3, an Al X Ga (1-X) N barrier layer with a thickness of 15 - 35 nm is grown; among them, the molar percentage of X is 20% - 25%, the introduction rate of trimethylgallium is 0 - 500 sccm / min, the introduction rate of trimethylaluminum is 50 - 500 sccm / min, the introduction rate of N2 is 0 - 100 L / min, the introduction rate of H2 is 50 - 200 L / min, and the introduction rate of NH3 is 1 - 100 L / min.

[0012] Preferably, in step 1), the conditions for growing the SiN dielectric cap layer include: at a temperature of 700 - 1100 °C and a growth pressure of 200 torr, by adjusting the flow rates of N2, H2, and NH3 and introducing disilane, a SiN dielectric cap layer with a thickness of 0.1 - 100 nm is grown; among them, the introduction rate of N2 is 0 - 100 L / min, the introduction rate of H2 is 50 - 200 L / min, the introduction rate of NH3 is 1 - 100 L / min, the concentration of disilane is 2%, and the introduction rate of disilane is 0 - 500 sccm / min.

[0013] Preferably, in step 3), the depth of the window region of the source electrode is below the two-dimensional electron gas; an inductively coupled plasma etching is used to remove the SiN dielectric capping layer in the window region; In step 4), after soaking in a strong oxidation solution tank before evaporation coating, then soak in dilute hydrochloric acid; the source electrode is an electrode metal composed of at least one of Ti, Al, Ni, TiN, and AlSi; In step 5), the elements for ion implantation include: at least one of F, Ar, B, and N; the depth of ion implantation is 0.1 - 20 μm.

[0014] Preferably, in step 6), the gate electrode is a Ti / Al / Ti electrode metal; In step 7), the passivation layer is composed of at least one of SiN, SiO2, and Al2O3; In step 9), the depth of the electrode contact region of the drain electrode is below the two-dimensional electron gas; the drain electrode is an electrode metal composed of at least one of Ti, Al, Ni, TiN, and AlSi; In step 10), the passivation layer is composed of at least one of SiN, SiO2, and Al2O3.

[0015] The present invention discloses a high-temperature ohmic GaN HEMT vertical structure chip, prepared by the above preparation method, including: a substrate; A GaN drift region, a channel layer, an AlN insertion layer, and an Al X Ga (1-X) N barrier layer and a SiN dielectric capping layer stacked in sequence on the substrate, where the value range of X is 0.2 - 0.25; A source electrode and a gate electrode located on the top of the SiN dielectric capping layer, the source electrode extends through the etched window region to the surface of the Al X Ga (1-X) N barrier layer to form an ohmic contact, and the sidewall inclination angle of the etched window region is 55 - 65°; A drain electrode located at the bottom of the substrate, and the sidewall inclination angle of the electrode contact region is 55 - 65°; A passivation layer covering the top and bottom of the chip, a conductive channel field plate structure covering the source electrode and the gate electrode is provided in the passivation layer; a drain electrode lead-out region, a gate electrode lead-out region, and a source electrode lead-out region are provided on the passivation layer; A deep etching opening penetrating through the substrate, the GaN drift region, the channel layer, the AlN insertion layer, the Al X Ga (1-X) N barrier layer and the SiN dielectric capping layer for vertical conduction of the drain electrode; The channel layer and the Al X Ga (1-X)The two-dimensional electron gas is restricted between the N barrier layers through an AlN insertion layer, and an isolation region formed by ion implantation is provided on the surface of the epitaxial layer of the chip.

[0016] Compared with the prior art, the present invention has the following beneficial effects: The present invention discloses a method for fabricating a high-temperature ohmic GaN HEMT vertical structure chip. Through the pretreatment of the substrate and the precise growth of the multi-layer structure, the high quality of the GaN HEMT vertical structure epitaxial wafer is ensured. The pretreatment helps to remove impurities on the substrate surface and improve the crystal quality of subsequent growth. The design of the multi-layer structure optimizes the electrical performance of the device and provides a stable substrate for subsequent steps. The high-quality epitaxial wafer reduces defects at the metal-semiconductor interface, thereby reducing interface reactions and diffusion at high temperatures. The cleaning and drying steps ensure the cleanliness of the epitaxial wafer, and the preparation marks facilitate the alignment and processing of subsequent processes. The clean surface reduces the influence of impurities on the metal-semiconductor interface and helps to reduce interface reactions. The precise photolithography and etching steps ensure the accurate positioning and shape of the source electrode window area, providing a basis for the preparation of subsequent electrodes. By controlling the photolithography and etching conditions, damage to the semiconductor surface can be reduced, thereby reducing the possibility of interface reactions. The rapid thermal annealing treatment helps to form ohmic contacts, reduce contact resistance, and improve the performance of the device. The annealing treatment can optimize the interface between the metal and the semiconductor, reducing chemical reactions and diffusion at the interface, especially under high-temperature conditions. The chip isolation region helps to prevent electrical interference between different devices and improve the integration and stability of the chip. The formation of the isolation region can reduce reactions and diffusion at the metal-semiconductor interface in unexpected regions. The precise preparation of the gate electrode is the key to the performance of the HEMT device, affecting the switching speed and threshold voltage of the device. Selecting appropriate electrode materials and process conditions can reduce interface reactions and diffusion at high temperatures. The passivation layer protects the device from the external environment, and the etched conductive channels ensure the electrical connection between the electrode and the semiconductor. The passivation layer acts as a barrier, reducing the direct contact and reaction at the metal-semiconductor interface at high temperatures. The deep etching opening provides a channel for the subsequent preparation of the electrode while maintaining the integrity of the device structure. By precisely controlling the etching depth and shape, damage to the semiconductor material can be reduced, thereby reducing interface reactions. The preparation of the drain electrode completes the electrode system of the device and ensures the normal operation of the device. The passivation layer protects the electrode system of the device, and the photolithographed electrode lead-out region facilitates the packaging and testing of the device. The passivation layer, as the final protective layer, further reduces reactions and diffusion at the metal-semiconductor interface at high temperatures. The etched depth should be above the two-dimensional electron gas to ensure that the etching process does not damage the two-dimensional electron gas, which is the key conductive region of the GaN HEMT device. Staying in the AlGaN layer means that the etching depth is precisely controlled, avoiding a decrease in device performance caused by over-etching. This is crucial for the stability of the device under high-temperature conditions because over-deep etching may expose more interfaces, increasing the risk of interface reactions and diffusion. The photolithography angle should be 55 - 65°, making the etched trenches smooth, which helps to uniformly deposit the subsequent metal layer and reduce stress concentration.Gentle grooves can reduce defects and cracks at the metal-semiconductor interface, thereby reducing the possibility of interface reaction and diffusion at high temperatures. Making the metal coating gentle and unbroken is the key to ensuring good electrical contact and reducing interface resistance. At high temperatures, the interface reaction and diffusion between the metal and the semiconductor can lead to an increase in resistance and degradation of device performance. A gentle and unbroken metal layer helps reduce these effects and improve the high-temperature stability of the device. After evaporation coating, alloying is carried out at a high temperature of 780 - 820 °C. The high-temperature alloying process helps form a good ohmic contact between the metal and the semiconductor. By allowing the metal to penetrate into the two-dimensional electron layer, the contact resistance can be significantly reduced and the conductivity can be improved. This process needs to be carried out at high temperatures, and the present invention effectively addresses the high reactivity between the metal and the semiconductor at high temperatures by precisely controlling the alloying temperature and conditions, avoiding excessive interface reaction and diffusion. The electron isolation should be placed after the source electrode preparation to avoid being affected by high temperatures. Placing the electron isolation step after the source electrode preparation can ensure that the isolation region is not affected by the high-temperature alloying during the source electrode preparation process. This helps maintain the integrity and effectiveness of the isolation region and prevents unnecessary reaction and diffusion between the metal and the semiconductor at high temperatures.

[0017] The present invention also discloses a high-temperature ohmic GaN HEMT vertical structure chip prepared by the above preparation method. The high-quality interface and stable structure enable the chip to still maintain good performance under high-temperature conditions, effectively addressing the interface problems caused by the high reactivity between the metal and the semiconductor. The formation of the high-temperature ohmic contact and the protection of the passivation layer further enhance the stability and lifespan of the chip in a high-temperature environment. The vertical structure design enables the chip to achieve higher power density and integration within a smaller size. Due to the excellent electrical properties of the GaN material itself, the high-temperature ohmic GaN HEMT vertical structure chip prepared by the present invention has great potential in application scenarios such as high frequency, high power, and high temperature. It is applicable to fields such as wireless communication, power management, motor drive, and renewable energy, especially in power electronic systems that require efficient, compact, and high-temperature stable operation, and has a broad market prospect. Brief Description of the Drawings

[0018] Figure 1 It is a schematic structural diagram of the GaN HEMT vertical structure epitaxy disclosed by the present invention; Figure 2 It is a schematic structural diagram of the GaN HEMT vertical structure power chip disclosed by the present invention; Figure 3 It is a flow chart of the preparation method of the high-temperature ohmic GaN HEMT vertical structure chip disclosed by the present invention. Detailed Embodiments

[0019] To enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0020] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0021] The present invention will be further described in detail below with reference to the accompanying drawings: A preparation method for a vertical structure epitaxy of GaN HEMT disclosed by the present invention includes the following steps: GaN substrate preparation: Select an n-type doped GaN substrate with a thickness of 300 - 1000 μm as the growth basis. Selecting a GaN substrate with an appropriate thickness can ensure the uniformity and stability of the epitaxial layer. A thicker substrate usually has better thermal stability and mechanical strength, which is beneficial to the subsequent epitaxial growth process.

[0022] GaN substrate treatment: Pretreat the GaN substrate at a temperature of 1000 - 1150 °C (preferably 1100 °C). At the same time, introduce nitrogen (N2) at a rate of 0 - 100 L / min (preferably 0 L / min), hydrogen (H2) at a rate of 50 - 200 L / min (preferably 120 L / min), and ammonia (NH3) at a rate of 1 - 100 L / min (preferably 50 L / min) to prepare for the subsequent epitaxial growth. High-temperature pretreatment helps to remove impurities and defects on the substrate surface and improve the growth quality of the epitaxial layer. By precisely controlling the gas flow rate, the pretreatment environment can be optimized to provide favorable conditions for the subsequent epitaxial growth.

[0023] GaN Drift Region Growth: In the temperature range of 1000 - 1150 °C (preferably 1100 °C), under a growth pressure of 200 torr, by precisely controlling the flow rates of trimethylgallium (TMGA), N2, H2, NH3, and silane (SiH4), a GaN drift region with a thickness of 0.5 - 50 μm (preferably 7 μm) is grown. This layer is crucial for the chip performance. Among them, the flow rate of TMGA is 200 - 1000 sccm / min (preferably 600 sccm / min), the flow rate of N2 is 0 - 100 L / min (preferably 10 L / min), the flow rate of H2 is 50 - 200 L / min (preferably 90 L / min), the flow rate of NH3 is 1 - 100 L / min (preferably 45 L / min), the concentration of the first SiH4 is 200 ppm, and the flow rate is 0 - 500 sccm / min (preferably 10 sccm / min). The growth temperature is 1000 - 1150 °C (preferably 1100 °C), and the growth rotation speed is 800 - 1200 rpm (preferably 1200 rpm). The drift region is a key part of the HEMT chip, and its thickness and growth conditions have an important impact on the chip performance. By precisely controlling the growth parameters, a high-quality drift region can be obtained, thereby improving the current transmission ability and breakdown voltage of the chip.

[0024] Ion Implantation: On the epitaxial drift region grown in the previous step, the carrier blocking layer region is defined by photolithography, and ion implantation is performed on the carrier blocking layer region. The high-energy ions implanted are N ions. The implanted ions damage the lattice of the implanted region, achieving a high resistance in the implanted region, thereby restricting the current direction. Among them, the implantation depth of N ions is 0.1 - 20 μm (preferably 3 μm).

[0025] Channel Layer Growth: On the epitaxial wafer after ion implantation, secondary epitaxy is carried out. The growth temperature is 1000 - 1150 °C (preferably 1080 °C), the rotation speed is 800 - 1200 rpm (preferably 1200 rpm), the growth pressure is 200 torr. At the same time, TMGa, N2, H2, and NH3 are introduced to grow undoped GaN, and its thickness is controlled within 150 - 400 nm (preferably 300 nm). Among them, the flow rate of TMGa is 200 - 1000 sccm / min (preferably 500 scmm / min), the flow rate of N2 is 0 - 100 L / min (preferably 64 L / min), the flow rate of H2 is 0 - 200 L / min (preferably 120 L / min), and the flow rate of NH3 is 0 - 100 L / min (preferably 50 L / min). The quality of this layer determines the mobility and electron concentration of the two-dimensional electron gas. By adjusting the temperature and growth rate, the flatness of the interface can be improved, and the scattering of the two-dimensional electron gas can be reduced.

[0026] Growth of AlN insertion layer: Subsequently, at a temperature of 800 - 1100 °C (preferably 1000 °C) and a growth pressure of 75 torr, trimethylaluminum (TMAL), H2, and NH3 are simultaneously introduced to grow an extremely thin AlN insertion layer with a thickness controlled within 0 - 2 nm (preferably 0.8 nm) to optimize the chip performance. Among them, the introduction rate of TMAL is 0 - 500 sccm / min (preferably 200 sccm / min), the introduction rate of H2 is 50 - 200 L / min (preferably 190 L / min), and the introduction rate of NH3 is 1 - 100 L / min (preferably 5 L / min). The introduction of the insertion layer can optimize the interface characteristics of the chip, reduce interface scattering and defects, thereby improving the carrier mobility and current density of the chip. By precisely controlling the thickness and growth conditions of the insertion layer, the chip performance can be further optimized.

[0027] Al X Ga (1-X) Growth of Al X Ga (1-X) N barrier layer: Next, within a temperature range of 800 - 1100 °C (preferably 1020 °C), at 800 - 1200 rpm (preferably 1000 rpm), and a growth pressure of 100 torr, by adjusting the flow rates of TMGA, TMAL, N2, H2, and NH3 gases, an Al

[0028] Ga (1-X) N barrier layer with a thickness of 15 - 35 nm (preferably 22 nm) is grown, where the Al component X ranges from 15% - 50% (preferably 20% - 25%). This layer plays a key role in controlling the current magnitude and reliability. Among them, the introduction rate of TMGA is 0 - 500 sccm / min (preferably 80 sccm / min), the introduction rate of TMAL is 50 - 500 sccm / min (preferably 300 sccm / min), the introduction rate of N2 is 0 - 100 L / min (preferably 64 L / min), the introduction rate of H2 is 50 - 200 L / min (preferably 120 L / min), and the introduction rate of NH3 is 1 - 100 L / min (preferably 50 L / min). The barrier layer is a key part of the HEMT chip, and its thickness and growth conditions have an important impact on the current transmission characteristics of the chip. By precisely controlling the growth parameters of the barrier layer, a high-quality barrier layer can be obtained, thereby improving the switching speed and current control ability of the chip.

[0028] SiN dielectric capping layer growth: Finally, at a temperature of 700 - 1100 °C (preferably 1000 °C) and a growth pressure of 200 torr, by adjusting the flow rates of N2, H2, and NH3 gases and introducing a second SiH4 gas, a SiN dielectric capping layer with a thickness of 0.1 - 100 nm (preferably 2 nm) is grown to protect and optimize the chip surface. Among them, the flow rate of N2 is 0 - 100 L / min (preferably 64 L / min), the flow rate of H2 is 50 - 200 L / min (preferably 120 L / min), the flow rate of NH3 is 1 - 100 L / min (preferably 50 L / min), the concentration of the second SiH4 is 2%, and the flow rate is 0 - 500 sccm / min (preferably 40 sccm / min). The above gases are introduced simultaneously. The introduction of the SiN dielectric capping layer can protect the chip surface from the influence of the external environment, improving the stability and reliability of the chip. At the same time, by precisely controlling the growth parameters of the capping layer and introducing an appropriate amount of the second SiH4, the electrical characteristics of the chip surface can be further optimized.

[0029] Finally, a vertical GaN HEMT epitaxial structure is obtained.

[0030] During the entire preparation process, the growth of each layer needs to be carried out under strictly controlled temperature, gas flow rate, and doping conditions to ensure the high-quality growth of the vertical GaN HEMT epitaxial structure.

[0031] A method for preparing a high-temperature ohmic GaN HEMT vertical structure chip disclosed in the present invention includes the following steps: 1. Prepare a vertical GaN HEMT epitaxial wafer; on the substrate, a GaN drift region, implanted ions, a channel layer, an AlN insertion layer, an Al X Ga (1-X) GaN barrier layer, and a SiN dielectric capping layer are sequentially grown by metal-organic chemical vapor deposition.

[0032] 2. Cleaning: Immerse the vertical GaN HEMT epitaxial wafer in a 511 strong oxidation solution tank at 90 °C for 10 min in a cleaning machine, then transfer it to an IPA solution tank at 60 °C for 10 min to remove the residual solution on the surface. Finally, transfer it to a pure water tank at room temperature for 10 min. After the vertical GaN HEMT epitaxial wafer is taken out from the pure water tank, it is transferred to a spin dryer. The spin dryer needs to blow N2 at all times, and the temperature is controlled at 60 °C. First, rinse the vertical GaN HEMT epitaxial wafer with pure water having a water resistance of more than 8. The rotation speed changes as 500 rpm for 5 min, 2000 rpm for 10 min, 1000 rpm for 5 min, and finally to 0 rpm.

[0033] 3. Positioning and Fabrication: Markings are fabricated using photolithography and evaporation processes to achieve the purpose of positioning. First, a negative photoresist of about 1 μm is evenly coated on the surface. The pattern is exposed using a lithography machine, baked at 100 °C, and the excess photoresist is removed using a positive photoresist developer. Before metal evaporation, the surface of the GaN HEMT vertical structure epitaxial wafer is bombarded with an ion source for 2 minutes. The metal evaporated is CrTiNi. After evaporation, stripping is performed using a stripper. The stripper is first soaked in a degluing tank for 10 minutes, and finally, high-pressure rinsing with pure water is carried out. During the rinsing process, a rotation of 1000 rpm for 2 minutes is added.

[0034] 4. Source Opening: Openings are made at the top using photolithography and etching processes. The window area of the source is lithographed, and the SiN dielectric capping layer in the window area is removed by inductively coupled plasma etching (ICP). For photolithography, a 3-μm positive photoresist is used. After exposure and development, a layer of pattern is made as a mask before etching. For etching, an ICP etcher is used with F - -based to etch the dielectric first, and then Cl - -based to etch GaN.

[0035] Note: The depth after etching should be above the two-dimensional electron gas and stop at the AlGaN layer. The photolithography angle should be 55 - 65° to make the etched trenches smooth.

[0036] 5. Source Fabrication: The source of the device is fabricated using photolithography and evaporation. The electrode contact area of the source is lithographed at the top, and electrode metal is grown by electron beam evaporation or magnetron sputtering. The metal is composed of at least one of Ti, Al, Ni, TiN, and AlSi; the source electrode is formed through a stripping process, and rapid thermal annealing (Rapid TermalAnneal) treatment is performed on the source electrode metal in a nitrogen atmosphere to form an ohmic contact in the source area. For photolithography, a 1 - 3-μm negative photoresist is used for lift off. The pattern is developed through exposure. TiAlNiAu is evaporated using a metal evaporator and annealed into an alloy using a rapid annealing furnace (Rapid Thermal Annealing).

[0037] Note: The metal covering layer should be made smooth and without breaks. After evaporation, alloying is carried out at a high temperature of 780 - 820 °C. The purpose is to let the gold-coated metal penetrate downward into the two-dimensional electron layer to achieve the effect of conductivity.

[0038] 6. Electronic isolation: At the top, use photolithography and ion implantation for electronic isolation. Form a chip isolation region to achieve electrical isolation of the active region. The implanted elements are at least one of F, Ar, B, and N. Use a 3-μm positive photoresist for photolithography, and develop a pattern through exposure as a mask before ion implantation. Use boron ions for ion implantation to dope the areas without a photolithography mask to achieve the purpose of electronic isolation. Electronic isolation should be placed after the source preparation. Avoid being affected by high temperatures of 780 - 820 degrees Celsius.

[0039] 7. Gate preparation: Photolithograph the electrode contact area of the gate at the top, and grow the electrode metal Ti / Al / Ti by electron beam evaporation or magnetron sputtering. Form the gate electrode through the lift-off process. Use photolithography and evaporation to make the gate of the device. Use a 1 - 3-μm negative photoresist for lift-off. Develop a pattern through exposure. Evaporate TiAlNi with a metal evaporator.

[0040] 8. Field plate preparation: First, grow a passivation layer at the top by Plasma Enhanced Chemical Vapor Deposition. The passivation layer is at least one of SiN, SiO2, and Al2O3. After photolithography, etch out the conductive channels of the source and the gate. Use a 1 - 3-μm negative photoresist for lift-off. Develop a pattern through exposure. Evaporate TiAlNi with a metal evaporator to complete the production of the field plate.

[0041] 9. Deep etching and opening holes: Use photolithography and etching for deep etching. Use a 7 - 9-μm photoresist as a mask. Make deep holes at specific positions through exposure and development. Then use an etching machine with Cl - to perform deep etching on the GaN HEMT vertical structure epitaxial wafer. The etching depth is 3 - 5 μm.

[0042] 10. Drain preparation: Photolithograph the electrode contact area of the drain at the bottom, and grow the electrode metal by electron beam evaporation or magnetron sputtering. The metal consists of at least one of Ti, Al, Ni, TiN, and AlSi; form the drain electrode through the lift-off process, and perform rapid thermal annealing treatment on the drain electrode metal in a nitrogen atmosphere to form an ohmic contact in the drain region. Use photolithography, etching, and evaporation to make the drain of the device. Use a 1 - 3-μm positive photoresist as a mask, and use an etching machine to etch out the drain channel at a specific position. Use a 1 - 3-μm negative photoresist for lift-off. Develop a pattern through exposure. Evaporate TiAlNiAu on the drain channel with a metal evaporator and anneal it with RTA to form an alloy.

[0043] Note: The metal coating should be smooth and without breaks. After evaporation, perform alloying at a high temperature of 780 - 820 degrees Celsius. The purpose is to allow the gold-coated metal to penetrate downward into the two-dimensional electron layer to achieve the effect of conductivity.

[0044] 11. Bonding metal preparation: A passivation layer is grown at the bottom by plasma-enhanced chemical vapor deposition. The passivation layer is composed of at least one of SiN, SiO2, and Al2O3, and the drain electrode lead-out area is lithographed. The gate electrode and source electrode lead-out areas are lithographed at the top to obtain the chip. Lithography and evaporation are used to make the required bonding metal. A negative photoresist with a thickness of 7-9 μm is used for lift-off in lithography. The pattern is developed by exposure. TiAlNi is evaporated using a metal evaporator. A bonder is used. Before bonding, infrared laser alignment is used to align the bonding metal with the deep etching holes, and the two chips A and B are bonded together in a vacuum manner.

[0045] See Figure 1 It is a schematic structural diagram of the GaN HEMT vertical structure epitaxy disclosed by the present invention; as can be seen from the figure, when preparing the GaN HEMT vertical structure epitaxy disclosed by the present invention, first, high-quality GaN is selected as the substrate material, which provides mechanical support and thermal conductivity for the entire epitaxial structure, and at the same time avoids the epitaxial layer defects introduced during the heteroepitaxial process. The GaN drift region and the GaN channel layer are successively epitaxially grown on the GaN substrate. This region is the key part of the chip to withstand the off-state voltage and has a direct impact on the on-resistance of the chip. Subsequently, a layer of AlN (aluminum nitride) insertion layer is deposited on the GaN channel layer. This AlN insertion layer is used to adjust the height and distribution of the electron barrier and further optimize the chip performance. Immediately afterwards, a barrier layer is epitaxially grown on the AlN insertion layer. This layer and the GaN channel layer form a heterojunction to induce a two-dimensional electron gas with high concentration and high mobility, which is the key to forming an efficient electron transport channel. Finally, a dielectric capping layer is in-situ deposited on the barrier layer. This dielectric capping layer not only plays a protective role to prevent damage to the underlying structure during subsequent processes, but also serves as an etch stop layer to ensure the accuracy of subsequent processes.

[0046] See Figure 2Schematic diagram of the vertical structure AlGaN / GaN power chip disclosed by the present invention; it can be seen from the figure that the AlGaN / GaN heterojunction provides a two-dimensional electron gas participating in the operation of the chip, serving as the carrier source for the chip to conduct electricity. The chip gate is located between the source electrodes, and the on-off of the current is controlled by applying a voltage. When the gate voltage is lower than the turn-on voltage (also known as the threshold voltage) of the chip, the two-dimensional electron gas in the channel layer region under the gate is depleted, and the chip is in the off state. The breakdown voltage of the chip depends on the thickness of the channel layer, drift region, and substrate. When the gate voltage is higher than the threshold voltage, the two-dimensional electron gas in the channel layer region under the gate is restored and flows vertically through the channel layer, drift region, and substrate to the drain under the action of the electric field. The dielectric layer in the gate region can effectively reduce gate leakage and lower the operating loss of the chip. The drift region and the substrate are doped with n-type to reduce the bulk resistance, achieving a low on-resistance of the chip. The carrier blocking layers on both sides of the drift region are used to regulate the current direction to ensure that the current does not flow to other regions of the chip. The entire structure shows a complete path of injecting current from the source electrode, efficiently conducting through the GaN epitaxial layer and the substrate, and finally flowing out through the drain. This vertical structure design optimizes the current path, weakens the influence of the interface states between the passivation layer / barrier layer on the carrier transport, and improves the efficiency and reliability of the chip.

[0047] See Figure 3 Flow chart of the preparation method of the high-temperature ohmic GaN HEMT vertical structure chip disclosed by the present invention; it can be seen from the figure that the incoming materials A and B are respectively cleaned and positioned for preparation, and then source electrode opening, source electrode preparation, electron isolation, alloy treatment, gate preparation, and field plate preparation are carried out on the A wafer, and deep etching opening is simultaneously carried out to form a vertical structure; on the B wafer, drain electrode opening, electron isolation, and drain electrode preparation are carried out. Finally, a complete vertical structure chip is formed through the bonding of the A and B wafers. Through specific processes and material selections, the stability of the chip in a high-temperature environment is significantly improved; the preparation processes of the source electrode and the drain electrode are optimized to achieve good ohmic contact and reduce the contact resistance; the vertical structure design greatly improves the current transmission efficiency and reduces the thermal resistance; the application of the electron isolation technology effectively reduces the parasitic capacitance and leakage, thereby improving the overall performance and reliability of the device.

[0048] Example 1 A preparation method for the vertical structure epitaxy of GaN HEMT, comprising the following steps: Substrate preparation: Select a 300-μm GaN substrate as the growth basis.

[0049] Substrate treatment: The GaN substrate is pre-treated at a temperature of 1000, while N2 is introduced at a rate of 10 L / min, H2 at a rate of 50 L / min, and NH3 at a rate of 1 L / min to prepare for subsequent epitaxial growth. High-temperature pretreatment helps remove impurities and defects on the substrate surface and improve the growth quality of the epitaxial layer. By precisely controlling the gas flow rates, the pretreatment environment can be optimized to provide favorable conditions for subsequent epitaxial growth.

[0050] Drift region growth: In the temperature range of 1000 °C and at a growth pressure of 200 torr, a drift region with a thickness of 0.5 μm is grown by precisely controlling the flow rates of TMGA, N2, H2, NH3, and the first SIH4. This layer is crucial for device performance. Among them, the flow rate of TMGA is 200 sccm / min, the flow rate of N2 is 0.1 L / min, the flow rate of H2 is 50 L / min, the flow rate of NH3 is 1 L / min, the concentration of the first SIH4 is 200 ppm, and the flow rate is 0 sccm / min. The growth temperature is 1100 °C, and the growth rotation speed is 1200 rpm. The drift region is a key part of the HEMT device, and its thickness and growth conditions have an important impact on device performance. By precisely controlling the growth parameters, a high-quality drift region can be obtained, thereby improving the current transmission ability and breakdown voltage of the device.

[0051] Ion implantation: The carrier blocking layer region is defined by photolithography on the epitaxial drift region grown in the previous step, and ion implantation is performed on the carrier blocking layer region. The high-energy ions implanted are N ions. The implanted ions damage the lattice of the implanted region, achieving high resistance in the implanted region, thereby restricting the current direction. Among them, the implantation depth of the N ions is 3 μm.

[0052] Channel layer growth: On the epitaxial wafer after ion implantation, secondary epitaxy is carried out. The growth temperature is 1080 °C, the rotation speed is 1200 rpm, and the growth pressure is 200 torr. At the same time, TMGa, N2, H2, and NH3 are introduced to grow undoped GaN with a thickness controlled at 300 nm. The flow rate of TMGa is 500 scmm / min, the flow rate of N2 is 64 L / min, the flow rate of H2 is 120 L / min, and the flow rate of NH3 is 50 L / min. The quality of this layer determines the mobility and electron concentration of the two-dimensional electron gas. By adjusting the temperature and growth rate, the flatness of the interface can be improved, and the scattering of the two-dimensional electron gas can be reduced.

[0053] Insertion layer growth: Subsequently, at a temperature of 800 °C and a growth pressure of 75 torr, the flow rates of the gases TMAL, N2, H2, and NH3 were adjusted. In particular, the N2 flow rate was reduced to almost zero to grow an extremely thin insertion layer with a thickness controlled at 0.1 nm to optimize device performance. Among them, the introduction rate of TMAL was 0.1 sccm / min, the introduction rate of N2 was 0.1 L / min, the introduction rate of H2 was 50 L / min, and the introduction rate of NH3 was 1 L / min. The introduction of the insertion layer can optimize the interface characteristics of the device, reduce interface scattering and defects, thereby improving the carrier mobility and current density of the device. By precisely controlling the thickness and growth conditions of the insertion layer, the device performance can be further optimized.

[0054] Al X Ga (1-X) AlGaN barrier layer growth: Next, in the temperature range of 800 °C, at 1000 rpm and a growth pressure of 100 torr, by adjusting the flow rates of the gases TMGA, TMAL, N2, H2, and NH3, an AlGaN barrier layer with a thickness of 15 nm was grown. X Ga (1-X) The AlGaN barrier layer, where the Al component X ranges from 20%, plays a key role in controlling current transport. Among them, the introduction rate of TMGA was 0.1 sccm / min, the introduction rate of TMAL was 50 sccm / min, the introduction rate of N2 was 0.1 L / min, the introduction rate of H2 was 50 L / min, and the introduction rate of NH3 was 1 L / min. The barrier layer is a key part of the HEMT device, and its thickness and growth conditions have an important impact on the current transport characteristics of the device. By precisely controlling the growth parameters of the barrier layer, a high-quality barrier layer can be obtained, thereby improving the switching speed and current control ability of the device.

[0055] SIN dielectric cap layer growth: Finally, at a temperature of 700 °C and a growth pressure of 200 torr, by adjusting the flow rates of the gases N2, H2, and NH3 and introducing the second SIH4 gas, a SIN dielectric cap layer with a thickness of 0.1 nm was grown to protect and optimize the device surface. Among them, the introduction rate of N2 was 0.1 L / min, the introduction rate of H2 was 50 L / min, the introduction rate of NH3 was 1 L / min, the concentration of the second SIH4 was 2%, and the introduction rate was 0.1 sccm / min. The introduction of the SIN dielectric cap layer can protect the device surface from the influence of the external environment and improve the stability and reliability of the device. At the same time, by precisely controlling the growth parameters of the cap layer and introducing an appropriate amount of the second SIH4, the electrical characteristics of the device surface can be further optimized.

[0056] Finally, a GaN HEMT vertical structure epitaxy was obtained.

[0057] A preparation method for a high-temperature ohmic GaN HEMT vertical structure chip, comprising the following steps: 1. Prepare a GaN HEMT vertical structure epitaxial wafer; sequentially grow a GaN drift region, an AlN insertion layer, an Al X Ga (1-X) GaN barrier layer, and a SiN dielectric capping layer on a substrate by metal organic chemical vapor deposition.

[0058] 2. Cleaning: Immerse the GaN HEMT vertical structure epitaxial wafer in a 511 strong oxidation solution tank at 90 °C for 10 min in a cleaning machine, then transfer it to an IPA solution tank at 60 °C for 10 min to remove the residual solution on the surface. Finally, transfer it to a pure water tank at room temperature for 10 min. After the GaN HEMT vertical structure epitaxial wafer is taken out of the pure water tank, transfer it to a spin dryer. The spin dryer needs to blow N2 at all times, and the temperature is controlled at 60 °C. First, rinse the GaN HEMT vertical structure epitaxial wafer with pure water having a water resistance of more than 8. The rotation speed changes are 500 rpm for 5 min, 2000 rpm for 10 min, 1000 rpm for 5 min, and finally to 0 rpm.

[0059] 3. Positioning preparation: Prepare marks by photolithography and evaporation processes to achieve the purpose of positioning. First, use a 1-μm negative photoresist and evenly coat it on the surface. Use a lithography machine to expose the pattern, bake it at 100 °C, and remove the excess photoresist with a positive photoresist developer. Before metal evaporation, bombard the surface of the GaN HEMT vertical structure epitaxial wafer with an ion source for 2 min. Evaporate the metal using CrTiNi. After evaporation, use a stripper for stripping. The stripper is first immersed in a degluing tank for 10 min, and finally rinsed with high-pressure pure water. During the rinsing process, add a 2-min rotation at 1000 rpm.

[0060] 4. Source opening: Make an opening at the top by photolithography and etching processes, photolithograph the window area of the source electrode, and remove the SiN dielectric capping layer in the window area by inductively coupled plasma etching (ICP). Use a 3-μm positive photoresist for photolithography, expose and develop to make a layer of pattern as a mask before etching. Use an ICP etching machine for etching, first etch the dielectric with F - radical, and then etch GaN with Cl - radical.

[0061] Note: The depth after etching should be above the two-dimensional electron gas and stay in the AlGaN layer. The photolithography angle should be 60°, so that the etched trench can be gentle.

[0062] 5. Source Electrode Preparation: The source electrode of the device is fabricated by photolithography and evaporation. The electrode contact area of the source electrode is lithographed on the top, and the electrode metal is grown by electron beam evaporation or magnetron sputtering. The metal consists of Ti. The source electrode is formed through a lift-off process, and the source electrode metal is subjected to rapid thermal annealing (RTA) treatment in a nitrogen atmosphere to form an ohmic contact in the source region. Photolithography uses a negative photoresist with a thickness of 1 - 3 μm for lift-off. The pattern is developed through exposure. TiAlNiAu is evaporated using a metal evaporator and annealed using a rapid thermal annealing furnace to form an alloy.

[0063] Note: The metal coating should be smooth and continuous without breaks. After evaporation, alloying is carried out at a high temperature of 800 °C. The purpose is to allow the gold-coated metal to penetrate downward into the two-dimensional electron layer to achieve the effect of conductivity.

[0064] 6. Electron Isolation: Electron isolation is performed on the top using photolithography and ion implantation. The chip isolation region is formed to achieve electrical isolation of the active region. The implanted element is F. Photolithography uses a positive photoresist with a thickness of 3 μm. A layer of pattern is developed through exposure as a mask before ion implantation. Boron ions are used for doping in the areas without a photolithography mask during ion implantation to achieve the purpose of electron isolation. Electron isolation should be carried out after source electrode preparation to avoid being affected by the high temperature of 800 °C.

[0065] 7. Gate Electrode Preparation: The electrode contact area of the gate electrode is lithographed on the top, and the electrode metal Ti / Al / Ti is grown by electron beam evaporation or magnetron sputtering. The gate electrode is formed through a lift-off process. The gate of the device is fabricated by photolithography and evaporation. Photolithography uses a negative photoresist with a thickness of 1 - 3 μm for lift-off. The pattern is developed through exposure. TiAlNi is evaporated using a metal evaporator.

[0066] 8. Field Plate Preparation: First, a passivation layer is grown on the top by plasma enhanced chemical vapor deposition (PECVD). The passivation layer is SiN. After photolithography, the conductive channels of the source and the gate are etched. A negative photoresist with a thickness of 1 - 3 μm is used for lift-off. The pattern is developed through exposure. TiAlNi is evaporated using a metal evaporator to complete the fabrication of the field plate.

[0067] 9. Deep Etching and Hole Opening: Deep etching is carried out using photolithography and etching. A photoresist with a thickness of 7 - 9 μm is used as a mask. Deep holes are made at specific positions through exposure and development. Then, a Cl-based etchant is used to perform deep etching on the GaN HEMT vertical structure epitaxial wafer, and the etching depth is 3 - 5 μm. - The etching depth is 3 - 5 μm.

[0068] 10. Drain Preparation: Photolithograph the electrode contact area of the drain at the bottom, grow the electrode metal by electron beam evaporation or magnetron sputtering, and the metal is composed of Ti; form the drain electrode through the lift-off process, and perform rapid thermal annealing treatment on the drain electrode metal in a nitrogen atmosphere to form an ohmic contact in the drain area. Use photolithography, etching, and evaporation to make the drain of the device. Use 1-3μm positive photoresist as a mask, and use an etching machine to etch the drain channel at a specific position. Use 1-3μm negative photoresist for lift-off in photolithography. Develop the pattern through exposure. Evaporate TiAlNiAu on the drain channel using a metal evaporator, and anneal it with RTA to form an alloy.

[0069] Note: The metal coating should be smooth and unbroken. After evaporation, alloy at 800°C. The purpose is to let the gold-coated metal penetrate downward into the two-dimensional electron layer to achieve the conductivity effect.

[0070] 11. Bonding Metal Preparation: Grow a passivation layer by plasma-enhanced chemical vapor deposition at the bottom, and the passivation layer is composed of SiN, and photolithograph the drain electrode lead-out area. Photolithograph the gate electrode and source electrode lead-out areas at the top to obtain the chip. Use photolithography and evaporation to make the required bonding metal. Use 7-9μm negative photoresist for lift-off in photolithography. Develop the pattern through exposure. Evaporate TiAlNi using a metal evaporator. Use a bonder, and align with an infrared laser before bonding to align the bonding metal with the deep etching hole, and bond the A and B wafers together in a vacuum manner.

[0071] Example 2 A preparation method for vertical structure epitaxy of GaN HEMT includes the following steps: Substrate Preparation: Select a 500μm GaN substrate as the growth base.

[0072] Substrate Treatment: Pretreat the GaN substrate at a temperature of 1100°C. At the same time, introduce N2 at a rate of 0.1L / min, H2 at a rate of 120 L / min, and NH3 at a rate of 50 L / min to prepare for subsequent epitaxial growth. High-temperature pretreatment helps remove impurities and defects on the substrate surface and improve the growth quality of the epitaxial layer. By precisely controlling the gas flow rate, the pretreatment environment can be optimized to provide favorable conditions for subsequent epitaxial growth.

[0073] Drift region growth: In the temperature range of 1100 °C, under a growth pressure of 200 torr, a drift region with a thickness of 7 μm is grown by precisely controlling the flow rates of TMGA, N2, H2, NH3, and the first SIH4. This layer is crucial for device performance. Among them, the feeding rate of TMGA is 600 sccm / min, the feeding rate of N2 is 10 L / min, the feeding rate of H2 is 90 L / min, the feeding rate of NH3 is 45 L / min, the concentration of the first SIH4 is 200 ppm, and the feeding rate is 5 sccm / min. The growth temperature is 1000 °C, and the growth rotation speed is 800 rpm.

[0074] Ion implantation: On the epitaxial drift region grown in the previous step, the carrier blocking layer region is defined by photolithography, and ion implantation is performed on the carrier blocking layer region. The high-energy ions implanted are N ions. The implanted ions damage the lattice of the implanted region, achieving high resistance in the implanted region, thereby restricting the current direction. Among them, the implantation depth of N ions is 0.1 μm.

[0075] Channel layer growth: On the epitaxial wafer after ion implantation, secondary epitaxy is carried out. Among them, the growth temperature is 1000 °C, the rotation speed is 800 rpm, the growth pressure is 200 torr, and at the same time, TMGa, N2, H2, and NH3 are introduced to grow undoped GaN, and its thickness is controlled within 150 nm. Among them, the feeding rate of TMGa is 200 scmm / min, the feeding rate of H2 is 0.1 L / min, and the feeding rate of NH3 is 0.1 L / min. The quality of this layer determines the mobility and electron concentration of the two-dimensional electron gas. By adjusting the temperature and growth rate, the flatness of the interface can be improved, and the scattering of the two-dimensional electron gas can be reduced.

[0076] Insertion layer growth: Subsequently, at a temperature of 1000 °C and a growth pressure of 75 torr, the flow rates of the gases TMAL, N2, H2, and NH3 are adjusted, especially reducing the N2 flow rate to almost zero, and an extremely thin insertion layer with a thickness controlled within 0.8 nm is grown to optimize device performance. Among them, the feeding rate of TMAL is 200 sccm / min, the feeding rate of N2 is 0.1 L / min, the feeding rate of H2 is 190 L / min, and the feeding rate of NH3 is 5 L / min.

[0077] Barrier layer growth: Then, in the temperature range of 1020 °C, at 1200 rpm, under a growth pressure of 100 torr, by adjusting the flow rates of the gases TMGA, TMAL, N2, H2, and NH3, an Al X Ga (1-X)N barrier layer, where the Al composition X ranges from 22%, and this layer plays a key role in controlling current transmission. Among them, the flow rate of TMGA is 80 sccm / min, the flow rate of TMAL is 300 sccm / min, the flow rate of N2 is 64 L / min, the flow rate of H2 is 120 L / min, and the flow rate of NH3 is 50 L / min.

[0078] Growth of SIN dielectric capping layer: Finally, at a temperature of 1000 °C and a growth pressure of 200 torr, by adjusting the flow rates of N2, H2, and NH3 gases and introducing the second SiH4 gas, a SIN dielectric capping layer with a thickness of 2 nm is grown to protect and optimize the device surface. Among them, the flow rate of N2 is 64 L / min, the flow rate of H2 is 120 L / min, the flow rate of NH3 is 50 L / min, the concentration of the second SiH4 is 2%, and the flow rate is 40 sccm / min.

[0079] Finally, a vertical structure epitaxy of GaN HEMT is obtained.

[0080] A preparation method for a high-temperature ohmic GaN HEMT vertical structure chip, comprising the following steps: Differing from Example 1: 3. Alignment preparation: First, use 1 μm negative photoresist and coat it evenly on the surface.

[0081] 4. Source opening: The lithography angle should be 55°, so that the etched trench can be smooth.

[0082] 5. Source preparation: The metal consists of Ti and Al. Use 1 μm negative photoresist for lift-off in lithography. After evaporation, alloying is carried out at a high temperature of 780 °C.

[0083] 6. Electron isolation: The implanted elements are F and Ar.

[0084] 7. Gate preparation: Use 1 μm negative photoresist for lift-off in lithography.

[0085] 8. Field plate preparation: The passivation layer is SiN and SiO2. Use 1 μm negative photoresist for lift-off.

[0086] 9. Deep etching opening: Use 7 μm photoresist as a mask. The etching depth is 3 μm.

[0087] 10. Drain preparation: The metal consists of Ti and Al. Use 1 μm positive photoresist as a mask. After evaporation, alloying is carried out at a high temperature of 780 °C.

[0088] 11. Bonding metal preparation: The passivation layer consists of SiN and SiO2. Use 7 μm negative photoresist for lift-off in lithography.

[0089] Example 3 A preparation method for the epitaxy of a vertical GaN HEMT structure includes the following steps: Substrate preparation: Select a 700-μm GaN substrate as the growth basis.

[0090] Substrate treatment: Pretreat the GaN substrate at a temperature of 1060°C. At the same time, introduce N2 at a rate of 60 L / min, H2 at a rate of 200 L / min, and NH3 at a rate of 100 L / min to prepare for subsequent epitaxial growth. High-temperature pretreatment helps remove impurities and defects on the substrate surface and improve the growth quality of the epitaxial layer. By precisely controlling the gas flow rate, the pretreatment environment can be optimized to provide favorable conditions for subsequent epitaxial growth.

[0091] Drift region growth: In a temperature range of 1150°C and a growth pressure of 200 torr, grow a drift region with a thickness of 50 μm by precisely controlling the flow rates of TMGA, N2, H2, NH3, and the first SIH4. This layer is crucial for device performance. Among them, the introduction rate of TMGA is 1000 sccm / min, the introduction rate of N2 is 100 L / min, the introduction rate of H2 is 200 L / min, the introduction rate of NH3 is 100 L / min, the concentration of the first SIH4 is 200 ppm, and the introduction rate is 500 sccm / min. The growth temperature is 1050°C, and the growth rotation speed is 900 rpm.

[0092] Ion implantation: Define the carrier blocking layer region on the epitaxial drift region grown in the previous step through photolithography, and perform ion implantation on the carrier blocking layer region. The high-energy ions implanted are N ions. The implanted ions damage the lattice of the implanted region to achieve high resistance in the implanted region, thereby restricting the current direction. Among them, the implantation depth of N ions is 5 μm.

[0093] Channel layer growth: On the epitaxial wafer after ion implantation, perform secondary epitaxy. Among them, the growth temperature is 1100°C, the rotation speed is 1000 rpm, the growth pressure is 200 torr, and at the same time introduce TMGa, N2, H2, and NH3 to grow undoped GaN, and its thickness is controlled within 200 nm. Among them, the introduction rate of TMGa is 600 scmm / min, the introduction rate of N2 is 80 L / min, the introduction rate of H2 is 100 L / min, and the introduction rate of NH3 is 80 L / min. The quality of this layer determines the mobility and electron concentration of the two-dimensional electron gas. By adjusting the temperature and growth rate, the flatness of the interface can be improved, and the scattering of the two-dimensional electron gas can be reduced.

[0094] Insertion layer growth: Subsequently, at a temperature of 1100 °C and a growth pressure of 75 torr, the flow rates of the gases TMAL, N2, H2, and NH3 are adjusted, especially reducing the N2 flow rate to almost zero, to grow an extremely thin insertion layer with a thickness controlled at 1 nm to optimize device performance. Among them, the flow rate of TMAL is 500 sccm / min, the flow rate of N2 is 100 L / min, the flow rate of H2 is 200 L / min, and the flow rate of NH3 is 100 L / min.

[0095] Barrier layer growth: Then, within the temperature range of 1100 °C, at 1100 rpm and a growth pressure of 100 torr, by adjusting the flow rates of the gases TMGA, TMAL, N2, H2, and NH3, an Al X Ga (1-X) N barrier layer with a thickness of 35 nm is grown, where the Al component X ranges from 24%, and this layer plays a key role in controlling current transmission. Among them, the flow rate of TMGA is 500 sccm / min, the flow rate of TMAL is 500 sccm / min, the flow rate of N2 is 100 L / min, the flow rate of H2 is 200 L / min, and the flow rate of NH3 is 100 L / min.

[0096] SIN dielectric cap layer growth: Finally, at a temperature of 1100 °C and a growth pressure of 200 torr, by adjusting the flow rates of the gases N2, H2, and NH3 and introducing the second SIH4 gas, a SIN dielectric cap layer with a thickness of 100 nm is grown to protect and optimize the device surface. Among them, the flow rate of N2 is 100 L / min, the flow rate of H2 is 200 L / min, the flow rate of NH3 is 100 L / min, the concentration of the second SIH4 is 2%, and the flow rate is 500 sccm / min.

[0097] Finally, a GaN HEMT vertical structure epitaxy is obtained.

[0098] A preparation method for a high-temperature ohmic GaN HEMT vertical structure chip includes the following steps: Differing from Example 1: 3. Alignment preparation: First, use 3 μm negative photoresist and coat it evenly on the surface.

[0099] 4. Source opening: The lithography angle should be 65° to make the etched trenches smooth.

[0100] 5. Source preparation: The metal is composed of Ni and TiN. Lithography uses 3 μm negative photoresist for lift-off. After evaporation, alloying is carried out at a high temperature of 810 °C.

[0101] 6. Electron isolation: The implanted element is B.

[0102] 7. Gate preparation: For lithography, a 3-μm negative photoresist is used for lift-off.

[0103] 8. Field plate preparation: The passivation layer is SiO2. A 3-μm negative photoresist is used for lift-off.

[0104] 9. Deep etching for opening holes: A 9-μm photoresist is used as a mask. The etching depth is 3 μm.

[0105] 10. Drain preparation: The metal consists of Ni and TiN. A 3-μm positive photoresist is used as a mask. After evaporation, alloying is carried out at a high temperature of 810 °C.

[0106] 11. Bonding metal preparation: The passivation layer consists of SiO2. For lithography, a 9-μm negative photoresist is used for lift-off.

[0107] Example 4 A preparation method for vertical structure epitaxy of GaN HEMT, comprising the following steps: Substrate preparation: A 1000-μm GaN substrate is selected as the growth basis.

[0108] Substrate treatment: At a temperature of 1150 °C, the GaN substrate is pre-treated, and at the same time, N2 is introduced at a speed of 100 L / min, H2 is introduced at a speed of 110 L / min, and NH3 is introduced at a speed of 40 L / min to prepare for subsequent epitaxial growth. High-temperature pre-treatment helps to remove impurities and defects on the substrate surface and improve the growth quality of the epitaxial layer. By precisely controlling the gas flow rate, the pre-treatment environment can be optimized to provide favorable conditions for subsequent epitaxial growth.

[0109] Drift region growth: In the temperature range of 1120 °C and a growth pressure of 200 torr, by precisely controlling the flow rates of TMGA, N2, H2, NH3, and the first SIH4, a drift region with a thickness of 15 μm is grown, and this layer is crucial for device performance. Among them, the introduction speed of TMGA is 700 sccm / min, the introduction speed of N2 is 5 L / min, the introduction speed of H2 is 80 L / min, the introduction speed of NH3 is 40 L / min, the concentration of the first SIH4 is 200 ppm, and the introduction speed is 50 sccm / min. The growth temperature is 1150 °C, and the growth rotation speed is 1150 rpm.

[0110] Ion implantation: On the epitaxial drift region grown in the previous step, the carrier blocking layer region is defined by lithography, and ion implantation is performed on the carrier blocking layer region. The high-energy ions implanted are N ions. The implanted ions damage the lattice of the implanted region to achieve high resistance in the implanted region, thereby restricting the current direction. Among them, the implantation depth of N ions is 20 μm.

[0111] Channel layer growth: On the epitaxial wafer after ion implantation, secondary epitaxy is carried out. The growth temperature is 1150 °C, the rotation speed is 1150 rpm, the growth pressure is 200 torr. At the same time, TMGa, N2, H2, and NH3 are introduced to grow undoped GaN, and its thickness is controlled at 400 nm. The flow rate of TMGa is 1000 sccm / min, the flow rate of H2 is 200 L / min, and the flow rate of NH3 is 100 L / min. The quality of this layer determines the mobility and electron concentration of the two-dimensional electron gas. By adjusting the temperature and growth rate, the flatness of the interface can be improved and the scattering of the two-dimensional electron gas can be reduced.

[0112] Insertion layer growth: Subsequently, at a temperature of 950 °C and a growth pressure of 75 torr, the flow rates of the gases TMAL, N2, H2, and NH3 are adjusted, especially reducing the N2 flow rate to almost zero, to grow an extremely thin insertion layer with a thickness controlled at 2 nm to optimize device performance. Among them, the flow rate of TMAL is 100 sccm / min, the flow rate of N2 is 5 L / min, the flow rate of H2 is 170 L / min, and the flow rate of NH3 is 15 L / min.

[0113] Barrier layer growth: Then, in the temperature range of 900 °C, at 800 rpm and a growth pressure of 100 torr, by adjusting the flow rates of the gases TMGA, TMAL, N2, H2, and NH3, an Al X Ga (1-X) N barrier layer with a thickness of 21 nm is grown, where the Al component X ranges from 25%. This layer plays a key role in controlling current transmission. Among them, the flow rate of TMGA is 70 sccm / min, the flow rate of TMAL is 200 sccm / min, the flow rate of N2 is 70 L / min, the flow rate of H2 is 130 L / min, and the flow rate of NH3 is 40 L / min.

[0114] SIN dielectric cap layer growth: Finally, at a temperature of 1050 °C and a growth pressure of 200 torr, by adjusting the flow rates of the gases N2, H2, and NH3 and introducing the second SIH4 gas, a SIN dielectric cap layer with a thickness of 5 nm is grown to protect and optimize the device surface. Among them, the flow rate of N2 is 70 L / min, the flow rate of H2 is 130 L / min, the flow rate of NH3 is 40 L / min, and the concentration of the second SIH4 is 2%, and the flow rate is 150 sccm / min.

[0115] Finally, a vertical structure epitaxy of GaN HEMT is obtained.

[0116] A preparation method of a high-temperature ohmic GaN HEMT vertical structure chip, comprising the following steps: Differing from Example 1: 5. Source electrode preparation: The metal is composed of AlSi. A 1-μm negative photoresist is used for lift-off in lithography. Alloying is carried out at a high temperature of 820 °C after evaporation coating.

[0117] 6. Electron isolation: The implanted element is N.

[0118] 8. Field plate preparation: The passivation layer is Al2O3.

[0119] 10. Drain electrode preparation: The metal is composed of AlSi. A 1-μm positive photoresist is used as a mask. Alloying is carried out at a high temperature of 820 °C after evaporation coating.

[0120] 11. Bonding metal preparation: The passivation layer is composed of Al2O3.

[0121] The above content is only to illustrate the technical idea of the present invention and cannot be used to limit the protection scope of the present invention. Any modification made on the basis of the technical solution according to the technical idea proposed by the present invention falls within the protection scope of the claims of the present invention.

Claims

1. A method for preparing a high-temperature ohmic GaN HEMT vertical structure chip, characterized in that: The following steps are involved: 1) After the substrate is pretreated, the GaN drift region growth, ion implantation, channel layer growth, AlN insertion layer growth, Al X Ga (1-X) Growth of N barrier layer and SiN dielectric cap layer to obtain GaN HEMT vertical structure epitaxial wafer; Among them, Al X Ga (1-X) In the N barrier layer, X is 0.2~0.25; 2) Clean and dry the GaN HEMT vertical structure epitaxial wafer and prepare the mark; 3) Photolithography the source window area at the top with a photolithography angle of 55-65°, and remove the SiN dielectric cap layer in the window area; 4) Photolithography the source electrode contact area on the top, and evaporate the electrode metal. After peeling, the source electrode is formed; after 780-820℃ rapid thermal annealing treatment, an ohmic contact is formed in the source area; 5) Form a chip isolation area on the top through photolithography and ion implantation; 6) Photolithography the gate electrode contact area on the top, and evaporate the electrode metal. After peeling off, the gate electrode is formed; 7) Grow a passivation layer on top using plasma enhanced chemical vapor deposition, etch out the conductive channels of the source and gate, and obtain the field plate; 8) Deeply etch and open holes in GaN HEMT vertical structure epitaxial wafers; 9) Photolithography the drain electrode contact area at the bottom, with a photolithography angle of 55-65°, and evaporate electrode metal. After stripping, a drain electrode is formed; 10) Grow a passivation layer at the bottom and photolithography the drain electrode lead-out area; 11) The gate electrode and source electrode lead-out regions are photolithographically formed on the top to obtain a high-temperature ohmic GaN HEMT vertical structure chip.

2. The method for preparing a high temperature ohmic GaN HEMT vertical structure chip according to claim 1, characterized in that: In step 1), 300-1000 μm n-type doped GaN is selected as the substrate; the pretreatment conditions of the substrate include: pretreating the GaN substrate at 1000-1150° C., while introducing N2 at a rate of 0-100 L / min, H2 at a rate of 50-200 L / min, and NH3 at a rate of 1-100 L / min.

3. The method for preparing a high temperature ohmic GaN HEMT vertical structure chip according to claim 1, characterized in that: In step 1), the conditions for the growth of the GaN drift region include: at 1000-1150° C. and a growth pressure of 200 torr, by controlling the flow rates of trimethylgallium, N2, H2, NH3 and the first monosilane, a GaN drift region with a thickness of 0.5-50 μm is grown, the growth temperature is 1000-1150° C., and the growth speed is 800-1200 rpm; wherein the introduction rate of trimethylgallium is 200-1000 sccm / min, the introduction rate of N2 is 0-100 L / min, the introduction rate of H2 is 50-200 L / min, the introduction rate of NH3 is 1-100 L / min, and the introduction rate of the first monosilane is 0-500 sccm / min.

4. The method for preparing a high temperature ohmic GaN HEMT vertical structure chip according to claim 1, characterized in that: In step 1), the temperature of the channel layer growth is 1000-1150°C, the rotation speed is 800-1200rpm, the growth pressure is 200torr, and trimethylgallium, N2, H2 and NH3 are introduced at the same time to grow undoped GaN with a thickness controlled at 150-400nm, wherein the introduction rate of trimethylgallium is 200-1000sccm / min, the introduction rate of N2 is 0-100L / min, the introduction rate of H2 is 0-200L / min, and the introduction rate of NH3 is 0-100L / min.

5. The method for preparing a high temperature ohmic GaN HEMT vertical structure chip according to claim 1, characterized in that: In step 1), the conditions for growing the AlN insertion layer include: at 800-1100°C and a growth pressure of 75 torr, trimethylaluminum, H2 and NH3 are introduced simultaneously to grow an extremely thin AlN insertion layer, and the thickness of the AlN insertion layer is 0-2nm; wherein the introduction rate of trimethylaluminum is 0-500sccm / min, the introduction rate of H2 is 50-200L / min, and the introduction rate of NH3 is 1-100L / min.

6. The method for preparing a high temperature ohmic GaN HEMT vertical structure chip according to claim 1, characterized in that: In step 1), Al X Ga (1-X) The conditions for the growth of the N barrier layer include: growing an Al layer with a thickness of 15-35 nm by adjusting the flow rates of trimethylgallium, trimethylaluminum, N2, H2, and NH3 at 800-1100°C, 800-1200rpm, and a growth pressure of 100 torr. X Ga (1-X) N barrier layer; wherein the molar percentage of X is 20%-25%, the introduction rate of trimethylgallium is 0-500sccm / min, the introduction rate of trimethylaluminum is 50-500sccm / min, the introduction rate of N2 is 0-100L / min, the introduction rate of H2 is 50-200L / min, and the introduction rate of NH3 is 1-100L / min.

7. The method for preparing a high temperature ohmic GaN HEMT vertical structure chip according to claim 1, characterized in that: In step 1), the conditions for growing the SiN dielectric cap layer include: growing a SiN dielectric cap layer with a thickness of 0.1-100 nm at 700-1100° C. and a growth pressure of 200 torr by adjusting the flow rates of N2, H2 and NH3 and introducing a second monosilane; wherein the N2 introduction rate is 0-100 L / min, the H2 introduction rate is 50-200 L / min, the NH3 introduction rate is 1-100 L / min, the concentration of the second monosilane is 2%, and the second monosilane introduction rate is 0-500 sccm / min.

8. The method for preparing a high temperature ohmic GaN HEMT vertical structure chip according to claim 1, characterized in that: In step 3), the window region of the source electrode has a depth below the two-dimensional electron gas; the SiN dielectric cap layer in the window region is removed by inductively coupled plasma etching; In step 4), before evaporation, the substrate is immersed in a strong oxidizing solution tank and then immersed in dilute hydrochloric acid; the source electrode is an electrode metal composed of at least one of Ti, Al, Ni, TiN and AlSi; In step 5), the ion implanted element includes: at least one of F, Ar, B and N; the depth of the ion implantation is 0.1-20 μm.

9. The method for preparing a high temperature ohmic GaN HEMT vertical structure chip according to claim 1, characterized in that: In step 6), the gate electrode is a Ti / Al / Ti electrode metal; In step 7), the passivation layer is composed of at least one of SiN, SiO2 and Al2O3; In step 9), the depth of the electrode contact region of the drain is below the two-dimensional electron gas; the drain electrode is an electrode metal composed of at least one of Ti, Al, Ni, TiN and AlSi; In step 10), the passivation layer is composed of at least one of SiN, SiO2 and Al2O3.

10. A high temperature ohmic GaN HEMT vertical structure chip, characterized in that: The method according to any one of claims 1 to 9 is used to prepare the substrate, comprising: a substrate; The GaN drift region, channel layer, AlN insertion layer, Al X Ga (1-X) N barrier layer and SiN dielectric cap layer, wherein the value of X ranges from 0.2 to 0.25; The source electrode and gate electrode are located on the top of the SiN dielectric cap layer, and the source electrode extends to the Al X Ga (1-X) An ohmic contact is formed on the surface of the N barrier layer, and the sidewall inclination angle of the etching window area is 55-65°; The drain electrode is located at the bottom of the substrate, and the sidewall inclination angle of the electrode contact area is 55-65°; A passivation layer covering the top and bottom of the chip, wherein the passivation layer is provided with a conductive channel field plate structure covering the source electrode and the gate electrode; a drain electrode lead-out region, a gate electrode lead-out region and a source electrode lead-out region are provided on the passivation layer; Through the substrate, GaN drift region, channel layer, AlN insertion layer, Al X Ga (1-X) Deep etching openings in the N barrier layer and the SiN dielectric cap layer are used for vertical conduction of the drain electrode; The channel layer and Al X Ga (1-X) Two-dimensional electron gas confinement is achieved through AlN insertion layers between N barrier layers, and an isolation area formed by ion implantation is provided on the surface of the chip epitaxial layer.

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