CV detection circuit and method for capacitive MEMS sensor

Abstract

The present invention discloses a CV detection circuit and method for a capacitive MEMS sensor, relates to the field of sensors, and is used to improve the measurement accuracy of the CV detection circuit. The detection electrodes of the capacitor array circuit of the CV detection circuit are used to connect to the sensitive detection structure of the capacitive MEMS sensor and to the amplifier circuit; the amplifier circuit, demodulation circuit, and filter circuit are connected in sequence; a clock power supply is connected to the clock generation circuit; the clock generation circuit generates a first clock signal and a second clock signal that do not overlap in two phases; the first clock signal is connected to the demodulation circuit, and the second clock signal is connected to the capacitor array circuit. The present invention achieves accurate measurement of tiny capacitance changes and saves area overhead.

Description

Technical Field

[0001] The present invention relates to the field of sensor technology, and in particular to a CV detection circuit and method for a capacitive MEMS sensor. Background Art

[0002] Capacitive MEMS sensors are highly sought after in the market due to their small size, excellent stability, reliability, and high sensitivity. In recent years, with the continuous advancement of micromachining technology, the manufacturing process of capacitive MEMS sensors has become increasingly mature, leading to growing demand in consumer electronics, automotive, industrial control, medical, aerospace, military, and other fields. Their core operating principle is to utilize the principle of charge conservation to convert inertial force into a capacitance change through the microelectromechanical system (MEMS). A CV (capacitance to voltage) detection circuit then converts this capacitance change into a voltage signal for subsequent processing. Because the capacitance change is very small, typically on the order of a Farad, it is particularly important to use a dedicated CV detection circuit to detect and process the tiny capacitance changes of the MEMS.

[0003] When detecting tiny capacitance changes, traditional CV detection circuits are affected by factors such as the matching accuracy between the interface circuit matching capacitor and the mechanical structure detection capacitor, clock noise, circuit parasitic capacitance, and offset, which can seriously affect their detection accuracy. This requires that the CV detection circuit needs to have sufficient matching accuracy to reduce the impact of mismatch on the signal itself. On the other hand, MEMS sensors will introduce process deviations during processing. The internal structure of MEMS sensors is delicate, with mass blocks, comb teeth, beams, gases, etc. The sensitive detection structure of capacitive MEMS sensors, such as Figure 1 As shown. The mass block is generally required to be in the order of 10-4 mg, the comb tooth gap is generally required to be below 10 μm, and the gas pressure is generally required to be controlled at low pressure. However, during manufacturing, process errors can cause these parameters to deviate from the design requirements, and there will be inconsistencies between different batches and different axial directions. Mechanical structures with different processes, design schemes, and different measuring ranges will also have different detection capacitance values ​​between the internal mass block and the fixed comb teeth. This requires the CV detection circuit to have a wide range of adaptability and gain adjustability to meet the matching requirements of different mechanical structures. At the same time, traditional solutions do not explain the power supply scheme for the modulation and demodulation clock. All use direct power supply, resulting in excessive clock jitter, which introduces new noise during signal modulation and demodulation, thereby affecting the detection accuracy of the CV detection circuit. Summary of the Invention

[0004] The object of the present invention is to provide a CV detection circuit and method for a capacitive MEMS sensor to improve the measurement accuracy of the CV detection circuit in order to address all or part of the above-mentioned problems.

[0005] The technical solution adopted in the present invention is as follows:

[0006] A CV detection circuit for a capacitive MEMS sensor includes a capacitor array circuit, a clock generation circuit, a clock power supply, an amplifier circuit, a demodulation circuit, and a filter circuit; the detection electrode of the capacitor array circuit is used to be connected to a sensitive detection structure of the capacitive MEMS sensor and to the amplifier circuit; the amplifier circuit, demodulation circuit, and filter circuit are connected in sequence; the clock power supply is connected to the clock generation circuit; the clock generation circuit generates a first clock signal and a second clock signal that do not overlap in two phases, the first clock signal is connected to the demodulation circuit, and the second clock signal is connected to the capacitor array circuit.

[0007] Furthermore, the capacitor array circuit includes a first capacitor group connected to the first detection electrode, and a second capacitor group connected to the second detection electrode; the first capacitor group and the second capacitor group are respectively connected to a common end, and the common end is connected to the second clock signal; the first capacitor group and the second capacitor group both include a coarse adjustment capacitor circuit and a fine adjustment capacitor branch.

[0008] Furthermore, the coarse adjustment capacitor circuit includes two groups of adjustable capacitors connected in parallel, and the fine adjustment capacitor branch includes a digital-to-analog converter and a fixed capacitor connected in series.

[0009] Furthermore, the amplifier circuit includes a fully differential operational amplifier, a first feedback resistor, a second feedback resistor, a first feedback capacitor and a second feedback capacitor; the first feedback resistor and the first feedback capacitor are connected in parallel between the non-inverting input and the inverting output of the fully differential amplifier, and the second feedback resistor and the second feedback capacitor are connected in parallel between the inverting input and the non-inverting output of the fully differential amplifier.

[0010] Furthermore, the clock power supply includes an error amplifier, a buffer, a PMOS tube, a first fixed resistor and a first variable resistor; the inverting input of the error amplifier is connected to a reference signal, the non-inverting input is connected to a feedback signal, and the output is connected to the input of the buffer; the output of the buffer is connected to the gate of the PMOS tube; the source of the PMOS tube is connected to the power supply, and the drain serves as the output of the clock power supply, and is connected in series with the first fixed resistor and the first variable resistor in sequence; the non-inverting input of the error amplifier is connected between the first fixed resistor and the first variable resistor.

[0011] Furthermore, the clock generation circuit includes a ring oscillation circuit, a drive buffer circuit and a non-overlapping clock generation circuit; the output end of the ring oscillation circuit is connected to the input end of the drive buffer circuit, the output end of the drive buffer circuit is connected to the input end of the non-overlapping clock generation circuit, and the non-overlapping clock generation circuit outputs a first clock signal and a second clock signal of two non-overlapping phases respectively.

[0012] Furthermore, the first clock signal is also used to access the capacitive MEMS sensor.

[0013] In another aspect, the present invention further provides a CV detection method for a capacitive MEMS sensor. The CV detection method is implemented based on the above-mentioned CV detection circuit for a capacitive MEMS sensor. The CV detection method includes:

[0014] Connecting the capacitive MEMS sensor to the detection electrode of the capacitor array circuit;

[0015] Access the clock signal for the capacitive MEMS sensor;

[0016] The capacitance connected to the capacitor array circuit is adjusted to a matching value.

[0017] Furthermore, a clock signal is connected to the capacitive MEMS sensor, including:

[0018] The first clock signal is connected to the capacitive MEMS sensor.

[0019] Furthermore, adjusting the capacitance connected to the capacitor array circuit to a matching value includes:

[0020] The capacitance value of the coarse adjustment capacitor circuit in the capacitor array circuit is adjusted so that the fine adjustment capacitor branch in the capacitor array circuit converts the change in voltage value into the change in connected capacitance value under the action of the second clock signal.

[0021] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0022] This application utilizes a capacitor array circuit to achieve precise matching of the capacitance of sensitive detection structures, reducing fixed errors introduced by mismatches and enabling accurate measurement of small capacitance changes. Furthermore, by powering the clock generation circuit via a clock power supply, the impact of power supply noise on the clock, as in traditional schemes where power is directly supplied to the clock generation circuit, is avoided, noise introduced by clock jitter is reduced, and the detection accuracy of the CV detection circuit is further improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The present invention will now be described by way of example with reference to the accompanying drawings, in which:

[0024] Figure 1 It is a structural diagram of the sensitive detection structure of a capacitive MEMS sensor.

[0025] Figure 2 It is a structural diagram of the CV detection circuit of the capacitive MEMS sensor.

[0026] Figure 3 It is a structural diagram of the capacitor array circuit.

[0027] Figure 4 It is a structural diagram of the clock power supply.

[0028] Figure 5 It is a structural diagram of the clock generation circuit. DETAILED DESCRIPTION

[0029] All features disclosed in this specification, or all steps in the disclosed methods or processes, except mutually exclusive features and / or steps, can be combined in any manner.

[0030] Any feature disclosed in this specification (including any appended claims and abstract), unless otherwise stated, may be replaced by other equivalent or similar features. In other words, unless otherwise stated, each feature is only an example of a series of equivalent or similar features.

[0031] To address the problem of poor detection accuracy of the CV detection circuit of a traditional capacitive MEMS sensor, an embodiment of the present application provides a CV detection circuit for a capacitive MEMS sensor, aiming to improve the detection accuracy of the CV detection circuit.

[0032] The CV detection circuit for a capacitive MEMS sensor provided in this application includes a capacitor array circuit CARR, a clock generation circuit CLKGEN, a clock power supply LDO, an amplifier circuit AMP, a demodulation circuit CHOPPER and a filter circuit LPF. Figure 2 As shown, the detection electrodes of the capacitor array circuit CARR are used to connect to the sensitive detection structure of the capacitive MEMS sensor and are connected to the amplifier circuit AMP. The amplifier circuit AMP, the demodulation circuit CHOPPER, and the filter circuit LPF are connected in sequence, and the filter circuit LPF outputs the detection results. The clock power supply LDO is connected to the clock generation circuit CLKGEN. The clock generation circuit CLKGEN generates a first clock signal CLK and a second clock signal CLKB that do not overlap. The first clock signal CLK is connected to the demodulation circuit CHOPPER, and the second clock signal CLKB is connected to the capacitor array circuit CARR.

[0033] Capacitive MEMS sensors also require a clock signal to operate. As an optional implementation, the clock signal used by the capacitive MEMS sensor can be the first clock signal CLK, i.e., the first clock signal CLK is also used to connect to the capacitive MEMS sensor. Of course, the capacitive MEMS sensor can also be connected to an independent clock signal.

[0034] The equivalent capacitances Cs1 and Cs2 of the capacitive MEMS sensor's sensitive detection structure together form the input signal for the CV detection circuit. The weak capacitance signal generated by the sensitive detection structure is read and modulated by the capacitance array circuit CARR. This signal is then amplified by the amplifier circuit AMP, demodulated by the demodulation circuit CHOPPER, and filtered by the filter circuit LPF to produce a high-quality detection signal.

[0035] like Figure 2 As shown, as an optional embodiment, the amplifier circuit AMP includes a fully differential operational amplifier OPA1, a first feedback resistor Rf1, a second feedback resistor Rf2, a first feedback capacitor Cf1, and a second feedback capacitor Cf2. The first feedback resistor Rf1 and the first feedback capacitor Cf1 are connected in parallel between the non-inverting input terminal Vp and the inverting output terminal Von of the fully differential operational amplifier OPA1; the second feedback resistor Rf2 and the second feedback capacitor Cf2 are connected in parallel between the inverting input terminal Vn and the non-inverting output terminal Vop of the fully differential operational amplifier OPA1. The two feedback resistors of the amplifier circuit AMP are used to provide a suitable DC operating point for the fully differential operational amplifier OPA1. The two feedback capacitors of the amplifier circuit AMP, together with the input of the previous stage, form a charge amplifier circuit, which amplifies and outputs weak charge changes. Together, they form a high-pass filter, filtering low-frequency noise while retaining high-frequency signal components for output to the demodulation circuit CHOPPER.

[0036] As an optional embodiment, the capacitor array circuit CARR includes a first capacitor group connected to the first detection electrode ST, and a second capacitor group connected to the second detection electrode SB. The first capacitor group and the second capacitor group are respectively connected to a common terminal, which is connected to the second clock signal CLKB. The first capacitor group and the second capacitor group both include a coarse adjustment capacitor circuit and a fine adjustment capacitor branch, and the two branches are connected in parallel. The coarse adjustment capacitor circuit is used to (roughly) adjust the capacitance value of the capacitor array circuit CARR (i.e., directly adjust the capacitance value), and the fine adjustment capacitor branch is used to convert the change in voltage value into the change in connected capacitance value, thereby realizing fine adjustment of the matching capacitance. That is, the capacitance value adjustment problem is converted into a voltage value adjustment problem, and the connected capacitance of the fine adjustment capacitor branch is finely adjusted by quantizing and adjusting the voltage.

[0037] In some feasible implementations, the coarse adjustment capacitor circuit includes two sets of adjustable capacitors connected in parallel, and the fine adjustment capacitor branch includes a digital-to-analog converter and a fixed capacitor connected in series. Figure 3 As shown, the first capacitor group includes an adjustable capacitor Cb1 and an adjustable capacitor Cb2, which are connected in parallel between the first detection electrode ST and the common terminal. In addition, between the first detection electrode ST and the common terminal, a fine-tuning capacitor branch is formed by a fixed resistor Cb3 and a first digital-to-analog converter CLKBF1 connected in series. The input terminal of the first digital-to-analog converter CLKBF1 is connected to the second clock signal CLKB. Similarly, the second capacitor group includes an adjustable capacitor Cb4 and an adjustable capacitor Cb5, which are connected in parallel between the second detection electrode SB and the common terminal. In addition, between the second detection electrode SB and the common terminal, a fine-tuning capacitor branch is formed by a fixed resistor Cb6 and a second digital-to-analog converter CLKBF2 connected in series. The input terminal of the second digital-to-analog converter CLKBF2 is connected to the second clock signal CLKB. The adjustment step size of adjustable capacitors Cb1 and Cb4 is greater than that of adjustable capacitors Cb2 and Cb5. That is, although adjustable capacitors Cb1 and Cb2 are both classified as coarse adjustment capacitor branches, the adjustment accuracy of adjustable capacitor Cb2 is higher than that of adjustable capacitor Cb1. The same applies to adjustable capacitors Cb4 and Cb5.

[0038] In the capacitor array circuit CARR of the aforementioned structure, adjustable capacitors Cb1 and Cb4 are referred to as coarse-tuning capacitors (or capacitor arrays), and adjustable capacitors Cb2 and Cb5 are referred to as fine-tuning capacitors (or capacitor arrays). In some feasible embodiments, both the coarse-tuning capacitors and the fine-tuning capacitors are composed of binary capacitor arrays, controlled by an M-bit register (M is an integer). The coarse-tuning capacitor adjustment step size is 0.5 pF, and the fine-tuning capacitor adjustment step size is 10 fF. By configuring the registers, capacitors of different capacitance values ​​can be selected for connection to the circuit. Thus, adjustable capacitors Cb1 and Cb4 implement coarse matching capacitance adjustment, while adjustable capacitors Cb2 and Cb5 implement fine matching capacitance adjustment. This allows for wide-range, high-precision capacitance matching, meeting the matching requirements of different sensitive detection structures and being suitable for various types of capacitive MEMS sensors. In addition, in traditional capacitor matching arrays, accurate matching with the detection capacitor of the sensitive detection structure is mostly achieved by reducing the capacitance of the lowest-bit capacitor, but this solution is often subject to process limitations and cannot accurately manufacture capacitors at the fF level. In an embodiment of the present application, the fine-tuning capacitor branch adopts capacitor array digital-to-analog conversion (capacitor array DAC) technology, using the principle of capacitance conservation, that is: Q=C×V, where Q represents the amount of charge, C represents the capacitance value, and V represents the voltage difference across the capacitor. The capacitor C is kept unchanged, and the purpose of equivalently changing the capacitor C is achieved by changing the voltage V. The specific implementation plan is that the first digital-to-analog converter CLKBF1 (or the second digital-to-analog converter CLKBF2) of Nbits (N is an integer) quantizes the second clock signal CLKB, that is, quantizes the voltage connected to the fixed capacitor Cb3 (or fixed capacitor Cb6), and the minimum quantization step is , thereby achieving a detailed decomposition of the matching capacitors and solving the problem of the inability to process small capacitors. The capacitance values ​​of the fixed capacitors Cb3 and Cb6 can be designed to be equal.

[0039] The minimum precision matching capacitance value that can be achieved by the capacitor array circuit CARR of the above structure is:

[0040] ,

[0041] Where C represents the matching capacitance value, |Cb3| represents the capacitance value of the fixed capacitor Cb3, and N represents the number of bits of the digital-to-analog converter.

[0042] In response to the problem of large modulation and demodulation clock noise in the existing CV detection circuit, the present application uses a clock power supply LDO to separately power the clock generation circuit CLKGEN, and utilizes the voltage stabilization technology of the clock power supply LDO to reduce the impact of power supply noise on the modulation and demodulation clocks, thereby further improving the detection accuracy of weak signals.

[0043] As an optional implementation, Figure 4 As shown, the clock power supply LDO includes an error amplifier EA, a buffer BUFFER, a PMOS transistor PM1, a first fixed resistor R1, and a first variable resistor VR1. The error amplifier EA's inverting input is connected to a reference signal Vref, its non-inverting input is connected to a feedback signal Vfb, and its output is connected to the input of the buffer BUFFER. The output of the buffer BUFFER is connected to the gate G of the PMOS transistor PM1. The source S of the PMOS transistor PM1 is connected to the power supply VDD. The drain D serves as the output of the clock power supply LDO, outputting the voltage VCK. The drain D is also connected in series with the first fixed resistor R1 and the first variable resistor VR1. The first variable resistor VR1 is grounded. The non-inverting input of the error amplifier EA is connected between the first fixed resistor R1 and the first variable resistor VR1.

[0044] In the clock power supply LDO structure described above, the error amplifier EA amplifies the difference between the reference signal Vref and the feedback signal Vfb. The buffer BUFFER enhances drive and ensures the bandwidth of the clock power supply LDO. The PMOS transistor PM1, the first fixed resistor R1, and the first variable resistor VR1 collectively provide a stable output voltage VCK while suppressing power and ground noise, providing a stable, low-noise power supply for the clock generation circuit CLKGEN.

[0045] The clock power supply LDO's ability to suppress power supply noise in the sensor signal frequency band is as follows:

[0046] ,

[0047] Where PSR is the noise suppression index, and Gain_EA is the low-frequency gain of the error amplifier EA.

[0048] like Figure 5 FIG. 1 is a circuit diagram of a clock generation circuit CLKGEN in an optional embodiment. Figure 5 As shown, the clock generation circuit CLKGEN includes a ring oscillator circuit OSC, a driver buffer circuit BUF, and a non-overlapping clock generation circuit NOCGC. The output of the ring oscillator circuit OSC is connected to the input of the driver buffer circuit BUF, which in turn is connected to the input of the non-overlapping clock generation circuit NOCGC. The non-overlapping clock generation circuit NOCGC outputs two non-overlapping clock signals, a first clock signal CLK and a second clock signal CLKB. The ring oscillator circuit OSC uses an adjustable output frequency to avoid clock skew caused by process errors. The clock generation circuit CLKGEN uses the voltage (VCK) output by the LDO (Low-Density Detector) as its power supply, reducing the impact of clock jitter on weak signals.

[0049] The demodulation circuit, CHOPPER, uses a demodulation clock that matches the modulation clock frequency, namely the first clock signal CLK. After demodulation, the high-frequency signal is restored to its original frequency, while the low-frequency noise introduced by the circuit is simultaneously modulated to a higher frequency by the clock signal. The CHOPPER demodulation circuit achieves spectral separation of the signal and noise.

[0050] The LPF filter circuit uses a low-pass filter circuit, such as a Butterworth filter, which features good in-band flatness and an adjustable bandwidth. By selecting the appropriate bandwidth configuration, high-frequency noise can be effectively filtered. The LPF filter circuit ultimately outputs detection signals C2Vop (in-phase output) and C2Von (inverting output).

[0051] The CV detection circuit provided by the present application, combined with the differential capacitance of the sensitive detection structure, utilizes the configurable capacitor array circuit CARR to achieve wide range and high precision matching requirements. Utilizing the principle of charge conservation, a digital-to-analog converter is used to quantize the clock signal, and the equivalent capacitor is used to realize the processing of weak signals. The advantage of this structure is that the interface capacitance matching saves a lot of area overhead while meeting the requirements of wide matching range and high precision, reduces the nonlinear problem caused by the excessive area of ​​high-bit capacitors, and improves the linearity of the system. At the same time, the use of the clock power supply LDO as the power supply for the clock generation circuit greatly reduces the signal noise and distortion introduced by the power supply (jitter) noise in the clock modulation and demodulation process, thereby further improving the circuit's detection capability for weak signals. The present application adopts a fully differential structure circuit to minimize the nonlinear problem caused by parasitic capacitance mismatch.

[0052] In another aspect, an embodiment of the present application further provides a CV detection method for a capacitive MEMS sensor, which is implemented based on the above-mentioned CV detection circuit for a capacitive MEMS sensor. The CV detection method includes:

[0053] 1) Connect the capacitive MEMS sensor to the detection electrode of the capacitor array circuit CARR. Figure 2 As shown, the capacitor array circuit CARR and the equivalent capacitors Cs1 and CS2 of the sensitive detection structure of the capacitive MEMS sensor together constitute the input signal of the CV detection circuit.

[0054] 2) A clock signal is connected to the capacitive MEMS sensor. For example, a first clock signal CLK generated by a clock generation circuit CLKGEN can be connected.

[0055] 3) Adjust the capacitor size connected to the capacitor array circuit CARR to the matching value.

[0056] As an optional implementation, the method for adjusting the capacitance connected to the capacitor array circuit CARR to a matching value includes:

[0057] The capacitance value of the coarse adjustment capacitor circuit in the capacitor array circuit CARR is adjusted, and the voltage of the fine adjustment capacitor branch in the capacitor array circuit is adjusted so that the fine adjustment capacitor branch converts the change in voltage value into the change in capacitance value.

[0058] In some feasible implementations, the capacitor array circuit CARR adopts Figure 3 The circuit structure shown in FIG. 1 adjusts the capacitance value of the coarse adjustment capacitor circuit in the capacitor array circuit CARR, including:

[0059] Adjust the capacitance values ​​of the adjustable capacitor Cb1 and the adjustable capacitor Cb4 to achieve coarse adjustment of the matching capacitance;

[0060] The capacitance values ​​of the adjustable capacitor Cb2 and the adjustable capacitor Cb5 are adjusted to achieve fine adjustment of the matching capacitance.

[0061] On this basis, the fine-tuning capacitor branch (consisting of a fixed capacitor Cb3 and a first D / A converter CLKBF1 connected in series, or a fixed capacitor Cb6 and a second D / A converter CLKBF2 connected in series) comprising a D / A converter converts the change in voltage into a change in capacitance under the influence of the second clock signal CLKB. Specifically, the first D / A converter CLKBF1 (or the second D / A converter CLKBF2) quantizes the second clock signal CLKB, thereby quantizing the voltage of the fixed capacitor Cb3 (or the fixed capacitor Cb6). Based on the principle of capacitance conservation, this quantization of the connected capacitor is achieved.

[0062] The present invention is not limited to the aforementioned specific embodiments, but extends to any new features or any new combination disclosed in this specification, as well as any new method or process steps or any new combination disclosed.

Claims

1. A CV detection circuit for a capacitive MEMS sensor, characterized in that: The device comprises a capacitor array circuit (CARR), a clock generation circuit (CLKGEN), a clock power supply (LDO), an amplifier circuit (AMP), a demodulation circuit (CHOPPER), and a filter circuit (LPF); the clock power supply is connected to the clock generation circuit (CLKGEN); the clock generation circuit (CLKGEN) generates a first clock signal (CLK) and a second clock signal (CLKB) that do not overlap with each other. The first clock signal (CLK) is connected to the demodulation circuit (CHOPPER) as a demodulation clock, and the second clock signal (CLKB) is connected to the capacitor array circuit (CARR) as a modulation clock. The first detection electrode (ST) and the second detection electrode (SB) of the capacitor array circuit (CARR) are respectively connected to the equivalent capacitors Cs1 and Cs2 of the sensitive detection structure of the capacitive MEMS sensor, and are also connected to the amplifier circuit (AMP); the equivalent capacitors Cs1 and Cs2 of the sensitive detection structure constitute a differential capacitor. The capacitor array circuit (CARR) includes a first capacitor group connected to a first detection electrode (ST) and a second capacitor group connected to a second detection electrode (SB); the first capacitor group and the second capacitor group are respectively connected to a common terminal, and the common terminal is connected to the second clock signal (CLKB); the first capacitor group and the second capacitor group each include a coarse adjustment capacitor circuit and a fine adjustment capacitor branch, and the coarse adjustment capacitor circuit and the fine adjustment capacitor branch are connected in parallel; the coarse adjustment capacitor circuit includes two groups of adjustable capacitors connected in parallel, and the adjustment step size of the first group of adjustable capacitors in the two groups of adjustable capacitors is greater than the adjustment step size of the second group of adjustable capacitors. Both groups of adjustable capacitors are composed of binary capacitor arrays, and the first group of adjustable capacitors is used for coarse adjustment of matching capacitance, and the second group of adjustable capacitors is used for fine adjustment of matching capacitance; the fine adjustment capacitor branch includes a digital-to-analog converter and a fixed capacitor connected in series; the amplifier circuit (AMP), the demodulation circuit (CHOPPER) and the filter circuit (LPF) are connected in sequence.

2. The CV detection circuit for a capacitive MEMS sensor according to claim 1, wherein: The amplifier circuit (AMP) includes a fully differential operational amplifier (OPA1), a first feedback resistor (Rf1), a second feedback resistor (Rf2), a first feedback capacitor (Cf1), and a second feedback capacitor (Cf2); the first feedback resistor (Rf1) and the first feedback capacitor (Cf1) are connected in parallel between the non-inverting input and the inverting output of the fully differential operational amplifier (OPA1), and the second feedback resistor (Rf2) and the second feedback capacitor (Cf2) are connected in parallel between the inverting input and the non-inverting output of the fully differential operational amplifier (OPA1).

3. The CV detection circuit for a capacitive MEMS sensor according to claim 1, wherein: The clock power supply (LDO) comprises an error amplifier (EA), a buffer (BUFFER), a PMOS transistor (PM1), a first fixed resistor (R1) and a first variable resistor (VR1); the inverting input of the error amplifier (EA) is connected to a reference signal (Vref), the non-inverting input is connected to a feedback signal (Vfb), and the output is connected to the input of the buffer (BUFFER); the output of the buffer (BUFFER) is connected to the gate of the PMOS transistor (PM1); the source of the PMOS transistor (PM1) is connected to a power supply, the drain serves as the output of the clock power supply (LDO), and is sequentially connected in series with the first fixed resistor (R1) and the first variable resistor (VR1); the non-inverting input of the error amplifier (EA) is connected between the first fixed resistor (R1) and the first variable resistor (VR1).

4. The CV detection circuit for a capacitive MEMS sensor according to claim 1, wherein: The clock generation circuit (CLKGEN) includes a ring oscillator circuit (OSC), a drive buffer circuit (BUF) and a non-overlapping clock generation circuit (NOCGC); the output end of the ring oscillator circuit (OSC) is connected to the input end of the drive buffer circuit (BUF), and the output end of the drive buffer circuit (BUF) is connected to the input end of the non-overlapping clock generation circuit (NOCGC). The non-overlapping clock generation circuit (NOCGC) outputs a first clock signal (CLK) and a second clock signal (CLKB) with two non-overlapping phases.

5. The CV detection circuit for a capacitive MEMS sensor according to claim 1, wherein: The first clock signal (CLK) is also used to access the capacitive MEMS sensor.

6. A CV detection method for a capacitive MEMS sensor, characterized in that: The CV detection method is implemented based on the CV detection circuit for a capacitive MEMS sensor according to any one of claims 1 to 5, and the CV detection method includes: Connect the capacitive MEMS sensor to the detection electrode of the capacitor array circuit (CARR); Access the clock signal for the capacitive MEMS sensor; Adjusting the capacitance connected to the capacitor array circuit (CARR) to a matching value includes: adjusting the capacitance of a coarse adjustment capacitor circuit in the capacitor array circuit (CARR), and adjusting the voltage of a fine adjustment capacitor branch in the capacitor array circuit (CARR) so that the fine adjustment capacitor branch converts a change in the voltage value into a change in the connected capacitance value; Adjusting the capacitance value of the coarse tuning capacitor circuit in the capacitor array circuit (CARR) includes: adjusting the capacitance value of a first group of adjustable capacitors in the coarse tuning capacitor circuit to achieve coarse adjustment of the matching capacitance; and adjusting the capacitance value of a second group of adjustable capacitors in the coarse tuning capacitor circuit to achieve fine adjustment of the matching capacitance.

7. The CV detection method for a capacitive MEMS sensor according to claim 6, wherein: Accessing clock signals for capacitive MEMS sensors includes: The first clock signal (CLK) is connected to the capacitive MEMS sensor.

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