Test Method for Phase Switching Stabilization Time, Control Module, and Program Product

Abstract

An embodiment of the present disclosure discloses a method for testing the phase switching stabilization time, a control module, and a program product. The method includes: traversing and assigning values to a first register and / or a second register of a component under test to change the phase shift of a first phase shifter and / or a second phase shifter of the component under test, and obtaining the value of a detected signal at each assignment, where the detected signal is obtained by detecting the signal after combining a first radio frequency channel and a second radio frequency channel; using the value of the first register and / or the second register when the detected signal is maximum or minimum as an initial value; based on the initial value, sending a trigger signal to change the value of the first register and / or the second register, so that the combined signal is phase-shifted by 180° relative to the initial value, and at the same time sending the trigger signal to an oscilloscope; obtaining the change time of the trigger signal and the change time of the detected signal from the oscilloscope; and obtaining the phase switching stabilization time based on the difference between the change time of the trigger signal and the change time of the detected signal.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of electronic device testing, and involve, but are not limited to, a method for testing the phase switching settling time, a control module, and a program product. Background Art

[0002] In a phased array transmit-receive chip with beamforming, the gain and directivity of the subsequent phased array antenna can be changed by adjusting the phases of the respective radio frequency channels in the phased array to meet different communication or detection requirements. Specifically, a phase shifter (PS) is integrated in the transmit channel and / or receive channel of the transmit-receive chip. By changing the register value of the phase shifter, the phase of the radio frequency signal passing through the phase shifter can be changed, thereby realizing the control of the electromagnetic wave beam.

[0003] The phase switching settling time of the phase shifter refers to the time required for the phase shifter to reach a stable state in response to a trigger signal when the register value of the phase shifter is changed from one value to another under the control of the trigger signal. The length of the phase switching settling time directly affects the phase switching speed in the system. If the phase switching settling time is too long and the switching speed is too slow, on the one hand, the accuracy of the phased array beam pointing will be reduced; on the other hand, too long a phase switching settling time may lead to unstable phase switching, thereby introducing distortion products, interfering with the transmission and reception of signals, and reducing the overall performance of the system. Therefore, when designing a phased array transmit-receive chip, it is necessary to consider the phase switching settling time characteristics of the phase shifter to ensure that the system can meet specific performance requirements.

[0004] How to improve the detection success rate and measurement accuracy of the phase switching settling time has become an urgent problem to be solved currently. Summary of the Invention

[0005] In view of this, embodiments of the present disclosure provide a method for testing the phase switching settling time, a control module, and a program product, which can improve the detection success rate and measurement accuracy of the phase switching settling time.

[0006] On the one hand, embodiments of the present disclosure provide a method for testing the phase switching settling time, where the component to be tested includes: a first radio frequency channel and a second radio frequency channel, the first radio frequency channel includes a first phase shifter and a first register, and the second radio frequency channel includes a second phase shifter and a second register;

[0007] The method includes:

[0008] Traversing and assigning values to the first register and / or the second register to change the phase shift of the first phase shifter and / or the second phase shifter,

[0009] At each of the said assignments, obtain the value of the detected signal, where the detected signal is obtained by detecting the signal after combining the first radio frequency channel and the second radio frequency channel;

[0010] Take the value of the first register and / or the second register when the detected signal is maximum or minimum as the initial value;

[0011] Based on the initial value, change the value of the first register and / or the second register through a trigger signal, so that the combined signal is phase-shifted by 180° relative to the initial value, and at the same time send the trigger signal to the oscilloscope;

[0012] Obtain the change time of the trigger signal and the change time of the detected signal from the oscilloscope;

[0013] Based on the difference between the change time of the trigger signal and the change time of the detected signal, obtain the phase switching stable time.

[0014] On the other hand, an embodiment of the present disclosure further provides a control module, where the control module includes a processor and a memory;

[0015] The processor is configured to execute the instructions stored in the memory, so that the control module executes any of the above methods.

[0016] On yet another aspect, an embodiment of the present disclosure further provides a computer program product, including instructions, which when running on a computer, cause any of the above methods to be executed.

[0017] The test method provided by the embodiment of the present disclosure includes traversing and assigning values to the first register and / or the second register; at each of the said assignments, obtaining the value of the detected signal; taking the value of the first register and / or the second register when the detected signal is maximum or minimum as the initial value; based on the initial value, changing the value of the first register and / or the second register, so that the first phase shifter and / or the second phase shifter are phase-shifted by 180° relative to the initial value, and at the same time sending a trigger signal to the oscilloscope; obtaining the change time of the trigger signal and the change time of the detected signal from the oscilloscope; based on the difference between the change time of the trigger signal and the change time of the detected signal, obtaining the phase switching stable time.

[0018] By finding the initial value, making the detected signal maximum or minimum, at this time the phase shifts of the first phase shifter and the second phase shifter differ by 0° or 180°, and the amplitude of the detected signal reaches a preset extreme value (maximum or minimum), which can be used as the basis for subsequent comparison;

[0019] Based on the initial value, control the values of the first register and / or the second register to be phase-shifted by 180° relative to the initial value. The detected signal changes from the maximum value to the minimum value, or from the minimum value to the maximum value. Therefore, compared with the initial value, the amplitude change of the detected signal is obvious, and there is a large enough voltage difference, so that the rising / falling edge of the detected signal can be accurately identified, improving the accuracy of the phase switching stability time test.

[0020] In addition, in this solution, the registers are sequentially assigned values to find the register values corresponding to the maximum or minimum of the detected signal after combining, and use them as the initial values, so that the register values in the state where the phases of the two phase shifters are closest to in-phase or anti-phase can be found, enhancing the obviousness of the signal change during testing, and further improving the test accuracy.

[0021] This solution can sequentially assign values to the registers, enabling automated testing. The use of an algorithm realizes fast initial phase optimization, maximizing the test efficiency while ensuring accuracy.

[0022] This solution can adopt single-channel initial value optimization and calibration: fix the value of the first register and traverse all values of the second register; or fix the value of the second register and traverse all values of the first register. It can effectively reduce the number of traversals of the register values, significantly shorten the test time, and improve the test efficiency.

[0023] This solution also introduces a decision level difference threshold: determine whether the difference between the detected signal in the middle and the detected signals on both sides is greater than a preset value. When the difference between the detected signal in the middle and the detected signals on both sides is greater than the preset value, the initial value is confirmed, avoiding test errors caused by noise on the oscilloscope link, and further improving the reliability and stability of the test. Description of the Drawings

[0024] Figure 1A It is a structural block diagram of the test platform in the embodiments of the present disclosure;

[0025] Figure 1B It is a schematic structural diagram of the device under test (DUT) in the test platform in the embodiments of the present disclosure;

[0026] Figure 2 It is a schematic diagram showing the relationship between the input power and the detected voltage of a logarithmic detector in the embodiments of the present disclosure;

[0027] Figure 3 It is a schematic diagram of the waveforms of a trigger signal and a detected signal shown by an oscilloscope in the embodiments of the present disclosure;

[0028] Figure 4 It is a schematic diagram of the test principle of the phase switching stability time in the embodiments of the present disclosure;

[0029] Figure 5 Schematic diagram of the test principle of another phase switching stabilization time in the embodiments of the present disclosure;

[0030] Figure 6 Schematic diagram of another trigger signal and detected signal waveforms shown by an oscilloscope in the embodiments of the present disclosure;

[0031] Figure 7 Schematic diagram of another test principle of phase switching stabilization time in the embodiments of the present disclosure;

[0032] Figure 8 Flowchart of a method for testing phase switching stabilization time provided by the embodiments of the present disclosure;

[0033] Figure 9A Schematic diagram of state 0 in the test method provided by the embodiments of the present disclosure;

[0034] Figure 9B Schematic diagram of state 1 in the test method provided by the embodiments of the present disclosure;

[0035] Figure 9C Schematic diagram of state 2 in the test method provided by the embodiments of the present disclosure;

[0036] Figure 10 Flowchart of the first traversal assignment method in the test method provided by the embodiments of the present disclosure;

[0037] Figure 11 Flowchart of the second traversal assignment method in the test method provided by the embodiments of the present disclosure;

[0038] Figure 12 Flowchart of the third traversal assignment method in the test method provided by the embodiments of the present disclosure;

[0039] Figure 13 Flowchart of the fourth traversal assignment method in the test method provided by the embodiments of the present disclosure;

[0040] Figure 14 Structural block diagram of a control module provided by the embodiments of the present disclosure. Detailed implementation manners

[0041] To facilitate the understanding of the present disclosure, the present disclosure will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present disclosure more thorough and comprehensive.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this disclosure pertains. The terms used in the description of this disclosure in this specification are only for the purpose of describing specific embodiments and are not intended to limit this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the related listed items. In the embodiments of this disclosure, the terms "first", "second", "third", and "fourth" are used only for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second", "third", and "fourth" may explicitly or implicitly include one or more of such features.

[0043] It should be understood that in the description of the embodiments of this disclosure, it should be noted that unless otherwise clearly specified and limited, the terms "connected" and "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a direct connection or an indirect connection through an intermediate medium, and it may be the internal communication of two components.

[0044] The beamforming transmit-receive (TR) chip of a phased array is the core integrated circuit for realizing the functions of beamforming and phased array antenna. It forms a directional beam by controlling the phase and amplitude of multiple antenna elements, thereby improving the signal quality, coverage range, and anti-interference ability of the communication system.

[0045] Beamforming refers to adjusting the phase and amplitude of each unit in the antenna array to enhance the signal superposition in a specific direction and weaken it in other directions.

[0046] A phased array refers to using electronic control of the phase difference to achieve rapid beam scanning without mechanically rotating the antenna.

[0047] Exemplarily, the phased array TR chip may include a radio frequency front end, a phase / amplitude control module, a beamforming algorithm module, an integrated transceiver switch, and a calibration and compensation circuit, etc.

[0048] For the beamforming phased array TR chip, its transmit or receive channel integrates a phase shifter (PS). Each PS corresponds to a register. When the value of the PS register changes, the phase of the radio frequency signal passing through the radio frequency channel corresponding to this PS register also changes, thereby changing the gain and directivity of the subsequent phased array antenna to meet different communication / detection scenarios.

[0049] The phase switching stabilization time of the PS is used to represent the time between when the PS receives a trigger signal (such as a trigger signal indicating a change in the register value) and when the output phase stabilizes at the target value. This parameter directly affects the beam scanning rate and system real-time performance, and is particularly crucial in scenarios with rapid movement, such as radar tracking, satellite communication, and other scenarios.

[0050] Register value refers to the numerical value stored in the register.

[0051] In some embodiments, the test of the phase switching stabilization time can be carried out through a test platform as Figure 1A shown. The test platform includes at least one device under test (DUT) 110, a signal generator 120, a combiner 130, a detector 140, an oscilloscope 150, and a control module 160. In addition, the test platform may further include a power supply module connected to the DUT 110 for providing a power supply voltage, and the control module 160 may also be connected to a host computer, which is used to provide relevant trigger signals or register values, etc.

[0052] Among them, the DUT 110 can be the above-mentioned phased array TR chip for beamforming. The signal generator 120 is used to output a test RF signal, which is input into the DUT 110 through the RF input port (RF in) of the DUT 110. After the signal passes through the internal circuit of the DUT 110, two RF signals are output at two RF output ports RF1 out and RF2 out; the two RF signals are vectorially added by the combiner 130 to obtain a combined RF signal, and then the combined RF signal is converted into a DC detection signal by the detector 140 and then enters the oscilloscope 150. The oscilloscope 150 is used to display the waveform of the detection signal.

[0053] Exemplarily, the structure of the DUT 110 can refer to the Figure 1B shown structure. The DUT 110 includes a first RF channel CH1 and a second RF channel CH2. The first RF channel CH1 includes a first phase shifter 01 and a first register 03, and the second RF channel CH2 includes a second phase shifter 02 and a second register 04. The value of the first register 03 is used to control the phase shift value of the first phase shifter 01, and the value of the second register 04 is used to control the phase shift value of the second phase shifter 02. That is to say, each PS corresponds to a register, and by changing the register value of the register corresponding to the PS, the phases of the RF signals output by the RF channel CH1 and the RF channel CH2 can be changed. The DUT 110 may further include a combiner / splitter 05, and the combiner / splitter 05 is used to divide a path of RF signal at the RF input port (RF in) into two paths, and the first phase shifter 01 and the second phase shifter 02 can be connected and receive the RF signals provided by the combiner / splitter 05.

[0054] It should be noted that the component to be measured can have multiple radio frequency channels, such as 3, 4, etc. Each radio frequency channel can include devices such as a phase shifter. When detecting the phase switching stabilization time, any 2 radio frequency channels can be selected for detection. For example, if the component to be measured has 3 radio frequency channels, the first and second radio frequency channels can be selected first for detection, and then the first and third or the second and third radio frequency channels can be selected as the first and second radio frequency channels respectively for detection.

[0055] In some embodiments, the first register can be disposed within the first phase shifter or can be separately disposed. Similarly, the second register can be located within the second phase shifter or can be disposed independently of the second phase shifter.

[0056] In addition, it can be understood that the values of the first register and the second register can be switched by a trigger signal provided externally. The trigger signal can be provided to the register through the interface of the control module to write a new value into the register, thereby realizing the switching of the register values. The oscilloscope 150 is also used to display the waveform of the trigger signal.

[0057] It should be noted that the above two radio frequency channels can be located on the same chip or can be located on different chips respectively. Figure 1A and Figure 1B shows that the two radio frequency channels can be located on the same chip. The embodiments of the present disclosure are not limited to this structure. The two radio frequency channels can be the same. Specifically, the two radio frequency channels have the same phase shifter, and other various elements (such as attenuators) in the channels are the same.

[0058] In some embodiments, the detector 140 is a measurement tool that converts a radio frequency input signal into a DC voltage signal, and the output voltage value is proportional to the power of the input signal. Therefore, according to the output voltage value of the detector 140, the power value of the input radio frequency signal can be correspondingly determined. The detector can be a logarithmic detector, an envelope detector, a phase-locked loop detector, a coherent detector, etc.

[0059] The input-output relationship of the logarithmic detector can be referred to the following formula (1):

[0060] (1)

[0061] Wherein, is the detected level output by the detector, with the unit of V (volt), is the logarithmic slope of the detector, with the unit of V / dB (volt per decibel), is the input signal power, with the unit of dBm (decibel-milliwatt), is the logarithmic intercept, with the unit of dBm (decibel - milliwatt).

[0062] When the logarithmic detector is a positive - slope detector. When the input power is minimum, the detected level is minimum; when the logarithmic detector is a negative - slope detector. When the input power is minimum, the detected level is maximum. Figure 2 Fig. shows a schematic diagram of the input power and detected voltage of a logarithmic detector, and the negative - slope detector is adopted in this figure.

[0063] When testing the phase - switching stabilization time of PS, usually one RF channel does not change its amplitude and phase, and the other RF channel keeps the amplitude unchanged while the phase changes. The phase and amplitude of the combined signal change. At this time, the amplitude of the output signal at the output end of the combiner 130 changes accordingly, that is, the voltage value of the detected signal of the detector 140 changes. At this time, the effective rising / falling edge of the detected signal can be read on the oscilloscope 150.

[0064] Combined with Figure 1A and Figure 1B 's test platform, the test process can refer to Figure 3 . As Figure 3 shown, State 1 (S1) is the starting state. At this time, the first register 03 and the second register 04 are written with their respective values, and the first phase shifter 01 and the second phase shifter 02 are controlled to phase - shift the RF signals flowing through them respectively. Assume that at State 1, the phase - shifts of the two phase shifters are the same, the amplitudes of the output signals of RF channel CH1 and RF channel CH2 are the same (both are 1), and the phases of the two channels are also the same (both are ∠0°). For the sake of convenience, the amplitude and phase are normalized to 1∠0°; where 1 represents the normalized amplitude and ∠0° represents the phase; after vector addition by the combiner 130, the output signal is 2∠0°, and assume that the detected signal level of the detector 140 is 0.9V at this time.

[0065] At State 2 (S2), the control module 160 sends a trigger signal to the DUT 110 and the oscilloscope 150. The trigger signal is an input signal used to start the change of the phase shifter and is provided by the control module. For example, after the trigger signal is sent, the register value of the first register 03 remains unchanged, the register value of the second register 04 changes, the phase - shift of the second phase shifter 02 changes, the PS of RF channel CH1 remains unchanged, and the PS of RF channel CH2 changes by 90°. After vector addition by the combiner 130, the output signal is ∠45°, and assume that the detected signal level of the detector 140 is 1.2V at this time.

[0066] Because the detected signal levels in state 1 and state 2 are different, the effective rising / falling edges of the detected signal can be read on the oscilloscope 150; when the level change is stable, it indicates that the PS setting of the RF channel CH2 is completed (i.e., the phase is stably switched to the post-switching state), and this is the termination state at this time.

[0067] In the embodiments of the present disclosure, the above phase switching stabilization time can be defined as the response speed of the PS to the trigger signal for the change in the register value when the register receives the trigger signal and changes from one value to another. For example, it can be defined as 50% of the rising / falling edge of the trigger signal to 90% or 95% or 99% etc. of the change in the detected signal, and specifically can be set according to the actual accuracy requirements.

[0068] As Figure 4 shown, the upper part of the figure shows the level waveform of the trigger signal, that is, waveform 1. Waveform 1 represents the control signal for switching the PS register value. In this embodiment, the falling edge in waveform 1 represents the control module 160 sending a trigger signal to the DUT 110 and the oscilloscope 150. The lower part of the figure shows the level of the detected signal output by the detector, that is, waveform 2, and the two waveforms are aligned in time. If the phase switching stabilization time of the PS is set to 50% of the falling edge of waveform 1 to 90% of the rising edge of the detected level, it can be shown as the distance between the two vertical dotted lines shown in the figure. Specifically, 50% of the falling edge of waveform 1 represents 50% of the high level and low level of waveform 1, and the ordinate position corresponding to the intersection of this horizontal dotted line and waveform 1 is the moment t1 of the vertical dotted line. 90% of the rising edge of waveform 2 represents 90% of the change from the low level to the high level of waveform 2, and the ordinate position corresponding to the intersection of this horizontal dotted line and waveform 2 is the moment t2 of the second vertical dotted line. The time period t between t1 and t2 is used to represent the phase switching stabilization time.

[0069] Since the detector 140 can only "scalarially" convert the power of the RF signal into voltage, if a high-frequency signal has a constant amplitude and only the phase changes, then the output voltage corresponding to the detector 140 will not change, and the waveform read on the oscilloscope 150 will be a horizontal straight line. At this time, the effective rising / falling edges of the detected signal cannot be read on the oscilloscope 150. As Figure 5 shown, in state 1, the amplitudes of the RF channel CH1 and the RF channel CH2 are the same and the phases are different (for example, differ by 180°), and the combined output at this time is ∠45°. In state 2, after the register value of the RF channel CH2 changes by +180°, the combined output at this time is ∠-45°. Therefore, in states 1 and 2, the scalar power entering the detector is always , the change range of the voltage change is too small, and the clutter interference during the test, the overshoot and undershoot of the radio frequency signal, and the non-ideal characteristics will cause the oscilloscope 150 to misidentify the rising / falling edge of the detected signal, resulting in an incorrect test result, such as Figure 6 as shown.

[0070] The applicant's research found that if the amplitude of the signal of the detector changes significantly after switching from state 1 to state 2, the rising / falling edge of the detected signal can be accurately identified. As Figure 7 shown, the signal amplitudes and phases of the radio frequency channel CH1 and the radio frequency channel CH2 are the same. At this time, the combined output is 2∠0°. In state 2, after the register value of the radio frequency channel CH2 changes by +180°, the combined output at this time is 0, and the scalar power entering the detector changes from 2 to 0, with an obvious change, and the rising / falling edge of the detected signal can be accurately identified, meeting the test requirements.

[0071] Based on this, the embodiments of the present disclosure provide a method for testing the phase switching stable time. By presetting the phases of two radio frequency channels, the amplitude of the combined signal changes significantly after switching from state 1 to state 2, so as to accurately test the phase switching stable time.

[0072] The test method provided by the embodiments of the present disclosure is as Figure 8 shown. Combining with the Figure 1A test platform shown, this method includes:

[0073] Step S101, traverse and assign values to the first register and / or the second register to change the phase shift of the first phase shifter and / or the second phase shifter; wherein, the value range of the traverse assignment depends on the phase adjustment range of the phase shifter;

[0074] Step S102, at each assignment, obtain the value of the detected signal. The detected signal is the voltage signal extracted by the detector 140 after the two radio frequency signals are vectorially superimposed by the combiner 130; in addition, the value of the detected signal can also be read out by the oscilloscope 150; the value of the detected signal can be understood as the amplitude size of the detected signal, which can reflect the amplitude of the combined signal;

[0075] Step S103, take the value of the first register and / or the second register when the detected signal is the largest or the smallest (the maximum or minimum value can be determined by the reading of the oscilloscope 150) as the initial value; when the detected signal is the largest, the phases of the two radio frequency signals are the same; when the detected signal is the smallest, the phases of the two radio frequency signals are opposite; when the detected signal is the largest or the smallest, the amplitude of the combined signal is the largest or the smallest, which means that the amplitude of the detected signal reaches the preset extreme value (the maximum or minimum value), and this is used as the basis for testing the phase switching stable time, which helps the amplitude of the detected signal to change significantly;

[0076] Step S104: Based on the initial value, the control module 160 sends a trigger signal to the DUT 110 to change the values of the first register and / or the second register, so that the signal after combining by the combiner 130 is phase-shifted by 180° relative to the initial value. Meanwhile, a trigger signal is sent to the oscilloscope, and the oscilloscope can display the rising edge or the falling edge of the trigger signal. The signal after combining by the combiner 130 being phase-shifted by 180° relative to the initial value includes two cases: when the two RF signals change from being in the same phase to being in the opposite phase, the detected signal changes from the maximum to the minimum, showing an obvious change; or when the two RF signals change from being in the opposite phase to being in the same phase, the detected signal changes from the minimum to the maximum, showing an obvious change.

[0077] Step S105: Obtain the change time of the trigger signal and the change time of the detected signal from the oscilloscope 150; the change time of the trigger signal can be the occurrence time of the rising edge or the falling edge of the trigger signal, such as 50% of the rising / falling edge of the trigger signal; the change time of the detected signal can be the time when the value of the detected signal changes to a certain extent, such as 90%, 95% or 99% of the rising / falling edge of the detected signal.

[0078] Step S106: Based on the difference between the change time of the trigger signal and the change time of the detected signal, obtain the phase switching stabilization time.

[0079] In the embodiment of the present disclosure, before performing the phase switching stabilization time test, the combinations of the register values of the RF channel CH1 and the RF channel CH2 are traversed first to find the minimum or maximum value of the amplitude after the vector addition of the two signals, and record the values of the PS registers of the two channels at this time as the "initial value".

[0080] When the PS register of one of the RF channels starts to be phase-shifted with the "initial value" as the reference, the combined output will increase or decrease significantly. A relatively large difference in the detected signal level before and after the trigger signal can be seen on the oscilloscope, meeting the test requirements for the PS phase switching stabilization time, and the change time of the trigger signal and the change time of the detected signal can be accurately found, so as to obtain the accurate phase switching stabilization time.

[0081] Here, traversing and assigning values means changing the value of at least one of the first register and the second register each time, thereby changing the phase shift value of the first phase shifter or the second phase shifter, and changing the register values multiple times. It can be understood that the set value of each register corresponds to the phase shift value of the phase shifter. The register value can include a preset number of different values, and each value can correspond to a different phase. The number of register values can be set according to the phase shift accuracy requirements. When the number of register values is small, the phase shift accuracy is low; when the number of register values is large, the phase shift accuracy can be high. It should be noted that the correspondence between the register value and the phase can be linear, non-linear or irregular, as long as the phase corresponding to each value is clear, and when performing phase shift, the value of the register can be modified to the value corresponding to the required phase through a trigger signal.

[0082] In addition, the above traversing and assigning values can be traversing all possible amplitudes of the register, or only traversing some of the set values, or stopping traversing other assignments when a register value that meets the conditions is traversed.

[0083] Since in the initial state, the correspondence between the register value and the phase is unknown, as Figure 9A shown, the current state is set to state 0 here. This is a non-ideal situation after powering on the component to be measured. The amplitudes and phases of radio frequency channel CH1 and radio frequency channel CH2 are uncertain. For the sake of simplicity of description, it is assumed that the amplitudes of radio frequency channel CH1 and radio frequency channel CH2 are the same and the phases are different. Exemplarily, as Figure 9A in the case of, the register value is an integer, and different numbers correspond to different phases. Exemplarily, the register can include 64 values from 0 to 63, corresponding to 64 different phases. In the default state, the register value of radio frequency channel CH1 is PS = 0, while the actual signal is 1∠45°, and the register state of radio frequency channel CH2 is PS = 0, while the actual signal is 1∠90°. At this time, the combined output is 0.77∠-22.5°.

[0084] In the embodiments of the present disclosure, through the above step S101, the first register and / or the second register are traversed and assigned values, and after each assignment, the value of the detection signal is obtained through the above step S102 to determine the combined output situation. It should be noted that the above step S101 and step S102 are repeatedly and alternately performed, or can be understood as being executed multiple times simultaneously, and are not executed in the order of the step numbers. The above order of each step number is only for convenience of description and does not limit the execution order of the method.

[0085] Then, after traversing the values, the phase state that meets the requirements is found as the calibrated initial state, as Figure 9BThe state 1 shown, namely the above-mentioned step S103. Exemplarily, in the embodiments of the present disclosure, the maximum or minimum value of the detection signal can be used as the calibrated initial value. In this way, the most obvious test effect can be obtained during subsequent tests. Then enter the test process and execute step S104. Based on the initial value obtained after calibration corresponding to state 1, change the values of the first register and / or the second register again, so that the first phase shifter and / or the second phase shifter are phase-shifted by 180° relative to the initial value.

[0086] For example, in the case of state 1, the detection signal is the minimum value. At this time, the amplitude of the output signal of the combiner 130 is 0, as Figure 9B shown. At this time, the register value of the radio frequency channel CH1 is PS = 55, and the register value of the radio frequency channel CH2 is PS = 47. At this time, the phase of the radio frequency channel CH1 is 0°, the phase of the radio frequency channel CH2 is 180°, and the combined output bit 0 has the maximum negative slope detection level (the positive slope detection level is the minimum). It can be seen that the phase of the radio frequency channel CH2 is switched from 90° to 180°, and the register value changes from 0 to 47. It should be noted that the register values here are only examples. In actual applications, the register value setting ranges and the corresponding phases of different products are different.

[0087] During the test process, taking the above state 1 as the initial state, maintain the register setting value of the radio frequency channel CH1 as PS = 55. And send a trigger signal to switch the register value of the radio frequency channel CH2. Exemplarily, as Figure 9C shown in state 2, set the register value to PS = 15, so that the phase of the radio frequency channel CH2 is switched from 180° to 0°, and the combined output is 2∠0°, and the negative slope detection level is the minimum (the positive slope detection level is the maximum).

[0088] It should be noted that the phase shift of the combined signal by 180° relative to the initial value proposed in the present disclosure can be understood as approximately 180°. Due to the influence of the phase shift value accuracy of the register setting, it may not be possible to achieve an accurate phase shift of 180° by adjusting the register value through the drive signal. Therefore, the phase shift from state 1 to state 2 can also be a phase shift slightly greater than or slightly less than 180°, such as a phase shift of 179° or 181°, or even 175°, 170°, 165°, 185°, etc. As long as it meets the phase shift range that can clearly detect the phase switching stable time, it is acceptable.

[0089] In addition, a 180° phase shift can be achieved by fixing one channel and phase-shifting the other channel. For example, fix the RF channel CH1 and phase-shift the RF channel CH2 by 180°; or fix the RF channel CH2 and phase-shift the RF channel CH1 by 180°. In addition, it can also be achieved by phase-shifting both the RF channel CH1 and the RF channel CH2 so that the combined signal of the two is phase-shifted by 180° in total. For example, the RF channel CH1 is phase-shifted by -90° and the RF channel CH2 is phase-shifted by 90°; or the RF channel CH1 is phase-shifted by 100° and the RF channel CH2 is phase-shifted by 80°, and so on.

[0090] In this way, in the embodiment of the present disclosure, by finding the initial value to make the detected signal maximum or minimum, at this time, the phase shifts of the first phase shifter and the second phase shifter differ by 0° or 180°, so that the amplitude of the detected signal reaches a preset extreme value (maximum or minimum), which can be used as the basis for subsequent comparison;

[0091] Based on the initial value, control the values of the first register and / or the second register to be phase-shifted by 180° relative to the initial value, and the detected signal changes from the maximum value to the minimum value, or from the minimum value to the maximum value. Therefore, compared with the initial value, the amplitude change of the detected signal is obvious, and there is a large enough voltage difference, so that the rising / falling edge of the detected signal can be accurately identified, improving the accuracy of the phase switching stability time test.

[0092] In addition, in this solution, the registers are sequentially assigned values to determine the initial value, which can accurately find the register values when the detected signal is maximum or minimum, avoiding the phase error that occurs when the first phase shifter and the second phase shifter have different register values, and can further improve the accuracy of the test.

[0093] In some embodiments, the step of traversing and assigning values to the first register and / or the second register includes:

[0094] Traverse all the values of the first register;

[0095] For each value of the first register, traverse all the values of the second register.

[0096] Exemplarily, assume that the first phase shifter or the second phase shifter is a 6-bit digital phase shifter, and the numerical values of 2 6 registers correspond to 64 different phases. Exemplarily, the register values can be consecutive numerical values from 0 to 63.

[0097] First, fix the RF channel CH1, that is, the value of the first register, traverse all the register values of the RF channel CH2, record the detected voltage of the combined output RF signal monitored on the oscilloscope, and obtain 64 groups of detected voltages.

[0098] Then, increment the register value of RF channel CH1 by 1, and traverse all the register values of RF channel CH2 again. Record the detected voltage of the combined output RF signal read on the oscilloscope. In this way, for all 64 values of RF channel CH1, traverse all 64 values of RF channel CH2 until all cases are traversed. Thus, a total of 64 × 64 = 4096 cases are traversed.

[0099] Among the 4096 detected levels, find the case with the minimum RF combined output of RF channel CH1 and RF channel CH2 as the initial register value.

[0100] Exemplarily, for the specific traversal process, reference can be made to the Figure 10 shown process.

[0101] Here, it is described in combination with the Figure 1A control program of the control module 160 in the shown platform:

[0102] Step S201: Determine that the value of the first register in RF channel CH1 is PS = i, and the value of the second register in RF channel CH2 is PS = j, and i = j = 0;

[0103] That is, initialize the register assignment data of the control module 160 for RF channel CH1 and RF channel CH2.

[0104] Step S202: Write the register value i into RF channel CH1 and the register value j into RF channel CH2, read the detected voltage on the oscilloscope, and record it as V_PSi_PSj;

[0105] After providing the initialized values to the first register and the second register, the first phase shifter and the second phase shifter both output corresponding phase shift signals. After being combined by the combiner 130, they are output to the detector 140. The detector 140 converts the RF signal into a DC detected signal and reads it out by the oscilloscope 150.

[0106] Step S203: Determine whether all the register values of RF channel CH2 have been traversed. If so, enter step S204. If not, set j = j + 1 and enter step S202;

[0107] In this step, the control module 160 can determine whether the traversal is completed according to all the preset values of j that need to be traversed, or the preset maximum value of j, and determine whether the current j is equal to the maximum value. If so, it proves that the traversal is completed.

[0108] Step S204: Determine whether all the register values of RF channel CH1 have been traversed. If so, enter step S205. If not, set i = i + 1 and enter step S202;

[0109] In this step, the control module 160 can also determine whether the traversal is completed according to all the preset values of i to be traversed, or the preset maximum value of i, and determine whether the current j is equal to the maximum value. If so, it proves that the traversal is completed.

[0110] Step S205: Among all 4096 cases from the detection voltage V_PS0_PS0 to V_PS63_PS63, find the maximum or minimum value, and record the register values of the radio frequency channel CH1 and the radio frequency channel CH2 at this time as the initial values: PS_init1 and PS_init2.

[0111] The control module 160 can be used to read and compare multiple values of the oscilloscope, or the oscilloscope 150 can compare multiple values until the maximum or minimum value is found.

[0112] It can be seen that in this solution, by sequentially assigning values to the registers, automated testing can be achieved, and fast initial phase optimization is realized using an algorithm, which maximally improves the testing efficiency while ensuring accuracy.

[0113] In some embodiments, the step of traversing and assigning values to the first register and / or the second register includes:

[0114] Fix the value of the first register and traverse all the values of the second register;

[0115] Or, fix the value of the second register and traverse all the values of the first register.

[0116] For the convenience of comparison and description, it is still assumed here that the first phase shifter or the second phase shifter is a 6-bit digital phase shifter, and 2 6 register values correspond to 64 different phases. Exemplarily, the register values can be consecutive values from 0 to 63.

[0117] In this solution, it is possible to only traverse all the values of the registers in one channel and fix the other channel, that is, adopt single-channel initial value optimization and calibration. For example, fix the register value in the radio frequency channel CH1 and traverse all the register values of the radio frequency channel CH2, and record that a total of 64 cases of the detected voltage of the combined RF output signal are read on the oscilloscope. Among the 64 detected levels, find the case where the combined RF output of the radio frequency channel CH1 and the radio frequency channel CH2 is the smallest as the initial register value.

[0118] Exemplarily, the above traversal process can refer to the process shown in Figure 11 as follows.

[0119] Step S301: Determine that the value of the first register PS in the radio frequency channel CH1 is 0, the value of the second register PS in the radio frequency channel CH2 is i, and set i = 0;

[0120] That is, initialize the register value. The fixed register value of radio frequency channel CH1 is 0, so a radio frequency signal with a fixed phase is output.

[0121] Step S302: Write the value i into the register in radio frequency channel CH2, read the detected voltage on the oscilloscope, and record it as V_PSi.

[0122] Similarly, provide the register value to the corresponding register for assignment, so that radio frequency channel CH2 outputs a corresponding radio frequency signal. After being combined with the radio frequency channel CH1 with a fixed phase by the combiner 130, it is provided to the detector 140, and the detected signal, that is, the above-mentioned detected voltage V_PSi, is read out through the oscilloscope 150.

[0123] Step S303: Determine whether all register values of radio frequency channel CH2 have been traversed. If so, enter step S304; if not, set i = i + 1 and enter step S302.

[0124] Here, the maximum value of i or all i values to be traversed can be preset by the control module, and then it is determined whether the traversal is completed.

[0125] Step S304: Among all 64 cases of the detected voltages V_PS0 to V_PS63, find the maximum or minimum value, and record the register value of radio frequency channel CH2 at this time as the initial value: PS_init2 (in addition, the initial value of radio frequency channel CH1 is still 0).

[0126] In this step, the control module 160 can also be used to read each detected voltage, or the oscilloscope 150 itself can be used to compare each detected voltage to find the maximum or minimum value.

[0127] This method only needs to traverse the values of one register, which can effectively reduce the traversal times of the register values, significantly shorten the test time, and improve the test efficiency.

[0128] In some embodiments, the step of traversing and assigning values to the first register and / or the second register includes: sequentially assigning 3 consecutive values to the first register or the second register;

[0129] In each assignment, the step of obtaining the value of the detected signal includes: obtaining 3 detected signals corresponding to 3 consecutive values;

[0130] The step of traversing and assigning values to the first register and / or the second register further includes:

[0131] Judging whether the magnitude of the middle detected signal is the maximum or minimum value among the 3;

[0132] If not, sequentially step 3 consecutive values and sequentially assign the first register or the second register;

[0133] If so, stop changing the assignments to the first register and the second register.

[0134] Here, by means of finding the extreme points, the maximum or minimum value of the detection signal is quickly found. Since the corresponding relationship between the numerical change of the register and the phase can be regular, therefore, if the middle value among three consecutive detection signals is the maximum or minimum value, then this value can be determined as the maximum or minimum value among all possible detection signals. If among the detection signals corresponding to three consecutive values, the first or the third detection signal is the maximum or minimum value, it indicates that the detection signal corresponding to the value will continue to rise or fall. Therefore, the detection signals corresponding to the three consecutive values at this time cannot be regarded as the maximum or minimum value, and it is necessary to move one value and take the next group of three consecutive values for detection.

[0135] Still assume that the first phase shifter or the second phase shifter is a 6-bit digital phase shifter, and the numerical values of 2 6 registers correspond to 64 different phases. Exemplarily, the register values can be consecutive numerical values from 0 to 63. At this time, the value of one register can be fixed and the values of the other register can be traversed.

[0136] Exemplarily, for the first time, select the register values 0, 1, and 2 and obtain the corresponding detection signals. If the values of these three detection signals increase or decrease in sequence, it indicates that the maximum or minimum value has not been found. Then continue to select the case where the register values are 1, 2, and 3 and obtain the corresponding detection signals. Until among the three detection signals, the second detection signal is the maximum or minimum value. It can be understood that the number of times of detection required in this way ranges from 1 to 63 times. For example, for the first detection, select the register values 0, 1, and 2. In the case where the register value is 1, the value of the detection signal is the largest or the smallest. Then at this time, the continuous detection can be stopped and the case where the register value is 1 can be set as the initial value. If the maximum or minimum value of the middle detection signal is not found after multiple detections, and when the last group is detected, such as when the register values are 61, 62, and 63, and still not found, it indicates that when the register value is 0 or 63, the detection signal is the maximum or minimum value, that is, the detection signal increases or decreases monotonically with the increase of the register value. Therefore, in this case, one of the cases where the register value is 0 or the register value is 63 can be selected as the initial value of this register.

[0137] To further simplify the algorithm, the idea of the dichotomy method can be utilized. Start the detection from the middle value of the register and traverse sequentially in one direction of decreasing or increasing. For the sake of illustration, assume here that the value of the register ranges from -32 to 31, with 0 as the initial register value. Select three consecutive values of -1, 0, and 1 as the first group for detection. If the corresponding detection signals increase sequentially, it indicates that the maximum value is the voltage value of the detection signal corresponding to a certain value of the register from 1 to 31, and the minimum value is the voltage value of the detection signal corresponding to a certain value of the register from -32 to 0. On the contrary, if the corresponding detection signals decrease sequentially, it indicates that the minimum value is the voltage value of the detection signal corresponding to a certain value of the register from 1 to 31, and the maximum value is the voltage value of the detection signal corresponding to a certain value of the register from -32 to 0.

[0138] According to the slope of the detector, the maximum or minimum value can be selected as the initial value. For example, if the detector is a negative slope detector, the initial value can be determined according to the maximum value; if the detector is a positive slope detector, the initial value can be determined according to the minimum value. In fact, the negative slope detector can also use the minimum value, and the positive slope detector can also use the maximum value, but the detection effect of the obvious degree may be slightly inferior, but it does not affect the detection of the subsequent phase switching stable time.

[0139] It can be seen that the above process only needs to traverse sequentially forward or backward. Therefore, it only needs to traverse 32 times at most to find the maximum or minimum value, which can reduce the detection times and improve the efficiency compared with the above several methods.

[0140] In some embodiments, when determining whether the size of the middle detection signal is the maximum among the three, the step of stepping three consecutive values sequentially includes:

[0141] If the three consecutive detection signals decrease sequentially, the three consecutive values step in the decreasing direction;

[0142] If the three consecutive detection signals increase sequentially, the three consecutive values step in the increasing direction.

[0143] In some embodiments, the step of using the value of the register when the detection signal is the largest or smallest as the initial value includes: using the middle value of the three consecutive values when the assignment stops as the initial value.

[0144] When starting the test, record the value of the PS register as i. First, test the three cases of PS = i - 1 / i / i + 1, and judge whether the value of the register at this time is in the decreasing interval of the combined output / the increasing interval of the combined output / the extreme value (the choice of the maximum value or the minimum value can be determined according to the slope of the detector);

[0145] If in the combined output falling / rising interval, the value of i moves towards the peak direction until, when a certain value of i is reached, the detected voltage is at the peak.

[0146] Exemplarily, the above traversal process can refer to the Figure 12 flow shown as follows. Here, finding the maximum value is taken as an example for illustration.

[0147] Step S401: Set i = 0; set the register value of radio frequency channel CH1 to 0;

[0148] That is, the register values of radio frequency channel CH1 and radio frequency channel CH2 are initialized through the control module 160.

[0149] Step S402: Write the register values of i - 1, i, and i + 1 into the radio frequency channel CH2 register in sequence, read the detected voltage on the oscilloscope, and record it as V_PSi - 1, V_PSi, V_PSi + 1;

[0150] Exemplarily, in the first group of detections, when i = 0, the register values of radio frequency channel CH2 are set to -1, 0, and 1 in sequence, so as to obtain the degrees of 3 detected voltages.

[0151] Step S403: Compare the 3 groups of corresponding detected signal levels: judge what kind of situation the levels meet: If V_PSi - 1 > V_PSi > V_PSi + 1 is satisfied, then set i = i - 1 and enter step S404; If V_PSi - 1 < V_PSi < V_PSi + 1 is satisfied, then set i = i + 1 and enter step S405; If V_PSi - 1 < V_PSi > V_PSi + 1 is satisfied, then enter step S406; Step S404: Write the PS register value of radio frequency channel CH2 as i - 1, read the detected voltage on the oscilloscope, and record it as V_PSi - 1;

[0152] That is, judge the change trend of the detected level with the register value through 3 groups of detected signals, so as to judge whether the maximum or minimum value is in the direction of increasing i or decreasing i.

[0153] Step S405: Write the PS register value of radio frequency channel CH2 as i + 1, read the detected voltage on the oscilloscope, and record it as V_PSi + 1;

[0154] Step S406: The current detected level is the maximum value, and record the register value of radio frequency channel CH2 at this time as the initial value: PS_init2.

[0155] If the middle one of the 3 groups of detected levels is the maximum or minimum value, the detection can be stopped.

[0156] It should be noted that for the above step 403, there is another possible situation: V_PSi-1 > V_PSi < V_PSi+1, that is, the middle value is the smallest. At this time, the maximum value may be in the direction of decreasing register value or in the direction of increasing register value. To further simplify the test process and reduce the number of traversals, the current register value can also be selected as the initial value, that is, the register value corresponding to the minimum detection voltage is used as the initial value.

[0157] In some embodiments, when determining whether the magnitude of the middle detection signal is the minimum among the three, the steps of stepping through three consecutive values in sequence include:

[0158] If the three consecutive detection signals decrease in sequence, the three consecutive values step in the increasing direction;

[0159] If the three consecutive detection signals increase in sequence, the three consecutive values step in the decreasing direction.

[0160] Here, taking the example of finding the minimum value of the detection voltage, it is similar to the process shown above, Figure 12 but the stepping direction is opposite, and the specific process can be referred to the above for understanding. Figure 12 Understood.

[0161] In some embodiments, the method further includes:

[0162] If the magnitude of the detection signal in the middle among the three detection signals is the maximum or minimum among the three, it is determined whether the difference between the middle detection signal and the detection signals on both sides is greater than a preset value;

[0163] If not, continue to step through three consecutive values;

[0164] If so, stop changing the assignment of the first register and the second register.

[0165] For the method of comparing three detection signals each time in the above embodiments, if the slope of the detector is small, it may lead to incorrect judgments due to slight fluctuations or errors in the detection signals. For example, when it is detected that among the three detection signals, the second detection voltage is the largest, in fact, it is caused by fluctuations in the detection signal and is not the true maximum value. Therefore, here, by setting a preset value and adding the above step of comparing the difference in detection voltages when finding that the middle value is the maximum or minimum. If the difference between the second and the first detection voltages is greater than the preset value, and the difference between the second and the third detection voltages is also greater than the preset value, it can be considered that the current detection result is not affected by interference but is the true maximum value; on the contrary, if the difference between the second and the first detection voltages is less than the preset value, and / or the difference between the second and the third detection voltages is less than the preset value, it is considered that the current result is an incorrect result, and it is necessary to continue stepping and perform the next round of detection.

[0166] When the selected value of i is the minimum of the combined RF channels CH1 and CH2 (the detected voltage is the maximum or minimum), at this time, the level difference between V_PSi and V_PSi-1, V_PSi+1 is relatively large and much larger than other register values. This is due to the characteristic of the detector itself: even when the input power is 0, there is still a detected level output.

[0167] Therefore, the new scheme introduces a decision level difference threshold V_threshold. If |V_PSi–V_PSi-1| and |V_PSi–V_PSi+1| are less than this threshold, it means that the current register value is in the interval with a smaller power / detected voltage. Therefore, the previous loop is executed (i=i+1 / i=i-1);

[0168] If |V_PSi–V_PSi-1| and |V_PSi–V_PSi+1| are greater than this threshold, it means that when the current register value is obtained, the combination of the two channels is the smallest. The register value at this time is used as the initial value of the PS register of RF channel CH2.

[0169] Exemplarily, the above traversal process can refer to the Figure 13 process shown below. Here, the example of finding the maximum value is used for illustration.

[0170] Step S501: Set the threshold value (i.e., the preset value in the above embodiment): Vth, and set i = 0; the register value of RF channel CH1 is set to 0; that is, perform initialization settings, fix the register value of RF channel CH1 to 0, and initialize the register value of RF channel CH2 to 0.

[0171] Step S502: Write the register values of i-1, i, and i+1 into the register of RF channel CH2 in sequence, read the detected voltage on the oscilloscope, and record it as V_PSi-1, V_PSi, V_PSi+1;

[0172] This step is the same as step 402 above.

[0173] Step S503: Compare the levels of the 3 groups of corresponding detected signals: Determine which situation the levels satisfy: If V_PSi-1>V_PSi>V_PSi+1 is satisfied, then set i = i-1 and enter step S504; if V_PSi-1<V_PSi<V_PSi+1 is satisfied, then set i = i+1 and enter step S505; if V_PSi-1<V_PSi>V_PSi+1 or V_PSi-1>V_PSi<V_PSi+1 is satisfied, then enter step S506;

[0174] This step is the same as step 403 above.

[0175] Step S504: Write the PS register value of radio frequency channel CH2 as i - 1, read the detected voltage on the oscilloscope, and record it as V_PSi-1;

[0176] Step S505: Write the PS register value of radio frequency channel CH2 as i + 1, read the detected voltage on the oscilloscope, and record it as V_PSi+1;

[0177] Step S506: Determine whether |V_PSi - V_PSi-1| > Vth and |V_PSi - V_PSi+1| > Vth are satisfied. If satisfied, go to step S507; if not satisfied, repeat the above steps S502 and S503 with the current register value.

[0178] The judgment of the threshold value is added here, so as to reduce the detection error caused by signal fluctuations.

[0179] Step S507: The current detected level is the maximum value, and the register value of radio frequency channel CH2 at this time is recorded as the initial value: PS_init2.

[0180] In this way, by introducing the judgment level difference threshold: judge whether the difference between the detected signal in the middle and the detected signals on both sides is greater than the preset value. When the difference between the detected signal in the middle and the detected signals on both sides is greater than the preset value, the initial value is confirmed, avoiding the test error caused by the noise on the oscilloscope link, and further improving the reliability and stability of the test.

[0181] Based on the same inventive concept, the embodiment of the present disclosure also provides a control module 160, as Figure 14 shown, the control module 160 includes a processor 201 and a memory 202;

[0182] The processor 201 is configured to execute the instructions stored in the memory 202, so that the control module 160 executes any one of the above test methods, for example Figures 8 to 13 any one of the test methods in.

[0183] Here, the control module can be a hardware module or a software module, and can be a module set in some detection devices or detection platforms, such as the above Figure 1A module in, or can be a separate device, such as a computer.

[0184] Based on the same inventive concept, the embodiment of the present disclosure also provides a computer program product, including instructions, when the instructions run on a computer, any one of the above test methods is executed, for example Figures 8 to 13 any one of the test methods in.

[0185] It should be understood that the "some embodiments", "one embodiment" or "an embodiment" mentioned throughout the specification mean that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, the appearances of "in one embodiment" or "in an embodiment" throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics may be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present disclosure, the magnitude of the serial numbers of the respective processes does not mean the sequence of execution, and the execution sequence of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

[0186] It should be noted that in this text, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of additional identical elements in the process, method, article or device comprising that element.

[0187] The above are only the implementation manners of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure.

Claims

1. A test method for the phase switching stabilization time, characterized in that, The component under test includes a first radio frequency channel and a second radio frequency channel. The first radio frequency channel includes a first phase shifter and a first register, and the second radio frequency channel includes a second phase shifter and a second register; The test method includes: Traversing and assigning values to the first register and / or the second register to change the phase shift of the first phase shifter and / or the second phase shifter; At each assignment, obtaining the value of the detected signal, where the detected signal is obtained by detecting the signal output after combining the first radio frequency channel and the second radio frequency channel; Taking the value of the first register and / or the second register when the detected signal is maximum or minimum as the initial value; Based on the initial value, changing the value of the first register and / or the second register by a trigger signal to shift the combined signal by 180° relative to the initial value, and simultaneously sending the trigger signal to an oscilloscope, where the oscilloscope is used to display the waveforms of the detected signal and the trigger signal; Obtaining the change time of the trigger signal and the change time of the detected signal from the oscilloscope; Based on the difference between the change time of the trigger signal and the change time of the detected signal, obtaining the phase switching stable time.

2. The method according to claim 1, wherein The step of traversing and assigning values to the first register and / or the second register includes: Traversing all values of the first register; For each value of the first register, traversing all values of the second register.

3. The method according to claim 1, characterized in that, The step of traversing and assigning values to the first register and / or the second register includes: Fixing the value of the first register and traversing all values of the second register; Or, fixing the value of the second register and traversing all values of the first register.

4. The method according to claim 1, wherein The step of traversing and assigning values to the first register and / or the second register includes: sequentially assigning 3 consecutive values to the first register or the second register; The step of obtaining the value of the detected signal at each assignment includes: obtaining 3 detected signals corresponding to the 3 consecutive values; The step of traversing and assigning values to the first register and / or the second register further includes: Judging whether the magnitude of the middle detected signal is the maximum or minimum among the 3; If not, sequentially stepping the 3 consecutive values and sequentially assigning them to the first register or the second register; If so, stopping changing the assignment of the first register and the second register.

5. The method according to claim 4, wherein When judging whether the magnitude of the middle detected signal is the maximum among the 3, the step of sequentially stepping the 3 consecutive values includes: If the 3 consecutive detected signals decrease in sequence, the 3 consecutive values are stepped in the decreasing direction; If the 3 consecutive detected signals increase in sequence, the 3 consecutive values are stepped in the increasing direction.

6. The method according to claim 4, characterized in that, When judging whether the magnitude of the middle detected signal is the minimum among the 3, the step of sequentially stepping the 3 consecutive values includes: If the 3 consecutive detected signals decrease in sequence, the 3 consecutive values are stepped in the increasing direction; If three consecutive ones of the detection signals increase in sequence, the three consecutive values step in the decreasing direction.

7. The method according to claim 4, characterized in that, The step of using the value of the register when the detection signal is the largest or the smallest as the initial value includes: Using the middle value of the three consecutive values when the step of stopping the assignment is performed as the initial value.

8. The method according to claim 4, characterized in that, The method further includes: If the magnitude of the detection signal in the middle among the three detection signals is the maximum or the minimum of the three, determining whether the differences between the detection signal in the middle and the detection signals on both sides are both greater than a preset value; If not, continuing to step the three consecutive values; If so, stopping changing the assignment to the first register and the second register.

9. A control module, characterized in that the control module includes a processor and a memory; the processor is configured to execute instructions stored in the memory so that the control module executes the method according to any one of claims 1 to 8.

10. A computer program product, characterized in that it contains instructions that, when run on a computer, cause the method according to any one of claims 1 to 8 to be executed.

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