Intellectual property core test method and device, computer equipment and storage medium
By creating target test projects and performing simulation tests in the intellectual property core test, the test failure caused by path failure or packaging errors is solved, and the effect of saving test time and improving testing efficiency is achieved.
Patent Information
- Application Number
- CN202510344148.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-21
- Publication Date
- 2025-06-27
AI Technical Summary
During the intellectual property core testing process, functional testing fails due to path failure or packaging errors, wasting test time and reducing engineering quality.
By obtaining the core and functional modules of the intellectual property to be tested, adding them to the initial test project, determining its connection relationship, and creating a target test project. Then, the netlist file and bitstream of the target test project are obtained, simulation test and functional test are performed, and the process of generating bitstream and functional tests is terminated when the simulation test fails.
Reduces the risk of functional test failure due to via failure or packaging errors, saves test time and improves test efficiency.
Smart Images
Figure CN120214541A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuit technology, and in particular, to a method, device, computer device, and storage medium for intellectual property core testing. Background Art
[0002] Currently, when testing self-developed intellectual property (IP) cores, it is necessary to create a test project (Block design) for testing the IP core, add the IP core to be verified and the functional modules required for the verification process in the test project, synthesize and route to generate a bitstream, and burn the bitstream into a heterogeneous multi-core programmable system-on-chip for functional testing. However, during the above testing process, in the process of adding the IP core, configuring the IP core, and synthesizing and routing, there may be manual operations or parameter configuration errors, resulting in faults in the basic paths in the synthesis and routing. In addition, packaging errors may also occur during the packaging of the IP core to be tested.
[0003] Since the functional testing of the IP core consumes a lot of time, if the functional testing fails due to faults in the basic paths in the synthesis and routing or packaging errors, on the one hand, it will waste the time in the functional testing process, and on the other hand, it is necessary to trace the root cause, further resulting in a waste of time and a reduction in engineering quality. Summary of the Invention
[0004] In view of this, the present invention provides a method, device, computer device, and storage medium for intellectual property core testing to solve the problems of waste of testing time and reduction of engineering quality caused by test failures due to path faults or packaging errors.
[0005] In a first aspect, the present invention provides a method for intellectual property core testing, the method comprising:
[0006] Obtain the intellectual property core to be tested and the functional modules corresponding to the intellectual property core to be tested;
[0007] Add the intellectual property core to be tested and the functional modules to an initial test project, and determine the connection relationship between the intellectual property core to be tested and the functional modules in the initial test project to obtain a target test project;
[0008] Obtain the netlist file and bitstream of the target test project, perform simulation testing on the target test project according to the netlist file, and perform functional testing on the intellectual property core to be tested according to the bitstream.
[0009] In a second aspect, the present invention provides an apparatus for intellectual property core testing, the apparatus comprising:
[0010] An acquisition unit, configured to acquire an intellectual property core to be tested and a function module corresponding to the intellectual property core to be tested;
[0011] A project creation unit, configured to add the intellectual property core to be tested and the function module to an initial test project, and determine the connection relationship between the intellectual property core to be tested and the function module in the initial test project, so as to obtain a target test project;
[0012] A test unit, configured to obtain a netlist file and a bitstream of the target test project, perform a simulation test on the target test project according to the netlist file, and perform a function test on the intellectual property core to be tested according to the bitstream.
[0013] In a third aspect, the present invention provides a computer device, including: a memory and a processor, which are communicatively connected to each other, wherein the memory stores computer instructions, and the processor executes the computer instructions to execute the intellectual property core test method according to the first aspect or any corresponding embodiment thereof.
[0014] In a fourth aspect, the present invention provides a computer-readable storage medium, on which computer instructions are stored, and the computer instructions are used to cause a computer to execute the intellectual property core test method according to the first aspect or any corresponding embodiment thereof.
[0015] In a fifth aspect, the present invention provides a computer program product, including computer instructions, and the computer instructions are used to cause a computer to execute the intellectual property core test method according to the first aspect or any corresponding embodiment thereof.
[0016] Through the present application, the intellectual property core to be tested and the function module are added to the initial test project, and the intellectual property core to be tested and the function module in the initial test project are connected to create a target test project. The netlist file and the bitstream of the target test project are obtained, a simulation test is performed on the target test project according to the netlist file, and a function test is performed on the intellectual property core to be tested according to the bitstream. A determination process is added. Whether there is a path fault or packaging error in the target test project is determined through the simulation test. If there is, the process of generating the bitstream and the function test can be terminated at any time. The problem of wasting test time and reducing the engineering quality caused by test failure due to path faults or packaging errors is solved. It has the effects of reducing the risk of function test failure caused by path faults or packaging errors, saving the test time cost, and improving the test efficiency. Description of the Drawings
[0017] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the related art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the related art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0018] Figure 1 It is a schematic flowchart of an intellectual property core testing method according to an embodiment of the present invention;
[0019] Figure 2 It is a flowchart of the improved engineering testing according to an embodiment of the present invention;
[0020] Figure 3 It is a flowchart of the simulation testing according to an embodiment of the present invention;
[0021] Figure 4 It is a structural block diagram of an intellectual property core testing device according to an embodiment of the present invention;
[0022] Figure 5 It is a schematic hardware structure diagram of a computer device according to an embodiment of the present invention. Specific Embodiments
[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.
[0024] Currently, a block design is built using an integrated design tool, such as the Vivado tool. The Vivado tool can provide an integrated design environment. The block design is a method for creating reusable modular hardware designs. In the block design, IP cores required for testing and self-developed module IP cores to be tested are added in sequence. An IP core is an intellectual property core. For example, it is a pre-designed circuit function module in an FPGA (Field Programmable Gate Array). Configure the configuration items of the intellectual property core, such as clock frequency, pin settings, pin attribute selection, IO (Input / Output) standard selection, etc. Connect the entire block design according to the signals and interface behaviors of the self-developed module intellectual property core. Perform synthesis and routing to generate a bitstream, and burn the bitstream into a ZYNQ board for testing. Here, ZYNQ is a programmable logic device integrating a processor and a field programmable gate array.
[0025] The following problems exist in the above test process: When adding the intellectual property cores required for testing and the intellectual property cores to be tested, configuring the parameters of the intellectual property cores, and connecting the intellectual property cores, there may be manual operations or incorrect parameter configurations in these processes. If the engineering synthesis and routing are allowed to complete to generate a bitstream, and finally the basic path test fails, it will waste a large amount of test time and is not conducive to improving the test efficiency. If the functional correctness of the code in the encapsulated intellectual property core is not checked, it may lead to the failure of the basic function test when the generated bitstream is tested on the board. Then, tracing back to the source, it will result in a waste of testing and a reduction in engineering quality. In addition, in the above test process, the field programmable gate array project generates the bitstream slowly, and there may be incorrect interface connections or incorrect parameter configurations during the building process, resulting in the failure of the final project test, which has caused a large waste of time.
[0026] Based on the above content, an embodiment of the present invention provides an intellectual property core test method, which realizes the reuse of the simulation environment, combines and reuses the verification environment with the field programmable gate array project, performs engineering routing and simulation simultaneously, and performs path testing and functional testing, including: The accuracy of the built project can be viewed according to the simulation results, and it can be judged whether the project can be released according to the simulation results. A judgment process is added, and the project can be terminated and rebuilt at any time according to the simulation results. It realizes better management of the field programmable gate array project, reduces the risk of manual operation errors and time costs in building the block design, and better encapsulates the self-developed code to facilitate the subsequent on-board test work. It has the effects of saving test time and improving test efficiency.
[0027] According to an embodiment of the present invention, an intellectual property core testing embodiment is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer device with data processing capabilities, such as a computer, a server, etc., and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.
[0028] In this embodiment, a method for testing an intellectual property core is provided. Figure 1 is a flow chart of an intellectual property core testing method according to an embodiment of the present invention. Figure 1 As shown, the process includes the following steps:
[0029] Step S101, obtaining an intellectual property core to be tested and a functional module corresponding to the intellectual property core to be tested.
[0030] Specifically, obtain the intellectual property core to be tested. For example, after completing the self-developed nand flash code module, encapsulate the nand flash code module to make it a callable IP, and name it nand flash IP, and use the nand flash IP as the intellectual property core to be tested, where nand flash is a flash memory based on nand technology, and nand is a non-volatile memory using floating gate transistors.
[0031] Get the functional modules corresponding to the intellectual property core to be tested. For example, the intellectual property cores that come with the vivado tool connected to the IP, such as AXI (Advanced eXtensible Interface), PLL (Phase-Locked Loop), clock reset and other intellectual property cores.
[0032] Step S102, adding the intellectual property core to be tested and the functional modules to the initial test project, and determining the connection relationship between the intellectual property core to be tested and the functional modules in the initial test project to obtain the target test project.
[0033] Specifically, an integrated design tool is used to build a block design as an initial test project, and an integrated design tool such as the Vivado tool is used.
[0034] Add the IP core to be tested and the functional modules in the initial test project in sequence. Connect the IP core to be tested and the functional modules in the initial test project according to the signal and interface behavior of the IP core to be tested, and obtain the connection relationship between the IP core to be tested and the functional modules. After the module connection in the initial test project is completed, it is called the target test project. The signal and interface behavior are, for example, nandIO, data transmission channel, etc.
[0035] Step S103: Obtain the netlist file and bitstream of the target test project, perform simulation testing on the target test project according to the netlist file, and perform functional testing on the intellectual property core to be tested according to the bitstream.
[0036] Specifically, when the intellectual property core to be tested is placed on a field-programmable gate array for testing, it indicates that the intellectual property core to be tested is already in the verification environment and has been comprehensively simulated at its RTL (Register Transfer Level). Therefore, the simulation environment is mature. In this embodiment, the field-programmable gate array and the simulation environment are reused. After setting up the target test project, obtain the netlist file of the project through synthesis. At the same time, generate the bitstream for the target test project through place and route.
[0037] Perform simulation testing on the target test project according to the netlist file. For example, place the netlist file in the simulation environment at the register transfer level and add the primitives in the vivado tool library to complete the adaptation of the netlist simulation environment, and then perform simulation testing on the target test project. If the simulation testing passes, continue with the process of generating the bitstream for the target test project through place and route, and perform functional testing on the intellectual property core to be tested according to the bitstream. For example, burn the bitstream into the ZYNQ board for functions such as erasing, writing, and reading. If the simulation testing fails, terminate the process of generating the bitstream for the target test project through place and route, and do not perform functional testing on the intellectual property core to be tested.
[0038] It should be noted that in this embodiment, not only can ZYNQ be used for functional testing, but also more field-programmable gate array platforms can be used, such as HAPS, etc. Among them, HAPS is a prototype verification system based on field-programmable gate arrays.
[0039] The intellectual property core testing method provided in this embodiment adds the intellectual property core to be tested and functional modules to the initial test project, connects the intellectual property core to be tested and the functional modules in the initial test project, and creates a target test project. Obtain the netlist file and bitstream of the target test project, perform simulation testing on the target test project according to the netlist file, and perform functional testing on the intellectual property core to be tested according to the bitstream. An additional determination process is added to determine whether there are path faults or packaging errors in the target test project through simulation testing. If there are any, the process of generating the bitstream and functional testing can be terminated at any time. This solves the problem of wasting test time and reducing the engineering quality caused by test failures due to path faults or packaging errors. It has the effects of reducing the risk of functional testing failures caused by path faults or packaging errors, saving the test time cost, and improving the test efficiency.
[0040] In some alternative embodiments, a netlist file and a bitstream of a target test project are obtained. The target test project is subjected to simulation testing according to the netlist file, and the intellectual property core to be tested is subjected to functional testing according to the bitstream, including:
[0041] Obtain the netlist file of the target test project;
[0042] Perform simulation testing on the target test project according to the netlist file, and execute a preset process, where the preset process is used to perform comprehensive wiring on the target test project to generate a bitstream;
[0043] In the case where the simulation testing fails, terminate the preset process;
[0044] In the case where the simulation testing passes, perform functional testing on the intellectual property core to be tested according to the bitstream.
[0045] Specifically, obtain the netlist file of the target test project. For example, in the TCL (Tool Command Language) dialog box of the vivado tool, inputting write_verilog - mode funcsimwb.v can obtain the netlist file of the target test project, where write_verilog - mode funcsimwb.v is used to generate a Verilog netlist file for functional simulation; use a field - programmable gate array design tool to synthesize register - transfer - level code into a netlist. A netlist is the gate - level representation of register - transfer - level code after logic synthesis, which is closer to the actual hardware implementation.
[0046] Perform simulation testing on the target test project according to the netlist file. For example, place the netlist file in the register - transfer - level simulation environment, and add the vivado tool library primitives to complete the adaptation of the netlist simulation environment, and perform simulation testing on the target test project. While performing the simulation testing, perform the preset process. The preset process is, for example, generating a bitstream for the comprehensive wiring of the target test project.
[0047] The time for executing the preset process and performing functional testing on the intellectual property core to be tested according to the bitstream is very long. For example, when the intellectual property core to be tested is a nand flash IP, the above process takes about seven or eight hours. Therefore, through the above simulation testing, problems in the project can be simulated in advance. If there are problems, the execution of the preset process will be terminated in advance, and the path errors in the project or the functional errors of the intellectual property core to be tested will be re - built or re - packaged, so as to improve the efficiency and test accuracy of the project, that is, improve the release quality. In the case where the simulation testing fails, terminate the preset process. In the case where the simulation testing passes, perform functional testing on the intellectual property core to be tested according to the bitstream.
[0048] The above process is as follows Figure 2 As shown, encapsulate the to-be-tested code of the self-developed NAND flash to make it a callable intellectual property core, which can be named NAND flash IP; open the Vivado tool to create a new initial test project; in the initial test project, add the NAND flash IP and the intellectual property cores provided by the Vivado tool connected to the NAND flash IP in sequence, such as advanced extensible interface, phase-locked loop, clock reset and other intellectual property cores; connect the entire initial test project according to the signals and interface behaviors of the NAND flash IP, such as NAND IO, data transmission channels, etc.; obtain the netlist file and perform simulation testing, determine whether the simulation testing passes, and at the same time perform synthesis and placement and routing to generate the bitstream; if the simulation testing fails, terminate the step of "synthesis and placement and routing to generate the bitstream", and re-execute the step of "encapsulate the to-be-tested code of the self-developed NAND flash to make it a callable intellectual property core, which can be named NAND flash IP".
[0049] In this embodiment, the target test project is simulated and tested according to the netlist file, and whether there are path faults or packaging errors in the target test project is determined through the simulation testing. Moreover, a determination process is added, and if the simulation testing fails, the processes of generating the bitstream and functional testing can be terminated at any time, avoiding functional testing in the case of path faults or packaging errors.
[0050] In some optional embodiments, the functional testing of the to-be-tested intellectual property core is performed according to the bitstream, including:[[]]
[0051] Burn the bitstream into the test component;
[0052] Use the test component to execute preset instructions based on the bitstream to obtain the execution results of the preset instructions.
[0053] Specifically, the test component is, for example, a field programmable gate array platform such as ZYNQ or HAPS. The preset instructions are, for example, instructions for performing functions such as erasing, writing, and reading.
[0054] Burn the bitstream into the test component, use the test component to execute preset instructions based on the bitstream to obtain the execution results of the preset instructions, and determine the functional test results through the execution results. For example, if it is determined according to the execution results that a certain preset instruction fails to execute, the test result is that the test fails; if it is determined according to the execution results that all preset instructions are executed successfully, the test result is that the test passes.
[0055] The above process is as follows Figure 2 As shown, perform synthesis and placement and routing to generate the bitstream, and burn the bitstream into the ZYNQ board to perform functions such as erasing, writing, and reading testing.
[0056] In some alternative embodiments, the target test project is simulated and tested according to the netlist file, including:
[0057] Determine the simulation environment corresponding to the intellectual property core to be tested;
[0058] Add the netlist file to the simulation environment, and add the library primitive provided by the preset tool to the simulation environment to obtain the target simulation environment;
[0059] Perform simulation testing on the target test project based on the target simulation environment to obtain simulation test results.
[0060] Specifically, when the intellectual property core to be tested is placed on a field-programmable gate array for testing, it indicates that the intellectual property core to be verified is already in the verification environment and has been comprehensively simulated at the register transfer level. Therefore, the simulation environment is mature and can be reused. Thus, determining the simulation environment corresponding to the intellectual property core to be tested means determining the simulation environment for the register transfer level of the intellectual property core to be tested. This simulation environment includes a testbench, stimulus signals, monitoring and inspection mechanisms, etc. Additionally, it is necessary to ensure that the simulation environment (including the testbench) is ready and can run properly.
[0061] Integrate the generated netlist file as the module to be tested into the original register transfer level simulation environment to complete the adaptation of the netlist simulation environment for simulation environment reuse. This involves modifying the testbench to be able to instantiate and connect to the netlist module. Preset tools such as vivado or other field-programmable gate array design tools. Add the library primitive provided by the preset tool to the simulation environment to obtain the target simulation environment. These library primitives may include specific hardware description language (HDL) modules or intellectual property cores for simulating the unique functions or behaviors of the field-programmable gate array. Additionally, it is necessary to adapt and verify the target simulation environment, including: ensuring the compatibility of the interface between the netlist and the testbench; running the simulation to verify whether the behavior of the netlist is consistent with the expected register transfer level behavior.
[0062] Perform simulation testing on the target test project based on the target simulation environment to obtain simulation test results. For example, configure the simulation settings according to the simulation tool used (such as ModelSim, Vivado Simulator, etc.), and specify parameters such as the netlist file, testbench file, and simulation time. Start the simulation tool, begin the simulation process, monitor the simulation output, check for error or warning messages, and obtain the simulation test results.
[0063] The above process is as Figure 3As shown, obtain the netlist; adapt the netlist simulation environment (reuse the simulation environment); build the path test inspection project and check the quality of the functional test inspection project; generate the bitstream file; release the version accurately and efficiently.
[0064] In this embodiment, the simulation environment is combined and reused with the field programmable gate array project, that is, while generating the bitstream, simulation testing is performed. The simulation testing can perform path testing on the target test project and determine whether the target test project can implement the corresponding functions, obtaining the simulation test results. This reduces the risk of functional test failure caused by wiring errors and packaging errors.
[0065] In some alternative embodiments, after obtaining the simulation test results, the method further includes:
[0066] Compare the simulation test results with the target simulation test results, where the target simulation test results are used to determine that the netlist file is a correct netlist file;
[0067] In the case where the simulation test results are inconsistent with the target simulation test results, use a preset debugging tool to determine the simulation error information;
[0068] In the case where it is determined that there is a module packaging error according to the simulation error information, obtain the code to be tested, package the code to be tested into a new intellectual property core to be tested, and start executing the subsequent steps from adding the intellectual property core to be tested and the functional module to the initial test project until the simulation test is successful, then end;
[0069] In the case where it is determined that there is a path error according to the simulation error information, start executing the subsequent steps from determining the connection relationship between the intellectual property core to be tested and the functional module in the initial test project until the simulation test is successful, then end.
[0070] Specifically, use the waveform viewer or log analyzer provided by the simulation tool to view the simulation test results, compare the simulation test results with the target simulation test results, and verify the correctness of the netlist. The target simulation test results are, for example, the expected register transfer level simulation results.
[0071] In the case where the simulation test results are inconsistent with the target simulation test results, use a preset debugging tool to locate the problem to determine the simulation error information, modify the register transfer level code or the netlist integration method as needed, and re - perform the simulation verification.
[0072] By reusing the above simulation environment, engineering problems can be simulated in advance. If there are problems, the engineering generation of the bitstream will be terminated in advance, and for the path errors in the engineered path or the functional errors of the intellectual property core to be tested, re - construction or encapsulation will be carried out to improve the engineering efficiency and test accuracy, that is, to improve the release quality. Therefore, when it is determined that there is a module encapsulation error according to the simulation error information, the code to be tested is obtained, and the code to be tested is encapsulated into a new intellectual property core to be tested to solve the functional error of the intellectual property core to be tested, and the subsequent steps are executed starting from "adding the intellectual property core to be tested and the functional module to the initial test project" in the above step S102 until the simulation test is successful, then it ends. When it is determined that there is a path error according to the simulation error information, the subsequent steps are executed starting from "determining the connection relationship between the intellectual property core to be tested and the functional module in the initial test project" in the above step S102 to solve the path error until the simulation test is successful, then it ends.
[0073] In this embodiment, the simulation test is used to perform path testing on the target test project, and it is judged whether the target test project can achieve the corresponding function to obtain the simulation test result. To better manage the field - programmable gate array project, reduce the risk of connection operation errors and time costs, etc., and better encapsulate the code to be tested for the subsequent on - board test work.
[0074] In some optional embodiments, obtaining the intellectual property core to be tested includes:
[0075] Obtaining the code to be tested;
[0076] Generating the encapsulated intellectual property core according to the preset encapsulation method and the code to be tested;
[0077] Verifying the function of the encapsulated intellectual property core, and after successful verification, using the encapsulated intellectual property core as the intellectual property core to be tested.
[0078] Specifically, obtaining the code to be tested, for example: the code of the self - developed nand flash module.
[0079] The preset encapsulation methods are, for example: soft - core encapsulation based on the source code of the hardware description language, solid - core encapsulation based on the netlist, hard - core encapsulation based on the standardized interface, etc. Encapsulating the code to be tested to make it a callable intellectual property core, that is, the encapsulated intellectual property core, and determining the name of this intellectual property core, for example: nand flash IP.
[0080] In addition, to ensure the accuracy of the function of the encapsulated intellectual property core, its function needs to be verified first. For example: verifying the functions such as erasing, writing, and reading of nand flash IP. After successful verification, using the encapsulated intellectual property core as the intellectual property core to be tested.
[0081] In this embodiment, the code to be tested is encapsulated as an intellectual property core and its function is verified. Only after the function verification of the intellectual property core is successful, it is tested to ensure the accurate function of the intellectual property core before testing.
[0082] In some alternative embodiments, determining the connection relationship between the intellectual property core to be tested and the functional module in the initial test project includes:
[0083] Obtaining the first signal and the first interface behavior of the intellectual property core to be tested;
[0084] Determining the second signal and the second interface behavior of the functional module;
[0085] Matching the first signal with the second signal to obtain a first matching result, and matching the first interface behavior with the second interface behavior to obtain a second matching result;
[0086] According to the first matching result and the second matching result, determining the first target interface corresponding to the first interface in the intellectual property core to be tested and the second target interface corresponding to the second interface in the functional module;
[0087] Connecting the first interface to the first target interface and connecting the second interface to the second target interface to obtain the connection relationship.
[0088] Specifically, the signals of the intellectual property core or the functional module are, for example: ALE (Address Latch Enable), CLE (Command Latch Enable), DQ (Data / Address Bus), DQS (Data Strobe), etc., and the interface behaviors are, for example: the behaviors of output signals or received signals.
[0089] Obtaining the signals and interface behaviors of the intellectual property core to be tested, and obtaining the signals and interface behaviors of the functional module. For the convenience of distinction, the signals and interface behaviors of the intellectual property core to be tested are respectively called the first signal and the first interface behavior, and the signals and interface behaviors of the functional module are respectively called the second signal and the second interface behavior.
[0090] Match the first signal with the second signal to obtain a first matching result. For example, the signal corresponding to interface 1 of the intellectual property core to be tested is the same as the signal corresponding to interface 2 of module A; the signal corresponding to interface 3 of the intellectual property core to be tested is the same as the signal corresponding to interface 4 of module B. Match the first interface behavior with the second interface behavior to obtain a second matching result. For example, the interface behavior of interface 1 is to output a signal, the interface behavior of interface 2 is to receive a signal, the interface behavior of interface 3 is to receive a signal, and the interface behavior of interface 4 is to output a signal.
[0091] According to the first matching result and the second matching result, determine the first target interface corresponding to the first interface in the intellectual property core to be tested and the second target interface corresponding to the second interface in the functional module. For example, the first interface in the intellectual property core to be tested is interface 1, and the second interface in the functional module is interface 2. It is necessary to connect interface 1 and interface 2, and interface 1 outputs a signal while interface 2 receives a signal; the first interface in the intellectual property core to be tested is interface 3, and the second interface in the functional module is interface 4. It is necessary to connect interface 3 and interface 4, and interface 4 outputs a signal while interface 3 receives a signal. Connect the first interface with the first target interface, and connect the second interface with the second target interface to obtain a connection relationship.
[0092] In some alternative embodiments, the specific process of using a test component to perform a functional test on the intellectual property core to be tested based on a bitstream may include step A1 and step A2.
[0093] Step A1: Send different types of data files to the test component to trigger the test component to perform a functional test on the intellectual property core to be tested in a read / write mode.
[0094] Specifically, controlling the test component to start the read / write mode may include at least one of the following: controlling the test component to perform sequential single-word read / write access operations; controlling the test component to perform random single-word read / write access operations; controlling the test component to perform burst sequential read / write access operations; controlling the test component to perform burst random read / write access operations. Verify the function of the intellectual property core to be tested through at least one of sequential single-word read / write access operations, random single-word read / write access operations, burst sequential read / write access operations, and burst random read / write access operations.
[0095] Sending different types of data files to the test component to trigger the test component to perform write-mode testing and read-mode testing may include at least two of the following: sending a fixed data file to the test component to trigger the test component to perform write-mode testing; reading the written fixed data file from the test component to trigger the test component to perform read-mode testing; sending a linear data file to the test component to trigger the test component to perform write-mode testing; reading the written linear data file from the test component to trigger the test component to perform read-mode testing. Sending a random data file to the test component to trigger the test component to perform write-mode testing; reading the written random data file from the test component to trigger the test component to perform read-mode testing. For general test data, it can be directly sent to the test component through the link layer; while for special test data, such as high-order random data, non-linear test data, etc., the data needs to be cached in an external memory for testing use, which can reduce the time overhead generated by test data and improve test efficiency.
[0096] Step A2, statistically cover the data according to the read-write mode test.
[0097] Specifically, verify the consistency of the written fixed data file and the read fixed data file to statistically cover the first coverage rate; verify the consistency of the written linear data file and the read linear data file to statistically cover the second coverage rate; verify the consistency of the written random data file and the read random data file to statistically cover the third coverage rate; statistically covering the data according to the write-mode test and the read-mode test may include: statistically covering the overall coverage rate based on at least two of the first coverage rate, the second coverage rate, and the third coverage rate to obtain a test conclusion.
[0098] In this embodiment, the test component performs a functional test on the intellectual property core to be tested according to the received different types of data files and control instructions, which not only improves the density, speed of test data generation, and test speed, but also improves the scalability and flexibility of the test method.
[0099] In this embodiment, an intellectual property core test device is further provided. This device is used to implement the above embodiments and preferred implementation manners, and those that have been described will not be repeated. As used hereinafter, the term "module" may be a combination of software and / or hardware that can implement a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware is also possible and contemplated.
[0100] This embodiment provides an intellectual property core test device, as Figure 4 shown, including:
[0101] An acquisition unit 401, configured to acquire the intellectual property core to be tested and the function modules corresponding to the intellectual property core to be tested;
[0102] An engineering creation unit 402, configured to add an intellectual property core to be tested and a functional module to an initial test project, and determine the connection relationship between the intellectual property core to be tested and the functional module in the initial test project, so as to obtain a target test project;
[0103] A testing unit 403, configured to obtain a netlist file and a bitstream of the target test project, perform a simulation test on the target test project according to the netlist file, and perform a functional test on the intellectual property core to be tested according to the bitstream.
[0104] In some alternative embodiments, the testing unit 403 includes:
[0105] A first acquisition sub-module, configured to obtain the netlist file of the target test project;
[0106] A first testing sub-module, configured to perform a simulation test on the target test project according to the netlist file and execute a preset process, where the preset process is used to perform comprehensive wiring on the target test project to generate a bitstream;
[0107] A first judgment sub-module, configured to terminate the preset process when the simulation test fails;
[0108] A second judgment sub-module, configured to perform a functional test on the intellectual property core to be tested according to the bitstream when the simulation test passes.
[0109] In some alternative embodiments, the testing unit 403 includes:
[0110] A programming sub-module, configured to program the bitstream into a test component;
[0111] A second testing sub-module, configured to use the test component to execute a preset instruction based on the bitstream to obtain an execution result of the preset instruction.
[0112] In some alternative embodiments, the testing unit 403 includes:
[0113] A first determination sub-module, configured to determine a simulation environment corresponding to the intellectual property core to be tested;
[0114] A simulation environment setting sub-module, configured to add the netlist file to the simulation environment and add library primitive sentences provided by a preset tool to the simulation environment to obtain a target simulation environment;
[0115] A third testing sub-module, configured to perform a simulation test on the target test project based on the target simulation environment to obtain a simulation test result.
[0116] In some alternative embodiments, the testing unit 403 includes:
[0117] A comparison sub-module for comparing the simulation test results with the target simulation test results, where the target simulation test results are used to determine whether the netlist file is a correct netlist file;
[0118] A second determination sub-module for determining the simulation error information using a preset debugging tool when the simulation test results are inconsistent with the target simulation test results;
[0119] A first loop sub-module for obtaining the code to be tested when it is determined that there is a module encapsulation error based on the simulation error information, encapsulating the code to be tested into a new intellectual property core to be tested, and starting to execute the subsequent steps from adding the intellectual property core to be tested and the functional module to the initial test project until the simulation test is successful, and then ending;
[0120] A second loop sub-module for starting to execute the subsequent steps from determining the connection relationship between the intellectual property core to be tested and the functional module in the initial test project when it is determined that there is a path error based on the simulation error information until the simulation test is successful, and then ending.
[0121] In some alternative embodiments, the obtaining unit 401 includes:
[0122] A second obtaining sub-module for obtaining the code to be tested;
[0123] A generating sub-module for generating an encapsulated intellectual property core according to a preset encapsulation method and the code to be tested;
[0124] A verifying sub-module for verifying the function of the encapsulated intellectual property core and, after successful verification, using the encapsulated intellectual property core as the intellectual property core to be tested.
[0125] In some alternative embodiments, the project creating unit 402 includes:
[0126] A third obtaining sub-module for obtaining the first signal and the first interface behavior of the intellectual property core to be tested;
[0127] A third determination sub-module for determining the second signal and the second interface behavior of the functional module;
[0128] A matching sub-module for matching the first signal with the second signal to obtain a first matching result and matching the first interface behavior with the second interface behavior to obtain a second matching result;
[0129] A fourth determination sub-module for determining the first target interface corresponding to the first interface in the intellectual property core to be tested and the second target interface corresponding to the second interface in the functional module according to the first matching result and the second matching result;
[0130] A connection sub-module, configured to connect a first interface to a first target interface and connect a second interface to a second target interface, so as to obtain a connection relationship.
[0131] The further function descriptions of the above-mentioned various modules and units are the same as those in the corresponding embodiments above, and will not be elaborated here.
[0132] The intellectual property core testing device in this embodiment is presented in the form of functional units. Here, the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and a memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.
[0133] An embodiment of the present invention further provides a computer device having the above-mentioned Figure 4 shown intellectual property core testing device.
[0134] Please refer to Figure 5 , Figure 5 which is a schematic structural diagram of a computer device provided by an optional embodiment of the present invention. As shown in Figure 5 , the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including a high-speed interface and a low-speed interface. Each component communicates with each other using different buses and can be installed on a common motherboard or installed in other ways as needed. The processor can process instructions executed within the computer device, including instructions stored in the memory or on the memory to display graphical information of the GUI on an external input / output device (such as a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a set of blade servers, or a multi-processor system). Figure 5 In
[0135] Processor 10 can be a central processing unit, a network processor, or a combination thereof. Among them, processor 10 can further include a hardware chip. The above-mentioned hardware chip can be an application specific integrated circuit, a programmable logic device, or a combination thereof. The above-mentioned programmable logic device can be a complex programmable logic device, a field programmable gate array, a general array logic, or any combination thereof.
[0136] Among them, the memory 20 stores instructions executable by at least one processor 10, so that at least one processor 10 executes the method shown in the above embodiment.
[0137] The memory 20 may include a program storage area and a data storage area. Among them, the program storage area can store an operating system and application programs required for at least one function; the data storage area can store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state storage devices. In some alternative embodiments, the memory 20 may optionally include a memory remotely provided with respect to the processor 10, and these remote memories can be connected to the computer device through a network. Examples of the above-mentioned network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.
[0138] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk, or a solid-state drive; the memory 20 may further include a combination of the above types of memories.
[0139] The computer device further includes a communication interface 30 for the computer device to communicate with other devices or communication networks.
[0140] Embodiments of the present invention also provide a computer-readable storage medium. The methods according to the embodiments of the present invention can be implemented in hardware, firmware, or be implemented as computer code that can be recorded on a storage medium, or be implemented as computer code originally stored in a remote storage medium or a non-temporary machine-readable storage medium and downloaded through a network and to be stored in a local storage medium, so that the methods described herein can be stored in such software processes on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid-state drive, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code, and when the software or computer code is accessed and executed by the computer, the processor, or the hardware, the methods shown in the above embodiments are implemented.
[0141] A part of the present invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can call or provide the methods and / or technical solutions according to the present invention through the operations of the computer. Those skilled in the art should understand that the forms in which computer program instructions exist in a computer-readable medium include but are not limited to source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include but are not limited to: the computer directly executes the instructions, or the computer compiles the instructions and then executes the corresponding compiled program, or the computer reads and executes the instructions, or the computer reads and installs the instructions and then executes the corresponding installed program. Herein, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible by the computer.
[0142] Although embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations all fall within the scope defined by the present invention.
Claims
1. A method for testing an intellectual property core, characterized in that: The method comprises: Acquire an intellectual property core to be tested and a functional module corresponding to the intellectual property core to be tested; Adding the intellectual property core to be tested and the functional module to an initial test project, and determining the connection relationship between the intellectual property core to be tested and the functional module in the initial test project to obtain a target test project; The netlist file and bit stream of the target test project are obtained, a simulation test is performed on the target test project according to the netlist file, and a functional test is performed on the intellectual property core to be tested according to the bit stream.
2. The method according to claim 1, characterized in that The obtaining of the netlist file and the bitstream of the target test project, performing simulation test on the target test project according to the netlist file, and performing functional test on the intellectual property core to be tested according to the bitstream includes: Obtaining the netlist file of the target test project; Performing simulation test on the target test project according to the netlist file, and executing a preset process, wherein the preset process is used to perform integrated wiring on the target test project to generate the bit stream; If the simulation test fails, terminating the preset process; When the simulation test passes, a functional test is performed on the intellectual property core to be tested according to the bit stream.
3. The method according to claim 1 or 2, characterized in that: The performing functional testing on the intellectual property core to be tested according to the bit stream comprises: Burning the bitstream into a test component; The test component is used to execute preset instructions based on the bit stream to obtain execution results of the preset instructions.
4. The method according to claim 1 or 2, characterized in that: The performing simulation test on the target test project according to the netlist file includes: Determine a simulation environment corresponding to the intellectual property core to be tested; Adding the netlist file to the simulation environment, and adding the library original sentence provided by the preset tool to the simulation environment, to obtain a target simulation environment; The target test project is simulated and tested based on the target simulation environment to obtain a simulation test result.
5. The method according to claim 4, characterized in that After obtaining the simulation test results, the method further includes: Comparing the simulation test result with a target simulation test result, wherein the target simulation test result is used to determine whether the netlist file is a correct netlist file; In the case where the simulation test result is inconsistent with the target simulation test result, using a preset debugging tool to determine simulation error information; In the case where it is determined according to the simulation error information that there is a module encapsulation error, the code to be tested is obtained, and the code to be tested is encapsulated into a new intellectual property core to be tested, and subsequent steps are performed from adding the intellectual property core to be tested and the functional module to the initial test project until the simulation test succeeds, and then the test ends; When it is determined that there is a path error according to the simulation error information, subsequent steps are performed starting from determining the connection relationship between the IP core to be tested and the functional module in the initial test process until the simulation test succeeds, and then the process ends.
6. The method according to claim 1, characterized in that Acquiring the intellectual property core to be tested includes: Get the code to be tested; Generate a packaged intellectual property core according to a preset packaging method and the code to be tested; The function of the packaged intellectual property core is verified, and after successful verification, the packaged intellectual property core is used as the intellectual property core to be tested.
7. The method according to claim 1, characterized in that The determining of the connection relationship between the intellectual property core to be tested and the functional module in the initial test project includes: Acquire a first signal and a first interface behavior of the intellectual property core to be tested; Determine a second signal and a second interface behavior of the functional module; Matching the first signal with the second signal to obtain a first matching result, and matching the first interface behavior with the second interface behavior to obtain a second matching result; Determine, according to the first matching result and the second matching result, a first target interface corresponding to the first interface in the intellectual property core to be tested and a second target interface corresponding to the second interface in the functional module; The first interface is connected to the first target interface, and the second interface is connected to the second target interface to obtain the connection relationship.
8. An intellectual property nuclear testing device, characterized in that: The device comprises: An acquisition unit, used for acquiring an intellectual property core to be tested and a functional module corresponding to the intellectual property core to be tested; A project creation unit, used for adding the intellectual property core to be tested and the functional module to an initial test project, and determining a connection relationship between the intellectual property core to be tested and the functional module in the initial test project to obtain a target test project; The test unit is used to obtain the netlist file and bit stream of the target test project, perform simulation test on the target test project according to the netlist file, and perform functional test on the intellectual property core to be tested according to the bit stream.
9. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the intellectual property nuclear testing method according to any one of claims 1 to 7 by executing the computer instructions.
10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the intellectual property nuclear testing method according to any one of claims 1 to 7.