A data migration method, apparatus, storage medium and electronic device

Abstract

Embodiments of the present disclosure provide a data migration method, apparatus, storage medium, and electronic device, relating to the field of computer technologies. The method includes: obtaining first information of a solid-state drive, where the first information is used to reflect the input / output conditions of the solid-state drive; if it is determined according to the first information that the solid-state drive meets a first condition, performing a first migration operation; if the solid-state drive does not meet the first condition, performing a second migration operation; where the first migration operation includes: performing a migration operation on cached data; the second migration operation includes: performing a migration operation on cached data according to the cache margin. In this way, by obtaining the first information of the solid-state drive and making a decision on the migration operation according to its input / output conditions, intelligent data migration is realized, and the timing and manner of data migration are optimized.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technologies, and particularly to a data migration method, apparatus, storage medium, and electronic device. Background Art

[0002] As the main storage device in this era, solid state drives (SSDs, Solid State Disk) are deeply favored by users due to their advantages such as low power consumption, small size, and high shock resistance. With the evolution of the manufacturing process of NAND (a non-volatile flash memory technology), flash memory particles have developed from the initial single-bit storage cells (SLC, Single-Level Cell, i.e., 1 bit / cell), multi-bit storage cells (MLC, Multi-Level Cell, i.e., 2 bit / cell) to today's three-bit storage cells (TLC, Trinary-Level Cell, i.e., 3 bit / cell), four-bit storage cells (QLC, Quad-Level Cell, i.e., 4 bit / cell), and even five-bit storage cells (PLC, Penta-level cell, i.e., 5 Bit / cell). Investigations show that storage devices based on high-density flash memory particles have occupied a relatively large market share, and currently, some manufacturers have completed the productization of solid state storage based on QLC particles, leading a new trend in the development of SSDs.

[0003] Limited by physical characteristics, the higher the storage density of flash memory particles, the more obvious the programming influence between storage cells (cells). To solve this problem, the two-step programming method (TSP, Two-Step Program) has been proposed in related technologies, that is, after the rough programming of the lower-level word line (WL, Word Line) is completed, the fine programming of the upper-level WL is performed. Therefore, the TSP method requires the SSD to retain the data of at least one layer (layer) of WL. To save costs, most manufacturers adopt the strategy of SLC cache (cache) to reduce the use of dynamic random access memory (DRAM, Dynamic Random Access Memory) and balance the input / output (IO, Input-Output) performance. This strategy requires the host (host) data to be first written into the SLC cache (cache), and then the data in the SLC cache is migrated to the QLC. The migration timing is usually during the IO execution process or after the SLC cache is exhausted. This strategy has two problems:

[0004] 1. From the perspective of migration timing, if data is migrated during IO processing, it will occupy the normal IO bandwidth and reduce the SSD performance; if the migration is performed after the SLC cache is exhausted, there will be a phenomenon of a cliff-like drop in IO performance;

[0005] 2. From the perspective of the processing scenario, if the host continuously issues write commands, it is impossible to balance the two processes of data migration and IO processing, or data migration can only be started after the SLC cache is exhausted. Summary of the Invention

[0006] The present disclosure provides a data migration method, apparatus, storage medium, and electronic device to at least solve the above technical problems existing in the prior art.

[0007] The technical solution of the embodiment of the present disclosure is implemented as follows:

[0008] In a first aspect, an embodiment of the present disclosure provides a data migration method, the method including:

[0009] Obtain first information of the solid-state drive, the first information being used to reflect the input / output situation of the solid-state drive;

[0010] If it is determined according to the first information that the solid-state drive meets a first condition, perform a first migration operation; if the solid-state drive does not meet the first condition, perform a second migration operation;

[0011] Wherein, the first migration operation includes: performing a migration operation on cached data; the second migration operation includes: performing a migration operation on cached data according to the cache margin.

[0012] In the above solution, the obtaining of the first information of the solid-state drive includes:

[0013] Obtain the total amount of input / output in each statistical period;

[0014] Determine the first information according to the total amount of input / output in each statistical period.

[0015] In the above solution, the solid-state drive meets the first condition, including:

[0016] The input / output of the solid-state drive is in an idle state in a first statistical period; the first statistical period is the previous period of a second statistical period for which cached data migration is to be performed.

[0017] In the above solution, the performing of the first migration operation includes:

[0018] Determine a first migration speed, and migrate the cached data of the flash memory to the storage unit of the flash memory according to the first migration speed.

[0019] In the above solution, the determining of the first migration speed includes:

[0020] Obtain third information of the solid-state drive, and determine a first migration duration according to the third information, the first migration duration being the time required to complete The time required for migrating the cached data of N parallel pages; N is greater than or equal to 1;

[0021] Determine a first migration speed according to the first migration duration;

[0022] Wherein, the third information includes: a first read duration, a first programming duration, a second programming duration, the number of parallel logical unit numbers (LUNs), and the size of a page.

[0023] In the above solution, the performing the second migration operation includes:

[0024] Obtain second information, where the second information is used to reflect the cache margin of the solid-state drive;

[0025] Determine a second migration speed according to the cache margin;

[0026] Migrate the cached data of the flash memory to the storage unit of the flash memory according to the second migration speed.

[0027] In the above solution, before determining the second migration speed according to the cache margin, the method further includes:

[0028] Compare the cache margin with a first threshold. If the cache margin is less than or equal to the first threshold, determine the second migration speed;

[0029] If the cache margin is greater than the first threshold, determine not to perform data migration.

[0030] In the above solution, the determining the second migration speed includes:

[0031] Obtain the maximum migration speed of the solid-state drive, where the maximum migration speed corresponds to the recycling speed;

[0032] Determine the second migration speed according to the maximum migration speed, the cache margin, the first threshold, and a second threshold.

[0033] In the above solution, the obtaining the maximum migration speed of the solid-state drive includes:

[0034] Determine the maximum migration speed according to a first write duration, a first recycling duration, and a first migration speed.

[0035] In the above solution, the method is applied to a solid-state drive, and the solid-state drive includes: a flash memory chip; the flash memory chip includes: a cache part and a storage unit part;

[0036] The performing the migration operation of the cached data includes: migrating the data of the cache part to the storage unit part;

[0037] Performing a migration operation on cached data according to the cache margin includes: migrating the data in the cache part to the storage unit part according to the cache margin of the cache part.

[0038] In the above solution, the cache part includes an SLC cache; the storage unit part includes at least one of the following: TLC, QLC, PLC.

[0039] In a second aspect, an embodiment of the present disclosure provides a data migration device, which includes:

[0040] A processing module, configured to obtain first information of a solid-state drive, where the first information is used to reflect the input / output situation of the solid-state drive;

[0041] A migration module, configured to perform a first migration operation if it is determined according to the first information that the solid-state drive meets a first condition; if the solid-state drive does not meet the first condition, perform a second migration operation;

[0042] Among them, the first migration operation includes: performing a migration operation on cached data; the second migration operation includes: performing a migration operation on cached data according to the cache margin.

[0043] In the above solution, the processing module is configured to obtain the total input / output amount in each statistical period;

[0044] Determine the first information according to the total input / output amount in each statistical period.

[0045] In the above solution, the solid-state drive meets the first condition, including:

[0046] The input / output of the solid-state drive is in an idle state in a first statistical period; the first statistical period is the previous period of a second statistical period for which cached data migration is to be performed.

[0047] In the above solution, the migration module is configured to determine a first migration speed and migrate the cached data of the flash memory to the storage unit of the flash memory according to the first migration speed.

[0048] In the above solution, the migration module is configured to obtain third information of the solid-state drive and determine a first migration duration according to the third information. The first migration duration is the time required to complete the migration of cached data of N parallel pages; N is greater than or equal to 1;

[0049] Determine the first migration speed according to the first migration duration;

[0050] Among them, the third information includes: a first read duration, a first programming duration, a second programming duration, the number of parallel logical unit numbers (LUNs), and the size of a page (Page).

[0051] In the above solution, the migration module is configured to obtain second information, where the second information is used to reflect the cache remaining amount of the solid-state drive.

[0052] Determine a second migration speed according to the cache remaining amount.

[0053] Migrate the cache data of the flash memory to the storage unit of the flash memory according to the second migration speed.

[0054] In the above solution, before determining the second migration speed according to the cache remaining amount, the migration module is configured to compare the cache remaining amount with a first threshold. If the cache remaining amount is less than or equal to the first threshold, determine the second migration speed.

[0055] If the cache remaining amount is greater than the first threshold, determine not to perform data migration.

[0056] In the above solution, the migration module is configured to obtain the maximum migration speed of the solid-state drive, where the maximum migration speed corresponds to the recycling speed.

[0057] Determine the second migration speed according to the maximum migration speed, the cache remaining amount, the first threshold, and a second threshold.

[0058] In the above solution, the migration module is configured to determine the maximum migration speed according to a first write duration, a first recycling duration, and a first migration speed.

[0059] In the above solution, the device is applied to a solid-state drive, and the solid-state drive includes: a flash memory chip; the flash memory chip includes: a cache part and a storage unit part.

[0060] Performing the migration operation of the cache data includes: migrating the data in the cache part to the storage unit part.

[0061] Performing the migration operation of the cache data according to the cache remaining amount includes: migrating the data in the cache part to the storage unit part according to the cache remaining amount of the cache part.

[0062] In the above solution, the cache part includes an SLC cache; the storage unit part includes at least one of the following: TLC, QLC, PLC.

[0063] In a third aspect, an embodiment of the present disclosure provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and when the instructions are executed by the at least one processor, the at least one processor is enabled to execute any one of the data migration methods.

[0064] In a fourth aspect, embodiments of the present disclosure provide a non-transitory computer-readable storage medium storing computer instructions for causing a computer to execute the data migration method according to any one of the above.

[0065] Embodiments of the present disclosure have the following beneficial effects:

[0066] Applying the data migration method, apparatus, storage medium and electronic device provided by the embodiments of the present disclosure, first information of a solid-state drive is obtained, and the first information is used to reflect the input / output condition of the solid-state drive; if it is determined according to the first information that the solid-state drive meets a first condition, a first migration operation is executed; if the solid-state drive does not meet the first condition, a second migration operation is executed; wherein, the first migration operation includes: executing a migration operation of cached data; the second migration operation includes: executing a migration operation of cached data according to the cache margin. In this way, by obtaining the first information of the solid-state drive and making a decision on the migration operation according to its input / output condition, intelligent data migration is achieved, and the timing and manner of data migration are optimized.

[0067] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] Figure 1 is a schematic flowchart of a data migration method provided by an embodiment of the present disclosure;

[0069] Figure 2 is a schematic diagram of the change of the second cache rate provided by an embodiment of the present disclosure;

[0070] Figure 3 is a schematic diagram of a cache migration process provided by an embodiment of the present disclosure;

[0071] Figure 4 is a schematic flowchart of a data migration method provided by an application embodiment of the present disclosure;

[0072] Figure 5 is a schematic diagram of the structure of a solid-state drive provided by an embodiment of the present disclosure;

[0073] Figure 6 is a schematic diagram of the structure of a data migration apparatus provided by an embodiment of the present disclosure;

[0074] Figure 7 is a schematic diagram of the structure of an electronic device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0075] To make the objectives, features, and advantages of the present disclosure more apparent and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present disclosure.

[0076] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0077] If similar descriptions such as "first / second" appear in the application documents, the following explanation is added. In the following description, the terms "first\second\third" are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence when permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0078] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0079] Before further elaborating on the embodiments of the present disclosure, the nouns and terms involved in the embodiments of the present disclosure are explained. The nouns and terms involved in the embodiments of the present disclosure are subject to the following explanations.

[0080] A solid-state drive (SSD) is a hard disk based on flash storage technology that uses flash memory cells instead of the rotating disks of a traditional hard disk drive (HDD). The advantages of SSDs include faster read and write speeds, lower power consumption, and higher shock resistance. The core storage unit of an SSD is typically NAND flash memory, and there are different types of NAND flash memory, such as SLC (single-level cell), MLC (multi-level cell), TLC (triple-level cell), and QLC (quadruple-level cell).

[0081] SLC (Single-Level Cell) is the most basic storage type, with each cell storing one bit of data (0 or 1). SLC flash memory has high durability and faster write speeds and is suitable for applications with high performance requirements.

[0082] QLC (Quad-Level Cell) is a type of flash memory with the highest storage density, storing 4 bits of data per cell. Compared with SLC, QLC has a higher storage density but a slower write speed.

[0083] Two-Step Program (TSP) is a technology proposed for high-density flash memory to avoid interference between cells of different layers of WL (word line). The meaning of "two-step" is to write to the same WL twice. There are generally two ways to implement TSP. One is to use DRAM to implement TSP, but this method is costly. Therefore, another method is proposed, that is, the data is first written into the SLC cache, and then the data in the SLC cache is migrated to QLC. This migration process usually occurs in the following two situations:

[0084] During the IO execution process: When the SSD has idle time, the cached data is written to QLC in the background;

[0085] After the SLC cache is exhausted: When the SLC cache is full, new data will be directly written to QLC, and the data in the cache will be migrated to QLC at the same time.

[0086] The SLC cache serves as a temporary storage area for storing frequently written data. It enables the SSD to provide high performance in a short time because the write speed of SLC is much higher than that of QLC. When the cache is full, the cached data must be migrated to QLC, which may cause performance fluctuations.

[0087] Therefore, the choice of the data migration timing is crucial. In most cases, the migration operation is asynchronous, which means that the data writing process will not be interrupted due to the migration process. If there is too much cached data, the migration operation will slow down the new writing process. However, in related technologies, the migration generally occurs during the IO execution process or after the SLC cache is exhausted, which will inevitably affect the IO performance and even result in a cliff-like decline in IO performance. Therefore, it is necessary to solve the problem of reasonably scheduling and managing data migration and IO processing to reduce performance fluctuations caused by migration.

[0088] Based on this, embodiments of the present disclosure provide a data migration method, apparatus, storage medium, and electronic device. The method includes obtaining first information of a solid-state drive (SSD), where the first information is used to reflect the input / output (IO) situation of the SSD. If it is determined according to the first information that the SSD meets a first condition, a first migration operation is performed; if the SSD does not meet the first condition, a second migration operation is performed. The first migration operation includes performing a migration operation on cached data, and the second migration operation includes performing a migration operation on cached data according to the cache margin. In this way, by obtaining the first information of the SSD and making a decision on the migration operation based on its input / output situation, intelligent data migration is achieved, and the timing and manner of data migration are optimized.

[0089] Figure 1 FIG. 4 is a flowchart of a data migration method provided by an embodiment of the present disclosure. As Figure 1 shown, the data migration method includes:

[0090] Step 101: Obtain first information of a solid-state drive (SSD); the first information is used to reflect the input / output (IO) situation of the SSD.

[0091] Step 102: If it is determined according to the first information that the SSD meets a first condition, perform a first migration operation; if the SSD does not meet the first condition, perform a second migration operation.

[0092] Among them, the first migration operation includes performing a migration operation on cached data; the second migration operation includes performing a migration operation on cached data according to the cache margin.

[0093] Here, the first migration operation is a migration operation that starts quickly and performs data migration at a first migration speed; the second migration operation performs data migration at a second migration speed.

[0094] The second migration speed and the first migration speed represent the migration speed of the data in the cache. The second migration speed is lower than the first migration speed, and during the second migration operation, the second migration speed can change according to the size of the cache margin, that is, the second migration operation performs data migration at a variable migration speed (i.e., the second migration speed).

[0095] In this way, when the SSD meets the first condition, data migration is performed at a first rate, and when it does not meet the first condition, a migration operation on cached data is performed according to the cache margin (the migration speed can be adjusted), taking into account both cache migration and IO processing, balancing the two processes of IO processing and cached data migration, and avoiding a cliff-like drop in IO performance.

[0096] Specifically, determining whether to perform the first migration operation or the second migration operation according to the input / output conditions of the solid-state drive helps avoid excessive occupation of the IO bandwidth, thereby reducing interference with normal IO operations and maintaining the high performance of the SSD. Moreover, when performing the second migration operation, the data migration speed can be flexibly adjusted according to the cache margin to prevent the phenomenon of a cliff-like drop in IO performance.

[0097] In some embodiments, obtaining the first information of the solid-state drive includes:

[0098] Obtaining the total amount of input / output within the first statistical period;

[0099] Determining the first information according to the total amount of input / output within the first statistical period.

[0100] Here, the total amount of input / output represents the data input and / or output by the solid-state drive within the first statistical period. According to the first information, it can be determined whether the IO is in an idle state.

[0101] Here, the input and / or output data may include read data and / or write data.

[0102] The first statistical period may be a predetermined time window, which may be dozens to hundreds of milliseconds or other appropriate time periods. Within this time period, the SSD will count all the input / output data volumes it processes.

[0103] Here, by calculating the total amount of input / output of the SSD within the first statistical period, the operating condition of the SSD, that is, whether it is in such an idle state, can be obtained. For example, if the total amount of input / output is high, it can be considered that the SSD is in a relatively busy state; if the total amount of input / output is low, it can be considered that the SSD is in a low-load state; if the total amount of input / output is 0 or close to 0, it can be considered that the SSD is in an idle state.

[0104] The first information may specifically represent that the input / output condition is in an idle state or a non-idle state; it may also be a busy state, an idle or low-load state, etc.

[0105] Here, by obtaining the first information of the solid-state drive and evaluating the load condition of the SSD based on the total amount of input / output within the first statistical period, the system can effectively monitor the real-time performance and resource utilization of the SSD. The total amount of input / output reflects the data processing volume of the SSD within this period, can intuitively reflect the current IO load, and further determine whether the SSD is in an idle state. Based on these data, the system can dynamically adjust the IO processing and cache data migration strategies to optimize performance under different load conditions.

[0106] Specifically, if it is detected that the IO is in an idle state, the migration rate of the cached data can be appropriately increased in a timely manner to improve the cache recovery efficiency and avoid performance waste caused by resource idleness. In a high-load situation, the system will limit the data migration speed, reduce the occupation of the IO bandwidth, and prevent a sharp decline in the IO performance or excessive consumption of the bandwidth.

[0107] In this way, the dynamic adjustment based on the IO situation can not only avoid the performance fluctuations caused by frequent migrations in the traditional method, but also ensure the stable operation of the SSD in different usage scenarios. By optimizing the resource allocation, avoiding the excessive occupation of the IO bandwidth and performance fluctuations, the efficiency and reliability of the SSD are improved.

[0108] In some embodiments, the solid-state drive satisfies the first condition, including:

[0109] The input and output of the solid-state drive are in an idle state within the first statistical period; the first statistical period is the previous period of the second statistical period for which the cached data migration is to be executed.

[0110] Here, using the principle of temporal locality, it is considered that if the IO was in an idle state in the previous time period (equivalent to the first statistical period), it can be reasonably considered that there is a high probability that the IO will be idle at the next moment (equivalent to the second statistical period). Therefore, it is possible to determine whether to start the background migration of the cached data (i.e., the first migration operation) based on the state of the previous time period.

[0111] It should be noted that the next moment can refer to the start moment of the second statistical period. The first statistical period and the second statistical period are equivalent to two time windows that slide as time changes. Therefore, for the current moment, if the IO has been in an idle state within the first statistical period between them, it is equivalent to the current moment being a time point at which data migration can be executed, and these time points continuously form the second statistical period. Therefore, it is not difficult to understand that, in terms of time, the second statistical period represents a period of time after the first statistical period, and the time length of the second statistical period can be the same as or different from the time length of the first statistical period. For example, if IO processing suddenly occurs after the cached data migration is executed, the time length of the second statistical period can be less than the length of the first statistical period.

[0112] In this way, the regularity brought by temporal locality is utilized, effectively improving the resource scheduling efficiency of the system. Specifically, if the input / output is in an idle state during the first statistical period, it means that the load on the SSD is relatively low during this time period, and there is a high probability that the system will continue to maintain a low IO load in the subsequent second statistical period. At this time, by starting the background data migration operation, this idle time can be effectively utilized to complete the migration task of the cached data in advance without affecting the current IO performance. The cache migration method based on the state prediction of the previous cycle can not only avoid the delay caused by waiting for the IO idle state, but also reasonably process the data when the SSD load is low, improving the overall performance of the system; by avoiding starting the migration operation during high load, the occupation of the SSD bandwidth can be reduced, avoiding the generation of performance bottlenecks.

[0113] In some embodiments, the performing the first migration operation includes:

[0114] Determine a first migration speed;

[0115] Migrate the cached data of the flash memory to the storage unit of the flash memory according to the first migration speed.

[0116] Here, the cached data of the flash memory refers to the data in the SLC cache of the solid-state drive; the cache refers to the SLC cache, which is simply referred to as the cache here;

[0117] The storage unit of the flash memory includes at least one of the following: TLC, QLC, PLC;

[0118] Migrate the cached data of the flash memory to the storage unit of the flash memory means: migrate the data in the SLC cache to the storage unit (such as QLC) of the flash memory.

[0119] When starting a normal migration (i.e., the first migration operation), the amount of migration data processed by the SSD per unit time (i.e., the migration speed) needs to match the current statistical period (denoted as dt), so as to ensure a rapid response to bursty IOs in the next statistical period.

[0120] In some embodiments, the determining the first migration speed includes:

[0121] Obtain third information of the solid-state drive, and determine a first migration duration according to the third information, where the first migration duration is the time required to complete the migration of the cached data of N parallel pages; N is greater than or equal to 1;

[0122] Determine the first migration speed according to the first migration duration;

[0123] Among them, the third information includes: the first read duration, the first programming duration, the second programming duration, the number of parallel logical unit numbers (LUNs, Logical Unit Numbers), and the size of a page.

[0124] Here, the first read duration is the time required to read one SLC (Single-Level Cell) page.

[0125] The first programming duration is the duration for roughly writing data into one QLC (quad-level cell) page (i.e., the duration for roughly programming one QLC page).

[0126] The second programming duration is the time for finely writing data into one QLC page (i.e., the duration for finely programming one QLC page); among them, rough programming refers to the write operation of the flash memory, which means a process of quickly writing but not fully optimizing, while fine programming usually means that more precise optimization of data is performed during the write process to improve storage stability and long-term service life. Therefore, the second programming duration is generally longer than the first programming duration.

[0127] A LUN is a logical unit number used to represent a storage unit in the flash memory chip. In the flash memory, multiple LUNs can usually operate in parallel to improve the system performance. Therefore, the number of parallel LUNs (denoted as N, N is greater than or equal to 1) represents the number of storage units supported by the flash memory chip for parallel processing. Generally, the larger N is, the stronger the parallel read / write ability of the flash memory.

[0128] A page refers to the page of the flash memory, usually a fixed storage block size (such as 4KB, 8KB, etc.). The page of the flash memory is the basic unit for read / write operations.

[0129] The N parallel pages refer to the N SLC pages corresponding to N parallel LUNs. It should be noted that since these N parallel pages here are on N different LUNs, and a LUN is the smallest unit for parallel read / write. Therefore, the time to migrate one page on one LUN is close to the time to simultaneously migrate the N corresponding parallel pages on N LUNs.

[0130] The first migration speed characterizes the amount of migration data processed by the solid-state drive per unit time.

[0131] It should be noted that the first read duration, the first programming duration, the second programming duration, the number of parallel logical unit numbers, and the size of the page in the above third information are determined based on the attributes or parameters of the solid-state drive itself. Different solid-state drives may have different third information. The following description of the third information is only an example for understanding the determination method of the first migration speed.

[0132] For example, assume that the time to read an SLC page (i.e., the first read duration) is , and the time to roughly program a QLC page (i.e., the first program duration) is , and the time to finely program a QLC page (i.e., the second program duration) is , the number of parallel LUNs of the flash memory chip (i.e., the number of parallel logical unit numbers) is , the size of each page (i.e., the size of the page) is , then it is determined that the time required to complete the cache data migration of parallel pages is approximately ;

[0133] Then, according to the time required to complete the cache data migration of pages, the first migration speed (i.e., the amount of migration data processed per unit time) is determined to be . That is indicates that when in the idle state, the solid-state drive only performs data migration operations to migrate the data in the cache part to the storage unit part (such as SLC cache to QLC), and when operating at full load, it represents the maximum rate of data migration (or SLC recycling).

[0134] Here, within the statistical period, combined with the first migration speed it can be known that the maximum amount of data that the solid-state drive can migrate is , where dt represents the duration of the statistical period;

[0135] Therefore, when the IO is in the idle state, within the statistical period, the solid-state drive can at most continuously process of cache data volume to ensure the response time of burst IO in the next statistical period.

[0136] Here is an application embodiment. Assume , , , , , , then the first migration speed is approximately , then the amount of data migrated within dt = 100 ms is at most approximately 48 MiB.

[0137] In some embodiments, the performing of the second migration operation includes:

[0138] Obtaining second information, where the second information is used to reflect the cache margin of the solid-state drive;

[0139] Determining a second migration speed according to the cache margin;

[0140] Migrate the cached data of the flash memory to the storage unit of the flash memory according to the second migration speed.

[0141] Here, the cache refers to the SLC cache, and the cache margin refers to the remaining space of the SLC cache of the solid-state drive;

[0142] The cached data of the flash memory refers to the data in the SLC cache of the solid-state drive;

[0143] The cache unit of the flash memory may include at least one of the following: TLC, QLC, PLC;

[0144] Migrate the cached data of the flash memory to the storage unit of the flash memory means: migrate the data in the SLC cache to the storage unit (such as QLC) of the flash memory.

[0145] In actual design, a detection unit may be designed in the solid-state drive. The detection unit is used to detect the cache margin of the solid-state drive, and according to the detected cache margin, the size of the cache (i.e., SLC cache) in the solid-state drive that is in the released state and has not been written with data can be judged.

[0146] In this way, by monitoring the cache margin and performing targeted cache data migration, it helps to avoid the cache space being filled up, ensure the smooth migration of cached data, and avoid a cliff-like drop in SSD performance. This method can balance the process of data migration and normal IO processing by dynamically adjusting the data migration strategy, avoid suddenly starting data migration when the cache is exhausted, and reduce the risk of system instability and performance fluctuations.

[0147] In some embodiments, before determining the second migration speed according to the cache margin, the method further includes:

[0148] Compare the cache margin with a first threshold. If the cache margin is less than or equal to the first threshold, determine the second migration speed;

[0149] If the cache margin is greater than the first threshold, determine not to perform data migration.

[0150] In some embodiments, determining the second migration speed includes:

[0151] Obtain the maximum migration speed of the solid-state drive; the maximum migration speed corresponds to the recycling speed;

[0152] Determine the second migration speed according to the maximum migration speed, cache margin, first threshold, and second threshold.

[0153] Wherein, obtaining the maximum migration speed of the solid-state drive includes:

[0154] Determine the maximum value of the migration speed based on the first write duration, the first recycling duration, and the first migration speed.

[0155] Here, the second migration speed characterizes the amount of migrated data processed by the solid-state drive per unit time. Since the cache margin changes during the migration and / or recycling process, it is not difficult to understand that the second migration speed is a variable value.

[0156] The first write duration represents the time required to write data to an SLC page.

[0157] The first recycling duration represents the time required to recycle (i.e., complete data migration) the data of N parallel pages. Here, the N parallel pages refer to the N SLC pages corresponding to N parallel LUNs. The time required to recycle the data of one page on one LUN is very close to, and equivalent to, the time required to simultaneously recycle the data of the N corresponding parallel pages on N LUNs.

[0158] To implement the second migration operation, it is necessary to determine the ratio of the amount of cached migrated data to the amount of IO data. For example, assume that the time (i.e., the first write duration) required to write data to an SLC page is , and the time (the first recycling duration) required to recycle the data of N parallel SLC pages is ;

[0159] Determine that the maximum value of the migration speed in the second migration operation is .

[0160] Specifically, when the cache margin reaches the second threshold (i.e., close to ), the SSD needs to ensure that the recycling rate of the cache is basically the same as the consumption rate, so as to stabilize the cache margin for subsequent IO to proceed smoothly. Therefore, within the time period of the statistical cycle (dt), of the time should be allocated to cache data migration, and the remaining time should be allocated to normal IO; here, determine that the maximum value of the amount of cached data migrated within the dt time period is . Therefore, according to the maximum value of the migration speed can be determined as being .

[0161] When the cache margin just reaches the first threshold (i.e., greater than , and close to ), the SLC data migration just starts, and the amount of SLC data migrated within the dt time period is almost zero; according to ( , 0) and ( , For two nodes, a functional relationship between the cache margin and the amount of cached data migrated within the dt time period T can be established, obtaining the following relationship: ;

[0162] Based on this relationship, the second migration speed is further determined

[0163] where T represents the amount of migrated data within the dt time period, represents the maximum value of the amount of migrated data within the dt time period, r represents the cache margin, and dt represents the duration of the statistical period.

[0164] Through the above method, when starting hybrid processing (i.e., migrating cached data and performing IO processing simultaneously), the amount of cached data migrated and the amount of IO data processed within the statistical period (dt) are reasonably allocated. On the one hand, it avoids a cliff-like drop in IO performance and ensures stability; on the other hand, it delays the consumption of the cache and ensures that subsequent IO can proceed normally.

[0165] By designing two thresholds and , when the cache margin is just less than the first threshold , the SSD starts to migrate the cached data during the IO process, and at this time, the IO performance slightly decreases; when the cache margin approaches (here, approaching means that the difference between the cache margin and the second threshold is close to 0) the second threshold , the SSD needs to ensure that the cache recovery rate is basically the same as the consumption rate, so as to stabilize the cache margin and smoothly perform subsequent IO.

[0166] From the first threshold to the second threshold , the bandwidth occupancy ratio caused by the cache migration gradually increases, and the IO bandwidth occupancy ratio gradually decreases, effectively avoiding a cliff-like drop in IO performance. In addition, during the second migration operation, there may be a situation where the IO is idle, and at this time, the migration method can be directly switched to the first migration operation, thereby accelerating the cache recovery speed.

[0167] Figure 2 is a schematic diagram of the change in the second cache rate provided by the embodiment of the present disclosure; as Figure 2 shown, the second migration speed varies with the change of the cache margin r. When the cache margin r is greater than the threshold , there is no need to migrate the cached data. When the cache margin r is just less than the threshold , the SSD starts to migrate the cached data during the IO process, and at this time, the IO performance slightly decreases; as the cache margin r changes from the threshold to the threshold , and its migration speed also increases from 0 to the maximum , the is used to ensure that the cache recycling rate is basically consistent with the consumption rate, so as to stabilize the cache margin and smoothly perform subsequent I / O.

[0168] Figure 3 is a schematic diagram of a cache migration process provided by an embodiment of the present disclosure; Figure 3 In it, I / O indicates the existence of an I / O operation and a non-idle state, idle indicates an idle state without an I / O operation, and reaching the first threshold means that when there is an I / O operation and a non-idle state, the cache margin exceeds the first threshold. As Figure 3 shown, at the beginning, the cache margin space is sufficient, and no cache data migration will occur when the system accepts I / O operations; when the firmware captures the idle state, it migrates the cache data at the migration speed when idle (the speed is ), and stops until the next I / O operation occurs; after continuing the I / O operation for a period of time, the cache margin is insufficient and has reached the first threshold ( ), then the second migration operation starts, and the system gradually increases the cache data migration speed, with a maximum of v mix ; when the idle state is detected again, the system continues to migrate data quickly (at this time the migration speed is ).

[0169] In some embodiments, the method is applied to a solid-state drive, and the solid-state drive includes: a flash memory chip; the flash memory chip includes: a cache part and a storage unit part;

[0170] Performing the migration operation of the cache data includes: migrating the data in the cache part to the storage unit part;

[0171] Performing the migration operation of the cache data according to the cache margin includes: migrating the data in the cache part to the storage unit part according to the cache margin of the cache part.

[0172] Here, the cache part includes an SLC cache; the storage unit part includes at least one of the following: TLC, QLC, PLC.

[0173] Among them, QLC (Quad-Level Cell): Each storage unit (NAND flash memory unit) can store 4 bits of data.

[0174] TLC (Triple-Level Cell): Each storage unit can store 3 bits of data. Compared with QLC, TLC has slightly higher durability, but each unit stores more data, which means its storage density is relatively high and its performance is also more balanced.

[0175] PLC (Penta-Level Cell): Each storage cell can store 5 bits of data. Compared with QLC, PLC stores more data per cell, thus further improving the storage density.

[0176] In the embodiments of the present disclosure, by taking advantage of the fact that the SLC cache has a higher read / write speed, the short-term random read / write performance of the SSD is significantly improved. After writing data into the SLC cache, the data is migrated to storage units such as TLC, QLC, or PLC according to the cache margin. This not only optimizes the utilization of storage space but also reduces the write latency.

[0177] In addition, this dynamic management can also keep the performance of the SSD stable and avoid performance fluctuations caused by cache fullness. By dynamically managing (i.e., based on whether the first condition is met and combined with the cache margin) the cache data migration, the SSD can optimize the storage space while improving the performance, enhancing the cost performance and user experience of the device.

[0178] Figure 4 It is a schematic flowchart of a data migration method provided by an application embodiment of the present disclosure; as Figure 4 shown, the method is applied to a solid-state drive, such as the solid-state drive shown below Figure 5 shown, and the method includes:

[0179] Step 401, periodically detect the IO status;

[0180] Here, the total input / output (IO) of the solid-state drive is monitored according to the statistical period, and it is determined whether the IO status within the statistical period is an idle state based on the total input / output.

[0181] Step 402, determine whether the IO is in an idle state; if the IO is in an idle state, perform the first migration operation; if the IO is not in an idle state, go to step 403;

[0182] Here, using the principle of temporal locality, it is considered that if the IO in the previous statistical period (equivalent to the first statistical period) is in an idle state, it can be reasonably considered that the IO in the next moment (equivalent to the second statistical period) has a high probability of being idle, and the IO status in the next statistical period is speculated based on this.

[0183] Step 403, detect the cache margin;

[0184] Here, the cache refers to the SLC cache of the solid-state drive. Correspondingly, the cache margin refers to the remaining space of the SLC cache of the solid-state drive;

[0185] Step 404, determine whether there is a cache margin warning; if there is a cache margin warning, perform the second migration operation, and if there is no cache margin warning, perform normal IO.

[0186] Here, two thresholds are provided, denoted as and , Greater than ; Denote the cache margin as r. Judging whether there is a cache margin warning includes: comparing the cache margin r with the threshold and the threshold . If , then perform the second migration operation. If , then perform normal IO processing.

[0187] Here, performing the second migration operation requires balancing IO performance and cache migration. When the cache margin r is just less than the threshold , the SSD starts to migrate the cached data during the IO process, and at this time, the IO performance decreases slightly; when the cache margin slowly approaches the threshold , the SSD needs to ensure that the cache recovery rate is basically the same as the consumption rate, so as to stabilize the cache margin to smoothly perform subsequent IO.

[0188] A method for determining the second migration speed is proposed. According to the two nodes of ( , 0) and ( , ), calculate according to the following formula:

[0189] ;

[0190] Among them, T represents the amount of migrated data within dt time, represents the maximum value of the amount of migrated data within dt time, r represents the cache margin, and dt represents the duration of the statistical period. Specifically, reference can be made to the description in the method shown in Figure 1 , which will not be elaborated here.

[0191] The method provided by the embodiments of the present disclosure dynamically adjusts the data migration operation according to the input and output conditions of the solid state drive (SSD) to optimize the SSD performance and balance the cache data migration and IO processing. Specifically, when the SSD meets specific conditions (i.e., the idle state), data migration is performed at a relatively high rate to ensure that the SSD performance is fully exerted under low load; while when the load is high (i.e., the non-idle state), the migration speed is adjusted according to the cache margin to avoid over-occupying resources, thereby reducing the impact on IO performance.

[0192] In this way, it is possible to effectively avoid the cliff-like decline of IO performance and ensure that relatively stable performance can be maintained under various load conditions. At the same time, this dynamic adjustment method enables the cache data migration and IO processing processes to coordinate with each other, avoiding the performance fluctuations caused by frequent migrations in traditional methods.

[0193] In addition, performing the migration operation according to the cache margin can also reduce frequent writes to the hard disk and lower the write pressure. Since the cache migration speed can be flexibly adjusted, this method can better adapt to different load conditions and ensure that the SSD can still maintain high stability and response speed during use.

[0194] Figure 5 Schematic diagram of the structure of a solid-state drive provided by an embodiment of the present disclosure; as Figure 5 shown, the solid-state drive includes: an IO interface, a cache migration module, and a flash memory;

[0195] Among them, the IO interface is used for data transmission with external devices (such as a host).

[0196] The cache migration module is responsible for migrating data between the SLC cache and the QLC particles, and it can manage the cache space and ensure data migration as needed.

[0197] The flash memory is the storage medium of the solid-state drive, the place where data is actually stored.

[0198] Specifically, the cache migration module may include: a timer, an IO statistics unit, a cache margin detection unit, and a cache migration processing unit;

[0199] The timer is used to notify the IO statistics unit to periodically count the IO situation; for example, it can be set to count once every dozens or hundreds of milliseconds.

[0200] The cache margin monitoring unit is used to monitor the margin of the SLC cache in real time (i.e., the above-mentioned cache margin);

[0201] The IO statistics unit and the cache margin monitoring unit respectively output two parameters, the IO situation and the cache margin, in the previous statistical period to the cache migration processing unit;

[0202] The cache migration processing unit is used to determine the amount of cache migration data per cycle, configure cache migration information, etc., so as to notify the flash memory side to complete the data migration from the cache to the QLC particles, that is, the cache migration processing unit determines how much data should be migrated per cycle, that is, determines the migration speed, and configures relevant cache migration information according to the statistical data (IO situation and cache margin) provided by the former two. For the specific operations performed by the cache migration processing unit, reference can be made to Figure 1 the method shown, which will not be elaborated here.

[0203] Figure 6 Schematic diagram of the structure of a data migration device provided by an embodiment of the present disclosure; as Figure 6 shown, the device includes:

[0204] A processing module, configured to obtain first information of a solid-state drive, where the first information is used to reflect the input / output condition of the solid-state drive;

[0205] A migration module, configured to perform a first migration operation if it is determined according to the first information that the solid-state drive meets a first condition; and perform a second migration operation if the solid-state drive does not meet the first condition;

[0206] Wherein, the first migration operation includes: performing a migration operation on cached data; and the second migration operation includes: performing a migration operation on cached data according to the cache margin.

[0207] In some embodiments, the processing module is configured to obtain the total input / output amount within each statistical period;

[0208] Determine the first information according to the total input / output amount within each statistical period.

[0209] In some embodiments, the solid-state drive meets the first condition, including:

[0210] The input / output of the solid-state drive is in an idle state within a first statistical period; and the first statistical period is the previous period of a second statistical period for which cached data migration is to be performed.

[0211] In some embodiments, the migration module is configured to determine a first migration speed, and migrate the cached data of the flash memory to the storage unit of the flash memory according to the first migration speed.

[0212] In some embodiments, the migration module is configured to obtain third information of the solid-state drive, and determine a first migration duration according to the third information, where the first migration duration is the time required to complete the migration of cached data of N parallel pages; N is greater than or equal to 1;

[0213] Determine the first migration speed according to the first migration duration;

[0214] Wherein, the third information includes: a first read duration, a first programming duration, a second programming duration, the number of parallel logical unit numbers (LUNs), and the size of a page.

[0215] In some embodiments, the migration module is configured to obtain second information, where the second information is used to reflect the cache margin of the solid-state drive;

[0216] Determine a second migration speed according to the cache margin;

[0217] Migrate the cached data of the flash memory to the storage unit of the flash memory according to the second migration speed.

[0218] In some embodiments, the migration module is configured to compare the cache margin with a first threshold before determining a second migration speed according to the cache margin. If the cache margin is less than or equal to the first threshold, the second migration speed is determined.

[0219] If the cache margin is greater than the first threshold, it is determined not to perform data migration.

[0220] In some embodiments, the migration module is configured to obtain the maximum migration speed of the solid-state drive, and the maximum migration speed corresponds to the recycling speed.

[0221] The second migration speed is determined according to the maximum migration speed, the cache margin, the first threshold, and the second threshold.

[0222] In some embodiments, the migration module is configured to determine the maximum migration speed according to a first write duration, a first recycling duration, and a first migration speed.

[0223] In some embodiments, the device is applied to a solid-state drive, and the solid-state drive includes: a flash memory chip; the flash memory chip includes: a cache part and a storage unit part;

[0224] Performing the migration operation of the cache data includes: migrating the data in the cache part to the storage unit part;

[0225] Performing the migration operation of the cache data according to the cache margin includes: migrating the data in the cache part to the storage unit part according to the cache margin of the cache part.

[0226] In some embodiments, the cache part includes an SLC cache; the storage unit part includes at least one of the following: TLC, QLC, PLC.

[0227] It can be understood that when the data migration device provided in the above embodiments implements the corresponding data migration method, the above processing can be allocated to different program modules as needed to complete all or part of the processing described above. In addition, the device provided in the above embodiments and the embodiments of the corresponding method belong to the same concept, and the specific implementation process can be seen in the method embodiments, which will not be elaborated here.

[0228] An embodiment of the present application provides a computer program product or a computer program, and the computer program product or the computer program includes computer instructions, and the computer instructions are stored in a computer-readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the data migration method.

[0229] An embodiment of the present application provides a computer-readable storage medium storing executable instructions, where the executable instructions, when executed by a processor, cause the processor to execute the data migration method provided by the embodiment of the present application.

[0230] In some embodiments, the computer-readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disc, or CD-ROM; or may be various devices including one or any combination of the above memories.

[0231] In some embodiments, the executable instructions may be in the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including being deployed as an independent program or being deployed as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0232] As an example, the executable instructions may or may not correspond to a file in the file system, may be stored as part of a file that stores other programs or data, for example, in one or more scripts in a Hyper Text Markup Language (HTML) document, stored in a single file dedicated to the program being discussed, or stored in multiple cooperating files (for example, files that store one or more modules, subroutines, or code portions).

[0233] As an example, the executable instructions may be deployed to execute on one computing device, or on multiple computing devices located at one location, or, on multiple computing devices distributed at multiple locations and interconnected by a communication network.

[0234] Figure 7 A schematic structural diagram of an electronic device provided by an embodiment of the present disclosure; as Figure 7 shown, the electronic device 70 includes: a processor 701, and a memory 702 communicatively connected to the processor 701; the memory 702 stores instructions executable by the processor 701. The instructions are executed by the processor 701 to enable the processor 701 to execute:

[0235] Obtain first information of the solid-state drive, where the first information is used to reflect the input / output situation of the solid-state drive; if it is determined according to the first information that the solid-state drive meets the first condition, perform a first migration operation; if the solid-state drive does not meet the first condition, perform a second migration operation; where the first migration operation includes: performing a migration operation of cached data; the second migration operation includes: performing a migration operation of cached data according to the cache margin.

[0236] The electronic device provided in the above embodiment and the embodiment of the corresponding data migration method belong to the same concept. For the specific implementation process, refer to the method embodiment, which will not be elaborated here.

[0237] In practical applications, the electronic device 70 may further include: at least one network interface 703. Each component in the electronic device 70 is coupled together through a bus system 704. It can be understood that the bus system 704 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 704 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clear illustration, in Figure 7 all kinds of buses are labeled as the bus system 704. Among them, the number of the processors 701 can be at least one, and the number of the memories 702 can be at least one. The network interface 703 is used for the communication between the electronic device 70 and other devices in a wired or wireless manner.

[0238] The memory 702 in the embodiments of the present disclosure is used to store various types of data to support the operation of the electronic device 70.

[0239] The method disclosed in the above embodiments of the present disclosure can be applied to the processor 701 or implemented by the processor 701. The processor 701 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit in the hardware of the processor 701 or the instructions in the form of software. The above processor 701 may be a general-purpose processor, a digital signal processor (DSP, Digital Signal Processor), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor 701 can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present disclosure. The general-purpose processor may be a microprocessor or any conventional processor, etc. Combining the steps of the method disclosed in the embodiments of the present disclosure, it can be directly embodied as being executed by the hardware decoding processor, or executed by the combination of the hardware and software modules in the decoding processor. The software module may be located in the storage medium, and this storage medium is located in the memory 702. The processor 701 reads the information in the memory 702 and combines its hardware to complete the steps of the foregoing data migration method.

[0240] In some embodiments, the electronic device 70 may be implemented by one or more application specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field programmable gate arrays (FPGAs), general purpose processors, controllers, microcontroller units (MCUs), microprocessors, or other electronic components for performing the foregoing methods.

[0241] It should be understood that the various forms of the processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved. No limitation is imposed herein.

[0242] In the above description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0243] Unless otherwise defined, all technical and scientific terms used in this disclosure have the same meaning as commonly understood by those of ordinary skill in the technical field to which this disclosure belongs. The terms used in this disclosure are only for the purpose of describing the embodiments of this disclosure and are not intended to limit this disclosure.

[0244] It should be understood that in the various embodiments of this disclosure, the magnitude of the sequence numbers of the various implementation processes does not imply the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of this disclosure.

[0245] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of this disclosure, "a plurality of" means two or more unless otherwise specifically defined.

[0246] As described above, this is only a specific implementation manner of the present disclosure. However, the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claimed rights.

Claims

1. A data migration method, characterized in that, The method includes: Obtaining first information of the solid-state drive, where the first information is used to reflect the input / output condition of the solid-state drive; If it is determined according to the first information that the solid-state drive meets a first condition, performing a first migration operation; if the solid-state drive does not meet the first condition, performing a second migration operation; Wherein, the first migration operation includes: performing a migration operation on cached data; the second migration operation includes: performing a migration operation on cached data according to the cache margin; Wherein, the solid-state drive meeting the first condition includes: The input / output of the solid-state drive is in an idle state within a first statistical period; the first statistical period is the previous period of a second statistical period for which cached data migration is to be performed; Performing the first migration operation includes: Determining a first migration speed, and migrating the cached data of the flash memory to the storage unit of the flash memory according to the first migration speed; Performing the second migration operation includes: Obtaining second information, where the second information is used to reflect the cache margin of the solid-state drive; Determining a second migration speed according to the cache margin; Migrating the cached data of the flash memory to the storage unit of the flash memory according to the second migration speed.

2. The method according to claim 1, wherein Obtaining the first information of the solid-state drive includes: Obtaining the total amount of input / output within each statistical period; Determining the first information according to the total amount of input / output within each statistical period.

3. The method according to claim 1, wherein Determining the first migration speed includes: Obtain the third information of the solid-state drive, and determine a first migration duration according to the third information, where the first migration duration is the time required to complete the cache data migration of N parallel pages; N is greater than or equal to 1; Determining the first migration speed according to the first migration duration; Wherein, the third information includes: a first read duration, a first programming duration, a second programming duration, the number of parallel logical unit numbers LUN, and the size of a page.

4. The method according to claim 1, wherein Before determining the second migration speed according to the cache margin, the method further includes: Comparing the cache margin with a first threshold, if the cache margin is less than or equal to the first threshold, determining the second migration speed; If the cache margin is greater than the first threshold, determining not to perform data migration.

5. The method according to claim 1, characterized in that Determining the second migration speed includes: Obtaining the maximum migration speed of the solid-state drive, where the maximum migration speed corresponds to the recycling speed; Determining the second migration speed according to the maximum migration speed, the cache margin, the first threshold, and the second threshold.

6. The method according to claim 5, characterized in that Obtaining the maximum migration speed of the solid-state drive includes: Determining the maximum migration speed according to a first write duration, a first recycling duration, and a first migration speed.

7. The method according to claim 1, characterized in that, The method is applied to a solid-state drive, and the solid-state drive includes: a flash memory chip; the flash memory chip includes: a cache part and a storage unit part; Performing the migration operation on cached data includes: migrating the data in the cache part to the storage unit part; Performing the migration operation on cached data according to the cache margin includes: migrating the data in the cache part to the storage unit part according to the cache margin of the cache part.

8. The method according to claim 7, wherein The cache part includes a single-bit storage cell SLC cache; the storage unit part includes at least one of the following: a three-bit storage cell TLC, a four-bit storage cell QLC, and a five-bit storage cell PLC.

9. A data migration device, characterized in that, The device includes: A processing module, configured to obtain first information of a solid-state drive, where the first information is used to reflect the input / output condition of the solid-state drive; A migration module, configured to perform a first migration operation if it is determined according to the first information that the solid-state drive meets a first condition; and perform a second migration operation if the solid-state drive does not meet the first condition; Wherein, the first migration operation includes: performing a migration operation of cache data; and the second migration operation includes: performing a migration operation of cache data according to the cache margin; Wherein, the solid-state drive meets the first condition, including: The input / output of the solid-state drive is in an idle state within a first statistical period; the first statistical period is the previous period of a second statistical period for which cache data migration is to be performed; Performing the first migration operation includes: Determining a first migration speed, and migrating the cache data of the flash memory to the storage unit of the flash memory according to the first migration speed; Performing the second migration operation includes: Obtaining second information, where the second information is used to reflect the cache margin of the solid-state drive; Determining a second migration speed according to the cache margin; Migrating the cache data of the flash memory to the storage unit of the flash memory according to the second migration speed.

10. The device according to claim 9, characterized in that, The apparatus is applied to a solid-state drive, and the solid-state drive includes: a flash memory chip; the flash memory chip includes: a cache part and a storage unit part; Performing the migration operation of cache data includes: migrating the data of the cache part to the storage unit part; Performing the migration operation of cache data according to the cache margin includes: migrating the data of the cache part to the storage unit part according to the cache margin of the cache part; The cache part includes an SLC cache; the storage unit part includes at least one of the following: TLC, QLC, PLC.

11. An electronic device, characterized in that, Including: At least one processor; And a memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method according to any one of claims 1 to 8.

12. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause a computer to execute the method according to any one of claims 1 to 8.

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