A method and system for simulating and testing temperature distribution in active area of ​​power semiconductor device chip

Abstract

The present invention discloses a method and system for simulating and testing the temperature distribution in the active area of ​​a power semiconductor device chip. The method involves designing a metal pattern mask based on the cell information of the active area of ​​the power semiconductor device chip. A semiconductor wafer with a completed semiconductor multilayer structure and an undoped surface semiconductor layer is selected for deposition of the metal pattern. Using a confocal Raman spectrometer and a hot stage, the Raman characteristic temperature curve of the semiconductor layer on the chip sample's surface is calibrated. The bottom surface of the chip sample is connected to the device package heat dissipation structure, and the metal pattern on the chip sample's surface is connected to a DC power supply circuit. The DC power supply output is adjusted to simulate heat generation by the chip sample's active area heat source and achieve a target heat generation power. The temperature distribution in the chip sample's active area is measured based on the calibrated Raman characteristic temperature curve. The present invention enables simulation testing of the chip's active area junction temperature and temperature distribution during the design and manufacturing process of power semiconductor devices, allowing for experimental evaluation of the actual performance of the power semiconductor device's thermal design.

Description

Technical Field

[0001] The present invention belongs to the field of design and manufacture of power semiconductor devices, and in particular relates to a method and system for simulating and testing temperature distribution in an active area of ​​a power semiconductor device chip. Background Art

[0002] The trend toward miniaturization and higher performance in power semiconductor devices places higher demands on device thermal design. Insufficient heat dissipation during high-power density operation can lead to excessively high junction temperatures, accelerating device degradation and impacting switching performance and efficiency. Furthermore, uneven temperature distribution in the active area can cause localized hot spots, further shortening device life. Therefore, thermal design is a core challenge in the design and application of power semiconductor devices.

[0003] During the design and manufacturing of power semiconductor devices, thermal simulation methods are currently used only for preliminary evaluation of thermal characteristics such as the junction temperature and temperature distribution in the chip's active area. However, the accuracy of these thermal simulation results is limited. Existing methods for measuring the junction temperature of power semiconductor devices are primarily targeted at finished power semiconductor devices and fall into two general categories: contact temperature measurement methods, which primarily measure temperature using thermocouples or thermistors, and non-contact temperature measurement methods, which primarily measure temperature using optical signals. These power semiconductor device junction temperature measurement methods primarily measure the near-junction temperature of the package structure, making it difficult to accurately measure the junction temperature and temperature distribution within the chip's active area. Summary of the Invention

[0004] The present invention aims to provide a method and system for simulating and testing the temperature distribution in the active area of ​​a power semiconductor device chip.

[0005] The technical solution for achieving the purpose of the present invention is: a method for simulating and testing the temperature distribution in the active area of ​​a power semiconductor device chip, comprising the following steps:

[0006] Step 1: Collect the active area size of the power semiconductor device chip, the cell pattern size and layout, and the gate size information of the cell unit, and design the corresponding metal pattern mask;

[0007] Step 2: Select a semiconductor wafer on which a semiconductor multilayer structure has been grown and whose surface semiconductor layer is undoped, and deposit a metal pattern corresponding to the metal pattern mask on the surface of the semiconductor wafer;

[0008] Step 3: Cut a chip sample from the semiconductor wafer with the metal pattern deposited thereon, and calibrate the Raman characteristic temperature curve f(T) of the surface semiconductor layer of the chip sample using a confocal Raman spectrometer and a hot stage;

[0009] Step 4: Connect the bottom surface of the chip sample to the device package heat dissipation structure, and connect the metal pattern on the surface of the chip sample to the DC power supply circuit;

[0010] Step 5: Mount the chip sample and the device package heat dissipation structure connected to the DC power supply circuit on the stage of the confocal Raman spectrometer, adjust the DC power supply output, simulate the heat generation of the chip sample active area heat source and achieve the target heat generation power P;

[0011] Step 6: Measure the Raman spectral signals at different locations of the semiconductor layer on the surface of the chip sample at the target heat generation power P, calculate the temperature distribution of the active area of ​​the chip sample based on the calibrated Raman characteristic temperature curve f(T), and evaluate the thermal design performance of the power semiconductor device.

[0012] Furthermore, in step 1, the size of the active area of ​​the power semiconductor device chip, the size and layout of the cell pattern, and the gate size information of the cell unit are collected, and the metal pattern mask is designed accordingly, specifically:

[0013] Collect information on the active area size of power semiconductor device chips, the size and layout of the cell unit patterns in the active area, and the gate size of the cell unit;

[0014] A metal pattern mask is designed. For strip cells, the metal pattern mask includes metal wires and metal disks, where the metal wires are used to simulate the heat source within the cell unit. The metal wires are parallel to each other, the metal wire width is set to the gate width, and the metal wire length is set to the cell unit length. The metal disks are set outside the active area at both ends of the metal wires to connect all the metal wires to achieve parallel connection of the metal wires. The side length of the metal disk is greater than or equal to 1mm and is used to connect the DC power supply circuit. For square cells, the metal pattern mask also includes strip metal strips. The strip metal strips are set in the cell spacing area in the extension direction of the metal wires of adjacent cell units and are perpendicular to the metal wires. The strip metal strips interconnect all metal wires to form a mesh metal pattern.

[0015] Furthermore, in step 2, a semiconductor wafer on which a semiconductor multilayer structure has been grown and on which a surface semiconductor layer is not doped is selected, and a metal pattern corresponding to the metal pattern mask is deposited on the surface of the semiconductor wafer, specifically:

[0016] Metal silver with excellent conductive properties is selected as the metal pattern material. On the surface of a semiconductor wafer with a completed semiconductor multilayer structure and an undoped surface semiconductor layer, a metal pattern corresponding to the metal pattern mask is deposited using a photolithography process. The thickness of the metal pattern ranges from 100nm to 1um.

[0017] Furthermore, in step 3, a chip sample is cut from the semiconductor wafer on which the metal pattern is deposited, and the Raman characteristic temperature curve f(T) of the surface semiconductor layer of the chip sample is calibrated using a confocal Raman spectrometer and a hot stage, specifically:

[0018] A chip sample is cut from a semiconductor wafer with a deposited metal pattern, placed on a hot plate with the metal pattern facing upward, and mounted on the stage of a confocal Raman spectrometer. The hot plate is controlled to heat from room temperature to 400°C, with temperature measurement points set every 10 to 30°C. The confocal Raman spectrometer is used to collect Raman spectral signals of the semiconductor layer on the surface of the chip sample at each temperature measurement point. The laser wavelength of the confocal Raman spectrometer is selected to be 532nm, the laser power is controlled to be less than 0.5mW, and the vertical measurement depth is less than or equal to 4μm.

[0019] Find the Raman spectrum characteristic peak corresponding to the surface semiconductor layer, obtain the displacement value of the characteristic peak through baseline calibration and Gaussian model peak fitting, perform quadratic polynomial fitting on the characteristic peak displacement values ​​at all temperature points, and calibrate the Raman characteristic temperature curve f(T) of the semiconductor layer on the surface of the chip sample. The specific expression is:

[0020]

[0021] Where f is the characteristic peak displacement value, unit is cm -1 ;T is temperature, unit is K, a, b, c are the fitting coefficients of quadratic term, linear term and constant term respectively.

[0022] Furthermore, in step 4, the bottom surface of the chip sample is connected to the device package heat dissipation structure, and the metal pattern on the surface of the chip sample is connected to the DC power supply circuit, specifically:

[0023] Connect the bottom surface of the chip sample to the package heat dissipation structure of the power semiconductor device to form a channel for the heat source in the active area of ​​the chip sample to dissipate heat downward;

[0024] The metal pattern on the surface of the chip sample is connected in series to a DC power supply circuit, which also includes a DC power supply and a precision resistor, wherein the resistance value of the precision resistor is equivalent to the resistance value of the metal pattern.

[0025] Furthermore, in step 5, the chip sample and the device package heat dissipation structure connected to the DC power supply circuit are mounted on the stage of the confocal Raman spectrometer, and the DC power supply output is adjusted to simulate the heat generation of the chip sample active area heat source and achieve the target heat generation power P, specifically:

[0026] The chip sample and device package heat dissipation structure connected to the DC power supply circuit are mounted on the stage of the confocal Raman spectrometer. The DC power supply output is adjusted to simulate the heat generation of the chip sample active area heat source and achieve the target heat generation power P.

[0027] Use a multimeter to measure the voltage across the precision resistor and the voltage across the metal pattern to calculate the target heat generation power P of the heat source in the active area of ​​the chip sample. The specific formula is as follows:

[0028]

[0029] Where P is the heat generation power, in W; R is the resistance value of the precision resistor, in Ω; U1 is the voltage across the precision resistor, in V; and U2 is the voltage across the metal pattern, in V.

[0030] Furthermore, in step 6, the Raman spectral signals at different positions of the semiconductor layer on the surface of the chip sample are measured under the target heat generation power P, and the temperature distribution of the active area of ​​the chip sample is calculated based on the calibrated Raman characteristic temperature curve f(T) to evaluate the thermal design performance of the power semiconductor device. Specifically,

[0031] After reaching the target heat generation power P, the same confocal Raman spectrometer sampling parameters as in step 3 are used to sample Raman spectral signals at different locations on the semiconductor layer of the chip sample surface. The spatial resolution of the signal sampling is less than or equal to 1 μm.

[0032] Substitute the Raman characteristic temperature curve f(T) calibrated in step 3 to calculate the temperature distribution of the active area of ​​the chip sample under the target heat generation power;

[0033] Evaluate the thermal design performance of power semiconductor devices. If the junction temperature and temperature distribution uniformity of the active area of ​​the chip sample meet the design requirements, the thermal design of the power semiconductor device meets the standards. If the junction temperature and temperature distribution uniformity of the active area of ​​the chip sample do not meet the design requirements, the thermal design of the power semiconductor device needs to be optimized.

[0034] A power semiconductor device chip active area temperature distribution simulation test system implements the power semiconductor device chip active area temperature distribution simulation test method to achieve power semiconductor device chip active area temperature distribution simulation test, and is divided into six modules to respectively perform steps 1 to 6.

[0035] Compared with the existing technology, the present invention has the following significant advantages: 1) By designing a metal pattern mask according to the cell information of the active area of ​​the power semiconductor device chip, the present invention can accurately simulate the heat source array in the active area of ​​the power semiconductor device chip; 2) Based on the Raman spectroscopy temperature measurement method, the present invention can realize high-spatial-resolution temperature distribution measurement in the chip active area, and the spatial resolution of the temperature measurement is less than or equal to 1um; 3) The present invention performs experimental testing based on semiconductor wafers in the front-end process, and can realize simulation testing of the junction temperature and temperature distribution of the chip active area during the design and manufacturing process of the power semiconductor device, and experimentally evaluate the actual performance of the thermal design of the power semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 This is a flow chart of the temperature distribution simulation test method for the active area of ​​a power semiconductor device chip according to the present invention.

[0037] Figure 2 Schematic diagram of the metal pattern mask design corresponding to the stripe and square cells of the present invention.

[0038] Figure 3 1 is the temperature distribution measurement result of the embodiment. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0040] like Figure 1 As shown, the present invention provides a method for simulating and testing the temperature distribution in the active area of ​​a power semiconductor device chip, comprising the following steps:

[0041] Step 1: Collect the active area size of the power semiconductor device chip, the cell pattern size and layout, and the gate size information of the cell unit, and design the corresponding metal pattern mask, specifically:

[0042] Collect information on the active area size of power semiconductor device chips, the size and layout of the cell unit patterns in the active area, and the gate size of the cell unit;

[0043] Design a metal pattern mask. For strip cells, the metal pattern mask includes metal wires and metal disks, where the metal wires are used to simulate the heat source within the cell unit. The metal wires are parallel to each other, the metal wire width is set to the gate width, and the metal wire length is set to the cell unit length. The metal disks are set outside the active area at both ends of the metal wires to connect all the metal wires to achieve parallel connection of the metal wires. The side length of the metal disk is greater than or equal to 1mm and is used to connect the DC power supply circuit. For square cells, the metal pattern mask also includes strip metal strips. The strip metal strips are set in the cell spacing area in the extension direction of the metal wires of adjacent cell units and are perpendicular to the metal wires. The strip metal strips interconnect all metal wires to form a mesh metal pattern. To enhance the explanation effect, the metal pattern mask design schematics corresponding to the strip and square cell layouts can be referenced. Figure 2 .

[0044] Step 2: Select a semiconductor wafer on which a semiconductor multilayer structure has been grown and the surface semiconductor layer is undoped, and deposit a metal pattern corresponding to the metal pattern mask on the surface of the semiconductor wafer, specifically:

[0045] Metal silver with excellent conductive properties is selected as the metal pattern material. On the surface of a semiconductor wafer with a completed semiconductor multilayer structure and an undoped surface semiconductor layer, a metal pattern corresponding to the metal pattern mask is deposited using a photolithography process. The thickness of the metal pattern ranges from 100nm to 1um.

[0046] Step 3: Cut a chip sample from the semiconductor wafer with the metal pattern deposited on it, and calibrate the Raman characteristic temperature curve f(T) of the surface semiconductor layer of the chip sample using a confocal Raman spectrometer and a hot stage. Specifically:

[0047] A chip sample is cut from a semiconductor wafer with a deposited metal pattern, placed on a hot plate with the metal pattern facing upward, and mounted on the stage of a confocal Raman spectrometer. The hot plate is controlled to heat from room temperature to 400°C, with temperature measurement points set every 10 to 30°C. The confocal Raman spectrometer is used to collect Raman spectral signals of the semiconductor layer on the surface of the chip sample at each temperature measurement point. The laser wavelength of the confocal Raman spectrometer is selected to be 532nm, the laser power is controlled to be less than 0.5mW, and the vertical measurement depth is less than or equal to 4μm.

[0048] Find the Raman spectrum characteristic peak corresponding to the surface semiconductor layer, obtain the displacement value of the characteristic peak through baseline calibration and Gaussian model peak fitting, perform quadratic polynomial fitting on the characteristic peak displacement values ​​at all temperature points, and calibrate the Raman characteristic temperature curve f(T) of the semiconductor layer on the surface of the chip sample. The specific expression is:

[0049]

[0050] Where f is the characteristic peak displacement value, unit is cm -1 ;T is temperature, unit is K, a, b, c are the fitting coefficients of quadratic term, linear term and constant term respectively.

[0051] Step 4: Connect the bottom surface of the chip sample to the device package heat dissipation structure, and connect the metal pattern on the surface of the chip sample to the DC power supply circuit. Specifically:

[0052] Connect the bottom surface of the chip sample to the package heat dissipation structure of the power semiconductor device to form a channel for the heat source in the active area of ​​the chip sample to dissipate heat downward;

[0053] The metal pattern on the surface of the chip sample is connected in series to a DC power supply circuit, which also includes a DC power supply and a precision resistor, wherein the resistance value of the precision resistor is equivalent to the resistance value of the metal pattern.

[0054] Step 5: Install the chip sample and device package heat dissipation structure connected to the DC power supply circuit on the stage of the confocal Raman spectrometer, adjust the DC power supply output, simulate the heat generation of the chip sample active area heat source and achieve the target heat generation power P, specifically:

[0055] The chip sample and device package heat dissipation structure connected to the DC power supply circuit are mounted on the stage of the confocal Raman spectrometer. The DC power supply output is adjusted to simulate the heat generation of the chip sample active area heat source and achieve the target heat generation power P.

[0056] Use a multimeter to measure the voltage across the precision resistor and the voltage across the metal pattern to calculate the target heat generation power P of the heat source in the active area of ​​the chip sample. The specific formula is as follows:

[0057]

[0058] Where P is the heat generation power, in W; R is the resistance value of the precision resistor, in Ω; U1 is the voltage across the precision resistor, in V; and U2 is the voltage across the metal pattern, in V.

[0059] Step 6: Measure the Raman spectral signals at different locations of the semiconductor layer on the surface of the chip sample at the target heat generation power P. Calculate the temperature distribution of the active area of ​​the chip sample based on the calibrated Raman characteristic temperature curve f(T) to evaluate the thermal design performance of the power semiconductor device. Specifically:

[0060] After reaching the target heat generation power P, the same confocal Raman spectrometer sampling parameters as in step 3 are used to sample Raman spectral signals at different locations on the semiconductor layer of the chip sample surface. The spatial resolution of the signal sampling is less than or equal to 1 μm.

[0061] Substitute the Raman characteristic temperature curve f(T) calibrated in step 3 to calculate the temperature distribution of the active area of ​​the chip sample under the target heat generation power;

[0062] Evaluate the thermal design performance of power semiconductor devices. If the junction temperature (maximum temperature) and temperature distribution uniformity of the active area of ​​the chip sample meet the design requirements, the thermal design of the power semiconductor device meets the standards. If the junction temperature and temperature distribution uniformity of the active area of ​​the chip sample do not meet the design requirements, the thermal design of the power semiconductor device needs to be optimized.

[0063] The present invention also proposes a power semiconductor device chip active area temperature distribution simulation test system, which implements the power semiconductor device chip active area temperature distribution simulation test method to achieve power semiconductor device chip active area temperature distribution simulation test, and is divided into six modules to perform steps 1 to 6 respectively.

[0064] In summary, the present invention can accurately simulate the heat source array within the active area of ​​a power semiconductor device chip, implement simulation testing of the chip active area junction temperature and temperature distribution during the design and manufacturing process of the power semiconductor device, and experimentally evaluate the actual performance of the thermal design of the power semiconductor device.

[0065] Example

[0066] In order to verify the effectiveness of the scheme of the present invention, the following experimental design was carried out.

[0067] In this embodiment, a sapphire-based gallium nitride (GaN) wafer is selected to perform a temperature distribution simulation test of the active area of ​​a GaN power semiconductor device chip.

[0068] Assume that the active area of ​​a GaN power semiconductor device chip measures 5mm x 50µm, containing only a single strip-shaped cell with a length of 5mm and a gate width of 10µm. Based on this information, a metal pattern mask is designed with a metal line width of 10µm and a length of 5mm, connected at both ends to a square metal disk with a side length of 2mm.

[0069] A 2-inch GaN-on-sapphire wafer was selected, with a sapphire layer thickness of 430 μm and an undoped GaN layer thickness of 4 μm. Using a designed metal pattern mask, a 1 μm thick silver pattern was deposited on the GaN wafer surface using a photolithography process.

[0070] A square chip sample with a side length of 15 mm was cut from the GaN wafer and placed on a hot plate with the metal pattern facing upward. The hot plate was then mounted on the stage of the confocal Raman spectrometer. Temperature measurement points were set every 25°C, and the Raman spectral signal of the GaN layer was measured using confocal Raman spectroscopy from room temperature to 400°C. The Raman characteristic temperature curve of the GaN layer was calibrated based on the E2 characteristic peak as follows:

[0071]

[0072] The bottom surface of the chip sample is connected to the package heat dissipation structure, and the metal pattern on the surface of the chip sample, a 1.0000Ω precision resistor, and a DC power supply are connected in series to form a DC power supply loop.

[0073] The chip sample and device package heat dissipation structure connected to the DC power supply circuit were mounted on the stage of the confocal Raman spectrometer. The DC power supply output was adjusted and U1=0.709V and U1=7.80V were measured. The target heat generation power P of the heat source in the active area of ​​the simulated chip sample was 5.530W.

[0074] After reaching the target heat generation power P, the Raman spectrum signal at different distances in the vertical direction from the center point of the metal wire is collected by the confocal Raman spectrometer, and the temperature distribution is calculated by substituting the calibrated Raman characteristic temperature curve f(T) into the calculated temperature distribution. Figure 3 The figure shows the temperature distribution at different distances from the metal wire, where the junction temperature is 121.3±3.8℃ and the spatial resolution of the temperature measurement is less than or equal to 1μm.

[0075] The above embodiments show that the method proposed in the present invention can effectively simulate the heat generation of heat sources in the active area of ​​the power semiconductor device chip based on the semiconductor wafer, and can also realize the temperature distribution measurement with high spatial resolution in the chip active area. This means that the method can realize the temperature distribution simulation test of the chip active area during the design and manufacturing process of power semiconductor devices, and experimentally evaluate the actual performance of the thermal design of power semiconductor devices.

[0076] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0077] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A method for simulating and testing the temperature distribution in the active area of ​​a power semiconductor device chip, characterized in that: The steps include: Step 1: Collect the active area size of the power semiconductor device chip, the cell pattern size and layout, and the gate size information of the cell unit, and design the corresponding metal pattern mask; Step 2: Select a semiconductor wafer on which a semiconductor multilayer structure has been grown and whose surface semiconductor layer is undoped, and deposit a metal pattern corresponding to the metal pattern mask on the surface of the semiconductor wafer; Step 3: Cut a chip sample from the semiconductor wafer with the metal pattern deposited thereon, and calibrate the Raman characteristic temperature curve f(T) of the surface semiconductor layer of the chip sample using a confocal Raman spectrometer and a hot stage; Step 4: Connect the bottom surface of the chip sample to the device package heat dissipation structure, and connect the metal pattern on the surface of the chip sample to the DC power supply circuit; Step 5: Mount the chip sample and the device package heat dissipation structure connected to the DC power supply circuit on the stage of the confocal Raman spectrometer, adjust the DC power supply output, simulate the heat generation of the chip sample active area heat source and achieve the target heat generation power P; Step 6: Measure the Raman spectral signals at different locations of the semiconductor layer on the surface of the chip sample at the target heat generation power P, calculate the temperature distribution of the active area of ​​the chip sample based on the calibrated Raman characteristic temperature curve f(T), and evaluate the thermal design performance of the power semiconductor device.

2. A power semiconductor device chip active area temperature distribution simulation test method according to claim 1, characterized in that: In step 1, the active area size of the power semiconductor device chip, the cell pattern size and layout, and the gate size information of the cell unit are collected, and the corresponding metal pattern mask is designed, specifically: Collect information on the active area size of power semiconductor device chips, the size and layout of the cell unit patterns in the active area, and the gate size of the cell unit; A metal pattern mask is designed. For strip cells, the metal pattern mask includes metal wires and metal disks, where the metal wires are used to simulate the heat source within the cell unit. The metal wires are parallel to each other, the metal wire width is set to the gate width, and the metal wire length is set to the cell unit length. The metal disks are set outside the active area at both ends of the metal wires to connect all the metal wires to achieve parallel connection of the metal wires. The side length of the metal disk is greater than or equal to 1mm and is used to connect the DC power supply circuit. For square cells, the metal pattern mask also includes strip metal strips. The strip metal strips are set in the cell spacing area in the extension direction of the metal wires of adjacent cell units and are perpendicular to the metal wires. The strip metal strips interconnect all metal wires to form a mesh metal pattern.

3. The method for simulating temperature distribution in the active area of ​​a power semiconductor device chip according to claim 1, wherein: In step 2, a semiconductor wafer on which a semiconductor multilayer structure has been grown and whose surface semiconductor layer is not doped is selected, and a metal pattern corresponding to the metal pattern mask is deposited on the surface of the semiconductor wafer, specifically: Metal silver with excellent conductive properties is selected as the metal pattern material. On the surface of a semiconductor wafer with a completed semiconductor multilayer structure and an undoped surface semiconductor layer, a metal pattern corresponding to the metal pattern mask is deposited using a photolithography process. The thickness of the metal pattern ranges from 100nm to 1um.

4. The method for simulating temperature distribution in the active area of ​​a power semiconductor device chip according to claim 1, wherein: In step 3, a chip sample is cut from the semiconductor wafer with the metal pattern deposited thereon, and the Raman characteristic temperature curve f(T) of the surface semiconductor layer of the chip sample is calibrated using a confocal Raman spectrometer and a hot stage, specifically: A chip sample is cut from a semiconductor wafer with a deposited metal pattern, placed on a hot plate with the metal pattern facing upward, and mounted on the stage of a confocal Raman spectrometer. The hot plate is controlled to heat from room temperature to 400°C, with temperature measurement points set every 10 to 30°C. The confocal Raman spectrometer is used to collect Raman spectral signals of the semiconductor layer on the surface of the chip sample at each temperature measurement point. The laser wavelength of the confocal Raman spectrometer is selected to be 532nm, the laser power is controlled to be less than 0.5mW, and the vertical measurement depth is less than or equal to 4μm. Find the Raman spectrum characteristic peak corresponding to the surface semiconductor layer, obtain the displacement value of the characteristic peak through baseline calibration and Gaussian model peak fitting, perform quadratic polynomial fitting on the characteristic peak displacement values ​​at all temperature points, and calibrate the Raman characteristic temperature curve f(T) of the semiconductor layer on the surface of the chip sample. The specific expression is: ； Where f is the characteristic peak displacement value, unit is cm -1 ;T is temperature, unit is K, a, b, c are the fitting coefficients of quadratic term, linear term and constant term respectively.

5. The method for simulating temperature distribution in active area of ​​a power semiconductor device chip according to claim 1, wherein: In step 4, the bottom surface of the chip sample is connected to the device package heat dissipation structure, and the metal pattern on the surface of the chip sample is connected to the DC power supply circuit, specifically: Connect the bottom surface of the chip sample to the package heat dissipation structure of the power semiconductor device to form a channel for the heat source in the active area of ​​the chip sample to dissipate heat downward; The metal pattern on the surface of the chip sample is connected in series to a DC power supply circuit, which also includes a DC power supply and a precision resistor, wherein the resistance value of the precision resistor is equivalent to the resistance value of the metal pattern.

6. A power semiconductor device chip active area temperature distribution simulation test method according to claim 5, characterized in that: In step 5, the chip sample and the device package heat dissipation structure connected to the DC power supply circuit are mounted on the stage of the confocal Raman spectrometer. The DC power supply output is adjusted to simulate the heat generation of the chip sample active area heat source and achieve the target heat generation power P. Specifically, The chip sample and device package heat dissipation structure connected to the DC power supply circuit are mounted on the stage of the confocal Raman spectrometer. The DC power supply output is adjusted to simulate the heat generation of the chip sample active area heat source and achieve the target heat generation power P. Use a multimeter to measure the voltage across the precision resistor and the voltage across the metal pattern to calculate the target heat generation power P of the heat source in the active area of ​​the chip sample. The specific formula is as follows: ； Where P is the heat generation power, in W; R is the resistance value of the precision resistor, in Ω; U1 is the voltage across the precision resistor, in V; and U2 is the voltage across the metal pattern, in V.

7. A power semiconductor device chip active area temperature distribution simulation test method according to claim 1, characterized in that: In step 6, the Raman spectral signals at different locations of the semiconductor layer on the surface of the chip sample are measured at the target heat generation power P. The temperature distribution of the active area of ​​the chip sample is calculated based on the calibrated Raman characteristic temperature curve f(T) to evaluate the thermal design performance of the power semiconductor device. Specifically: After reaching the target heat generation power P, the same confocal Raman spectrometer sampling parameters as in step 3 are used to sample Raman spectral signals at different locations on the semiconductor layer of the chip sample surface. The spatial resolution of the signal sampling is less than or equal to 1 μm. Substitute the Raman characteristic temperature curve f(T) calibrated in step 3 to calculate the temperature distribution of the active area of ​​the chip sample under the target heat generation power; Evaluate the thermal design performance of power semiconductor devices. If the junction temperature and temperature distribution uniformity of the active area of ​​the chip sample meet the design requirements, the thermal design of the power semiconductor device meets the standards. If the junction temperature and temperature distribution uniformity of the active area of ​​the chip sample do not meet the design requirements, the thermal design of the power semiconductor device needs to be optimized.

8. A power semiconductor device chip active area temperature distribution simulation test system, characterized in that: Implement the power semiconductor device chip active area temperature distribution simulation test method described in any one of claims 1-7 to realize the power semiconductor device chip active area temperature distribution simulation test, and perform steps 1 to 6 respectively in six modules.

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