A method for ALD deposition of a seed layer in a high aspect ratio through silicon via

Abstract

The application provides an ALD deposition method for a seed layer in a high-aspect-ratio through silicon via, comprising the following steps: preparing a high-aspect-ratio through silicon via on a substrate, the aspect ratio of the through silicon via being greater than or equal to 10:1; depositing a copper film or a cobalt film in the through silicon via by ALD, or depositing a copper seed layer after preparing an insulating layer and a diffusion barrier layer; wherein the precursors used for depositing the copper film or the copper seed layer comprise at least one of copper bis(hexafluoroacetylacetonate), dimethylamino-2-propoxy copper, bis(dimethylamino-2-propoxy) copper and bis(N,N'-disec-butylacetamidine) copper, and ZnEt2; and a secondary annealing treatment is performed, the temperature of the secondary annealing being higher than that of the primary annealing. By using the technical scheme of the application, the seed layer obtained is more compact, flat and uniform, and has good coverage on the surface, sidewall and bottom, which is beneficial to the successful preparation of a subsequent electroplated layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chip integration advanced packaging, and particularly relates to an ALD deposition method of a seed layer in a high aspect ratio TSV. BACKGROUND

[0002] TSV (through silicon via) is a key technology for 3D integrated circuits, which provides vertical interconnection to improve chip performance and functional density. Small diameter (<3 µm) and high aspect ratio TSVs are widely used in artificial intelligence chips, radio frequency chips, CMOS image sensors and MEMS devices, but the internal deposition process of the through hole still faces significant challenges. Traditional methods such as physical vapor deposition (PVD) and chemical vapor deposition (CVD) have insufficient coverage and film uniformity in high aspect ratio TSVs. Atomic layer deposition (ALD) can effectively improve the uniformity of deposition, reduce film surface defects, and improve the reliability of subsequent copper electroplating filling due to its surface self-limiting reaction and atomic-level film thickness control capability, and can be one of the promising potential solutions.

[0003] Currently, TSV filling research mainly focuses on using PVD and CVD methods to prepare insulating layers such as SiO2 and Al2O3, using ALD and magnetron sputtering principles to prepare diffusion barrier layers (such as TaN and TiN), and using PVD and sputtering methods to prepare seed layers, and finally using electroplating methods for copper filling. However, the above methods face challenges in high aspect ratio TSV applications, such as precursor diffusion limitations and deposition uniformity. SUMMARY

[0004] To solve the above technical problems, the present application discloses an ALD deposition method of a seed layer in a high aspect ratio TSV. The high aspect ratio refers to a depth: width ratio of ≥10:1.

[0005] To this end, the technical solution adopted by the present application is as follows:

[0006] An ALD deposition method of a seed layer in a high aspect ratio TSV, comprising the following steps:

[0007] Step S1: preparing a high aspect ratio TSV on a substrate, wherein the aspect ratio of the TSV is ≥10:1;

[0008] Step S2, insulating layer and diffusion barrier layer are prepared in the through silicon via by ALD, and then copper film or cobalt film seed layer is deposited; wherein, the precursors used in the deposition of copper film or copper seed layer include at least one of bis(hexafluoroacetylacetone) copper, dimethylamino-2-propoxy copper, Cu(dmamb)2 (bis(dimethylamino-2-propoxy) copper) and Cu(sBu-Me-amd)2 (bis(N,N'-disilylacetamid) copper), and diethyl zinc (ZnEt2); the precursors used in the deposition of cobalt film include at least one of Co(C5H5)2, C5H5Co(CO)2 and C 12 H 10 Co2O6, and ZnEt2;

[0009] Step S3, secondary annealing treatment is performed, wherein the temperature of the second annealing is higher than that of the first annealing. Further, the temperature of the second annealing is 300-400℃ higher than that of the first annealing.

[0010] As a further improvement of the present application, in step S1, after the substrate is cleaned, dried and subjected to argon plasma treatment before the through silicon via is prepared.

[0011] As a further improvement of the present application, the cleaning and drying include ultrasonic cleaning with isopropyl alcohol, followed by second ultrasonic cleaning with deionized water, and then dried with nitrogen; further, each cleaning time is at least 15 min.

[0012] As a further improvement of the present application, the argon plasma treatment time is 15-30 min. Further, the temperature of the argon plasma treatment is 20-40℃.

[0013] As a further improvement of the present application, in step S1, the through silicon via with high aspect ratio is formed by deep reactive ion etching, BOSCH process cycle etching and passivation on the substrate. Further, the gas required for the deep reactive ion etching is sulfur hexafluoride (SF6) and octafluorocyclobutane (C4F8).

[0014] As a further improvement of the present application, in step S3, the secondary annealing treatment includes:

[0015] First time: in-situ vacuum environment or protective atmosphere environment in the ALD cavity, 200-300℃ annealing for 3-5h;

[0016] Second time: in vacuum environment or protective atmosphere environment in the CVD tube furnace, 500-700℃ annealing for 3-5h.

[0017] As a further improvement of the present application, the protective gas is nitrogen or inert gas. Further, the inert gas is argon.

[0018] As a further improvement of the present application, the insulating layer is prepared by thermal oxidation, plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD).

[0019] As a further improvement of the present application, the diffusion barrier layer is prepared by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electrochemical deposition (ECD), magnetron sputtering, molecular beam epitaxy (MBE) or electroless plating.

[0020] As a further improvement of the present application, the thickness of the insulating layer is 100 nm to 1 µm.

[0021] As a further improvement of the present application, the thickness of the diffusion barrier layer is 2 to 20 nm.

[0022] As a further improvement of the present application, the material of the insulating layer comprises at least one of SiO2, Al2O3, HfO2, PI and BCB.

[0023] As a further improvement of the present application, the material of the diffusion barrier layer comprises at least one of Ta, Ti, TaN, TiN.

[0024] Compared with the prior art, the present application has the following beneficial effects:

[0025] By using the technical solution of the present application, the seed layer obtained is more dense, flat and uniform, whether in the middle sidewall or the through hole bottom, the coverage rate and thickness uniformity of the seed layer are good, the seed layer particles are dense and uniform, which is convenient for subsequent electroplating hole filling, and compared with the seed layer prepared by magnetron sputtering, the seed layer has better conformal effect and better copper film connectivity; solve the problem of uneven subsequent electroplating hole filling caused by low deposition coverage and poor uniformity of the seed layer in the prior art. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 It is an optical microscope schematic diagram of the deep reactive ion etched high aspect ratio silicon through hole surface of embodiment 1 of the present application.

[0027] Figure 2 It is a scanning electron microscope (SEM) schematic diagram of the deep reactive ion etched high aspect ratio silicon through hole surface of embodiment 1 of the present application.

[0028] Figure 3 It is a whole scanning electron microscope (SEM) schematic diagram of the deep reactive ion etched high aspect ratio silicon through hole of embodiment 1 of the present application.

[0029] Figure 4 A partial sidewall scanning electron microscope (SEM) schematic diagram of a deep reactive ion etching high aspect ratio through silicon via of Example 1 of the present application.

[0030] Figure 5 A bottom scanning electron microscope (SEM) schematic diagram of a deep reactive ion etching high aspect ratio through silicon via of Example 1 of the present application.

[0031] Figure 6 SEM images of a copper seed layer prepared by atomic layer deposition of Example 1 of the present application and a copper seed layer prepared by magnetron sputtering of Comparative Example 1, wherein (a) is Comparative Example 1 and (b) is Example 1.

[0032] Figure 7 An AFM schematic diagram of the thickness of a copper seed layer on a silicon substrate surface prepared by atomic layer deposition for 400 cycles of Example 1 of the present application, wherein (b) is a partial enlarged view of the boxed area in (a) and (c) is the film thickness obtained by atomic force microscopy.

[0033] Figure 8 An EDS schematic diagram of a through silicon via prepared by atomic layer deposition for 400 cycles of Example 1 of the present application.

[0034] Figure 9 A photograph of the four-probe test resistance characteristics after annealing of Example 1 of the present application. DETAILED DESCRIPTION

[0035] The following further details a preferred embodiment of the present application.

[0036] An ALD deposition method for a seed layer in a high aspect ratio through silicon via, comprising the following steps:

[0037] Step S1, preparing a high aspect ratio through silicon via on a substrate, wherein the aspect ratio of the through silicon via is ≥ 10:1.

[0038] Step S2, using ALD to prepare an insulating layer and a diffusion barrier layer in the through silicon via, and then depositing a copper film or a cobalt film seed layer.

[0039] Step S3, performing secondary annealing treatment.

[0040] For the insulating layer and diffusion barrier layer, the insulating layer prepared by PVD, CVD, thermal oxidation method and ALD method is located between the TSV and the diffusion barrier layer, which performs electrical interruption and reduces leakage current. At the same time, the insulating material with low dielectric constant can also reduce the parasitic capacitance of the interconnection, reduce the total signal delay and loss in the transmission process, and also reduce crosstalk. In addition, the insulating layer can also enhance the mechanical strength of the TSV and improve the stability. The material of the insulating layer includes at least one of SiO2, Al2O3, HfO2, PI and BCB, and the thickness of the insulating layer is 100 nm to 1 µm.

[0041] Then, the diffusion barrier layer is prepared by sputtering, ALD, PVD and CVD, etc., which is located between the insulating layer and the seed layer. The diffusion barrier layer plays an important role between the film layers of the TSV. Since copper and aluminum metals will diffuse to the silicon substrate or dielectric layer, causing device short circuit or leakage, the diffusion barrier layer mainly blocks the diffusion and migration of metal atoms to the internal silicon substrate or dielectric layer through a dense film layer, ensuring that the device can work stably and improving the reliability of the interconnection. Special diffusion barrier layers such as Ti and Ta can also be selected. At the same time, these materials can also act as an adhesion layer to enhance the bonding strength of the subsequent seed layer and improve the uniformity of the seed layer. The material of the diffusion barrier layer includes at least one of Ta, Ti and TaN, TiN, and the thickness of the diffusion barrier layer is 2 to 20 nm.

[0042] The seed layer is a process flow before electroplating, which is located between the diffusion barrier layer and the electroplated metal. Its main role is to serve as a conductive substrate to provide a current path for subsequent copper electroplating, ensuring that metal ions in the electroplating solution can uniformly cover the surface of the seed layer. The film layer effect of the seed layer directly determines the quality of subsequent electroplating. If the seed layer is not uniformly covered, the electroplated metal may have holes or uneven coverage, etc. The conventional method is sputtering and PVD.

[0043] In step S2 of the embodiment, the copper source precursor for depositing copper film or seed layer is at least one of copper hexafluoroacetylacetonate (Cu(hfac)2), dimethylamino-2-propoxy copper, Cu(dmamb)2 and Cu(sBu-Me-amd)2, or the cobalt source precursor is at least one of Co(C5H5)2, C5H5Co(CO)2 and C 12 H 10 Co2O6, and the other precursor is ZnEt2. The cobalt source precursor for depositing cobalt film is at least one of Co(C5H5)2, C5H5Co(CO)2 and C 12 H 10 Co2O6, and the other precursor is ZnEt2.

[0044] In step S1, before the high aspect ratio through silicon via is prepared, the substrate is processed, including:

[0045] After the substrate is ultrasonically cleaned with isopropyl alcohol for the first time for 15 min, the substrate is ultrasonically cleaned with deionized water for the second time for 15 min, and then dried with nitrogen. The nitrogen-dried substrate is subjected to argon plasma treatment.

[0046] Further, the argon plasma treatment time is 15-30 min, and the argon plasma treatment temperature is 20-40℃.

[0047] The substrate is cleaned to ensure the cleanliness of the substrate surface. Taking silicon wafer cleaning as an example, the cleaning steps can be as follows: first, place the silicon wafer in a beaker, pour in an appropriate amount of isopropyl alcohol, and ultrasonically clean for 15 min. Then, pour out the isopropyl alcohol, inject an appropriate amount of deionized water, and ultrasonically clean again for 15 min. After the end, take out the silicon wafer, dry it with nitrogen, and then place the silicon wafer in a plasma treatment device, and treat it with argon plasma at 20-40℃ for 15-30 min. Through the plasma treatment, defects can be introduced on the substrate surface, the adhesion of the substrate can be improved, and the activity of the substrate surface is higher, which is beneficial to the bonding between the substrate and the subsequent film layer.

[0048] In step S3, the secondary annealing treatment includes the following steps:

[0049] The first vacuum annealing is performed at 200-300℃ in an ALD chamber. Then, the sample is placed in the heating area of a CVD tube furnace for the second annealing, and the annealing temperature is set to 500-700℃. During the above two annealing processes, a vacuum or an inert gas atmosphere can be maintained, and the inert gas can be N2 or Ar. The annealing time is set to about 3-5h.

[0050] The technical solutions of the present application will be further described in detail in combination with specific embodiments and drawings. It should be understood that the following embodiments are only used to explain the present application, and are not used to limit the present application. Embodiment 1

[0051] A method for depositing a cobalt film seed layer in a high aspect ratio (10:1) through silicon via by using an atomic layer deposition system (ALD), including:

[0052] In step S1, the substrate material is Si. First, the substrate is ultrasonically cleaned with isopropyl alcohol, and then ultrasonically cleaned with deionized water for the second time. After that, dry it with nitrogen. Each cleaning time is 15 min. Then, perform argon plasma treatment. The argon plasma treatment time is 15 min, and the argon plasma treatment temperature is 40℃.

[0053] Then, a high aspect ratio (≥10:1) TSV is formed by using deep reactive ion etching on the surface of the substrate, and using a BOSCH process to repeatedly etch and passivate using sulfur hexafluoride (SF6) and octafluorocyclobutane (C4F8) gases.

[0054] In step S2, an insulating layer and a diffusion barrier layer are first prepared in the TSV by ALD, and then a Co film seed layer is deposited in the high aspect ratio TSV by ALD. In the deposition of the copper film or the copper seed layer, the precursors used are at least one of Co(C5H5)2, C5H5Co(CO)2, and C 12 H 10 Co2O6, and diethyl zinc (ZnEt2). In this embodiment, Co(C5H5)2 and diethyl zinc are used as the precursors. The insulating layer is prepared by a thermal oxidation method, and the material is SiO2 with a thickness of 100 nm. The diffusion barrier layer is prepared by a physical vapor deposition method, and the material is Ti with a thickness of 5 nm.

[0055] In step S3, a secondary annealing process is performed, including: setting 300°C in the ALD cavity for the first vacuum annealing; and then placing the sample in the heating area of the CVD tube furnace for the second annealing, with the annealing temperature set to 700°C. In the above two annealing processes, a vacuum or an inert gas atmosphere can be maintained, and the inert gas can be selected from N2 or Ar. In this embodiment, a vacuum is maintained, and the annealing time is 3h. Embodiment 2

[0056] A copper film seed layer is deposited in a high aspect ratio (10:1) TSV by an atomic layer deposition system (ALD). The difference between this embodiment and the previous embodiment is that, in step S2, an insulating layer and a diffusion barrier layer are first prepared in the TSV by ALD, and then a copper film seed layer is deposited, and the process parameters of the secondary annealing in step S3. Specifically:

[0057] In step S2, the insulating layer is prepared by PVD, is arranged between the TSV and the diffusion barrier layer, and is made of SiO2 with a thickness of 200 nm.

[0058] The diffusion barrier layer is prepared by Sputtering, is arranged between the insulating layer and the seed layer, and is made of Ta with a thickness of 10 nm.

[0059] Then, a Cu film is deposited in the high aspect ratio TSV by ALD. In the deposition of the copper film, the precursors used are at least one of bis(hexafluoroacetylacetone) copper, dimethylamino-2-propoxy copper, Cu(dmamb)2, and Cu(sBu-Me-amd)2, and diethyl zinc (ZnEt2). In this embodiment, bis(hexafluoroacetylacetone) copper and diethyl zinc are used as the precursors.

[0060] Step S3, a secondary annealing process is performed, including: setting 200℃ in the ALD cavity for the first vacuum annealing; then placing the sample in the heating area of the CVD tube furnace for the second annealing, and setting the annealing temperature to 500℃. In the above two annealing processes, a vacuum or an inert gas atmosphere can be maintained, the inert gas can be selected from N2 or Ar, in this embodiment, the N2 atmosphere, and the annealing time is 5h. Example 3

[0061] A method for depositing a cobalt film seed layer in a high aspect ratio (10:1) through silicon via (TSV) by using an atomic layer deposition (ALD) system, comprising:

[0062] Step S1, the substrate material is Si; first, the substrate is ultrasonically cleaned with isopropyl alcohol, then ultrasonically cleaned with deionized water for the second time, and then dried with nitrogen, each cleaning time being 15 min. Then, argon plasma treatment is performed, the argon plasma treatment time being 30 min, and the argon plasma treatment temperature being 20℃.

[0063] Then, a high aspect ratio (≥10:1) TSV is formed on the surface of the substrate by using a BOSCH process to repeatedly etch and passivate the substrate with sulfur hexafluoride (SF6) and octafluorocyclobutane (C4F8).

[0064] Step S2, an ALD is used to first prepare an insulating layer and a diffusion barrier layer in the TSV, and then deposit a Co film seed layer.

[0065] The insulating layer is prepared by CVD, is arranged between the TSV and the diffusion barrier layer, and is made of Al2O3; and has a thickness of 500 nm.

[0066] The diffusion barrier layer is prepared by CVD, is arranged between the insulating layer and the seed layer, and is made of TiN; and has a thickness of 20 nm.

[0067] The Co film is deposited in the high aspect ratio TSV by using the ALD. The precursors used in the deposition of the cobalt film include Co(C5H5)2, C5H5Co(CO)2, and C 12 H 10 Co2O6, and ZnEt2.

[0068] Step S3, a secondary annealing process is performed, including: setting 250℃ in the ALD cavity for the first vacuum annealing; then placing the sample in the heating area of the CVD tube furnace for the second annealing, and setting the annealing temperature to 600℃. In the above two annealing processes, a vacuum or an inert gas atmosphere can be maintained, the inert gas can be selected from N2 or Ar, in this embodiment, the N2 atmosphere, and the annealing time is 5h.

[0069] Comparative Example 1

[0070] The preparation of the Cu film in Comparative Example 1 was different from that in Example 1 in that the preparation method was sputtering. Due to the poor conformality of the process of the Cu film in Comparative Example 1, the coverage of the film layer was not good, and the thickness uniformity was poor, the thickness at the opening was thicker, and the uniformity of the Cu on the middle sidewall and the bottom was poor, thus in the subsequent electroplating process, the filling metal was prone to have holes and gaps, and was not uniformly distributed, leading to the stability of the final interconnection, which might cause the increase of the overall resistance of the TSV, increase the power consumption, affect the transmission speed of the signal, and introduce parasitic capacitance or parasitic inductance in high-frequency applications, causing signal delay or crosstalk.

[0071] The Cu film seed layer deposited in the through silicon via obtained in Example 2 was subjected to performance characterization test.

[0072] As shown in Figure 1 is a schematic diagram of the optical microscope after the deposition of the Cu seed layer on the surface of the TSV after deep reactive ion etching by atomic layer deposition, Figure 2 is a scanning electron microscope characterization of the surface on which the Cu thin film has been deposited, and Figure 2 It can be seen that the Cu particles are closely arranged, which indicates that the Cu film has good compactness. Further, the TSV was cut by laser hidden cutting, and then the through silicon via was subjected to scanning electron microscope characterization, as shown in Figure 3 , which shows the overall morphology of the TSV, the aspect ratio is about 30:3, and the morphology of the TSV is good, indicating that the etching effect is good. The local details of the TSV were observed under magnification, as shown in Figure 4 and Figure 5 , the details of the sidewall and the bottom of the TSV were characterized, respectively, and it can be clearly seen that the Cu coverage is good whether in the middle sidewall or in the bottom of the through hole, and the thickness uniformity is also good, the Cu particles are dense and uniform, which shows the good conformality effect of the ALD process. Figure 6 In , the Cu seed layers prepared by magnetron sputtering and atomic layer deposition were compared, and the left and right in the figure are the magnetron sputtering preparation and the atomic layer deposition preparation, respectively. Obviously, the Cu seed layer prepared by atomic layer deposition has better conformality effect, and the Cu film has better connectivity. Figure 7 In , the thickness of the Cu layer was measured by atomic force microscope (AFM), and the results of the thickness scanning showed that after 400 cycles of cycling, the thickness of the deposited Cu film was about 64.511 nm. Then, EDS element analysis was performed on the inside of the TSV through hole, and the element distribution is shown in Figure 8 , in the element distribution, it can be seen that the concentration of Cu element is relatively high, indicating that the Cu element is uniformly distributed in the through hole.

[0073] The deposited Cu layer is subjected to relevant electrical performance test. Before annealing, the resistance of the Cu layer is in the order of mega-ohm, showing non-conductive state, indicating that the internal connection of the Cu film is not good. Subsequently, annealing is performed, and the resistance of the annealed Cu is measured again by using a four-probe square resistance meter. It is found that the resistance is significantly reduced, about 0.67 mΩ·cm, and the conductivity is greatly increased. The test results are shown in Table 1. Figure 9 As can be seen, the secondary annealing treatment can effectively improve the uniformity of the seed layer, repair the material, rearrange the internal structure of the crystal, restore the integrity of the crystal lattice, and at the same time, the key point is to improve the conductivity and electrical properties.

[0074] The above is a further detailed description of the present application in combination with specific preferred embodiments, and the specific implementation of the present application cannot be limited to these descriptions. For ordinary skilled persons in the technical field to which the present application belongs, a number of simple deductions or substitutions can be made without departing from the concept of the present application, and all of them should be regarded as falling within the protection scope of the present application.

Claims

1. An ALD deposition method for a seed layer in a through silicon via with a high aspect ratio, characterized in that: The steps include: Step S1, preparing a through silicon via with a high aspect ratio on a substrate, wherein the aspect ratio of the through silicon via is ≥10:1; Step S2, using ALD to prepare an insulating layer and a diffusion barrier layer in the silicon through hole, and then depositing a copper film or a cobalt film seed layer; wherein the precursor used in depositing the copper film or the copper seed layer includes at least one of bis(hexafluoroacetylacetonate)copper, dimethylamino-2-propoxycopper, bis(dimethylamino-2-propoxy)copper and bis(N,N'-di-secondary acetamidine)copper, and ZnEt2; the precursor used in depositing the cobalt film includes Co(C5H5)2, C5H5Co(CO)2 and C 12 H 10 At least one of Co2O6, and ZnEt2; Step S3, performing a secondary annealing treatment, wherein the temperature of the second annealing is higher than the temperature of the first annealing; the secondary annealing treatment includes annealing at 200-300°C for 3-5 hours in an ALD chamber in an in-situ vacuum environment or a protective atmosphere environment, and annealing at 500-700°C for 3-5 hours in a CVD tube furnace in a vacuum environment or a protective atmosphere environment.

2. The ALD deposition method for a seed layer in a high aspect ratio through silicon via according to claim 1, wherein: In step S1 , before forming the through silicon via, the substrate is cleaned and dried, and then subjected to argon plasma treatment.

3. The ALD deposition method for a seed layer in a high aspect ratio through silicon via according to claim 2, wherein: The cleaning and drying include ultrasonic cleaning with isopropyl alcohol, followed by a second ultrasonic cleaning with deionized water, and then drying with nitrogen; each cleaning time is at least 15 minutes.

4. The ALD deposition method for a seed layer in a high aspect ratio through silicon via according to claim 2, wherein: The time of the argon plasma treatment is 15-30 minutes; the temperature of the argon plasma treatment is 20-40°C.

5. The ALD deposition method for a seed layer in a high aspect ratio through silicon via according to claim 1, wherein: In step S1, a deep reactive ion etching method and a BOSCH process are used to perform cyclic etching and passivation on the substrate to form a through silicon via with a high aspect ratio; the gases used in the deep reactive ion etching are sulfur hexafluoride and octafluorocyclobutane.

6. The ALD deposition method for a seed layer in a high aspect ratio through silicon via according to claim 1, wherein: The protective atmosphere is nitrogen or an inert gas, and the inert gas is argon.

7. The ALD deposition method for a seed layer in a high aspect ratio through silicon via according to claim 1, wherein: The thickness of the insulating layer is 100 nm to 1 μm, and the thickness of the diffusion barrier layer is 2 to 20 nm.

8. The ALD deposition method for a seed layer in a high aspect ratio through silicon via according to claim 7, wherein: The material of the insulating layer includes at least one of SiO2, Al2O3, HfO2, PI, and BCB; The material of the diffusion barrier layer includes at least one of Ta, Ti, TaN, and TiN.

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