Electrogilding and stress removing method for P surface of semiconductor wafer

Abstract

The invention provides a semiconductor wafer P surface gold electroplating and stress removing method, and relates to the technical field of semiconductors. According to the method, part of secondary photoresist is reserved on a non-gold-plating area to serve as an insulating layer, part of the secondary photoresist is removed to form an inter-region conductive bridge, an intra-region conductive bridge and a stress release area are arranged on a gold-plating area, and then a thick gold layer is electroplated on the gold-plating area. Compared with the traditional process, the inter-region conductive bridges which are gradually increased from the edge to the middle are designed on the non-gold-plating region, so that the electroplating current density difference between the gold-plating regions of the wafer is favorably reduced; and the uniformly distributed intra-region conductive bridges are arranged on the gold plating region, so that the electroplating current density difference in a single gold plating region is reduced, and the uniformity of the plating layer is ensured. Besides, the stress release area is arranged, so that the stress generated by hydrogen evolution heat release of a cathode, pH value change of a deposition solution and impurity introduction in the electroplating process can be released, and the thermal stress in the alloying process can be released, so that the bulging of a plating layer is reduced, and the product yield is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and more particularly to a method for electroplating gold on the P side of a semiconductor wafer and removing stress. Background Art

[0002] Gold has the advantages of high electrical conductivity, high thermal conductivity, and good chemical stability, and is widely used in semiconductors, integrated circuits, electronic component products, etc. At present, in the field of electroplating gold on the P side of semiconductor wafers, generally, the P side of the semiconductor wafer is patterned, a seed layer is evaporated, then a photoresist barrier is prepared on the non-gold plating area, and finally a thick gold layer is electroplated on the area to be gold plated.

[0003] However, since electroplating is an unbalanced crystallization process, during electroplating, hydrogen is evolved at the cathode and heat is released, and the change in the pH value of the deposition solution and the introduction of impurities will generate coating stress, resulting in the coating bulging, which greatly affects the coating yield.

[0004] In addition, the current density difference between the edge and the middle of the gold electroplated by the traditional method is large, and the coating uniformity cannot be guaranteed, thus reducing the wafer-level bonding efficiency and the finished product rate. Summary of the Invention

[0005] In view of the above problems, a method for electroplating gold on the P side of a semiconductor wafer and removing stress provided by the present application can not only release the stress generated by the hydrogen evolution heat at the cathode during electroplating, as well as the change in the pH value of the deposition solution and the introduction of impurities, reduce the coating bulge, and improve the product yield, but also improve the coating uniformity.

[0006] The technical solution adopted by the present invention to solve its technical problems is as follows:

[0007] A method for electroplating gold on the P side of a semiconductor wafer and removing stress includes the following steps:

[0008] S1, using an etching solution to etch at the edge of the wafer to obtain a circular ring layer, and a convex portion is formed inside the circular ring layer;

[0009] S2, dividing the upper surface area of the convex portion into a plurality of non-gold plating areas arranged in parallel, and the gold plating areas are between adjacent non-gold plating areas, and etching a plurality of cleavage grooves in each of the gold plating areas through the etching solution;

[0010] S3, evaporating a gold seed layer on the surfaces of the circular ring layer and the convex portion;

[0011] S4, spin-coating a photoresist once on the gold seed layer, and performing exposure and development, so as to form a plurality of exposed areas on the cleavage grooves to expose the gold seed layer in the exposed areas;

[0012] S5, using ICP etching to remove the gold seed layer exposed in step S4;

[0013] S6. Remove the photoresist for the first time, and stress release regions and intra-region conductive bridges arranged at intervals are formed in the cleavage groove (2).

[0014] S7. Spin-coat the photoresist for the second time on the upper surface of the convex portion, and perform exposure and development, so as to form a barrier layer in the non-gold-plated region. The barrier layer includes a plurality of barrier sub-layers, and inter-region conductive bridges are formed between adjacent barrier sub-layers.

[0015] S8. Perform electroplating of gold, so as to form an electroplated thick gold layer on the region other than the barrier sub-layers on the upper surface of the convex portion.

[0016] Furthermore, the width of the circular ring layer is 1 - 3 mm, and the etching depth is 100 nm.

[0017] Furthermore, the depth of the cleavage groove is 5 - 7 μm, and the width B of the cleavage groove is 20 - 30 μm.

[0018] Furthermore, the thickness of the gold seed layer is 100 - 200 nm.

[0019] Furthermore, the gold seed layer is a TiPtAu seed layer.

[0020] Furthermore, the thicknesses of the first photoresist and the second photoresist are 1 - 3 μm.

[0021] Furthermore, the length C of the intra-region conductive bridge is 200 μm - 500 μm.

[0022] Furthermore, the length of the inter-region conductive bridge is 200 μm - 500 μm.

[0023] Furthermore, the thickness of the electroplated thick gold layer obtained in step S8 is 4 - 6 μm.

[0024] The beneficial effects of the present invention are as follows:

[0025] 1. In the method for electroplating gold on the P surface of a semiconductor wafer and removing stress provided by the embodiment of the present application, inter-region conductive bridges are designed in the non-gold-plated region, and intra-region conductive bridges are designed in the gold-plated region. The number of inter-region conductive bridges in the non-gold-plated region gradually increases from the edge to the middle, and the current flows between the gold-plated regions along the inter-region conductive bridges, which is beneficial to reducing the electroplating current density difference in the gold-plated areas of the entire wafer. Uniformly distributed intra-region conductive bridges are designed in the gold-plated region, and the current flows in the gold-plated region along the intra-region conductive bridges, which is beneficial to reducing the electroplating current density difference within a single gold-plated region. The above two types of designs ensure that the coating uniformity of the entire wafer is stably maintained at 6%, which is beneficial to the wafer-level bonding efficiency and the yield.

[0026] 2. The semiconductor wafer P-side gold plating and stress removal method provided by the embodiments of the present application designs a stress release area on the gold plating area to release the plating stress along the stress release area, which can not only release the stress generated by the hydrogen evolution heat release at the cathode during the electroplating process, the change of the pH value of the deposition solution and the introduction of impurities, but also release the thermal stress during the alloying process, thus greatly reducing the bulging of the plating layer and improving the product yield. Description of the Drawings

[0027] Figure 1 It is a three-dimensional structural schematic diagram of the wafer after being processed by step S2;

[0028] Figure 2 It is a top view of the wafer after being processed by step S2;

[0029] Figure 3 It is a top view of the wafer after being processed by step S3;

[0030] Figure 4 It is a top view of the wafer after being processed by step S4;

[0031] Figure 5 It is Figure 4 the A-A cross-sectional view in

[0032] Figure 6 It is a top view of the wafer after being processed by step S5;

[0033] Figure 7 It is a top view of the wafer after being processed by step S6;

[0034] Figure 8 It is Figure 7 the B-B cross-sectional view in

[0035] Figure 9 It is a top view of the wafer after being processed by step S7.

[0036] In the figure: 1. Ring layer; 2. Cleavage groove; 21. Stress release area; 22. Intra-region conductive bridge; 3. Gold seed layer; 4. Primary photoresist; 41. Exposed area; 5. Barrier layer; 51. Barrier sub-layer; 52. Inter-region conductive bridge. Detailed Embodiments

[0037] In order to enable those skilled in the art to better understand the technical solutions in the present application, the following will describe the technical solutions in the embodiments of the present application in detail with reference to the accompanying drawings in the embodiments of the present application. The described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those skilled in the art without creative efforts based on the embodiments of the present application shall fall within the protection scope of the present application.

[0038] A method for electroplating gold on the P side of a semiconductor wafer and removing stress, comprising the following steps:

[0039] S1, as shown in Figure 1 and Figure 2 , a corrosion solution is used to etch the edge of the P side of the wafer to obtain an annular layer 1 with a width A of 1-3 mm, and a raised portion is formed inside the annular layer 1.

[0040] As a specific implementation, in this embodiment, the etching depth of the annular layer 1 is 100 nm;

[0041] S2, as shown in Figure 1 and Figure 2 , the upper surface area of the raised portion is divided into a plurality of non-gold-plated areas arranged in parallel, and the gold-plated areas are between adjacent non-gold-plated areas. A plurality of cleavage grooves 2 with a depth of 5-7 μm are etched in each of the gold-plated areas by a corrosion solution, and the width B of the cleavage grooves 2 is 20-30 um. Exemplarily, one cleavage groove 2 is provided in the gold-plated areas at both ends, and two cleavage grooves 2 are provided in the remaining gold-plated areas, and the width B of the cleavage grooves 2 is 30 um.

[0042] S3, as shown in Figure 3 , an electron beam evaporation process is used to deposit a gold seed layer 3 with a thickness of 100-200 nm on the surfaces of the annular layer 1 and the raised portion obtained in step S2.

[0043] As a specific implementation, in this embodiment, the gold seed layer 3 is a TiPtAu seed layer, and the thickness of the gold seed layer 3 is 150 nm.

[0044] S4, as shown in Figure 4 and Figure 5 , a layer of primary photoresist 4 with a thickness of 1-3 μm is spin-coated on the gold seed layer 3 obtained in step S3, and exposure and development are performed, so as to form a plurality of exposed areas 41 along the cleavage grooves 2 on the cleavage grooves 2 to expose the gold seed layer 3 in the exposed areas 41.

[0045] As a specific implementation, in this embodiment, the exposed areas 41 in different gold-plated areas are aligned with each other, and the thickness of the primary photoresist 4 is 2 μm.

[0046] S5, as shown in Figure 6 , ICP etching is used to remove the gold seed layer 3 exposed in step S4.

[0047] S6, as shown in Figure 7 and Figure 8 , the primary photoresist 4 is removed, and stress release areas 21 and in-region conductive bridges 22 arranged at intervals are sequentially formed along the length direction of the cleavage grooves 2 in the cleavage grooves 2.

[0048] Preferably, the length C of the conductive bridge 22 within the region is 200 μm - 500 μm.

[0049] As a specific implementation manner, in this embodiment, the length of the conductive bridge 22 within the region is 350 μm.

[0050] S7, spin - coat a layer of secondary photoresist with a thickness of 1 - 3 μm on the upper surface of the convex portion, and perform exposure and development, so as to form a barrier layer 5 as shown in Figure 9 The barrier layer 5 is in an intermittent state and includes a number of barrier sub - layers 51. An inter - region conductive bridge 52 is formed between adjacent barrier sub - layers 51. The barrier sub - layer 51 is the secondary photoresist remaining on the wafer surface.

[0051] Preferably, the length C of the inter - region conductive bridge 52 is 200 μm - 500 μm.

[0052] As a specific implementation manner, in this embodiment, the length D of the inter - region conductive bridge 52 is 350 μm, and the thickness of the secondary photoresist is 2 μm.

[0053] S8, perform gold electroplating at 60 °C using an electroplating process, so as to form a 4 - 6 μm thick electroplated thick gold layer on the region other than the barrier sub - layer 51 on the upper surface of the convex portion.

[0054] As a specific implementation manner, in this embodiment, the thickness of the electroplated thick gold layer is 5 μm.

[0055] Based on the embodiments provided in the present application, other embodiments obtained by those skilled in the art through means such as combining, splitting, and recombining the embodiments of the present application do not exceed the protection scope of the present application.

[0056] The above - mentioned specific implementation manners have elaborated in detail the purpose, technical solutions, and beneficial effects of the embodiments of the present application. The above are only the specific implementation manners of the embodiments of the present application, and are not used to limit the protection scope of the embodiments of the present application. That is, any modifications, equivalent replacements, improvements, etc. made on the basis of the embodiments of the present application shall be included within the protection scope of the embodiments of the present application.

Claims

1. A method for electroplating gold on the P side of a semiconductor wafer and removing stress, characterized in that: It includes the following steps: S1. Use an etching solution to etch at the edge of the wafer to obtain an annular layer (1), and a raised portion is formed inside the annular layer (1). S2. Divide the upper surface area of the raised portion into several non-gilded areas arranged in parallel, and the gilded areas are between adjacent non-gilded areas. Use the etching solution to etch several cleavage grooves (2) in each of the gilded areas. S3. Evaporate a gold seed layer (3) on the surfaces of the annular layer (1) and the raised portion. S4. Spin-coat a layer of photoresist (4) on the gold seed layer (3), and perform exposure and development, so as to form several exposed areas (41) on the cleavage grooves (2) to expose the gold seed layer (3) in the exposed areas (41). S5. Use ICP etching to remove the exposed gold seed layer (3) in step S4. S6. Remove the photoresist (4) once, and stress release areas (21) and intra-region conductive bridges (22) arranged at intervals are formed in the cleavage grooves (2). S7. Spin-coat a second layer of photoresist on the upper surface of the raised portion, and perform exposure and development, so as to form a barrier layer (5) in the non-gilded area. The barrier layer (5) includes several barrier sub-layers (51), and inter-region conductive bridges (52) are formed between adjacent barrier sub-layers (51). S8. Perform electroplating of gold, so as to form an electroplated thick gold layer on the area other than the barrier sub-layers (51) on the upper surface of the raised portion.

2. A method for electroplating gold on the P side of a semiconductor wafer and removing stress according to claim 1, characterized in that: The width of the annular layer (1) is 1 - 3 mm, and the etching depth is 100 nm.

3. A method for electroplating gold on the P side of a semiconductor wafer and removing stress according to claim 1, characterized in that: The depth of the cleavage grooves (2) is 5 - 7 μm, and the width B of the cleavage grooves (2) is 20 - 30 μm.

4. A method for electroplating gold on the P side of a semiconductor wafer and removing stress according to claim 1, characterized in that: The thickness of the gold seed layer (3) is 100 - 200 nm.

5. A method for electroplating gold on the P side of a semiconductor wafer and removing stress according to claim 1, characterized in that: The gold seed layer (3) is a TiPtAu seed layer.

6. A method for electroplating gold on the P side of a semiconductor wafer and removing stress according to claim 1, characterized in that: The thicknesses of the first photoresist (4) and the second photoresist are 1 - 3 μm.

7. A method for electroplating gold on the P side of a semiconductor wafer and removing stress according to claim 1, characterized in that: The length C of the intra-region conductive bridges (22) is 200 μm - 500 μm.

8. A method for electroplating gold on the P side of a semiconductor wafer and removing stress according to claim 1, characterized in that: The length of the inter-region conductive bridges (52) is 200 μm - 500 μm.

9. A method for electroplating gold on the P side of a semiconductor wafer and removing stress according to claim 1, characterized in that: The thickness of the electroplated thick gold layer obtained in step S8 is 4 - 6 μm.

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