Three-level inverter and program

Abstract

In a three-level inverter (30), each upper arm path, which is an electrical path from a connection portion (72c) of a high-potential-side conductive member (72) to a positive-electrode-side bus bar (31), via upper arm diodes (DUH1-DWH2) and an intermediate conductive member (70) to intermediate switches (SQH1-SQW2), is configured such that the impedance of the upper arm paths corresponding to each upper arm diode is equal. Each lower arm path, which is an electrical path from a connection portion between the low-potential-side conductive member (71) and the negative-electrode-side bus bar (32) to the intermediate switch via the lower arm diodes (DUL1 to DWL2) and the intermediate conductive member, is configured such that the lower arm paths corresponding to the lower arm diodes have the same impedance.

Description

Citation of Related Applications

[0001] This application is based on Japanese Patent Application No. 2022-210644 filed on December 27, 2022, the contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a three-level inverter and a program. Background Art

[0003] Conventionally, as described in Patent Document 1, an inverter including two semiconductor switches (specifically, IGBTs) connected in parallel is known. Specifically, the inverter includes a gate drive circuit for driving the two switches, a comparator, an AND circuit, and a transformer. When driving the two switches by the gate drive circuit, the differential value of the collector current flowing in the switch with the higher temperature among the two switches is detected by the comparator, and the primary winding of the transformer is driven via the AND circuit. As a result, an induced voltage is generated in the secondary winding connected between the gates of the two switches, which are the windings constituting the transformer, and the gate voltage of the switch with the higher temperature rises. As a result, the imbalance of the collector current flowing through the two switches is suppressed. Prior Art Documents Patent Documents

[0004] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2004-15910 Summary of the Invention

[0005] As an inverter, a three-level inverter is also known. In a three-level inverter, each phase includes a series connection body of a plurality of upper and lower arm switches, and the series connection bodies are connected in parallel in each phase. The three-level inverter includes an upper arm diode reversely connected in parallel with each upper arm switch, a lower arm diode reversely connected in parallel with each lower arm switch, and an intermediate switch provided corresponding to each.

[0006] In each phase and each arm of the three-level inverter, an imbalance in the recovery current flowing through each diode may occur. Therefore, a structure capable of suppressing the imbalance of the recovery current is desired.

[0007] A main object of the present disclosure is to provide a three-level inverter and a program capable of suppressing the imbalance of the recovery current.

[0008] The three-level inverter of the present disclosure includes a series connection body of a plurality of upper and lower arm switches in each phase, and the series connection bodies are connected in parallel in each phase. The three-level inverter includes: An upper arm diode reversely connected in parallel with each upper arm switch; A lower arm diode reversely connected in parallel with each lower arm switch; Intermediate switches respectively provided corresponding thereto; High-potential-side conductive members respectively provided corresponding thereto and electrically connecting the high-potential-side terminals of the respective upper-arm switches to the positive-side busbar; Low-potential-side conductive members respectively provided corresponding thereto and electrically connecting the low-potential-side terminals of the respective lower-arm switches to the negative-side busbar; and Intermediate conductive members respectively provided corresponding thereto and electrically connecting the low-potential-side terminals of the respective upper-arm switches and the high-potential-side terminals of the respective lower-arm switches to the first end of the intermediate switches, Each upper-arm path is an electrical path from the connection portion with the positive-side busbar in the high-potential-side conductive member via the upper-arm diode and the intermediate conductive member to the intermediate switch, and is configured such that the impedances of the upper-arm paths corresponding to the respective upper-arm diodes are equal, Each lower-arm path is an electrical path from the connection portion with the negative-side busbar in the low-potential-side conductive member via the lower-arm diode and the intermediate conductive member to the intermediate switch, and is configured such that the impedances of the lower-arm paths corresponding to the respective lower-arm diodes are equal.

[0009] According to the present disclosure configured such that the impedances of the respective upper-arm paths are equal and the impedances of the respective lower-arm paths are equal, an imbalance in the recovery current can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above objects, other objects, features, and advantages of the present disclosure can be made more apparent by referring to the drawings and the following detailed description. The drawings are as follows. Figure 1 It is an overall structural diagram of a control system according to the first embodiment. Figure 2 It is a diagram showing the electrical connection of the U-phase circuit. Figure 3 It is a perspective view of each module. Figure 4 It is a top view of each module. Figure 5 It is a diagram showing a switching mode. Figure 6 It is a diagram showing an imbalance state of the recovery current. Figure 7 It is a diagram showing an imbalance state of the recovery current. Figure 8 It is a timing diagram showing an example of oscillation suppression control of the gate voltage. Figure 9 It is a diagram showing a current flow mode in oscillation suppression control. Figure 10 It is a diagram showing a current flow mode in oscillation suppression control. Figure 11 It is a diagram showing the current flow pattern in oscillation suppression control. Figure 12 It is a diagram showing the current flow pattern in oscillation suppression control. Figure 13 It is a diagram showing the current flow pattern in oscillation suppression control. Figure 14 It is a diagram showing the current flow pattern in oscillation suppression control. Figure 15 It is a diagram showing the current flow pattern in oscillation suppression control. Figure 16 It is a timing diagram showing the switching control of the inverter in the comparative example. Figure 17 It is a diagram showing the current flow pattern in the comparative example. Figure 18 It is a diagram showing the current flow pattern in the comparative example. Figure 19 It is a diagram showing the current flow pattern in the comparative example. Figure 20 It is a diagram showing the current flow pattern in the comparative example. Figure 21 It is a flowchart showing the steps of the oscillation suppression control of the gate voltage. Figure 22 It is a flowchart showing the steps of the oscillation suppression control of the gate voltage in the second embodiment. Figure 23 It is a diagram showing the electrical connection of the U-phase circuit in the third embodiment. Figure 24 It is a flowchart showing the steps of the oscillation suppression control of the gate voltage. Detailed Embodiment

[0011] Hereinafter, a plurality of embodiments will be described with reference to the drawings. In a plurality of embodiments, parts and / or related parts that are functionally and / or structurally corresponding are sometimes marked with the same reference numerals or reference numerals with more than three digits different. For corresponding parts and / or related parts, the description of other embodiments can be referred to.

[0012] <First Embodiment> Hereinafter, a first embodiment in which the three-level inverter of the present disclosure is embodied will be described with reference to the drawings. In this embodiment, a control system including a three-level inverter is installed in an electric vehicle such as an electric vehicle or a hybrid vehicle.

[0013] As Figure 1As shown, the control system includes a rotary electric machine 10, a storage battery 20 serving as a DC power source, and an inverter 30. The rotary electric machine 10 is a vehicle-mounted main machine, which includes a rotor (not shown). The rotor can transmit power to the drive wheels of the vehicle. The rotary electric machine 10 in this embodiment is a three-phase synchronous machine, and as a stator winding, it includes a star-connected U-phase winding 11U, a V-phase winding 11V, and a W-phase winding 11W. Each of the phase windings 11U, 11V, and 11W is arranged such that they are electrically angled 120° apart from each other. The rotary electric machine 10 is, for example, a permanent magnet synchronous machine.

[0014] The storage battery 20 is electrically connected to each of the phase windings 11U, 11V, and 11W of the rotary electric machine 10 via the inverter 30. The storage battery 20 is, for example, a battery pack including a series connection of battery cells. The storage battery 20 is, for example, a secondary battery such as a lithium-ion battery that can be charged and discharged.

[0015] The inverter 30 converts the DC power supplied from the storage battery 20 into three-phase AC power by switch control, and supplies the converted AC power to each of the phase windings 11U, 11V, and 11W. The inverter 30 is a three-level inverter, which includes a first capacitor 21 and a second capacitor 22. The first capacitor 21 and the second capacitor 22 are connected in series. The series connection of the first capacitor 21 and the second capacitor 22 is connected in parallel with the storage battery 20. In this embodiment, the electrostatic capacitance of the first capacitor 21 is the same as that of the second capacitor 22.

[0016] The inverter 30 includes an upper arm switch and a lower arm switch corresponding to the three phases. In this embodiment, each arm switch is composed of a parallel connection of a plurality of semiconductor switch elements, specifically, a parallel connection of two semiconductor switch elements. The semiconductor switch element in this embodiment is an IGBT.

[0017] As the upper arm switch and the lower arm switch of the U phase, there are included a U-phase first upper arm switch SUH1, a U-phase second upper arm switch SUH2, a U-phase first lower arm switch SUL1, and a U-phase second lower arm switch SUL2. The U-phase first upper arm switch SUH1 and the U-phase second upper arm switch SUH2 are reversely connected in parallel with a U-phase first upper arm diode DUH1 and a U-phase second upper arm diode DUH2 serving as freewheeling diodes. The U-phase first lower arm switch SUL1 and the U-phase second lower arm switch SUL2 are reversely connected in parallel with a U-phase first lower arm diode DUL1 and a U-phase second lower arm diode DUL2.

[0018] As the upper-arm switches and lower-arm switches of the V phase, they include the first upper-arm switch SVH1 of the V phase, the second upper-arm switch SVH2 of the V phase, the first lower-arm switch SVL1 of the V phase, and the second lower-arm switch SVL2 of the V phase. The first upper-arm switch SVH1 of the V phase and the second upper-arm switch SVH2 of the V phase are reversely connected in parallel with the first upper-arm diode DVH1 of the V phase and the second upper-arm diode DVH2 of the V phase. The first lower-arm switch SVL1 of the V phase and the second lower-arm switch SVL2 of the V phase are reversely connected in parallel with the first lower-arm diode DVL1 of the V phase and the second lower-arm diode DVL2 of the V phase.

[0019] As the upper-arm switches and lower-arm switches of the W phase, they include the first upper-arm switch SWH1 of the W phase, the second upper-arm switch SWH2 of the W phase, the first lower-arm switch SWL1 of the W phase, and the second lower-arm switch SWL2 of the W phase. The first upper-arm switch SWH1 of the W phase and the second upper-arm switch SWH2 of the W phase are reversely connected in parallel with the first upper-arm diode DWH1 of the W phase and the second upper-arm diode DWH2 of the W phase. The first lower-arm switch SWL1 of the W phase and the second lower-arm switch SWL2 of the W phase are reversely connected in parallel with the first lower-arm diode DWL1 of the W phase and the second lower-arm diode DWL2 of the W phase.

[0020] Taking the U phase as an example, the electrical connections of the inverter 30, the storage battery 20, and the rotating electrical machine 10 will be described. The collectors of the first upper-arm switch SUH1 of the U phase and the second upper-arm switch SUH2 of the U phase, which serve as the high-potential-side terminals, are connected to the positive-side busbar 31, which is a conductive member such as a busbar. The positive-side busbar 31 is connected to the positive terminal of the storage battery 20 and the first end of the first capacitor 21. The second end of the first capacitor 21 is connected to the first end of the second capacitor 22. The emitters of the first lower-arm switch SUL1 of the U phase and the second lower-arm switch SUL2 of the U phase, which serve as the low-potential-side terminals, are connected to the negative-side busbar 32, which is a conductive member such as a busbar. The negative-side busbar 32 is connected to the negative terminal of the storage battery 20 and the second end of the second capacitor 22.

[0021] The emitters of the first upper-arm switch SUH1 of the U phase and the second upper-arm switch SUH2 of the U phase, and the collectors of the first lower-arm switch SUL1 of the U phase and the second lower-arm switch SUL2 of the U phase are connected to the first end of the U-phase winding 11U. The second ends of the phase windings 11U, 11V, and 11W are connected to each other at the neutral point.

[0022] The inverter 30 includes intermediate switches corresponding to three phases that conduct and cut off the current in both directions. In the present embodiment, each intermediate switch is composed of two semiconductor switch elements, and the semiconductor switch element is an IGBT.

[0023] As the intermediate switch of the U phase, it includes the first U-phase switch SQU1 and the second U-phase switch SQU2. The first U-phase switch SQU1 and the second U-phase switch SQU2 are reversely connected in parallel with the first U-phase diode DQU1 and the second U-phase diode DQU2 serving as freewheeling diodes. As the intermediate switch of the V phase, it includes the first V-phase switch SQV1 and the second V-phase switch SQV2. The first V-phase switch SQV1 and the second V-phase switch SQV2 are reversely connected in parallel with the first V-phase diode DQV1 and the second V-phase diode DQV2. As the intermediate switch of the W phase, it includes the first W-phase switch SQW1 and the second W-phase switch SQW2. The first W-phase switch SQW1 and the second W-phase switch SQW2 are reversely connected in parallel with the first W-phase diode DQW1 and the second W-phase diode DQW2.

[0024] When the electrical connection of the intermediate switch is described by taking the U phase as an example, the emitters of the first U-phase switch SQU1 and the second U-phase switch SQU2 are connected to each other. The collector of the first U-phase switch SQU1 is connected to the second end of the first capacitor 21 and the second end of the second capacitor 22. The emitter of the second U-phase switch SQU2 is connected to the emitters of the first upper-arm switch SUH1 and the second upper-arm switch SUH2 of the U phase and the collectors of the first lower-arm switch SUL1 and the second lower-arm switch SUL2 of the U phase.

[0025] The control system includes a current sensor 40 and a rotation angle sensor 41. The current sensor 40 detects the phase currents flowing through the phase windings 11U, 11V, and 11W. The rotation angle sensor 41 detects the rotation angle (specifically, the electrical angle) of the rotating motor 10, which is, for example, a resolver. The detection values of the sensors 40 and 41 are input to the control device 50 included in the control system.

[0026] The control device 50 is mainly composed of a microcomputer 51, and the microcomputer 51 includes a CPU. The functions provided by the microcomputer 51 can be provided by software recorded in a physical memory device and a computer that executes the software, software only, hardware only, or a combination thereof. For example, when the microcomputer 51 is provided by an electronic circuit as hardware, it can be provided by a digital circuit or an analog circuit including a plurality of logic circuits. For example, the microcomputer 51 executes a program stored in a non-temporary physical recording medium serving as a storage unit included in itself. The program contains, for example, the Figure 21 programs of the processes shown later, etc. By executing the program installed in the control device 50, the method corresponding to the program is executed. The storage unit is, for example, a non-volatile memory. In addition, the program stored in the storage unit can be downloaded and updated via a communication network such as OTA (Over The Air) or the Internet.

[0027] The control device 50 generates drive signals for the switches SUH1 to SWL2 and SQU1 to SQW2 of the inverter 30 to control the control amount of the rotating electric machine 10 to the command value. The drive signals are composed of an on command and an off command. The control device 50 turns on / off the switches SUH1 to SWL2 and SQU1 to SQW2 based on the generated drive signals. In the present embodiment, the control amount is torque, and the command value is the commanded torque Trq*.

[0028] In the present embodiment, the inverter 30 is composed of switch modules. Hereinafter, Figures 2 to 4 is used to illustrate by taking the U-phase as an example.

[0029] The circuit of the U-phase of the inverter 30 is composed of three switch modules. Specifically, it is composed of a first module M1, a second module M2 (equivalent to "upper arm module and lower arm module"), and an intermediate module MM. Each of the modules M1, M2, and MM includes a housing 60, and semiconductor switching elements and freewheeling diodes are built in the housing 60. The housing 60 is formed in a flat rectangular parallelepiped shape. In the present embodiment, the housings 60 of the modules M1, M2, and MM are formed in the same shape.

[0030] In the housing 60 of the first module M1, a U-phase first upper arm switch SUH1, a U-phase first upper arm diode DUH1, a U-phase first lower arm switch SUL1, and a U-phase first lower arm diode DUL1 are housed. The collector of the U-phase first upper arm switch SUH1 is connected to the high-potential side external terminal CP provided on the housing 60 of the first module M1. The emitter of the U-phase first lower arm switch SUL1 is connected to the low-potential side external terminal CN provided on the housing 60 of the first module M1. The emitter of the U-phase first upper arm switch SUH1 and the collector of the U-phase first lower arm switch SUL1 are connected to the intermediate external terminal CO provided on the housing 60 of the first module M1.

[0031] In the housing 60 of the second module M2, a U-phase second upper arm switch SUH2, a U-phase second upper arm diode DUH2, a U-phase second lower arm switch SUL2, and a U-phase second lower arm diode DUL2 are housed. In the present embodiment, the structure of the second module M2 is the same as that of the first module M1. Therefore, the detailed description of the inside of the second module M2 is omitted.

[0032] In this embodiment, the first module M1 and the second module M2 have the same specifications. Therefore, the internal structures of the first module M1 and the second module M2 are the same. Specifically, the specifications of the switches SUH1, SUL1, SUH2, and SUL2 housed in the first module M1 and the second module M2 are the same. In addition, the specifications of the diodes DUH1, DUL1, DUH2, and DUL2 are also the same. Therefore, the design values of the threshold voltages Vth of the switches SUH1, SUL1, SUH2, and SUL2 are set to the same value, and the design values of the rated currents of the switches SUH1, SUL1, SUH2, and SUL2 are set to the same value. In addition, the design values of the reverse recovery times of the diodes DUH1, DUL1, DUH2, and DUL2 are set to the same value, and the design values of the on-resistances of the diodes DUH1, DUL1, DUH2, and DUL2 are also set to the same value.

[0033] In the housing 60 of the intermediate module MM, a U-phase first switch SQU1, a U-phase second switch SQU2, a U-phase first diode DQU1, and a U-phase second diode DQU2 are housed. The collector of the U-phase first switch SQU1 is connected to the neutral point terminal CM2 provided on the housing 60 of the intermediate module MM. The collector of the U-phase second switch SQU2 is connected to the intermediate terminal CM1 provided on the housing 60 of the intermediate module MM.

[0034] As Figure 3 and Figure 4 shown, the housing 60 of each of the modules M1, M2, and MM includes a pair of main board portions 61 facing each other in the thickness direction (X direction) and a terminal setting surface 62 connecting the ends of the main board portions 61. The modules M1, M2, and MM are arranged and configured in the thickness direction with the main board portions 61 facing each other. The terminal setting surfaces 62 of the modules M1, M2, and MM face a common specific direction (Z direction) orthogonal to the X direction. The intermediate module MM is sandwiched between the first module M1 and the second module M2.

[0035] In the first module M1 and the second module M2, a high-potential side external terminal CP, a low-potential side external terminal CN, and an intermediate external terminal CO are arranged and provided on the terminal setting surface 62 of the housing 60 along the Y direction orthogonal to the X direction and the Z direction. In the intermediate module MM, the neutral point terminal CM2 and the intermediate terminal CM1 are arranged and provided on the terminal setting surface 62 of the housing 60 along the Y direction. In each of the modules M1, M2, and MM, the high-potential side external terminal CP and the neutral point terminal CM2 are arranged and configured in the X direction, and the intermediate external terminal CO and the intermediate terminal CM1 are also arranged and configured in the X direction. In addition, in the first module M1 and the second module M2, the low-potential side external terminal CN is arranged and configured in the X direction.

[0036] As Figure 2and Figure 4 As shown, the high-potential-side external terminal CP of the first module M1 and the high-potential-side external terminal CP of the second module M2 are connected by a high-potential-side bus bar 72 (equivalent to the "high-potential-side conductive member"). As Figure 4 shown, when viewed from the front on the terminal setting surface 62, the high-potential-side bus bar 72 is formed in a shape symmetric with respect to a reference axis BL passing through the central portion in the thickness direction of the housing 60 of the intermediate module MM. Specifically, the high-potential-side bus bar 72 includes two terminal connection portions 72a, a first connection portion 72b, and a second connection portion 72c. When viewed from the front on the terminal setting surface 62, the first connection portion 72b extends in the X direction. The terminal connection portions 72a extend in the Y direction from both ends in the length direction of the first connection portion 72b. One of the two terminal connection portions 72a is connected to the high-potential-side external terminal CP of the first module M1, and the other is connected to the high-potential-side external terminal CP of the second module M2. The second connection portion 72c extends from the central portion in the length direction of the first connection portion 72b in a direction opposite to the direction in which the terminal connection portion 72a extends with respect to the first connection portion 72b. The second connection portion 72c is connected to the positive-side bus bar 31.

[0037] The high-potential-side external terminals CP of the first module M1 and the second module M2 are connected to the intermediate terminal CM1 of the intermediate module MM by an intermediate bus bar 70 (equivalent to the "intermediate conductive member"). As Figure 4 shown, when viewed from the front on the terminal setting surface 62, the intermediate bus bar 70 is in a shape symmetric with respect to the reference axis BL. Specifically, the intermediate bus bar 70 includes a first connection portion 70a and a second connection portion 70b. The first connection portion 70a extends in the X direction. The second connection portion 70b extends from the central portion in the length direction of the first connection portion 70a in the Y direction in a direction opposite to that of the high-potential-side bus bar 72. The second connection portion 70b is connected to the neutral-point terminal CM2 of the intermediate module MM and the first end of the winding of the rotating electric machine 10.

[0038] The symmetrical structure of the high-potential side bus bar 72, the same specifications of the first module M1 and the second module M2, and the symmetrical structure of the intermediate bus bar 70 help to make the impedances of the first upper-arm path and the second upper-arm path equal. The first upper-arm path is an electrical path that reaches the intermediate terminal CM1 of the intermediate module MM from the second connection portion 72c via the first connection portion 72b, the high-potential side external terminal CP of the first module M1, the U-phase first upper-arm diode DUh1, the intermediate external terminal CO of the first module M1, the first connection portion 70a, and the second connection portion 70b, and it is an electrical path corresponding to the U-phase first upper-arm diode DUh1. The second upper-arm path is an electrical path that reaches the intermediate terminal CM1 of the intermediate module MM from the second connection portion 72c via the first connection portion 72b, the high-potential side external terminal CP of the second module M2, the U-phase second upper-arm diode DUh2, the intermediate external terminal CO of the second module M2, the first connection portion 70a, and the second connection portion 70b, and it is an electrical path corresponding to the U-phase second upper-arm diode DUh2. In addition, the equal impedances of the first upper-arm path and the second upper-arm path mean, for example, that the deviation amount of the impedances of the first upper-arm path and the second upper-arm path is within the range of 20% of the impedance of the larger one of the impedances of the first upper-arm path and the second upper-arm path, and preferably, the above deviation amount is within the range of 15% of the impedance of the larger one of the impedances of the first upper-arm path and the second upper-arm path, and more preferably, the above deviation amount is within the range of 5% of the impedance of the larger one of the impedances of the first upper-arm path and the second upper-arm path.

[0039] The low-potential side external terminal CN of the first module M1 and the low-potential side external terminal CN of the second module M2 are connected by a low-potential side bus bar 71 (equivalent to a "low-potential side conductive member"). As Figure 4 shown, when viewed from the front on the terminal setting surface 62, the low-potential side bus bar 71 has a shape symmetrical with respect to the reference axis BL and extends in the X direction. The central portion of the low-potential side bus bar 71 in the X direction is connected to the negative-side bus bar 32.

[0040] The symmetrical structure of the low-potential side busbar 71, the same specifications of the first module M1 and the second module M2, and the symmetrical structure of the intermediate busbar 70 contribute to making the impedances of the first lower-arm path and the second lower-arm path equal. The first lower-arm path is an electrical path that starts from the central portion in the X direction of the low-potential side busbar 71, passes through the low-potential side external terminal CN of the first module M1, the U-phase first lower-arm diode DUL1, the intermediate external terminal CO of the first module M1, the first connection portion 70a, and the second connection portion 70b, and reaches the intermediate terminal CM1 of the intermediate module MM. It is the electrical path corresponding to the U-phase first lower-arm diode DUL1. The second lower-arm path is an electrical path that starts from the central portion in the X direction of the low-potential side busbar 71, passes through the low-potential side external terminal CN of the second module M2, the U-phase second lower-arm diode DUL2, the intermediate external terminal CO of the second module M2, the first connection portion 70a, and the second connection portion 70b, and reaches the intermediate terminal CM1 of the intermediate module MM. It is the electrical path corresponding to the U-phase second lower-arm diode DUL2. In addition, the equality of the impedances of the first lower-arm path and the second lower-arm path means, for example, that the deviation amount of the impedances of the first lower-arm path and the second lower-arm path is within the range of 20% of the impedance of the larger one of the impedances of the first lower-arm path and the second lower-arm path. Preferably, the above deviation amount is within the range of 15% of the impedance of the larger one of the impedances of the first lower-arm path and the second lower-arm path. More preferably, the above deviation amount is within the range of 5% of the impedance of the larger one of the impedances of the first lower-arm path and the second lower-arm path.

[0041] In addition, in the present embodiment, in the terminal setting surface 62 of the intermediate module MM, no external terminal is provided between the intermediate terminal CM1 and the neutral point terminal CM2. Therefore, it is possible to reduce the density of the external terminals when the three modules M1, M2, and MM are assembled in each phase and improve the heat dissipation.

[0042] The control device 50 includes a drive circuit 52 (refer to Figure 6 ). The drive circuit 52 is provided separately corresponding to each of the switches SUH1 to SWL2 included in the inverter 30, for example.

[0043] When the drive circuit 52 determines that the input drive signal is an on command, it supplies a charging current to the gate of the switch corresponding to itself. As a result, the gate voltage of the switch becomes equal to or higher than the threshold voltage Vth, and the switch is set to the on state. On the other hand, when the drive circuit 52 determines that the drive signal is an off command, it causes a discharge current to flow from the gate of the switch corresponding to itself to the ground terminal. As a result, the gate voltage of the switch becomes less than the threshold voltage Vth, and the switch is set to the off state.

[0044] Next, use Figure 5, the three-level voltage that can be output from the inverter 30 will be described. Hereinafter, the U-phase will be taken as an example for description.

[0045] The inverter 30 can output voltages of three levels: H, M, and L. When the voltage of the L level is set to 0, the voltage of the H level is equal to the terminal voltage of the series connection of the first capacitor 21 and the second capacitor 22, and the voltage of the M level is equal to the terminal voltage of the second capacitor 22.

[0046] When outputting the voltage of the H level, the control device 50 turns on the U-phase first upper-arm switch SUH1 and the U-phase second upper-arm switch SUH2, and turns off the U-phase first lower-arm switch SUL1 and the U-phase second lower-arm switch SUL2. In addition, the control device 50 turns on the U-phase first switch SQU1 and turns off the U-phase second switch SQU2. Turning off the U-phase second switch SQU2 is to prevent a short circuit between both ends of the first capacitor 21 via the U-phase first upper-arm switch SUH1, the U-phase second upper-arm switch SUH2, the U-phase second switch SQU2, and the U-phase first diode DQU1. Hereinafter, the switching pattern when outputting the voltage of the H level is sometimes referred to as the H-level pattern.

[0047] When outputting the voltage of the M level, the control device 50 turns off the U-phase first upper-arm switch SUH1, the U-phase second upper-arm switch SUH2, the U-phase first lower-arm switch SUL1, and the U-phase second lower-arm switch SUL2. In addition, the control device 50 turns on the U-phase first switch SQU1 and the U-phase second switch SQU2. Hereinafter, the switching pattern when outputting the voltage of the M level is sometimes referred to as the M-level pattern.

[0048] When switching from one of the H-level pattern and the M-level pattern to the other, the control device 50 inserts the H-M dead-time pattern therebetween. The H-M dead-time pattern is a switching pattern in which the U-phase first upper-arm switch SUH1, the U-phase second upper-arm switch SUH2, the U-phase first lower-arm switch SUL1, the U-phase second lower-arm switch SUL2, and the U-phase second switch SQU2 are turned off, and the U-phase first switch SQU1 is turned on.

[0049] When outputting the voltage of the L level, the control device 50 turns off the U-phase first upper-arm switch SUH1 and the U-phase second upper-arm switch SUH2, and turns on the U-phase first lower-arm switch SUL1 and the U-phase second lower-arm switch SUL2. In addition, the control device 50 turns off the U-phase first switch SQU1 and turns on the U-phase second switch SQU2. Turning off the U-phase first switch SQU1 is to prevent a short circuit between both ends of the second capacitor 22 via the U-phase first lower-arm switch SUL1, the U-phase second lower-arm switch SUL2, the U-phase second switch SQU2, and the U-phase first diode DQU1. Hereinafter, the switching pattern when outputting the voltage of the L level is sometimes referred to as the L-level pattern.

[0050] When switching from one of the M-level mode and the L-level mode to the other, the control device 50 interposes the M-L dead time mode therebetween. The M-L dead time mode is a switching mode in which the U-phase first upper-arm switch SUH1, the U-phase second upper-arm switch SUH2, the U-phase first lower-arm switch SUL1, the U-phase second lower-arm switch SUL2, and the U-phase first switch SQU1 are turned off, and the U-phase second switch SQU2 is turned on.

[0051] When switching from one of the H-level mode and the L-level mode to the other, the control device 50 interposes the H-L dead time mode therebetween. The H-L dead time mode is a switching mode in which the U-phase first upper-arm switch SUH1, the U-phase second upper-arm switch SUH2, the U-phase first lower-arm switch SUL1, the U-phase second lower-arm switch SUL2, the U-phase first switch SQU1, and the U-phase second switch SQU2 are turned off.

[0052] However, in each phase, an imbalance in the recovery current flowing through the freewheeling diodes of the switches connected in parallel may occur. In this case, the gate voltage of each switch may oscillate, and thus each switch may malfunction. Hereinafter, Figure 6 and Figure 7 are used, and the U-phase upper arm will be taken as an example for explanation. Figure 6 and Figure 7 show the current flow mode immediately after switching from the L-level mode to the H-level mode via the H-L dead time mode when the current flows from the inverter 30 side to the winding side.

[0053] The ground terminal GND1 of the drive circuit 52 electrically connected to the gate of the U-phase first upper-arm switch SUH1 is connected to a position between, for example, the emitter of the U-phase first upper-arm switch SUH1 and the intermediate external terminal CO of the first module M1 in the first upper-arm path. In addition, the ground terminal GND2 of the drive circuit 52 electrically connected to the gate of the U-phase second upper-arm switch SUH2 is connected to a position between, for example, the emitter of the U-phase second upper-arm switch SUH2 and the intermediate external terminal CO of the second module M2 in the second upper-arm path.

[0054] Figure 6R1 and L1 shown schematically represent the resistance component and impedance component of the electrical path from the emitter of the U-phase first upper-arm switch SUH1 to the ground terminal GND1 existing in the first upper-arm path, and R2 and L2 shown schematically represent the resistance component and impedance component of the electrical path from the emitter of the U-phase second upper-arm switch SUH2 to the ground terminal GND2 existing in the second upper-arm path. In addition, ΔV1 represents the voltage difference (hereinafter, the first voltage difference) in the electrical path from the emitter of the U-phase first upper-arm switch SUH1 to the ground terminal GND1 in the first upper-arm path, and ΔV2 represents the voltage difference (hereinafter, the second voltage difference) in the electrical path from the emitter of the U-phase second upper-arm switch SUH2 to the ground terminal GND2 in the second upper-arm path.

[0055] Due to the deviation of the threshold voltage Vth of the U-phase first upper-arm switch SUH1 and the U-phase second upper-arm switch SUH2, the deviation of the reduction rate dif / dt of the forward current of the U-phase first lower-arm diode DUL1 and the U-phase second lower-arm diode DUL2 when switching from the L-level mode to the H-L dead-time mode, and the deviation of the forward voltage of the U-phase first lower-arm diode DUL1 and the U-phase second lower-arm diode DUL2, etc., an imbalance in the recovery current flowing through the U-phase first upper-arm diode DUH1 and the U-phase second upper-arm diode DUH2 occurs. In Figure 6 the example shown, the recovery current flowing through the U-phase first upper-arm diode DUH1 is less than the recovery current flowing through the U-phase second upper-arm diode DUH2, and the first voltage difference ΔV1 is less than the second voltage difference ΔV2.

[0056] [[ID=Z8]]In this case, the gate voltage of the U-phase first upper-arm switch SUH1, which is the one with the smaller voltage difference among the switches SUH1 and SUH2, is higher than the gate voltage of the U-phase second upper-arm switch SUH2, which is the one with the larger voltage difference. As a result, the on-resistance of the U-phase first upper-arm switch SUH1 is less than the on-resistance of the U-phase second upper-arm switch SUH2, and as Figure 7 shown, the recovery current flowing through the U-phase first upper-arm diode DUH1 next time is greater than the recovery current flowing through the U-phase second upper-arm diode DUH2. As a result, the second voltage difference ΔV2 is less than the first voltage difference ΔV1.

[0057] In this case, the gate voltage of the U-phase second upper-arm switch SUH2, which is the one with the smaller voltage difference among the switches SUH1 and SUH2, is higher than the gate voltage of the U-phase first upper-arm switch SUH1, which is the one with the larger voltage difference. As a result, the on-resistance of the U-phase second upper-arm switch SUH2 is less than the on-resistance of the U-phase first upper-arm switch SUH1, and the recovery current flowing through the U-phase second upper-arm diode DUH2 next time is greater than the recovery current flowing through the U-phase first upper-arm diode DUH1.

[0058] When such a phenomenon occurs repeatedly, the gate voltages of the switches SUH1 and SUH2 oscillate. When the oscillation phenomenon of the gate voltage occurs, the gate voltage will exceed the allowable upper limit of the gate voltage, and the switches SUH1 and SUH2 may malfunction.

[0059] Therefore, in this embodiment, the characteristic structure of the inverter 30 and the characteristic control of the inverter 30 are used to suppress the occurrence of the oscillation phenomenon of the gate voltage and suppress the imbalance of the recovery current.

[0060] The characteristic structure refers to a structure in which the impedance of the first upper arm path and the second upper arm path is made equal, and the impedance of the first lower arm path and the second lower arm path is made equal.

[0061] In addition, the characteristic control refers to the oscillation suppression control described below. When it is determined that the magnitude of the phase current detected by the current sensor 40 in each phase exceeds the threshold current Ith, the control device 50 performs the oscillation suppression control, and when it is determined that the magnitude of the phase current is less than the threshold current Ith, the control device 50 performs the normal switching control of the inverter 30. Taking the magnitude of the phase current exceeding the threshold current Ith as a condition is to perform the oscillation suppression control only in the situation where the imbalance degree of the recovery current increases and the oscillation of the gate voltage is likely to occur. Hereinafter, taking Figures 8 to 15 the case where the magnitude of the U-phase current in the U, V, and W phases exceeds the threshold current Ith and the oscillation suppression control is performed for the U phase as an example for explanation.

[0062] Figure 8 The figure shows the changes in the phase currents IU, IV, and IW flowing through the U, V, and W phase windings 11U, 11V, and 11W and the changes in the switching patterns of the U, V, and W phases. For the phase currents IU, IV, and IW, the case of flowing in the direction from the inverter 30 toward the winding is defined as positive.

[0063] As Figure 8 shown, the control device 50 switches to the M-level mode at time t1 and switches to the H-level mode at time t2. When the control device 50 switches from the L-level mode to the H-level mode, the execution of the H-L dead time mode is prohibited, and the M-level mode is interposed therebetween.

[0064] Figure 9 is a diagram showing the current flow mode when the L-level mode is executed before time t1. Figure 10 shows the current flow mode when switching from the L-level mode to the M-L dead time mode near time t1.

[0065] Then, at time t1, it switches from the M-L dead time mode to the M-level mode. Thus, as Figure 11As shown, a reverse voltage is applied to the U-phase first lower-arm diode DUL1 and the U-phase second lower-arm diode DUL2, and then a recovery current flows through the U-phase first lower-arm diode DUL1 and the U-phase second lower-arm diode DUL2. In this case, in the upper arm and the lower arm, the recovery current flows only in the lower arm. Therefore, a path including the U-phase first upper-arm diode DUH1, the U-phase second upper-arm diode DUH2, and the high-potential-side bus 72 can be removed from the path through which the recovery current flows. As a result, the main factors causing the impedance deviation between the two paths for the recovery current to flow can be reduced, thereby suppressing the imbalance of the recovery current. Thereby, the oscillation of the gate voltage is suppressed.

[0066] Figure 12 FIG. is a diagram showing the current flow mode when the M-level mode is executed before time t3. Figure 13 FIG. shows the current flow mode when switching from the M-level mode to the H-M dead time mode near time t3. The execution period of the H-M dead time mode is preferably set to a period longer than the reverse recovery time of the upper-arm diodes DUH1, DUH2 and the lower-arm diodes DUL1, DUL2.

[0067] Then, at time t3, it is switched from the H-M dead time mode to the H-level mode. Thus, as Figure 14 shown, a reverse voltage is applied to the U-phase first upper-arm diode DUH1 and the U-phase second upper-arm diode DUH2, and then a recovery current flows through the U-phase first upper-arm diode DUH1 and the U-phase second upper-arm diode DUH2. In this case, in the upper arm and the lower arm, the recovery current flows only in the upper arm. Therefore, a path including the U-phase first lower-arm diode DUL1, the U-phase second lower-arm diode DUL2, and the low-potential-side bus 71 can be removed from the path through which the recovery current flows. As a result, the main factors causing the impedance deviation between the two paths for the recovery current to flow can be reduced, thereby suppressing the imbalance of the recovery current. Thereby, the oscillation of the gate voltage is suppressed. In addition, Figure 15 FIG. shows the current flow path after the recovery ends immediately after time t3.

[0068] In contrast, in the case of a comparative example in which when switching from the L-level mode to the H-level mode, the H-L dead time mode is executed and the M-level mode is not interposed therebetween, the imbalance of the recovery current is larger than that of the present embodiment. Hereinafter, Figures 16 to 20 the comparative example will be described.

[0069] As Figure 16 shown, the control device of the comparative example switches the U-phase from the L-level mode to the H-level mode at time t1, and switches the V-phase from the L-level mode to the H-level mode at time t2.

[0070] Figure 17 It is a diagram showing the current flow pattern when the L-level mode is executed before time t1. Figure 18 It shows the current flow pattern when switching from the L-level mode to the H-L dead time mode near time t1.

[0071] Then, at time t1, it switches from the H-L dead time mode to the H-level mode. Thus, as Figure 19 shown, a recovery current flows through the U-phase first upper-arm diode DUH1, the U-phase second upper-arm diode DUH2, the U-phase first lower-arm diode DUL1, and the U-phase second lower-arm diode DUL2. In this case, the current path for the recovery current includes paths for both the upper arm and the lower arm. As a result, the main factors causing impedance deviation between the two paths for the recovery current to flow cannot be reduced. Additionally, Figure 20 It shows the current flow path after the end of recovery immediately after time t1.

[0072] Figure 21 It shows a flowchart of the switching control of the inverter 30 executed by the control device 50. This control is executed in each phase.

[0073] In step S10, it is determined whether the magnitude of the phase current detected by the current sensor 40 exceeds the threshold current Ith.

[0074] When a negative determination is made in step S10, it proceeds to step S11 to perform normal switching control of the inverter 30. On the other hand, when an affirmative determination is made in step S10, it proceeds to step S12 to perform the oscillation suppression control Figures 8 to 15 described above.

[0075] As described above, in the present embodiment, when switching from the L-level mode to the H-level mode, the M-level mode is temporarily interposed therebetween. Specifically, when switching from the L-level mode to the H-level mode, the control device 50 prohibits the execution of the H-L dead time mode and switches from the L-level mode via the M-L dead time mode, the M-level mode, and the H-M dead time mode to the H-level mode. Thereby, the imbalance of the recovery current can be suppressed, and further, the oscillation of the gate voltage can be suppressed.

[0076] <Second Embodiment> Hereinafter, with reference to the drawings, the second embodiment will be described centering on the differences from the first embodiment. In the present embodiment, as Figure 22As shown, the execution conditions of the oscillation suppression control are changed. Specifically, in step S13, it is determined whether the command torque Trq* exceeds the torque threshold Trqth. If an affirmative determination is made in step S13, the process proceeds to step S12 to perform the oscillation suppression control.

[0077] According to the present embodiment described above, when the command torque Trq* exceeds the torque threshold Trqth, the oscillation suppression control is executed regardless of the magnitude of the phase current in each phase. Thus, the same effect as the first embodiment can be achieved.

[0078] <Third Embodiment> Hereinafter, with reference to the drawings, the third embodiment will be described centering on the differences from the first embodiment. In the present embodiment, the control system includes individual current sensors for detecting the collector current flowing through each switch. In Figure 23 As an example of the individual current sensors, a first current sensor 42 for detecting the collector current flowing through the first upper-arm switch SUH1 of the U-phase and a second current sensor 43 for detecting the collector current flowing through the second upper-arm switch SUH2 of the U-phase are provided. The detection values of the respective current sensors 42 and 43 are input to the control device 50.

[0079] In the present embodiment, as Figure 24 shown, the execution conditions of the oscillation suppression control are changed. Specifically, in step S14, the current difference ΔI, which is the difference between the collector current detected by the first current sensor 42 and the collector current detected by the second current sensor 43, is calculated. Then, it is determined whether the calculated current difference ΔI exceeds a specified current difference Iα (for example, 50 A). If an affirmative determination is made in step S14, the process proceeds to step S12 to perform the oscillation suppression control.

[0080] In addition, for the first lower-arm switch SUL1 and the second lower-arm switch SUL2 of the U-phase, individual current sensors are also provided in the same manner as for the upper arms, and the processing shown in Figure 24 can be executed.

[0081] According to the present embodiment described above, it is possible to accurately grasp the situation where the imbalance degree of the recovery current becomes large and execute the oscillation suppression control.

[0082] <Other Embodiments> In addition, the above-described embodiments can also be implemented with the following changes.

[0083] · In Figure 23In the structure shown, it is also possible that, for example, either the first current sensor 42 or the second current sensor 43, which is a separate current sensor, is provided at a position in the intermediate bus bar 70 that can detect the phase current flowing through the winding. In this case, the collector current flowing through the switch on the side where the separate current sensor is not provided among the U-phase first upper-arm switch SUH1 and the U-phase second upper-arm switch SUH2 can be calculated based on the detection values of the first current sensor 42 and the second current sensor 43.

[0084] · The arrangement positions of the U-phase first switch SQU1 and the U-phase second switch SQU2 can also be reversed. The same applies to the intermediate switches of the V-phase and W-phase.

[0085] · As the semiconductor switch elements constituting the inverter, they are not limited to IGBTs. For example, they can also be N-channel MOSFETs with body diodes. In this case, the high-potential side terminal of the semiconductor switch element is the drain, and the low-potential side terminal is the source. In addition, in this case, the intermediate switch of each phase can be constituted by two N-channel MOSFETs connected by their sources or their drains to each other.

[0086] · It is also possible that instead of adopting both the characteristic structure that makes the impedances of each arm path equal and the oscillation suppression control as the characteristic control, only either one of them is adopted for the three-level inverter.

[0087] · The number of parallel connections of the switches for each phase and each arm is not limited to two, and can also be three or more.

[0088] · As the rotating electrical machine, it is not limited to the star connection, and can also be the delta connection.

[0089] · As the installation destinations of the inverter, the rotating electrical machine, and the control device, they are not limited to vehicles. For example, they can also be moving bodies such as airplanes or ships. In addition, as the installation destinations of the inverter, the rotating electrical machine, and the control device, they are not limited to moving bodies.

[0090] · The control unit and its method described in the present disclosure can also be implemented by a dedicated computer provided by configuring a processor and a memory, and the above-mentioned processor is programmed to execute one or more functions embodied by a computer program. Alternatively, the control unit and the method of the control unit described in the present disclosure can be implemented by a dedicated computer provided by configuring a processor composed of one or more dedicated hardware logic circuits. Alternatively, the control unit and the method of the control unit described in the present disclosure can be implemented by one or more dedicated computers, and the dedicated computers are composed of a combination of a processor programmed to execute one or more functions and a memory and a processor composed of one or more hardware logic circuits. In addition, the computer program can also be stored in a computer-readable non-transitory tangible recording medium as instructions executed by a computer.

[0091] Hereinafter, the characteristic structures extracted from the above-described respective embodiments will be described. [Structure 1] A three-level inverter (30) includes, in each phase, a series connection body of a plurality of upper and lower arm switches (SUH1 to SWL2), and in each phase, the respective series connection bodies are connected in parallel. The three-level inverter includes: Upper arm diodes (DUH1 to DWH2) reversely connected in parallel with the respective upper arm switches; Lower arm diodes (DUL1 to DWL2) reversely connected in parallel with the respective lower arm switches; Intermediate switches (SQU1 to SQW2) provided corresponding to each phase; High-potential side conductive members (72) provided corresponding to each phase and electrically connecting the high-potential side terminals of the respective upper arm switches to the positive side bus bar (31); Low-potential side conductive members (71) provided corresponding to each phase and electrically connecting the low-potential side terminals of the respective lower arm switches to the negative side bus bar (32); and An intermediate conductive member (70) provided corresponding to each phase and electrically connecting the low-potential side terminals of the respective upper arm switches and the high-potential side terminals of the respective lower arm switches to the first end of the intermediate switch, Each upper arm path is an electrical path from the connection portion (72c) of the high-potential side conductive member with the positive side bus bar via the upper arm diode and the intermediate conductive member to the intermediate switch, and is configured such that the impedances of the upper arm paths corresponding to the respective upper arm diodes are equal. Each lower arm path is an electrical path that starts from the connection part of the low-potential side conductive member to the negative-side bus bar, passes through the lower arm diode and the intermediate conductive member, and reaches the intermediate switch, and is configured to make the impedances of the lower arm paths corresponding to the respective lower arm diodes equal. [Structure 2] The three-level inverter according to Structure 1, For each series connection body of the upper and lower arm switches, the series connection body, the upper arm diode reversely connected in parallel with the upper arm switch included in the series connection body, and the lower arm diode reversely connected in parallel with the lower arm switch included in the series connection body are housed in a housing (60) and integrated, thereby forming upper and lower arm modules (M1, M2). [Structure 3] The three-level inverter according to Structure 2, The intermediate switch has: a first switch (SQU1); a first diode (DQU1) reversely connected in parallel with the first switch; a second switch (SQU2) connected in series with the first switch; and a second diode (DQU2) reversely connected in parallel with the second switch. The first switch, the first diode, the second switch, and the second diode are housed in a housing (60) and integrated, thereby forming an intermediate module (MM). [Structure 4] The three-level inverter according to Structure 3, Each phase includes two series connection bodies of the upper and lower arm switches. The housings of the respective upper and lower arm modules and the intermediate module are formed in a flat rectangular parallelepiped shape. The respective upper and lower arm modules are modules of the same specification. In each phase, the respective upper and lower arm modules and the intermediate module are arranged and configured along the thickness direction of the housing. In each phase, the intermediate module is arranged in a state of being sandwiched by the respective upper and lower arm modules. In each phase, the terminal setting surfaces (62) of the housings of the respective upper and lower arm modules and the intermediate module face a common specific direction. On the terminal setting surface of each of the upper and lower arm modules, there are provided: a high-potential side external terminal (CP) electrically connected to the high-potential side terminal of the upper arm switch; a low-potential side external terminal (CN) electrically connected to the low-potential side terminal of the lower arm switch; and an intermediate external terminal (CO) electrically connected to the low-potential side terminal of the upper arm switch and the high-potential side terminal of the lower arm switch. On the intermediate module, there is provided an intermediate terminal (CM2) electrically connected to one end of the second switch. In each phase, the intermediate external terminals of the respective upper and lower arm modules and the intermediate terminal of the intermediate module are arranged along the thickness direction of the housing. In each phase, the high-potential side external terminals of the respective upper and lower arm modules are arranged along the thickness direction of the housing. In each phase, the low-potential side external terminals of the respective upper and lower arm modules are arranged along the thickness direction of the housing. The high-potential side conductive member electrically connects the high-potential side external terminals of the respective upper and lower arm modules. The low-potential side conductive member electrically connects the low-potential side external terminals of the respective upper and lower arm modules. The intermediate conductive member electrically connects the intermediate external terminals of the respective upper and lower arm modules and the intermediate terminal of the intermediate module. When viewed from the front of the terminal setting surface, the high-potential side conductive member, the low-potential side conductive member, and the intermediate conductive member are formed in a shape symmetric with respect to a reference axis (BL) that passes through the central portion in the thickness direction of the outer housing of the intermediate module. [Structure 5] The three-level inverter according to any one of Structures 1 to 4. The intermediate switch has: a first switch (SQU1); a first diode (DQU1) connected in anti-parallel with the first switch; a second switch (SQU2) connected in series with the first switch; and a second diode (DQU2) connected in anti-parallel with the second switch. The three-level inverter includes a control device (50) that switches between an H-level mode, an M-level mode, and an L-level mode. In the H-level mode, the upper arm switch is turned on and the lower arm switch is turned off to output a voltage of the H level. In the M-level mode, the first and second switches are turned on and the lower arm switch is turned off to output a voltage of the M level. In the L-level mode, the lower arm switch is turned on and the upper arm switch is turned off to output a voltage of the L level. When the control device switches from the L-level mode to the H-level mode, it performs oscillation suppression control that makes the M-level mode intervene between the L-level mode and the H-level mode. [Structure 6] The three-level inverter according to Structure 5. The oscillation suppression control is a control that prohibits the execution of the H-L dead time mode and switches from the L-level mode via the M-level mode and the H-M dead time mode to the H-level mode, where the H-L dead time mode is a switching mode in which the upper and lower arm switches and the intermediate switch are turned off. The H-M dead time control is a switching mode in which the upper and lower arm switches and the second switch are turned off and the first switch is turned on. The execution period of the H-M dead time control is set to a period longer than the reverse recovery time of the upper arm diode and the lower arm diode. [Structure 7] The three-level inverter according to Structure 5 or 6. The control device executes the oscillation suppression control on the condition that a specific condition is satisfied. The specific condition is any one of the following conditions: The magnitude of the output current of the three-level inverter exceeds a threshold current (Ith); The magnitude of the commanded torque of the rotating machine electrically connected to the three-level inverter exceeds a torque threshold (Trqth); The difference in the magnitudes of the currents flowing between the high-potential side terminals and the low-potential side terminals of the respective upper arm switches connected in parallel exceeds a specified current difference; or The difference in the magnitudes of the currents flowing between the high-potential side terminals and the low-potential side terminals of the respective lower arm switches connected in parallel exceeds a specified current difference. [Structure 8] The three-level inverter according to any one of Structures 1 to 7 includes: A first capacitor (21) that electrically connects the second end of the intermediate switch in each phase to the positive-side bus; and A second capacitor (22) that electrically connects the second end of the intermediate switch in each phase to the negative-side bus. [Structure 9] A three-level inverter (30) includes, in each phase, a series connection body of a plurality of upper and lower arm switches (SUH1 to SWL2), and in each phase, the respective series connection bodies are connected in parallel. The three-level inverter includes: Upper arm diodes (DUH1 to DWH2) reversely connected in parallel with the respective upper arm switches; Lower arm diodes (DUL1 to DWL2) reversely connected in parallel with the respective lower arm switches; Intermediate switches (SQU1 to SQW2) provided corresponding to each phase; A high-potential-side conductive member (72) that is correspondingly provided for each and electrically connects the high-potential-side terminal of each upper-arm switch and the positive-side bus bar (31); A low-potential-side conductive member (71) that is correspondingly provided for each and electrically connects the low-potential-side terminal of each lower-arm switch and the negative-side bus bar (32); An intermediate conductive member (70) that is correspondingly provided for each and electrically connects the low-potential-side terminal of each upper-arm switch and the high-potential-side terminal of each lower-arm switch to the first end of the intermediate switch; and A control device (50), The intermediate switch has: a first switch (SQU1); a first diode (DQU1) connected in anti-parallel with the first switch; a second switch (SQU2) connected in series with the first switch; and a second diode (DQU2) connected in anti-parallel with the second switch, The control device alternately implements an H-level mode, an M-level mode, and an L-level mode. In the H-level mode, the upper-arm switch is turned on and the lower-arm switch is turned off to output a voltage of the H level. In the M-level mode, the first and second switches are turned on and the upper and lower-arm switches are turned off to output a voltage of the M level. In the L-level mode, the lower-arm switch is turned on and the upper-arm switch is turned off to output a voltage of the L level, When the control device switches from the L-level mode to the H-level mode, oscillation suppression control is performed to make the M-level mode intermediate between the L-level mode and the H-level mode. [Structure 10] A program that is applied to a three-level inverter (30). The three-level inverter includes a series connection body of a plurality of upper and lower-arm switches (SUH1 to SWL2) in each phase, and the series connection bodies in each phase are connected in parallel, The three-level inverter includes: Upper-arm diodes (DUH1 to DWH2) connected in anti-parallel with the respective upper-arm switches; Lower-arm diodes (DUL1 to DWL2) connected in anti-parallel with the respective lower-arm switches; Intermediate switches (SQU1 to SQW2) correspondingly provided for each; A high-potential-side conductive member (72) that is correspondingly provided for each and electrically connects the high-potential-side terminal of each upper-arm switch and the positive-side bus bar (31); A low-potential-side conductive member (71) that is correspondingly provided for each and electrically connects the low-potential-side terminal of each lower-arm switch and the negative-side bus bar (32); An intermediate conductive member (70) is provided corresponding to each, and electrically connects the low-potential side terminals of the respective upper-arm switches and the high-potential side terminals of the respective lower-arm switches to the first end of the intermediate switch; and A control device (50), The intermediate switch has: a first switch (SQU1); a first diode (DQU1) connected in anti-parallel with the first switch; a second switch (SQU2) connected in series with the first switch; and a second diode (DQU2) connected in anti-parallel with the second switch, The program causes the control device to perform processing of alternately implementing an H-level mode, an M-level mode, and an L-level mode, where the H-level mode is a switching mode in which the upper-arm switch is turned on and the lower-arm switch is turned off to output a voltage of the H level, the M-level mode is a switching mode in which the first and second switches are turned on and the upper and lower-arm switches are turned off to output a voltage of the M level, and the L-level mode is a switching mode in which the lower-arm switch is turned on and the upper-arm switch is turned off to output a voltage of the L level, When switching from the L-level mode to the H-level mode, the program causes the control device to perform oscillation suppression control in which the M-level mode is interposed between the L-level mode and the H-level mode.

[0092] Although the present disclosure has been described based on the embodiments, it should be understood that the present disclosure is not limited to the above embodiments and structures. The present disclosure also includes various modifications and modifications within the equivalent range. In addition, various combinations, manners, and further combinations and manners including only one element, more than one, or less than one of them also belong to the scope and ideological range of the present disclosure.

Claims

1. A three-level inverter (30), wherein the three-level inverter includes, in each phase, a series connection body of a plurality of upper-arm switches and lower-arm switches (SUH1 to SWL2), and in each phase, the series connection bodies are connected in parallel, and the three-level inverter includes: Upper-arm diodes (DUH1 to DWH2) reversely connected in parallel with the respective upper-arm switches; Lower-arm diodes (DUL1 to DWL2) reversely connected in parallel with the respective lower-arm switches; Intermediate switches (SQU1 to SQW2) provided corresponding to each phase; High-potential-side conductive members (72) provided corresponding to each phase and electrically connecting the high-potential-side terminals of the respective upper-arm switches to the positive-side bus bar (31); Low-potential-side conductive members (71) provided corresponding to each phase and electrically connecting the low-potential-side terminals of the respective lower-arm switches to the negative-side bus bar (32); and An intermediate conductive member (70) provided corresponding to each phase and electrically connecting the low-potential-side terminals of the respective upper-arm switches and the high-potential-side terminals of the respective lower-arm switches to the first end of the intermediate switch, Each upper-arm path is an electrical path from the connection portion (72c) connected to the positive-side bus bar in the high-potential-side conductive member via the upper-arm diode and the intermediate conductive member to the intermediate switch, and is configured such that the impedances of the upper-arm paths corresponding to the respective upper-arm diodes are equal, Each lower-arm path is an electrical path from the connection portion connected to the negative-side bus bar in the low-potential-side conductive member via the lower-arm diode and the intermediate conductive member to the intermediate switch, and is configured such that the impedances of the lower-arm paths corresponding to the respective lower-arm diodes are equal.

2. The three-level inverter according to claim 1, wherein For each series connection body of the upper-arm switches and the lower-arm switches, the series connection body, the upper-arm diodes reversely connected in parallel with the upper-arm switches included in the series connection body, and the lower-arm diodes reversely connected in parallel with the lower-arm switches included in the series connection body are housed in a housing (60) and integrated, thereby forming upper-arm modules and lower-arm modules (M1, M2).

3. The three-level inverter according to claim 2, wherein The intermediate switch has: a first switch (SQU1); a first diode (DQU1) reversely connected in parallel with the first switch; a second switch (SQU2) connected in series with the first switch; and a second diode (DQU2) reversely connected in parallel with the second switch, The first switch, the first diode, the second switch, and the second diode are housed in a housing (60) and integrated, thereby forming an intermediate module (MM).

4. The three-level inverter according to claim 3, wherein In each phase, two series connection bodies of the upper-arm switches and the lower-arm switches are included, The housings of the respective upper-arm modules, lower-arm modules, and the intermediate module are formed in a flat rectangular parallelepiped shape, The respective upper-arm modules and lower-arm modules are modules of the same specification, In each phase, each of the upper arm modules, lower arm modules, and the intermediate module are arranged and configured in the thickness direction of the housing. In each phase, the intermediate module is configured in a state of being sandwiched by the upper arm modules and the lower arm modules. In each phase, the terminal setting surfaces (62) of the housing of each of the upper arm modules, lower arm modules, and the intermediate module face a common specific direction. On the terminal setting surfaces of each of the upper arm modules and lower arm modules, there are provided: a high-potential side external terminal (CP) electrically connected to the high-potential side terminal of the upper arm switch; a low-potential side external terminal (CN) electrically connected to the low-potential side terminal of the lower arm switch; and an intermediate external terminal (CO) electrically connected to the low-potential side terminal of the upper arm switch and the high-potential side terminal of the lower arm switch. An intermediate terminal (CM2) electrically connected to one end of the second switch is provided in the intermediate module. In each phase, the intermediate external terminals of each of the upper arm modules and lower arm modules and the intermediate terminal of the intermediate module are arranged and configured in the thickness direction of the housing. In each phase, the high-potential side external terminals of each of the upper arm modules and lower arm modules are arranged and configured in the thickness direction of the housing. In each phase, the low-potential side external terminals of each of the upper arm modules and lower arm modules are arranged and configured in the thickness direction of the housing. The high-potential side conductive member is electrically connected to the high-potential side external terminals of each of the upper arm modules and lower arm modules. The low-potential side conductive member is electrically connected to the low-potential side external terminals of each of the upper arm modules and lower arm modules. The intermediate conductive member electrically connects the intermediate external terminals of each of the upper arm modules and lower arm modules to the intermediate terminal of the intermediate module. When viewed from the front in the terminal setting surface, the high-potential side conductive member, the low-potential side conductive member, and the intermediate conductive member are formed in a shape symmetrical with respect to a reference axis (BL), and the reference axis passes through the central portion in the thickness direction of the housing of the intermediate module.

5. The three-level inverter according to any one of claims 1 to 4, characterized in that The intermediate switch has: a first switch (SQU1); a first diode (DQU1) connected in anti-parallel with the first switch; a second switch (SQU2) connected in series with the first switch; and a second diode (DQU2) connected in anti-parallel with the second switch. The three-level inverter includes a control device (50), and the control device alternately implements an H-level mode, an M-level mode, and an L-level mode. Among them, the H-level mode is a switching mode in which the upper arm switch is turned on and the lower arm switch is turned off to output a voltage of the H level, the M-level mode is a switching mode in which the first switch and the second switch are turned on and the upper arm switch and the lower arm switch are turned off to output a voltage of the M level, and the L-level mode is a switching mode in which the lower arm switch is turned on and the upper arm switch is turned off to output a voltage of the L level. When the control device switches from the L-level mode to the H-level mode, oscillation suppression control is performed to make the M-level mode lie between the L-level mode and the H-level mode.

6. The three-level inverter according to claim 5, characterized in that The oscillation suppression control is a control that prohibits the execution of the H-L dead time mode and switches from the L-level mode via the M-level mode and the H-M dead time mode to the H-level mode, where the H-L dead time mode is a switching mode in which the upper arm switch, the lower arm switch, and the intermediate switch are turned off. The H-M dead time control is a switching mode in which the upper arm switch, the lower arm switch, and the second switch are turned off and the first switch is turned on. The execution period of the H-M dead time control is set to a period longer than the reverse recovery time of the upper arm diode and the lower arm diode.

7. The three-level inverter according to claim 5, characterized in that The control device executes the oscillation suppression control on the condition that a specific condition is satisfied. The specific condition is any one of the following conditions: The magnitude of the output current of the three-level inverter exceeds a threshold current (Ith); The magnitude of the command torque of the rotating machine electrically connected to the three-level inverter exceeds a torque threshold (Trqth); The difference in the magnitudes of the currents flowing between the high-potential side terminal and the low-potential side terminal of each of the upper arm switches connected in parallel exceeds a specified current difference (Iα); or The difference in the magnitudes of the currents flowing between the high-potential side terminal and the low-potential side terminal of each of the lower arm switches connected in parallel exceeds a specified current difference (Iα).

8. The three-level inverter according to any one of claims 1 to 4, characterized in that, Comprising: A first capacitor (21) that electrically connects the second end of the intermediate switch in each phase to the positive side bus; And A second capacitor (22) that electrically connects the second end of the intermediate switch in each phase to the negative side bus.

9. A three-level inverter, the three-level inverter (30) includes a series connection body of a plurality of upper arm switches and lower arm switches (SUH1 to SWL2) in each phase, and each of the series connection bodies is connected in parallel in each phase. The three-level inverter includes: Upper arm diodes (DUH1 to DWH2) reversely connected in parallel with each of the upper arm switches; Lower arm diodes (DUL1 to DWL2) reversely connected in parallel with each of the lower arm switches; Intermediate switches (SQU1 to SQW2) provided corresponding to each phase; High-potential side conductive members (72) provided corresponding to each phase and electrically connecting the high-potential side terminals of each of the upper arm switches to the positive side bus (31); Low-potential side conductive members (71) provided corresponding to each phase and electrically connecting the low-potential side terminals of each of the lower arm switches to the negative side bus (32); An intermediate conductive member (70) provided corresponding to each phase and electrically connecting the low-potential side terminals of each of the upper arm switches and the high-potential side terminals of each of the lower arm switches to the first end of the intermediate switch; and A control device (50) The intermediate switch has: a first switch (SQU1); a first diode (DQU1) connected in anti-parallel with the first switch; a second switch (SQU2) connected in series with the first switch; and a second diode (DQU2) connected in anti-parallel with the second switch. The control device alternately implements an H-level mode, an M-level mode, and an L-level mode. Among them, the H-level mode is a switching mode in which the upper-arm switch is turned on and the lower-arm switch is turned off to output a voltage of the H level. The M-level mode is a switching mode in which the first switch and the second switch are turned on and the upper-arm switch and the lower-arm switch are turned off to output a voltage of the M level. The L-level mode is a switching mode in which the lower-arm switch is turned on and the upper-arm switch is turned off to output a voltage of the L level. When the control device switches from the L-level mode to the H-level mode, it performs oscillation suppression control that makes the M-level mode lie between the L-level mode and the H-level mode.

10. A program, which is applied to a three-level inverter (30). The three-level inverter includes, in each phase, a series connection body of a plurality of upper-arm switches and lower-arm switches (SUH1 to SWL2), and in each phase, the series connection bodies are connected in parallel. The three-level inverter includes: Upper-arm diodes (DUH1 to DWH2) connected in anti-parallel with the respective upper-arm switches; Lower-arm diodes (DUL1 to DWL2) connected in anti-parallel with the respective lower-arm switches; Intermediate switches (SQU1 to SQW2) provided corresponding to each phase; High-potential-side conductive members (72) provided corresponding to each phase and electrically connecting the high-potential-side terminals of the respective upper-arm switches to the positive-side bus bar (31); Low-potential-side conductive members (71) provided corresponding to each phase and electrically connecting the low-potential-side terminals of the respective lower-arm switches to the negative-side bus bar (32); An intermediate conductive member (70), which is provided corresponding to each phase and electrically connects the low-potential-side terminals of the respective upper-arm switches and the high-potential-side terminals of the respective lower-arm switches to the first end of the intermediate switch; and A control device (50), The intermediate switch has: a first switch (SQU1); a first diode (DQU1) connected in anti-parallel with the first switch; a second switch (SQU2) connected in series with the first switch; and a second diode (DQU2) connected in anti-parallel with the second switch. The program causes the control device to execute a process of alternately implementing an H-level mode, an M-level mode, and an L-level mode. Among them, the H-level mode is a switching mode in which the upper-arm switch is turned on and the lower-arm switch is turned off to output a voltage of the H level. The M-level mode is a switching mode in which the first switch and the second switch are turned on and the upper-arm switch and the lower-arm switch are turned off to output a voltage of the M level. The L-level mode is a switching mode in which the lower-arm switch is turned on and the upper-arm switch is turned off to output a voltage of the L level. In the case of switching from the L-level mode to the H-level mode, the program causes the control device to perform oscillation suppression control that makes the M-level mode lie between the L-level mode and the H-level mode.

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