Temperature compensation circuit for logarithmic detector and logarithmic detector

Abstract

The invention belongs to the technical field of integrated circuit signal processing, and discloses a temperature compensation circuit for a logarithmic detector and the logarithmic detector thereof, and the temperature compensation circuit for the logarithmic detector comprises a first temperature compensation module, a second temperature compensation module and a third temperature compensation module. The first temperature compensation module is used for performing temperature compensation on the current summation module, the second temperature compensation module is used for performing temperature compensation on bias voltage and current of the limiting amplifier module, and the third temperature compensation module is used for performing temperature compensation on bias voltage and current of the rectifier module. The logarithmic detector temperature compensation circuit is suitable for performing temperature compensation on the current summation module, the limiting amplifier module and the rectifier module of the logarithmic detector, and the output precision and consistency of the logarithmic detector are improved.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuit signal processing and relates to a temperature compensation circuit for a logarithmic detector and the logarithmic detector. Background Art

[0002] A logarithmic detector is a key component that converts the logarithm of an RF power signal to a baseband signal. It is widely used in fields such as automatic gain control and pulse detection. Ideally, the output voltage of a logarithmic detector varies linearly with the input signal amplitude or power, and can be quantified as a slope and an intercept. However, in practice, when the input signal amplitude remains constant, temperature changes can cause the intercept of the linear voltage to drift. Therefore, temperature compensation is necessary to ensure the output accuracy and consistency of the logarithmic detector under different temperature conditions.

[0003] The temperature compensation method in the prior art is usually to use Figure 1 The first temperature compensation module shown uses positive and negative temperature currents to perform temperature compensation on the current summing module, but only compensates the current summing module, ignoring the temperature characteristics of the remaining modules of the logarithmic detector. Moreover, the effect of temperature compensation only in the current summing module is limited, and the temperature compensation is not efficient. Summary of the Invention

[0004] The purpose of the present invention is to provide a temperature compensation circuit for a logarithmic detector. By introducing first to third temperature compensation modules, temperature compensation is performed on the current summing module, rectifier module, and limiting amplifier module of the logarithmic detector, thereby reducing the deviation of the logarithmic detector output under different temperature conditions.

[0005] Another object of the present invention is to provide a logarithmic detector that improves output accuracy and consistency by introducing an effective temperature compensation circuit.

[0006] In order to achieve the above-mentioned purpose, the present invention adopts the following technical solutions:

[0007] A temperature compensation circuit for a logarithmic detector includes a first temperature compensation module, the output end of the first temperature compensation module is connected to the input end of a current summing module in the logarithmic detector, and is used to perform temperature compensation on the current summing module. The circuit also includes a second temperature compensation module and a third temperature compensation module.

[0008] The first output end of the second temperature compensation module is connected to the first input end of the limiting amplifier bias module in the logarithmic detector, and the second output end of the second temperature compensation module is connected to the second input end of the limiting amplifier bias module. The second temperature compensation module is used to perform temperature compensation on the bias voltage and current of the limiting amplifier module in the logarithmic detector;

[0009] The output end of the third temperature compensation module is connected to the input end of the rectifier bias module, and is used to perform temperature compensation on the bias voltage and current of the rectifier module in the logarithmic detector.

[0010] As a limitation, the second temperature compensation module includes a fourth resistor, a fifth resistor, a sixth resistor, a sixth transistor, a seventh transistor and an eighth transistor;

[0011] The emitter of the sixth transistor is connected to the input current, the base and collector of the sixth transistor are connected and then respectively connected to one end of the fourth resistor, one end of the fifth resistor and one end of the sixth resistor, and the other end of the fourth resistor is grounded; the other end of the fifth resistor is connected to the base of the seventh transistor, the emitter of the seventh transistor is grounded, and the collector of the seventh transistor is connected to the first input end of the limiting amplifier bias module as the first output end of the second temperature compensation module; the other end of the sixth resistor is connected to the base of the eighth transistor, the emitter of the eighth transistor is grounded, and the collector of the eighth transistor is connected to the second input end of the limiting amplifier bias module as the second output end of the second temperature compensation module.

[0012] As a second limitation, the third temperature compensation module includes a tenth resistor, an eleventh resistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor and a first MOS tube, and also includes a plurality of second MOS tubes having the same number as the rectifiers in the rectifier module of the logarithmic detector;

[0013] One end of the tenth resistor is grounded and connected to the emitter of the seventeenth transistor, the other end of the tenth resistor is connected to the emitter of the fifteenth transistor, the base of the fifteenth transistor is respectively connected to the collector of the seventeenth transistor and the emitter of the sixteenth transistor, and the collector of the fifteenth transistor is respectively connected to the emitter of the fourteenth transistor and the base of the seventeenth transistor; the base of the fourteenth transistor is respectively connected to the base of the sixteenth transistor, one end of the eleventh resistor and the collector of the sixteenth transistor, the collector of the fourteenth transistor is respectively connected to the drain of the first MOSFET, the gate of the first MOSFET and the gate of each second MOSFET, the other end of the eleventh resistor, the source of the first MOSFET and the source of each second MOSFET are all connected to the power supply end, and the drain of each second MOSFET is respectively connected to the input end of the rectifier bias module as the output end of the third temperature compensation module.

[0014] The present invention also provides a logarithmic detector, comprising: a limiting amplifier module, a rectifier module, a current summing module, a DC offset elimination module, a reference module, a bias module, a voltage-to-current module, a current-to-voltage module, and the temperature compensation circuit for the logarithmic detector;

[0015] A limiting amplifier module, comprising N stages of limiting amplifiers, wherein the N stages of limiting amplifiers are cascaded in sequence, wherein an input end of a first stage limiting amplifier is connected to an input end of a radio frequency signal, wherein N is a natural number not less than 1, and the limiting amplifier module is configured to perform limiting amplification on an input signal;

[0016] A rectifier module, comprising N+1 rectifiers, wherein the input end of the first-stage limiting amplifier is connected to a rectifier, and the output end of each stage of the limiting amplifier is connected to a rectifier, and the rectifier module is used to convert the input signal of the limiting amplifier module into a detection current;

[0017] a current summing module connected to the output end of each rectifier in the rectifier module, and configured to sum the detection current of the rectifier module to the filter capacitor;

[0018] The current-to-voltage module is used to convert the detection current from the current summing module to the filter capacitor into a voltage output;

[0019] The voltage-to-current module is used to convert the input voltage into current to achieve a closed feedback loop;

[0020] A DC offset elimination module, connected between the input end of the first-stage limiting amplifier and the output end of the N-stage limiting amplifier, for reducing the DC deviation generated after passing through the limiting amplifier module;

[0021] A reference module, used to generate a reference and provide it to the bias module;

[0022] The bias module includes a limiting amplifier bias module and a rectifier bias module. The limiting amplifier bias module is used to provide a stable bias voltage and current for the limiting amplifier module; the rectifier bias module is used to provide a stable bias voltage and current for the rectifier module.

[0023] As a limitation, the limiting amplifier bias module includes a seventh resistor, an eighth resistor, a ninth resistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor;

[0024] The emitter of the ninth transistor is connected to the power supply terminal, the base of the ninth transistor is connected to the first bias voltage, the collector of the ninth transistor is connected to the emitter of the tenth transistor via the seventh resistor, the base of the tenth transistor is connected to the second bias voltage, the collector of the tenth transistor is connected to the collector of the eleventh transistor and the base of the twelfth transistor respectively, and then serves as the first input terminal of the limiting amplifier bias module and is connected to the first output terminal of the second temperature compensation module, the base of the eleventh transistor is connected to the third bias voltage and the base of the thirteenth transistor respectively, and the emitter of the eleventh transistor is grounded; the collector of the twelfth transistor is connected to the power supply terminal, the emitter of the twelfth transistor is connected to one end of the eighth resistor and one end of the ninth resistor respectively, and then serves as the output terminal of the limiting amplifier bias module and is connected to the input terminal of the limiting amplifier module; the other end of the eighth resistor is connected to the collector of the thirteenth transistor, and the emitter of the thirteenth transistor is grounded; the other end of the ninth resistor is connected to the second input terminal of the limiting amplifier bias module and is connected to the second output terminal of the second temperature compensation module.

[0025] As a second limitation, the rectifier bias module includes a plurality of rectifier bias circuits equal in number to the number of rectifiers in the rectifier module;

[0026] Each rectifier bias circuit includes a twelfth resistor and an eighteenth transistor, the emitter of the eighteenth transistor is connected to one end of the twelfth resistor, and the other end of the twelfth resistor is grounded; the bases of the eighteenth transistors in each rectifier bias circuit are connected together and connected to a fourth bias voltage, the collector of each eighteenth transistor is respectively connected to the drain of the corresponding second MOS tube in the third temperature compensation module, and the collectors of the eighteenth transistors are respectively connected as output terminals to the bias input terminals of the corresponding rectifiers.

[0027] Due to the adoption of the above technical solution, the present invention has achieved the following technical advancements compared with the prior art:

[0028] (1) The temperature compensation circuit for the logarithmic detector of the present invention includes a first temperature compensation module, a second temperature compensation module, and a third temperature compensation module, wherein the first temperature compensation module is used to perform temperature compensation on the current summing module, the second temperature compensation module is used to perform temperature compensation on the bias voltage and current of the limiting amplifier module, and the third temperature compensation module is used to perform temperature compensation on the bias voltage and current of the rectifier module. By adopting three independently adjustable temperature compensation modules, the compensation effects of different modules can be adjusted according to different situations to achieve better compensation results for the overall circuit.

[0029] (2) The second temperature compensation circuit of the present invention adopts a multi-stage transistor structure to generate a stable temperature compensation current, providing a temperature compensation basis for the limiting amplifier module;

[0030] (3) The third temperature compensation module of the present invention provides a temperature compensation basis for the rectifier module through a current mirror composed of a positive temperature current generating circuit and multiple second MOS tubes;

[0031] (4) The present invention introduces a first temperature compensation module, a second temperature compensation module, and a third temperature compensation module into the logarithmic detector. Compared with the existing logarithmic detector that performs temperature compensation on the circuit summing module alone, the present invention performs temperature compensation on the current summing module, the limiting amplifier module, and the rectifier module respectively, thereby achieving comprehensive temperature compensation for the modules that are easily affected by the logarithmic detector, thereby improving the overall temperature compensation effect and the output accuracy of the logarithmic detector.

[0032] (5) The present invention reduces the deviation of the logarithmic detector output under different temperature conditions by introducing an effective temperature compensation module into the logarithmic detector, thereby improving its output accuracy and consistency and meeting practical applications.

[0033] In summary, the present invention is suitable for performing temperature compensation on the current summing module, the limiting amplifier module, and the rectifier module of a logarithmic detector, thereby improving the output accuracy and consistency of the logarithmic detector. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 Shown is a circuit schematic diagram of a first temperature compensation module in the prior art;

[0035] Figure 2 FIG. 4 is a circuit diagram of the second temperature compensation module in Example 1 of the present invention;

[0036] Figure 3 FIG. 4 is a circuit diagram of the third temperature compensation module in Example 1 of the present invention;

[0037] Figure 4 FIG. 2 is a circuit diagram of a logarithmic detector according to a second embodiment of the present invention;

[0038] Figure 5 FIG. 2 is a circuit diagram of a current summing module in Embodiment 2 of the present invention;

[0039] Figure 6 FIG2 is a circuit schematic diagram of a second temperature compensation module and a limiting amplifier bias module in Embodiment 2 of the present invention;

[0040] Figure 7 FIG2 is a circuit schematic diagram of the third temperature compensation module and the rectifier bias module in Example 2 of the present invention;

[0041] Figure 8 FIG2 is a circuit diagram of a voltage-to-current module in Example 2 of the present invention;

[0042] Figure 9 FIG2 is a circuit diagram of an external radio frequency signal input circuit in Embodiment 2 of the present invention;

[0043] Figure 10 FIG2 is a circuit schematic diagram of a logarithmic detector using only the first temperature compensation module in Example 2 of the present invention;

[0044] Figure 11 FIG2 is a simulation diagram of a logarithmic detector using only the first temperature compensation module in Example 2 of the present invention;

[0045] Figure 12 FIG2 is a simulation diagram of the logarithmic detector using the first to third temperature compensation modules in Example 2 of the present invention. DETAILED DESCRIPTION

[0046] In order to better explain the present invention and facilitate understanding, the present invention is described in detail below through specific implementation methods in conjunction with the accompanying drawings.

[0047] Example 1 A temperature compensation circuit for a logarithmic detector

[0048] This embodiment provides a temperature compensation circuit for a logarithmic detector, comprising a first temperature compensation module, a second temperature compensation module, and a third temperature compensation module. The output of the first temperature compensation module is connected to the input of a current summing module in the logarithmic detector, for performing temperature compensation on the current summing module and improving the temperature consistency of the logarithmic detector output. The first output of the second temperature compensation module is connected to the first input of a limiting amplifier bias module in the logarithmic detector, and the second output of the second temperature compensation module is connected to the second input of the limiting amplifier bias module. The second temperature compensation module is used to perform temperature compensation on the bias voltage and current of the limiting amplifier module in the logarithmic detector. The output of the third temperature compensation module is connected to the input of the rectifier bias module, for performing temperature compensation on the bias voltage and current of the rectifier module in the logarithmic detector.

[0049] like Figure 1As shown, the first temperature compensation module includes a first resistor R1, a second resistor R2, a third resistor R3, an adjustable resistor RT, a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5 and a first operational amplifier; the first transistor Q1, the second transistor Q2, the third transistor Q3, the fourth transistor Q4, and the fifth transistor Q5 are all NPN transistors. Among them, one end of the adjustable resistor RT is grounded, and the other end of the adjustable resistor RT is respectively connected to one end of the first resistor R1, one end of the second resistor R2 and the positive input end of the first operational amplifier, the other end of the first resistor R1 is connected to the voltage input end Vb, and the other end of the second resistor R2 is grounded; the negative input end of the first operational amplifier is respectively connected to the emitter of the fifth transistor Q5 and one end of the third resistor R3, and the other end of the third resistor R3 is grounded; the output end of the first operational amplifier is connected to the base of the fifth transistor Q5, the collector of the fifth transistor Q5 is respectively connected to the emitter of the first transistor Q1 and the emitter of the second transistor Q2, the base of the first transistor Q1 is connected to the emitter of the third transistor Q3 and then connected to the input current Ib, the collector of the first transistor Q1 serves as the first output end Iout1 of the first temperature compensation module and is connected to the first input end ISETO of the current summing module in the logarithmic detector; the base of the second transistor Q2 is connected to the emitter of the fourth transistor Q4 and then connected to the input current I ptat The collector of the second transistor Q2 is connected as the second output terminal Iout2 of the first temperature compensation module and is connected to the second input terminal IDET of the current summing module in the logarithmic detector; the base of the third transistor Q3, the collector of the third transistor Q3, the base of the fourth transistor Q4 and the collector of the fourth transistor Q4 are respectively connected to the power supply terminal VDD.

[0050] like Figure 2 As shown, the second temperature compensation module includes a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a sixth transistor Q6, a seventh transistor Q7 and an eighth transistor Q8; the sixth transistor Q6 is a PNP transistor, and the seventh transistor Q7 and the eighth transistor Q8 are NPN transistors. The emitter of the sixth transistor Q6 is connected to the input current I PTAT The base and collector of the sixth transistor Q6 are connected to one end of the fourth resistor R4, one end of the fifth resistor R5, and one end of the sixth resistor R6, respectively. The other end of the fourth resistor R4 is grounded. The other end of the fifth resistor R5 is connected to the base of the seventh transistor Q7. The emitter of the seventh transistor Q7 is grounded. The collector of the seventh transistor Q7 serves as the first output terminal I of the second temperature compensation module. OUT1The other end of the sixth resistor R6 is connected to the base of the eighth transistor Q8, the emitter of the eighth transistor Q8 is grounded, and the collector of the eighth transistor Q8 serves as the second output terminal I of the second temperature compensation module. OUT2 Connected to the second input terminal of the limiting amplifier bias module.

[0051] like Figure 3 As shown, the third temperature compensation module includes a tenth resistor R10, an eleventh resistor R11, a fourteenth transistor Q14, a fifteenth transistor Q15, a sixteenth transistor Q16, a seventeenth transistor Q17 and a first MOSFET M1, and also includes a plurality of second MOSFETs M2, the same number as the rectifiers in the rectifier module of the logarithmic detector; wherein the fifteenth transistor Q15, the sixteenth transistor Q16, and the seventeenth transistor Q17 are all NPN transistors. One end of the tenth resistor R10 is grounded and connected to the emitter of the seventeenth transistor Q17, the other end of the tenth resistor R10 is connected to the emitter of the fifteenth transistor Q15, the base of the fifteenth transistor Q15 is respectively connected to the collector of the seventeenth transistor Q17 and the emitter of the sixteenth transistor Q16, the collector of the fifteenth transistor Q15 is respectively connected to the emitter of the fourteenth transistor Q14 and the base of the seventeenth transistor Q17; the base of the fourteenth transistor Q14 is respectively connected to the base of the sixteenth transistor Q16, One end of the eleventh resistor R11 is connected to the collector of the sixteenth transistor Q16. The collector of the fourteenth transistor Q14 is respectively connected to the drain of the first MOSFET M1, the gate of the first MOSFET M1, and the gate of each second MOSFET M2. The other end of the eleventh resistor R11, the source of the first MOSFET M1, and the source of each second MOSFET M2 are all connected to the power supply terminal VDD. The drain of each second MOSFET M2 serves as the output end of the third temperature compensation module and is connected to the input end of the rectifier bias module.

[0052] Example 2 A logarithmic detector

[0053] like Figure 4 As shown, this embodiment is a logarithmic detector, including: a limiting amplifier module, a rectifier module, a current summing module Σ, a DC offset cancellation module DC_OC, a reference module VREF, a bias module BIAS, a voltage-to-current module VI, a current-to-voltage module IV and the temperature compensation circuit for the logarithmic detector of Example 1.

[0054] The limiting amplifier module includes N-stage limiting amplifiers, which are cascaded in sequence. The input end of the first stage limiting amplifier is connected to the RF signal input end V IP 、V IN Connection, N is a natural number not less than 1, and the limiting amplifier module is used to perform limiting amplification on the input signal. Figure 4 In the figure, N=6, including six stages of limiting amplifiers, marked as LA1 to LA6.

[0055] The rectifier module includes N+1 rectifiers. The input end of the first-stage limiting amplifier is connected to a rectifier, and the output end of each stage of the limiting amplifier is connected to a rectifier. The rectifier module is used to convert the input signal of the limiting amplifier module into a detection current. Figure 4 The rectifier includes seven rectifiers, which are marked as DET1 to DET7 in the figure.

[0056] The current summing module Σ is connected to the output end of each rectifier in the rectifier module, and is used to sum the detection current of the rectifier module to the filter capacitor.

[0057] The current-to-voltage module IV is used to convert the detection current from the current summing module Σ to the filter capacitor into a voltage V O Output.

[0058] The voltage-to-current module VI is used to convert the input voltage Vs into current to implement a feedback closed loop.

[0059] The DC offset elimination module DC_OC is connected between the input end of the first-stage limiting amplifier and the output end of the N-stage limiting amplifier, and is used to reduce the DC deviation generated after passing through the limiting amplifier module.

[0060] The reference module VREF is used to generate a reference to provide to the bias module BIAS.

[0061] The bias module BIAS includes a limiting amplifier bias module and a rectifier bias module. The limiting amplifier bias module is used to provide a stable bias voltage and current for the limiting amplifier module; the rectifier bias module is used to provide a stable bias voltage and current for the rectifier module.

[0062] A temperature compensation circuit for a logarithmic detector includes a first temperature compensation module TEMPCOMP1, a second temperature compensation module TEMP COMP2, and a third temperature compensation module TEMP COMP3. The first temperature compensation module TEMP COMP1 is used to perform temperature compensation on a current summing module Σ. The second temperature compensation module TEMP COMP2 is used to perform temperature compensation on a bias voltage and current of a limiting amplifier module. The third temperature compensation module TEMPCOMP3 is used to perform temperature compensation on a bias voltage and current of a rectifier module.

[0063] like Figure 5The figure shows a circuit schematic diagram of the current summing module Σ, in which the first input terminal ISETO of the current summing module Σ is connected to the collector of the first transistor Q1 in the first temperature compensation module TEMPCOMP1, that is, the first output terminal Iout1; the second input terminal IDET of the current summing module Σ is connected to the collector of the second transistor Q2, that is, the second output terminal Iout2; in addition, the ISET terminal of the current summing module Σ is connected to the output terminal of the voltage-to-current module VI; the IDET terminal of the current summing module Σ is also connected to the output terminal of each rectifier; the output terminal of the current summing module Σ is the CLPF terminal, which is externally connected to a filter capacitor and then connected to the current-to-voltage module IV.

[0064] Specifically, through Figure 1 The operating principle of the first temperature compensation module TEMPCOMP1 when performing temperature compensation on the current summing module Σ is as follows: the adjustable resistor RT, the first resistor R1, and the second resistor R2 in the circuit form a voltage divider circuit. Adjusting the resistance value of the adjustable resistor RT can change the resistance value of the adjustable resistor RT and the second resistor R2 in parallel, thereby changing the voltage divided by the first resistor R1. Due to the presence of the first operational amplifier, the voltage on the third resistor R3 also changes with the change of the voltage divider circuit, thereby changing the current flowing through the third resistor R3. The first temperature compensation module TEMPCOMP1 has two input currents Ib and Iptat, and the input currents Ib and Iptat have different temperature coefficients. There are two outputs, including a first output terminal Iout1 and a second output terminal Iout2. The first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 are BJT transistors of the same size. Since the temperature coefficients of the input currents Ib and Iptatt are different and the third transistor Q3 and the fourth transistor Q4 are the same, the base current temperatures of the first transistor Q1 and the second transistor Q2 are also different. Through the circuit design of the first temperature compensation module TEMPCOMP1, the output currents of the first transistor Q1 and the second transistor Q2 have two temperature coefficients, the first output terminal Iout1 has a positive temperature coefficient, and the second output terminal Iout2 has a negative temperature coefficient. The first output terminal Iout1 is connected to the ISETO terminal of the current summing module Σ circuit, and the second output terminal Iout2 is connected to the IDET terminal of the current summing module Σ circuit. The current summing module Σ is temperature compensated via the first output terminal Iout1 and the second output terminal Iout2.

[0065] like Figure 6As shown, the limiting amplifier bias module includes a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a ninth transistor Q9, a tenth transistor Q10, an eleventh transistor Q11, a twelfth transistor Q12, and a thirteenth transistor Q13; the emitter of the ninth transistor Q9 is connected to the power supply terminal VDD, the base of the ninth transistor Q9 is connected to the first bias voltage Vb1, the collector of the ninth transistor Q9 is connected to the emitter of the tenth transistor Q10 through the seventh resistor R7, the base of the tenth transistor Q10 is connected to the second bias voltage Vb2, and the collector of the tenth transistor Q10 is connected to the collector of the eleventh transistor Q11 and the base of the twelfth transistor Q12, respectively, to serve as the first input terminal of the limiting amplifier bias module and the first output terminal I of the second temperature compensation module TEMPCOMP2. OUT1 The base of the eleventh transistor Q11 is connected to the third bias voltage Vb3 and the base of the thirteenth transistor Q13 respectively, and the emitter of the eleventh transistor Q11 is grounded; the collector of the twelfth transistor Q12 is connected to the power supply terminal VDD, and the emitter of the twelfth transistor Q12 is connected to one end of the eighth resistor R8 and one end of the ninth resistor R9 respectively, and then connected as the output terminal VB_LA of the limiting amplifier bias module to the input terminal of the limiting amplifier module, that is, connected to the base of the tail current transistor in each limiting amplifier in the limiting amplifier module; the other end of the eighth resistor R8 is connected to the collector of the thirteenth transistor Q13, and the emitter of the thirteenth transistor Q13 is grounded; the other end of the ninth resistor R9 serves as the second input terminal of the limiting amplifier bias module and is connected to the second output terminal I of the second temperature compensation module TEMPCOMP2. OUT2 connect.

[0066] Specifically, the working principle of the temperature compensation performed by the second temperature compensation module TEMPCOMP2 on the limiting amplifier module through the limiting amplifier bias module is as follows: there is an input current I in the circuit of the second temperature compensation module TEMPCOMP2. PTAT There are two output currents including the first output terminal I OUT1 and the second output terminal I OUT2 When the temperature is low, the input current I PTAT The voltage on the fourth resistor R4 is relatively low, and the seventh transistor Q7 and the eighth transistor Q8 are in the off state. As the temperature gradually increases, the input current I PTAT The voltage on the fourth resistor R4 increases gradually, the seventh transistor Q7 and the eighth transistor Q8 are turned on, and the first output terminal I OUT1 and the second output terminal I OUT2 Both channels are open, the first output terminal I OUT1 The base of the twelfth transistor Q12 in the limiting amplifier bias module circuit is compensated, and the second output terminal I OUT2One end of the ninth resistor R9 is connected, and the other end of the ninth resistor R9 is connected to the emitter of the twelfth transistor Q12 for compensation, so as to realize bias compensation of the limiting amplifier module. By setting the second temperature compensation module TEMPCOMP2, the output of the limiting amplifier module is adjusted, thereby adjusting the output of the subsequent rectifier module, the current summing module Σ and the current-to-voltage module IV, so as to achieve the purpose of temperature compensation.

[0067] The rectifier bias module includes a plurality of rectifier bias circuits having the same number as the rectifiers in the rectifier module; each rectifier bias circuit includes a twelfth resistor R12 and an eighteenth transistor Q18, the emitter of the eighteenth transistor Q18 is connected to one end of the twelfth resistor R12, and the other end of the twelfth resistor R12 is grounded; the bases of the eighteenth transistors Q18 in each rectifier bias circuit are connected together and to the fourth bias voltage Vb4, and the collectors of each eighteenth transistor Q18 are connected to the fourth bias voltage Vb4. Figure 3 The drain of the corresponding second MOS tube M2 in the third temperature compensation module TEMP COMP3 is connected, and the collector of the eighteenth transistor Q18 is connected to the bias input terminal of the corresponding rectifier as an output terminal.

[0068] like Figure 7 As shown, when the number of rectifiers in the rectifier module is seven, the rectifier bias module includes seven rectifier bias circuits, the third temperature compensation module TEMPCOMP3 includes seven second MOS tubes M2, and the collector of the eighteenth transistor Q18 in the rectifier bias circuit is connected to the rectifier and the second MOS tube M2 in a one-to-one correspondence.

[0069] by Figure 7 For example, when the third temperature compensation module TEMPCOMP3 performs temperature compensation on the bias voltage and current of the rectifier module, the fourteenth transistor Q14, the fifteenth transistor Q15, the sixteenth transistor Q16, the seventeenth transistor Q17, the tenth resistor R10 and the eleventh resistor R11 in the third temperature compensation module TEMPCOMP3 circuit are positive temperature current generating circuits, and the plurality of second MOSFETs M2 are current mirrors for copying the positive temperature current generated by the positive temperature current generating circuit. The copied current is subtracted from the current generated by the eighteenth transistor Q18 in each rectifier bias circuit, and the resulting currents are respectively output through the output terminals NIBO and NIBO. <0> ~NIBO <6> Output, output terminal NIBO <0> ~NIBO <6> After compensation, the current is provided to the seven rectifiers in the rectifier module, and then reaches the voltage output end through the current summing module Σ and the current-to-voltage module IV, thereby achieving the purpose of temperature compensation.

[0070] like Figure 8, which is a circuit schematic diagram of the voltage-to-current module VI, including a second operational amplifier, a twenty-third resistor R23, and a twenty-ninth transistor Q29; the positive input terminal of the second operational amplifier is connected to the input voltage Vs, the negative input terminal of the second operational amplifier is connected to one end of the twenty-third resistor R23 and the emitter of the twenty-ninth transistor Q29, respectively, the other end of the twenty-third resistor R23 is grounded, the output terminal of the second operational amplifier is connected to the base of the twenty-ninth transistor Q29, and the collector of the twenty-ninth transistor Q29 is connected to the ISET terminal of the current summing module Σ.

[0071] The voltage-to-current module VI is a structure similar to a linear regulator. The voltages at the two input terminals of the second operational amplifier are equal, that is, the voltage across the twenty-third resistor R23 is Vs. The collector of the twenty-ninth transistor Q29 outputs ISET=VS / R29 to the ISET terminal of the current summing module Σ.

[0072] The working principle of the logarithmic detector of this embodiment is:

[0073] The current summing module Σ is temperature compensated by the first temperature compensation module TEMPCOMP1, the bias voltage and current of the limiting amplifier module are temperature compensated by the second temperature compensation module TEMPCOMP2, and the bias voltage and current of the rectifier module are temperature compensated by the third temperature compensation module TEMPCOMP3.

[0074] The RF signal passes through Figure 9 The external RF signal input circuit shown is input to the RF input port V IP and V IN The RF signal is amplified by the six-stage limiting amplifiers LA1~LA6 in sequence, and then the input signal of the limiting amplifier is converted into a detection current through the rectifiers DET1~DET7. The output ends of the rectifiers are all connected to the IDET end of the current summing module Σ. The current summing module Σ aggregates the detection current of the rectifier module to the filter capacitor, and then converts the detection current into a voltage V through the current-to-voltage module IV. O Output.

[0075] In order to verify the effect of this embodiment, this embodiment is compared with Figure 10 The logarithmic detector that uses only the first temperature compensation module TEMPCOMP1 to perform temperature compensation on the current summing module Σ is compared. Figure 11 The simulation diagram of the comparative example shown, and Figure 12 The simulation diagram of this embodiment is shown. Figure 11 and Figure 12The simulation results are obtained when the input RF signal frequency is 100MHz, the power is -60dBm~10dBm, and the temperature is -40℃, 25℃ and 105℃. ERROR represents the output error of the logarithmic detector under different temperature conditions. Figure 11 and Figure 12 It can be seen from the figure that except when the input power is -60dBm, the output error of the embodiment is smaller than the output error of the comparative example, indicating that the logarithmic detector of the embodiment has high output accuracy.

[0076] It should be noted that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art may still modify the technical solutions described in the above embodiments or replace some of the technical features therein with equivalents. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A temperature compensation circuit for a logarithmic detector, comprising a first temperature compensation module, wherein an output terminal of the first temperature compensation module is connected to an input terminal of a current summing module in the logarithmic detector, and is used to perform temperature compensation on the current summing module, wherein: Also includes a second temperature compensation module and a third temperature compensation module; The first output end of the second temperature compensation module is connected to the first input end of the limiting amplifier bias module in the logarithmic detector, and the second output end of the second temperature compensation module is connected to the second input end of the limiting amplifier bias module. The second temperature compensation module is used to perform temperature compensation on the bias voltage and current of the limiting amplifier module in the logarithmic detector; The output end of the third temperature compensation module is connected to the input end of the rectifier bias module, and is used to perform temperature compensation on the bias voltage and current of the rectifier module in the logarithmic detector.

2. The temperature compensation circuit for a logarithmic detector according to claim 1, wherein: The second temperature compensation module includes a fourth resistor, a fifth resistor, a sixth resistor, a sixth transistor, a seventh transistor and an eighth transistor; The emitter of the sixth transistor is connected to the input current, the base and collector of the sixth transistor are connected and then respectively connected to one end of the fourth resistor, one end of the fifth resistor and one end of the sixth resistor, and the other end of the fourth resistor is grounded; the other end of the fifth resistor is connected to the base of the seventh transistor, the emitter of the seventh transistor is grounded, and the collector of the seventh transistor is connected to the first input end of the limiting amplifier bias module as the first output end of the second temperature compensation module; the other end of the sixth resistor is connected to the base of the eighth transistor, the emitter of the eighth transistor is grounded, and the collector of the eighth transistor is connected to the second input end of the limiting amplifier bias module as the second output end of the second temperature compensation module.

3. The temperature compensation circuit for a logarithmic detector according to claim 1, wherein: The third temperature compensation module includes a tenth resistor, an eleventh resistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor and a first MOS tube, and also includes a plurality of second MOS tubes having the same number as the rectifiers in the rectifier module of the logarithmic detector; One end of the tenth resistor is grounded and connected to the emitter of the seventeenth transistor, the other end of the tenth resistor is connected to the emitter of the fifteenth transistor, the base of the fifteenth transistor is respectively connected to the collector of the seventeenth transistor and the emitter of the sixteenth transistor, and the collector of the fifteenth transistor is respectively connected to the emitter of the fourteenth transistor and the base of the seventeenth transistor; the base of the fourteenth transistor is respectively connected to the base of the sixteenth transistor, one end of the eleventh resistor and the collector of the sixteenth transistor, the collector of the fourteenth transistor is respectively connected to the drain of the first MOSFET, the gate of the first MOSFET and the gate of each second MOSFET, the other end of the eleventh resistor, the source of the first MOSFET and the source of each second MOSFET are all connected to the power supply end, and the drain of each second MOSFET is respectively connected to the input end of the rectifier bias module as the output end of the third temperature compensation module.

4. A logarithmic detector, characterized in that include: A limiting amplifier module, a rectifier module, a current summing module, a DC offset cancellation module, a reference module, a bias module, a voltage-to-current module, a current-to-voltage module, and a temperature compensation circuit for a logarithmic detector as claimed in any one of claims 1 to 3; A limiting amplifier module, comprising N stages of limiting amplifiers, wherein the N stages of limiting amplifiers are cascaded in sequence, wherein an input end of a first stage limiting amplifier is connected to an input end of a radio frequency signal, wherein N is a natural number not less than 1, and the limiting amplifier module is configured to perform limiting amplification on an input signal; A rectifier module, comprising N+1 rectifiers, wherein the input end of the first-stage limiting amplifier is connected to a rectifier, and the output end of each stage of the limiting amplifier is connected to a rectifier, and the rectifier module is used to convert the input signal of the limiting amplifier module into a detection current; a current summing module connected to the output end of each rectifier in the rectifier module, and configured to sum the detection current of the rectifier module to the filter capacitor; The current-to-voltage module is used to convert the detection current from the current summing module to the filter capacitor into a voltage output; The voltage-to-current module is used to convert the input voltage into current to achieve a closed feedback loop; A DC offset elimination module, connected between the input end of the first-stage limiting amplifier and the output end of the N-stage limiting amplifier, for reducing the DC deviation generated after passing through the limiting amplifier module; A reference module, used to generate a reference and provide it to the bias module; The bias module includes a limiting amplifier bias module and a rectifier bias module. The limiting amplifier bias module is used to provide a stable bias voltage and current for the limiting amplifier module; the rectifier bias module is used to provide a stable bias voltage and current for the rectifier module.

5. The logarithmic detector according to claim 4, characterized in that The limiting amplifier bias module includes a seventh resistor, an eighth resistor, a ninth resistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a thirteenth transistor; The emitter of the ninth transistor is connected to the power supply terminal, the base of the ninth transistor is connected to the first bias voltage, the collector of the ninth transistor is connected to the emitter of the tenth transistor via the seventh resistor, the base of the tenth transistor is connected to the second bias voltage, the collector of the tenth transistor is connected to the collector of the eleventh transistor and the base of the twelfth transistor respectively, and then connected to the first output terminal of the second temperature compensation module as the first input terminal of the limiting amplifier bias module, the base of the eleventh transistor is connected to the third bias voltage and the base of the thirteenth transistor respectively, and the emitter of the eleventh transistor is grounded; the collector of the twelfth transistor is connected to the power supply terminal, the emitter of the twelfth transistor is connected to one end of the eighth resistor and one end of the ninth resistor respectively, and then connected to the input terminal of the limiting amplifier module as the output terminal of the limiting amplifier bias module; The other end of the eighth resistor is connected to the collector of the thirteenth transistor, and the emitter of the thirteenth transistor is grounded; the other end of the ninth resistor is connected to the second output end of the second temperature compensation module as the second input end of the limiting amplifier bias module.

6. The temperature compensation circuit for a logarithmic detector according to claim 4, wherein: The rectifier bias module includes a plurality of rectifier bias circuits having the same number as the rectifiers in the rectifier module; Each rectifier bias circuit includes a twelfth resistor and an eighteenth transistor, the emitter of the eighteenth transistor is connected to one end of the twelfth resistor, and the other end of the twelfth resistor is grounded; the bases of the eighteenth transistors in each rectifier bias circuit are connected together and connected to a fourth bias voltage, the collector of each eighteenth transistor is respectively connected to the drain of the corresponding second MOS tube in the third temperature compensation module, and the collectors of the eighteenth transistors are respectively connected as output terminals to the bias input terminals of the corresponding rectifiers.

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