Semiconductor laser chip structure and manufacturing method thereof

Abstract

The invention relates to the technical field of semiconductor laser manufacturing. The invention particularly relates to a semiconductor laser chip structure and a manufacturing method thereof. The semiconductor laser chip structure manufactured by the manufacturing method provided by the invention comprises a laser chip substrate and a heavily doped table, the length and the width of the heavily doped table are smaller than those of the laser chip substrate; the insulating layer covers the partial width of the heavily doped table close to the edge, the side part of the heavily doped table and the surface of the laser chip substrate at the side part of the heavily doped table; and the ion implantation region is positioned in the heavy doping table with partial thickness below the insulating layer and the laser chip substrate, and defines the strip width of a current injection window of the semiconductor laser chip together with the insulating layer. According to the invention, defects caused by defining a current injection window by using an isolation groove at the edge of a heavily doped table can be overcome.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor laser chips, and more particularly to a semiconductor laser chip structure and a manufacturing method thereof. Background Art

[0002] Semiconductor lasers, due to their compact structure, long life, high reliability, high electro-optical conversion efficiency, fast modulation rate, wide wavelength range, and ease of integration, are widely used in fields including industrial production, LiDAR, military attack and defense, optical communications, optical information storage, and medical aesthetics. With the development and advancement of technology, higher requirements are being placed on the power, efficiency, polarization degree, horizontal far-field divergence angle, and reliability of semiconductor lasers in various application fields.

[0003] Generally speaking, semiconductor laser chip designs use wet etching to remove the heavily doped ohmic contact layer and part of the higher-doped upper confinement layer along the cavity length to form strip-shaped isolation trenches to define the width of the light-emitting surface. However, this approach has the following consequences in subsequent processes: if a COS device is packaged using a P-face-down method, this will affect the degree of polarization (DOP); the thick insulating layer required to define the current injection window will generate significant stress, causing the semiconductor laser chip wafer to warp beyond the threshold; it will hinder lateral heat dissipation from the chip and create reliability risks near the isolation trench area; and the isolation trench itself will affect the far-field horizontal divergence angle. Therefore, a solution is needed to solve the above-mentioned defects caused by using isolation trenches at the edges of heavily doped mesas to define current injection windows. Summary of the Invention

[0004] Therefore, the present application provides a semiconductor laser chip structure and a manufacturing method thereof to solve the above-mentioned defects caused by using isolation trenches at the edges of heavily doped mesas to define current injection windows.

[0005] In one aspect of the present application: the present application provides a semiconductor laser chip structure, the semiconductor laser chip structure comprising: a laser chip substrate, the laser chip substrate comprising: a substrate layer, a buffer layer, a lower confinement layer, a lower waveguide layer, a quantum well active layer, an upper waveguide layer, and a first upper confinement layer stacked in sequence; a heavily doped platform, arranged on the surface of the first upper confinement layer of the laser chip substrate facing away from the substrate layer, comprising a second upper confinement layer and an ohmic contact layer; the length and width of the heavily doped platform are both smaller than the length and width of the laser chip substrate; an insulating layer, covering the width of the heavily doped platform near the edge, the side of the heavily doped platform, and the surface of the laser chip substrate at the side of the heavily doped platform; an ion implantation region, located in the partially thick heavily doped platform and the laser chip substrate below the insulating layer; the ion implantation region and the insulating layer jointly define the stripe width of the current injection window of the semiconductor laser chip.

[0006] The semiconductor laser chip structure provided by the present application is modified by the ion implantation area in the laser chip matrix and the heavily doped platform of the partial thickness located under the insulating layer, and the remaining area not modified by ion implantation is then limited by the insulating layer for a second time, and the remaining exposed area can be used as a current injection window. The unexposed part is blocked by the insulating layer, and the current is difficult to inject directly, and the side of the exposed area is modified by ion implantation, so that the resistance of the area is increased. The current injected through the P-surface electrode on the top surface cannot pass through this ion implantation area because the resistance of the area corresponding to the current injection window is much smaller than that of the ion implantation area, thereby achieving a better current lateral expansion effect, and at the same time, no additional photon loss is caused, thereby achieving the definition of the current injection window and the stripe width. In this way, the isolation trench of the heavily doped platform is avoided for definition, and the various stress problems caused thereby are not generated. Therefore, the related polarization degree, stress, reliability risk, heat dissipation defects caused by defining the current injection window and the stripe width using the isolation trench of the heavily doped platform can be solved, and the influence on the far-field divergence angle can be reduced.

[0007] In some embodiments of the present application, the depth of the ion implantation region does not exceed the upper surface of the quantum well active layer.

[0008] In the semiconductor laser chip structure provided by this application, the depth of the ion implantation region does not exceed the upper surface of the quantum well active layer, so the quantum well active layer is not modified. Since the quantum well active region is the core area of the laser's electro-optical conversion, the solution of this application does not affect the laser's electro-optical conversion capability.

[0009] In some embodiments of the present application, the ion implantation region is located in the ohmic contact layer below the insulating layer, the second upper confinement layer, the first upper confinement layer, and a partial thickness of the upper waveguide layer.

[0010] In some embodiments of the present application, the width of the insulating layer covering the edge of the heavily doped platform is greater than the width of the portion of the ion implantation region located in the heavily doped platform; the depth of the portion of the ion implantation region located in the heavily doped platform is shallower than the depth of the portion of the ion implantation region located in the laser chip substrate.

[0011] In the semiconductor laser chip structure provided by the present application, the ion implantation region is located in the portion of the heavily doped platform, and its width is less than the width of the insulating layer covering the heavily doped platform, and its depth is shallower than the portion of the laser chip substrate in which the ion implantation region is located on the side of the heavily doped platform. This allows the formation of a transition region, where the degree of lattice damage is relatively small, minimizing the adverse effects of this region on photon absorption and scattering, thereby avoiding unnecessary photon scattering and absorption losses at the edge of the strip width, and reducing electro-optical conversion efficiency and potential reliability risks. At the same time, the portion of the laser chip substrate in which the ion implantation region is located on the side of the heavily doped platform, where the implantation depth is deeper, can better isolate the lateral expansion of the current and improve the electro-optical conversion efficiency of the device.

[0012] In some embodiments of the present application, the implanted ions in the ion implantation region are Si ions or H ions.

[0013] In some embodiments of the present application, the material of the insulating layer is SiO2 or SiN x The thickness of the insulating layer is 50nm~100nm; the width of the single side of the insulating layer covering the heavily doped platform is 10μm~25μm; the semiconductor laser chip structure also includes a front electrode layer covering the surface of the current injection window and the surface of the insulating layer, and a back electrode layer covering the surface of the substrate layer facing away from the buffer layer; the material of the front electrode layer includes titanium, platinum, gold or their alloys; the material of the back electrode layer includes gold, germanium, nickel or their alloys.

[0014] In the semiconductor laser chip structure provided by the present application, since isolation trenches at the edges of heavily doped platforms are not used to define current injection windows, the insulating layer does not need to be set to a high thickness. Since increasing the thickness of the insulating layer often introduces more stress, there is a risk of warping the semiconductor wafer during the manufacturing process and possible breakage. The insulating layer thickness of the present application is relatively thin, thereby reducing the stress problem caused by the thickness of the insulating layer and improving the polarization degree of the semiconductor laser chip.

[0015] In another aspect of the present application, the present application also provides a method for manufacturing a semiconductor laser chip structure, comprising the following steps: providing a laser chip substrate epitaxial structure, comprising: a substrate layer, a buffer layer, a lower confinement layer, a lower waveguide layer, a quantum well active layer, an upper waveguide layer, an upper confinement layer and an ohmic contact layer stacked in sequence; etching the laser chip epitaxial layer to form a laser chip base and a heavily doped platform on its surface; wherein the portion of the upper confinement layer located on the laser chip base is a first upper confinement layer, and the portion located on the heavily doped platform is a second upper confinement layer; the laser chip base comprises: a substrate layer, a buffer layer, A lower confinement layer, a lower waveguide layer, a quantum well active layer, an upper waveguide layer, and a first upper confinement layer; the heavily doped platform includes a second upper confinement layer and an ohmic contact layer; the length and width of the heavily doped platform are both smaller than the length and width of the laser chip substrate; an ion implantation region is formed in a portion of the width and thickness of the heavily doped platform near the edge and in a portion of the thickness of the laser chip substrate; an insulating layer is formed on a surface of a portion of the width of the heavily doped platform near the edge, a side surface of the heavily doped platform, and a surface of the laser chip substrate at the side of the heavily doped platform; and the insulating layer and the ion implantation region together define a current injection window of the semiconductor laser chip.

[0016] The manufacturing method of the semiconductor laser chip structure provided by the present application can manufacture the semiconductor laser chip structure provided by the present application, and the laser chip structure is modified by the ion implantation area in the partially thick heavily doped platform and the laser chip matrix under the insulating layer, and the remaining area not ion implanted and modified is then limited by the insulating layer for a second time, and the remaining exposed area can be used as a current injection window. The unexposed part is blocked by the insulating layer, and the current is difficult to inject directly, and the side of the exposed area is modified by ion implantation, so that the resistance of the area is increased, and the current injected through the P-surface electrode on the top surface cannot pass through this ion implantation area, so that a better current lateral expansion effect can be achieved, and at the same time, no additional photon loss is caused, thereby realizing the definition of the current injection window and the stripe width. In this way, the isolation trench of the heavily doped platform is avoided for definition, and the various stress problems caused thereby are not generated. Therefore, the related polarization degree, stress, reliability risk, heat dissipation defects caused by the isolation trench of the heavily doped platform defining the current injection window and the stripe width can be solved, and the influence on the far-field divergence angle can be reduced.

[0017] In some embodiments of the present application, the step of forming an ion implantation area includes: forming an ion implantation protection layer, the ion implantation protection layer covering the surface of the partial width near the edge of the heavily doped platform, the side surface of the heavily doped platform, and the surface of the laser chip substrate on the side of the heavily doped platform; forming a photoresist layer, the photoresist layer covering the ohmic contact layer exposed by the ion implantation protection layer, and covering the partial width of the ion implantation protection layer, and being spaced a distance from the edge of the heavily doped platform; performing ion implantation to form an initial ion implantation area in the partial thickness of the heavily doped platform and the laser chip substrate under the ion implantation protection layer; removing the photoresist layer and the ion implantation protection layer; annealing to repair the ion implantation damage and activate the doped atoms in the initial ion implantation area to the correct lattice position.

[0018] The manufacturing method of the semiconductor laser chip structure provided by the present application first forms a thin ion implantation protection layer and then covers a portion with a photoresist. The photoresist can completely block the ion implantation in the covered area. At the same time, in the covered portion of the single ion implantation protection layer, due to the presence of the ion implantation protection layer, the implanted ions can be blocked to a certain extent under a certain degree of ion implantation conditions, thereby avoiding excessive ion implantation and serious damage to the laser substrate epitaxial structure, thus avoiding device performance degradation and potential reliability risks. The lattice damage to the laser chip substrate epitaxial structure caused by ion implantation is repaired by annealing, and the doped atoms are activated to the correct lattice position, thereby ensuring the performance of the laser chip structure.

[0019] In some embodiments of the present application, in the step of performing ion implantation: the material of the ion implantation protective layer is SiO2 or SiN x , with a thickness of 20nm~50nm; the width of the overlapping part of the photoresist layer and the ion implantation protection layer is 5μm~15μm, and the width distance from the photoresist layer to the edge of the insulating layer located on the heavily doped platform is 5μm~10μm.

[0020] In some embodiments of the present application, in the step of ion implantation: the implanted ions are Si ions or H ions, and the implantation is performed in multiple steps, and the ion energy and / or the implantation dose are gradually increased, while the tilt angle remains unchanged. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0022] Figure 1Schematic diagram of a top view of a semiconductor laser chip structure; Figure 2 A schematic top view of a semiconductor laser chip structure according to an embodiment of the present application; Figure 3 for Figure 2 Schematic cross-section of the MM section line; Figure 4 Schematic diagram of forming an ion implantation protection layer N during the process of forming an ion implantation region in a method for manufacturing a semiconductor laser chip structure according to an embodiment of the present application; Figure 5 Schematic diagram of forming a photoresist layer P during the process of forming an ion implantation region in a method for manufacturing a semiconductor laser chip structure according to an embodiment of the present application; Figure 6 A schematic diagram of ion implantation during the process of forming an ion implantation region in a method for manufacturing a semiconductor laser chip structure according to an embodiment of the present application; Figure 7 Schematic diagram of removing the photoresist layer P and the ion implantation protection layer N during the process of forming the ion implantation region in the method for manufacturing the semiconductor laser chip structure according to one embodiment of the present application; Figure 8 This is a schematic diagram of performing annealing to repair ion implantation damage during the process of forming an ion implantation region in a method for manufacturing a semiconductor laser chip structure according to an embodiment of the present application; Figure 9 FIG. 1 is a schematic diagram of forming an insulating layer in a method for manufacturing a semiconductor laser chip structure according to an embodiment of the present application.

[0023] Description of reference numerals: 110-substrate layer; 120-buffer layer; 130-lower confinement layer; 140-lower waveguide layer; 150-quantum well active layer; 160-upper waveguide layer; 171-first upper confinement layer; 172-second upper confinement layer; 180-ohmic contact layer; 200-insulating layer; A-laser chip substrate; B-heavily doped platform; C-current injection window; D-strip isolation groove; E-overlapping portion of photoresist layer and ion implantation protection layer; F-width distance from photoresist layer to the edge of the insulating layer located on the heavily doped platform; N-ion implantation protection layer; P-photoresist layer; W-strip width. DETAILED DESCRIPTION

[0024] refer to Figure 1 , Figure 1 This is a schematic diagram of a top view of a semiconductor laser chip structure. It includes a laser chip substrate A, which includes the following stacked layers: a substrate layer, a buffer layer, a lower confinement layer, a lower waveguide layer, a quantum well active layer, an upper waveguide layer, an upper confinement layer ( Figure 1It is a top view, and the above layers are not shown in detail. Only the exposed surface in the figure is the upper confinement layer); the heavily doped platform B is arranged on the surface of the upper confinement layer of the laser chip base A facing away from the substrate layer, and includes at least an ohmic contact layer; the length and width of the heavily doped platform B are both smaller than the length and width of the laser chip base A. This type of semiconductor laser chip is designed to form a strip-shaped isolation groove D in the cavity length direction by using wet etching to remove the ohmic contact layer and part of the higher-doped upper confinement layer of the heavily doped platform B to define the strip width W of the light-emitting surface, forming a current injection window C. The direction of the empty arrow in the figure is the direction of the light-emitting surface, that is, the direction from the rear cavity surface to the front cavity surface.

[0025] As mentioned above, this method has the following disadvantages: (1) When the COS device is subsequently formed using the P-down packaging method, the strip isolation groove will affect the degree of polarization (DOP) due to the shear stress introduced by the packaging, which is not conducive to the subsequent polarization beam combining requirements for high DOP, especially in products with small strip widths; (2) The method of defining the strip width W by the strip isolation groove D often requires the deposition of thicker SiO2 / SiN x An insulating layer (usually 100nm to 200nm thick) can achieve good current isolation and form a non-current injection window (i.e., other areas outside the current injection window pattern). Thicker insulating layers often form greater stress on the wafer surface, which can easily lead to warpage exceeding the threshold and even breakage during the manufacturing process, affecting the yield rate and increasing manufacturing costs. (3) Wet etching forms strip isolation trenches hundreds of nanometers deep, which will form a certain thermal path obstruction when the chip dissipates heat laterally. The wet etching process itself makes the area near the strip isolation trench more prone to reliability risks. (4) The strip isolation trench itself will have a certain impact on the far-field horizontal divergence angle.

[0026] Therefore, the present application provides a semiconductor laser chip structure and a manufacturing method thereof to solve the above-mentioned defects caused by using isolation trenches at the edges of heavily doped mesas to define current injection windows.

[0027] The present application provides a semiconductor laser chip structure, comprising: a laser chip substrate, the laser chip substrate comprising: a substrate layer, a buffer layer, a lower confinement layer, a lower waveguide layer, a quantum well active layer, an upper waveguide layer, and a first upper confinement layer stacked in sequence; a heavily doped platform disposed on a surface of the laser chip substrate on a side of the first upper confinement layer facing away from the substrate layer, comprising a second upper confinement layer and an ohmic contact layer; the heavily doped platform having a length and width both smaller than the length and width of the laser chip substrate; an insulating layer covering a portion of the width of the heavily doped platform near an edge, a side of the heavily doped platform, and a surface of the laser chip substrate at the side of the heavily doped platform; an ion implantation region located within a portion of the heavily doped platform and the laser chip substrate below the insulating layer; the ion implantation region and the insulating layer jointly defining a current injection window for the semiconductor laser chip.

[0028] The present application also provides a method for manufacturing a semiconductor laser chip structure, comprising the following steps: providing a laser chip substrate epitaxial structure, comprising: a substrate layer, a buffer layer, a lower confinement layer, a lower waveguide layer, a quantum well active layer, an upper waveguide layer, an upper confinement layer, and an ohmic contact layer stacked in sequence; etching the laser chip epitaxial layer to form a laser chip base and a heavily doped platform on its surface; wherein the portion of the upper confinement layer located on the laser chip base is a first upper confinement layer, and the portion located on the heavily doped platform is a second upper confinement layer; the laser chip base comprises: a substrate layer, a buffer layer, a lower confinement layer, a lower waveguide layer, and a quantum well active layer stacked in sequence. A waveguide layer, a quantum well active layer, an upper waveguide layer, and a first upper confinement layer; the heavily doped platform includes a second upper confinement layer and an ohmic contact layer; the length and width of the heavily doped platform are both smaller than the length and width of the laser chip substrate; an ion implantation region is formed in a portion of the width and thickness of the heavily doped platform near the edge and in a portion of the thickness of the laser chip substrate; an insulating layer is formed on a surface of a portion of the width of the heavily doped platform near the edge, a side surface of the heavily doped platform, and a surface of the laser chip substrate at the side of the heavily doped platform; and the insulating layer and the ion implantation region together define a current injection window of the semiconductor laser chip.

[0029] The technical solution of the present application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application. In the description of the present application, it should be noted that the terms "first", "second" and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0030] Example 1 refer to Figure 2 and Figure 3 , this embodiment provides a semiconductor laser chip structure, including: The laser chip substrate A includes the following stacked layers: a substrate layer 110, a buffer layer 120, a lower confinement layer 130, a lower waveguide layer 140, a quantum well active layer 150, an upper waveguide layer 160, and a first upper confinement layer 171; The heavily doped platform B is provided on the surface of the first upper confinement layer 171 on the laser chip substrate A facing away from the substrate layer, and includes a second upper confinement layer 172 and an ohmic contact layer 180. The length and width of the heavily doped platform B are both smaller than those of the laser chip substrate A. The insulating layer 200 covers the width of the heavily doped platform B near the edge, the side of the heavily doped platform B, and the surface of the laser chip substrate A on the side of the heavily doped platform B; Ion implantation area ( Figure 3 The ion implantation region and the insulating layer 200 together define the stripe width W of the current injection window C of the semiconductor laser chip.

[0031] It should be noted that Figure 2 In order to show the heavily doped mesa B covered by the insulating layer 200, a transparent display is used, showing only the frame, not the Figure 2 The insulating layer 200 and Figure 3 The insulating layer 200 is different. In addition, it should be noted that Figure 3 The dots in the middle represent only the implanted ions, not the particles visible to the naked eye. In fact, due to the very small size of the implanted ions and the corresponding lattice size, they are difficult to discern macroscopically.

[0032] The semiconductor laser chip structure of this embodiment is modified by a partially thick heavily doped platform B located below the insulating layer 200 and an ion implantation region within the laser chip substrate A. The remaining unmodified region is then redefined by the insulating layer 200, leaving the remaining exposed region as a current injection window C. The unexposed portion is shielded by the insulating layer 200, making direct current injection difficult. Furthermore, the exposed region's lateral resistance is increased by ion implantation, increasing the resistance of this region. Current injected through the top P-plane electrode is prevented from passing through the region corresponding to the current injection window C, as the resistance is significantly lower than that of the ion implantation region. This allows for better lateral current spreading without incurring additional photon loss, thereby effectively defining the current injection window and stripe width W. This approach avoids the use of isolation trenches for the heavily doped platform B for definition and the associated stress issues. Consequently, it can address the associated polarization, stress, reliability, and heat dissipation issues associated with using isolation trenches for the heavily doped platform B to define the current injection window and stripe width, and also reduces the impact on the far-field divergence angle.

[0033] Furthermore, in some embodiments, the depth of the ion implantation region does not exceed the upper surface of the quantum well active layer.

[0034] In the semiconductor laser chip structure of this embodiment, the depth of the ion implantation region does not exceed the upper surface of the quantum well active layer 150, and thus the quantum well active layer 150 is not modified. Since the quantum well active layer is the core region of the laser's electro-optical conversion, the solution of this application does not affect the laser's electro-optical conversion capability.

[0035] Specifically, in some embodiments, the ion implantation region is located in the ohmic contact layer 180 , the second upper confinement layer 172 , the first upper confinement layer 171 and a portion of the upper waveguide layer 160 below the insulating layer 200 .

[0036] Furthermore, in some embodiments, the width of the edge of the insulating layer 200 covering the heavily doped platform B is greater than the width of the portion of the ion implantation region located in the heavily doped platform B; the depth of the portion of the ion implantation region located in the heavily doped platform B is shallower than the depth of the portion of the ion implantation region located in the laser chip substrate A.

[0037] In the semiconductor laser chip structure of this embodiment, the ion implantation region is located in the portion of the heavily doped platform B, and its width is less than the width of the insulating layer 200 covering the heavily doped platform B. Its depth is shallower than the portion of the laser chip substrate A where the ion implantation region is located on the side of the heavily doped platform B, thereby forming a transition region. The degree of lattice damage in this portion is relatively small, which can minimize the adverse effects of this region on the absorption and scattering of photons, avoid unnecessary photon scattering and absorption losses at the edge of the strip width W, and reduce electro-optical conversion efficiency and potential reliability risks. At the same time, the ion implantation region is located in the portion of the laser chip substrate A on the side of the heavily doped platform B, and the deeper the implantation depth, the better the lateral expansion of the current can be isolated, thereby improving the electro-optical conversion efficiency of the device.

[0038] In some embodiments of the present application, the implanted ions in the ion implantation region are Si ions or H ions.

[0039] Specifically, in some embodiments, the material of the insulating layer is SiO2 or SiN x , the thickness of the insulating layer is 50nm~100nm; The width of the insulating layer covering the heavily doped platform on one side is 10μm~25μm; The semiconductor laser chip structure further includes a front electrode layer (P-side electrode, not shown in the figure) covering the surface of the current injection window C and the surface of the insulating layer 200, and a back electrode layer (N-side electrode, not shown in the figure) covering the surface of the substrate layer facing away from the buffer layer. The material of the front electrode layer includes titanium (Ti), platinum (Pt), gold (Au) or their alloys; the material of the back electrode layer includes gold (Au), germanium (Ge), nickel (Ni) or their alloys.

[0040] Example 2 This embodiment provides a method for manufacturing a semiconductor laser chip structure, comprising the following steps: A laser chip substrate epitaxial structure is provided, comprising: a substrate layer, a buffer layer, a lower confinement layer, a lower waveguide layer, a quantum well active layer, an upper waveguide layer, an upper confinement layer and an ohmic contact layer stacked in sequence; Etching the epitaxial layer of the laser chip to form a laser chip substrate and a heavily doped platform on its surface; wherein the portion of the upper confinement layer located on the laser chip substrate is the first upper confinement layer, and the portion located on the heavily doped platform is the second upper confinement layer; The laser chip substrate includes: a substrate layer, a buffer layer, a lower confinement layer, a lower waveguide layer, a quantum well active layer, an upper waveguide layer, and a first upper confinement layer stacked in sequence; the heavily doped platform includes a second upper confinement layer and an ohmic contact layer; the length and width of the heavily doped platform are both smaller than those of the laser chip substrate; forming an ion implantation region in a portion of the width and thickness of the heavily doped platform near the edge and in a portion of the thickness of the laser chip substrate; An insulating layer is formed on the surface of the partially width portion of the heavily doped platform close to the edge, the side surface of the heavily doped platform, and the surface of the laser chip substrate on the side of the heavily doped platform; and together with the ion implantation area, a current injection window of the semiconductor laser chip is defined.

[0041] The manufacturing method of the semiconductor laser chip structure provided in this embodiment can manufacture the semiconductor laser chip structure provided in this application, and the laser chip structure is modified by a partially thick heavily doped platform located under the insulating layer and an ion implantation area in the laser chip substrate. The remaining area that has not been ion implanted and modified is then secondary defined by the insulating layer, and the remaining exposed area can be used as a current injection window. The unexposed part is blocked by the insulating layer, making it difficult for current to be injected directly, and the side of the exposed area is modified by ion implantation, so that the resistance of the area is increased. The current injected through the P-side electrode on the top surface cannot pass through this ion implantation area because the resistance of the area corresponding to the current injection window is much smaller than that of the ion implantation area, thereby achieving a better current lateral expansion effect, while not causing additional photon loss, thereby achieving the definition of the current injection window and stripe width. This method avoids the use of isolation trenches of heavily doped platforms for definition and does not produce the various stress problems caused by this. Therefore, it can solve the related polarization, stress, reliability risk, heat dissipation defects caused by using isolation trenches of heavily doped platforms to define the current injection window and stripe width, and can reduce the impact on the far-field divergence angle.

[0042] For further reference, Figure 4-Figure 8 ,by Figure 2 Taking the cross-sectional view at the MM cross-sectional line as an example, in some embodiments, the step of forming the ion implantation region includes: refer to Figure 4 , forming an ion implantation protection layer N, the ion implantation protection layer N covers the surface of the heavily doped platform B close to the edge of the partial width, the side surface of the heavily doped platform B and the surface of the laser chip substrate A on the side of the heavily doped platform B; refer to Figure 5 , forming a photoresist layer P, the photoresist layer P covers the ohmic contact layer 180 exposed by the ion implantation protection layer N, and covers a portion of the width of the ion implantation protection layer, and is spaced a distance from the edge of the heavily doped mesa; refer to Figure 6 , perform ion implantation to form an initial ion implantation region in the heavily doped platform B with a partial thickness below the ion implantation protection layer N and in the laser chip substrate A; refer to Figure 7 , removing the photoresist layer P and the ion implantation protection layer N; refer to Figure 8 , annealing, repairing ion implantation damage and activating the doped atoms in the initial ion implantation area to the correct lattice position.

[0043] After this, a step of forming the insulating layer 200 is performed. Figure 9 An insulating layer 200 is formed on the surface of the heavily doped platform B near the edge, the side surface of the heavily doped platform B, and the surface of the laser chip substrate A on the side of the heavily doped platform B. The ion implantation area covered by the insulating layer 200 is the ion implantation area that has been repaired by annealing.

[0044] It should be noted that the P-side electrode and N-side electrode in the aforementioned embodiment refer to the electrodes located on the P-side and N-side when the semiconductor laser chip performs electro-optical conversion, and do not refer to the electrodes on the surface of the above-mentioned photoresist layer P and the electrodes on the surface of the ion implantation protection layer N.

[0045] The manufacturing method of the semiconductor laser chip structure of this embodiment first forms a relatively thin ion implantation protection layer N, and then covers a portion with a photoresist layer P. The photoresist layer P can completely block ion implantation in the covered area. At the same time, in the portion covered only by the ion implantation protection layer N, the presence of the ion implantation protection layer N can block the implanted ions to a certain extent while ensuring a certain degree of ion implantation conditions, thereby preventing the ion implantation from being too deep and from causing serious damage to the laser substrate epitaxial structure, thereby avoiding a decrease in device performance and potential reliability risks. Annealing repairs the lattice damage to the laser chip substrate epitaxial structure caused by ion implantation, and at the same time activates the doped atoms to the correct lattice position, thereby ensuring the performance of the laser chip structure.

[0046] Specifically, in some embodiments, during the step of ion implantation: The material of the ion implantation protective layer is SiO2 or SiN x , thickness is 20nm~50nm; The overlap E between the photoresist layer and the ion implantation protection layer is 5μm to 15μm wide, and the distance F from the photoresist layer to the edge of the insulating layer on the heavily doped platform is 5μm to 10μm. The ion implantation region corresponding to region F has more film layers and a shallower ion implantation depth because the underlying film layer still retains a complete epitaxial structure. This forms a transition region, preventing excessive lateral expansion of the ion implantation at the boundaries of the stripe width W (the intersection of W and E). This prevents unnecessary photon scattering and absorption losses at the edges of the stripe width W, which could reduce electro-optical conversion efficiency and potentially increase reliability risks.

[0047] The thinner ion implantation protective layer SiO2 or SiN xThis can avoid direct bombardment of the epitaxial structure surface during ion implantation, thus avoiding unnecessary surface damage, resulting in device performance degradation and potential reliability risks.

[0048] Specifically, in some embodiments, during the step of ion implantation: The implanted ions are Si ions or H ions, which are implanted in multiple steps, and the ion energy and / or implantation dose are gradually increased while the tilt angle remains unchanged.

[0049] Multi-step ion implantation with progressively higher ion energy ensures the proper depth and quantity of implanted ions. The same tilt angle ensures the ion implantation area does not exceed the intended range and allows for deeper implantation within the previously established range. This also prevents excessive implantation at one time, which could damage the quantum well active layer.

[0050] In some embodiments, Si ion implantation is performed in three steps, namely: The first Si ion implantation was performed with an ion energy of 20 KeV and an implantation dose of 3.0E+12 cm -2 , tilt angle 7°; The second Si ion implantation was performed with an ion energy of 100 KeV and an implantation dose of 3.0E+12 cm -2 , tilt angle 7°; The third Si ion implantation was performed with an ion energy of 180 KeV and an implantation dose of 3.0E+12 cm -2 , tilt angle 7°; Specifically, in some embodiments, during the step of ion implantation: In some embodiments, H ion implantation is performed in two steps: The first H ion implantation was performed with an ion energy of 30 KeV and an implantation dose of 5.0E+14 cm -2 , tilt angle 7°; The second H ion implantation was performed with an ion energy of 120 KeV and an implantation dose of 5.0E+15 cm -2 , with a tilt angle of 7°.

[0051] Furthermore, the method for manufacturing the semiconductor laser chip structure provided in this embodiment further includes: A front electrode layer is formed on the top surface of the laser chip substrate A and the heavily doped platform B, covering the surface of the current injection window C and the surface of the insulating layer 200; a back electrode layer is formed on the bottom surface of the laser chip substrate A, covering the surface of the substrate layer 110 facing away from the buffer layer 120.

[0052] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of this application.

Claims

1. A semiconductor laser chip structure, characterized in that: The semiconductor laser chip structure includes: A laser chip substrate, the laser chip substrate comprising: a substrate layer, a buffer layer, a lower confinement layer, a lower waveguide layer, a quantum well active layer, an upper waveguide layer, and a first upper confinement layer stacked in sequence; A heavily doped platform is provided on the surface of the first upper confinement layer on the laser chip substrate facing away from the substrate layer, and includes a second upper confinement layer and an ohmic contact layer; the length and width of the heavily doped platform are both smaller than the length and width of the laser chip substrate; an insulating layer covering a portion of the width of the heavily doped platform close to the edge, a side of the heavily doped platform, and a surface of the laser chip substrate at the side of the heavily doped platform; An ion implantation region is located in a portion of the heavily doped platform and the laser chip substrate below the insulating layer; the ion implantation region and the insulating layer together define a stripe width of a current injection window of the semiconductor laser chip.

2. The semiconductor laser chip structure according to claim 1, characterized in that: The depth of the ion implantation region does not exceed the upper surface of the quantum well active layer.

3. The semiconductor laser chip structure according to claim 2, characterized in that: The ion implantation region is located in the ohmic contact layer, the second upper confinement layer, the first upper confinement layer, and a partial thickness of the upper waveguide layer below the insulating layer.

4. The semiconductor laser chip structure according to claim 1, wherein: The width of the insulating layer covering the edge of the heavily doped platform is greater than the width of the portion of the ion implantation region located in the heavily doped platform; The depth of the portion of the ion implantation region located at the heavily doped mesa is shallower than the depth of the portion of the ion implantation region located at the laser chip substrate.

5. The semiconductor laser chip structure according to claim 1, characterized in that: The implanted ions in the ion implantation region are Si ions or H ions.

6. The semiconductor laser chip structure according to claim 1, characterized in that: The material of the insulating layer is SiO2 or SiN x , the thickness of the insulating layer is 50nm~100nm; The width of a single side of the insulating layer covering the heavily doped platform is 10 μm to 25 μm; The semiconductor laser chip structure further includes a front electrode layer covering the surface of the current injection window and the surface of the insulating layer, and a back electrode layer covering the surface of the substrate layer facing away from the buffer layer; The material of the front electrode layer includes titanium, platinum, gold or their alloys; The material of the back electrode layer includes gold, germanium, nickel or alloys thereof.

7. A method for manufacturing a semiconductor laser chip structure, characterized in that: The following steps are involved: A laser chip substrate epitaxial structure is provided, comprising: a substrate layer, a buffer layer, a lower confinement layer, a lower waveguide layer, a quantum well active layer, an upper waveguide layer, an upper confinement layer and an ohmic contact layer stacked in sequence; Etching the epitaxial structure of the laser chip substrate to form a laser chip base and a heavily doped platform on its surface; wherein the portion of the upper confinement layer located on the laser chip base is a first upper confinement layer, and the portion located on the heavily doped platform is a second upper confinement layer; The laser chip substrate comprises: a substrate layer, a buffer layer, a lower confinement layer, a lower waveguide layer, a quantum well active layer, an upper waveguide layer, and a first upper confinement layer, which are stacked in sequence; The heavily doped platform includes a second upper confinement layer and an ohmic contact layer; the length and width of the heavily doped platform are both smaller than the length and width of the laser chip substrate; forming an ion implantation region in a portion of the width and thickness of the heavily doped platform near the edge and in a portion of the thickness of the laser chip substrate; An insulating layer is formed on the surface of the partially width portion of the heavily doped platform close to the edge, the side surface of the heavily doped platform, and the surface of the laser chip substrate on the side of the heavily doped platform; the insulating layer and the ion implantation region jointly define a current injection window for the semiconductor laser chip.

8. The method for manufacturing a semiconductor laser chip structure according to claim 7, wherein: The step of forming the ion implantation region comprises: forming an ion implantation protection layer, wherein the ion implantation protection layer covers a surface of a portion of the width of the heavily doped platform close to the edge, a side surface of the heavily doped platform, and a surface of the laser chip substrate on the side of the heavily doped platform; forming a photoresist layer, wherein the photoresist layer covers the ohmic contact layer exposed by the ion implantation protection layer and covers a portion of the width of the ion implantation protection layer and is spaced a distance from the edge of the heavily doped mesa; Performing ion implantation to form an initial ion implantation region in a portion of the thickness of the heavily doped platform and the laser chip substrate below the ion implantation protection layer; removing the photoresist layer and the ion implantation protection layer; Annealing repairs ion implantation damage and activates the doped atoms in the initial ion implantation region to the correct lattice position.

9. The method for manufacturing a semiconductor laser chip structure according to claim 8, wherein: In the step of performing ion implantation: The material of the ion implantation protection layer is SiO2 or SiN x , thickness is 20nm~50nm; The width of the overlapping portion between the photoresist layer and the ion implantation protection layer is 5 μm to 15 μm, and the width distance from the photoresist layer to the edge of the insulating layer located on the heavily doped mesa is 5 μm to 10 μm.

10. The method for manufacturing a semiconductor laser chip structure according to claim 8, wherein: In the step of performing ion implantation: The implanted ions are Si ions or H ions, which are implanted in multiple steps, and the ion energy and / or implantation dose are gradually increased while the tilt angle remains unchanged.

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