Differential power amplifier, power amplifier and radio frequency front-end module

Abstract

The invention discloses a differential power amplifier, a power amplifier and a radio frequency front-end module. The differential power amplifier comprises a first amplification transistor, a second amplification transistor, a first variable capacitance circuit and a second variable capacitance circuit, the controlled end of the first amplification transistor is used for receiving a first input signal, and the first end of the first amplification transistor is used for outputting the first input signal processed by the first amplification transistor; the controlled end of the second amplification transistor is used for receiving a second input signal, and the first end of the second amplification transistor is used for outputting the second input signal processed by the second amplification transistor; the input end of the first variable capacitance circuit is connected with the controlled end of the first amplification transistor, the output end of the first variable capacitance circuit is connected with the first end of the second amplification transistor, and the bias end of the first variable capacitance circuit is used for receiving first bias voltage; the output end of the second variable capacitance circuit is connected with the first end of the first amplification transistor, and the bias end of the second variable capacitance circuit is used for receiving the second bias voltage. The gain and linearity of the power amplifier can be improved.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a differential power amplifier, a power amplifier, and a radio frequency front-end module. Background Art

[0002] The differential power amplifier (DPA) is a key component of RF front-end modules. Therefore, good performance is crucial to their design. Gain and linearity are key performance indicators in a DPA. In related technologies, as the power of a DPA increases, its parasitic capacitance changes with the power increase. This can cause phase misalignment (AM-PM misalignment) and gain compression (AM-AM misalignment) between the DPA's input and output power, impacting both gain and linearity. Summary of the Invention

[0003] Based on this, the embodiments of the present application provide a differential power amplifier, a power amplifier, and a radio frequency front-end module, aiming to effectively improve the gain and linearity of the differential power amplifier.

[0004] In a first aspect, an embodiment of the present application provides a differential power amplifier, comprising: a first amplifying transistor, a second amplifying transistor, a first varactor circuit, and a second varactor circuit; The controlled terminal of the first amplifying transistor is used to receive the first input signal, the first terminal of the first amplifying transistor is used to output the first input signal processed by the first amplifying transistor, and the second terminal of the first amplifying transistor is grounded; The controlled end of the second amplifying transistor is used to receive the second input signal, the first end of the second amplifying transistor is used to output the second input signal processed by the second amplifying transistor, and the second end of the second amplifying transistor is grounded; The first input signal and the second input signal are differential input signals. The input terminal of the first varactor circuit is connected to the controlled terminal of the first amplifying transistor, the output terminal of the first varactor circuit is connected to the first terminal of the second amplifying transistor, and the bias terminal of the first varactor circuit is used to receive a first bias voltage. The output terminal of the second varactor circuit is connected to the first terminal of the first amplifying transistor, and the bias terminal of the second varactor circuit is used to receive a second bias voltage. In some embodiments, the first varactor circuit includes a first capacitor unit and a first varactor unit. The first terminal of the first capacitor unit is connected to the controlled terminal of the first amplifying transistor, the second terminal of the first capacitor unit is connected to the anode terminal of the first varactor unit and is used to receive the first bias voltage, and the cathode terminal of the first varactor unit is connected to the first terminal of the second amplifying transistor. In addition, the second varactor circuit includes a second capacitor unit and a second varactor unit, the first end of the second capacitor unit is connected to the controlled end of the second amplifying transistor, the second end of the second capacitor unit is connected to the anode end of the second varactor unit and is used to receive the second bias voltage, and the cathode end of the second varactor unit is connected to the first end of the first amplifying transistor.

[0005] In some embodiments, during operation of the differential power amplifier, the variable capacitance value generated by the first varactor unit is less than 0.2 pF, and the variable capacitance value generated by the second varactor unit is less than 0.2 pF.

[0006] In some embodiments, during the operation of the differential power amplifier, the difference between the variable capacitance value generated by the first varactor unit and the parasitic capacitance value generated by the first amplifying transistor is less than a first threshold; the difference between the variable capacitance value generated by the second varactor unit and the parasitic capacitance value generated by the second amplifying transistor is less than a second threshold.

[0007] In some embodiments, the first varactor unit includes at least one first diode, the second end of the first capacitor unit is connected to the anode end of the first diode, and the cathode end of the first diode is connected to the first end of the second amplifying transistor; Alternatively, the first varactor unit includes at least one first triode, the base of the first triode is connected to the collector and to the second end of the first capacitor unit, and the emitter of the first triode is connected to the first end of the second amplifying transistor.

[0008] In some embodiments, the second varactor unit includes at least one second diode, the second end of the second capacitor unit is connected to the anode end of the second diode, and the cathode end of the second diode is connected to the first end of the first amplifying transistor; Alternatively, the second varactor unit includes at least one second triode, the base of the second triode is connected to the collector and to the second end of the second capacitor unit, and the emitter of the second triode is connected to the first end of the first amplifying transistor.

[0009] In some embodiments, the first capacitor unit includes at least one first capacitor, and the capacitance value of the first capacitor unit is less than 0.5 pF; And / or, the second capacitor unit includes at least one second capacitor, and the capacitance value of the second capacitor unit is less than 0.5 pF.

[0010] In some embodiments, the capacitance value of the first capacitor unit is greater than 0.05 pF and less than 0.3 pF; and / or the capacitance value of the second capacitor unit is greater than 0.05 pF and less than 0.3 pF.

[0011] In some embodiments, during operation of the differential power amplifier, a first bias voltage received by the first varactor circuit and a second bias voltage received by the second varactor circuit are equal in magnitude.

[0012] In some embodiments, the first terminal of the first amplifying transistor is further configured to receive a first power supply voltage Vcc1, and the first terminal of the second amplifying transistor is further configured to receive a second power supply voltage Vcc2; Where Vdc1≥V EG1 + Vcc2, and Vdc2 ≥ V EG2 +Vcc1,V EG1 is the on-state voltage of the first varactor unit, V EG2 is the on-state voltage of the second varactor unit, Vdc1 is the first bias voltage, and Vdc2 is the second bias voltage.

[0013] In some embodiments, the voltage level of the first bias voltage is adjustable; and / or the voltage level of the second bias voltage is adjustable.

[0014] In some embodiments, the differential power amplifier includes a plurality of first amplifying transistors and a plurality of second amplifying transistors; the plurality of first amplifying transistors are connected in parallel and have a first common input terminal and a first common output terminal, and the plurality of second amplifying transistors are connected in parallel and have a second common input terminal and a second common output terminal; Each first amplifying transistor corresponds to a first varactor circuit, the input end of each first varactor circuit is connected to the controlled end of the corresponding first amplifying transistor, the output end of each first varactor circuit is connected to the first end of the corresponding second amplifying transistor, and each second amplifying transistor corresponds to a second varactor circuit, the input end of each second varactor circuit is connected to the controlled end of the corresponding second amplifying transistor, and the output end of each second varactor circuit is connected to the first end of the corresponding first amplifying transistor; Alternatively, a plurality of first amplifier transistors connected in parallel share a first varactor circuit, the input end of the first varactor circuit is connected to the first common input end, the input end of the first varactor circuit is connected to the second common output end, and a plurality of second amplifier transistors connected in parallel share a second varactor circuit, the input end of the second varactor circuit is connected to the second common input end of the second amplifier transistor, and the input end of the second varactor circuit is connected to the first common output end.

[0015] In some embodiments, the first amplifying transistor is an HBT transistor, a BJT transistor, or a field effect transistor; and / or the second amplifying transistor is an HBT transistor, a BJT transistor, or a field effect transistor.

[0016] In some embodiments, when the first varactor unit includes at least one first triode, the first triode and the first amplifying transistor are both HBT transistors, or the first triode and the first amplifying transistor are both BJT transistors; In the case where the second varactor unit includes at least one second triode, the second triode and the second amplifying transistor are both HBT transistors, or the second triode and the second amplifying transistor are both BJT transistors.

[0017] In some embodiments, the differential power amplifier further includes a balun, the balun including a primary coil and a secondary coil coupled to the primary coil; The first input end of the primary coil can be used to receive a signal outputted by the first end of the first amplifying transistor, the second input end of the primary coil can be used to receive a signal outputted by the first end of the second amplifying transistor, and the secondary coil is used to connect to a load.

[0018] In some embodiments, the differential power amplifier also includes a third amplifier transistor and a fourth amplifier transistor, the controlled end of the third amplifier transistor is used to receive the first initial input signal, and the first end of the third amplifier transistor is used to connect to the controlled end of the first amplifier transistor; the controlled end of the fourth amplifier transistor is used to receive the second initial input signal, and the first end of the fourth amplifier transistor is used to connect to the controlled end of the second amplifier transistor.

[0019] In some embodiments, the differential power amplifier further includes a third varactor circuit and a fourth varactor circuit, wherein both the third varactor circuit and the fourth varactor circuit can generate variable capacitance, and the input end of the third varactor circuit is connected to the controlled end of the third amplifying transistor, and the output end of the third varactor circuit is connected to the first end of the fourth amplifying transistor; the input end of the fourth varactor circuit is connected to the controlled end of the fourth amplifying transistor, and the output end of the fourth varactor circuit is connected to the first end of the third amplifying transistor.

[0020] In some embodiments, the differential power amplifier also includes a first inter-stage matching circuit and a second inter-stage matching circuit, wherein the first end of the first inter-stage matching circuit is connected to the first end of the third amplifying transistor, and the second end of the first inter-stage matching circuit is connected to the controlled end of the first amplifying transistor; the first end of the second inter-stage matching circuit is connected to the first end of the fourth amplifying transistor, and the second end of the second inter-stage matching circuit is connected to the controlled end of the second amplifying transistor.

[0021] In a second aspect, the present application further provides a differential power amplifier, comprising: a first amplifying transistor, a second amplifying transistor, a first varactor circuit, and a second varactor circuit; The controlled terminal of the first amplifying transistor is used to receive the first input signal, the first terminal of the first amplifying transistor is used to output the first input signal processed by the first amplifying transistor, and the second terminal of the first amplifying transistor is grounded; The controlled end of the second amplifying transistor is used to receive the second input signal, the first end of the second amplifying transistor is used to output the second input signal processed by the second amplifying transistor, and the second end of the second amplifying transistor is grounded; The first input signal and the second input signal are differential input signals, the input end of the first varactor circuit is connected to the controlled end of the first amplifying transistor, the output end of the first varactor circuit is connected to the first end of the second amplifying transistor, and during operation of the differential power amplifier, the first varactor circuit can generate a first variable capacitance to compensate for the parasitic capacitance of the first amplifying transistor; The input end of the second varactor circuit is connected to the controlled end of the second amplifying transistor, and the output end of the second varactor circuit is connected to the first end of the first amplifying transistor. During the operation of the differential power amplifier, the second varactor circuit can generate a second variable capacitance to compensate for the parasitic capacitance of the second amplifying transistor.

[0022] In a third aspect, the present application further provides a power amplifier, comprising: A power distribution circuit, configured to distribute the power of an input signal and output a first signal and a second signal with a preset phase difference; A first amplifier circuit, configured to amplify the first signal; a second amplifying circuit, configured to amplify the second signal; A power synthesis circuit, configured to synthesize and output the first signal amplified by the first amplifying circuit and the second signal amplified by the second amplifying circuit; At least one of the first amplifier circuit and the second amplifier circuit includes an unbalanced-balanced converter circuit and the aforementioned differential power amplifier. In some embodiments, the second amplifier circuit is turned on when the output power of the first amplifier circuit reaches a peak value; The power synthesis circuit includes a phase shift unit and a synthesis unit, wherein the phase shift unit is used to perform phase shift on the second signal amplified by the second amplification circuit; The synthesis unit is used to synthesize and output the first signal amplified by the first amplifier circuit and the second signal after phase shifting.

[0023] In a fourth aspect, the present application also provides a radio frequency front-end module, including the aforementioned differential power amplifier, or the aforementioned power amplifier.

[0024] It can be seen from the above technical solutions that the differential power amplifier, power amplifier and RF front-end module provided by the present application are provided with a first varactor circuit and a second varactor circuit. During the operation of the differential power amplifier, the first varactor circuit can generate a first variable capacitor to compensate for the parasitic capacitance of the first amplifying transistor of the differential power amplifier, and the second varactor circuit can generate a second variable capacitor to compensate for the parasitic capacitance of the second amplifying transistor of the differential power amplifier, thereby reducing the influence of the parasitic capacitance of the differential power amplifier itself changing with the increase of power due to the increase of power, thereby effectively improving the phase accuracy and gain accuracy between the input power and output power of the differential power amplifier, and ultimately effectively improving the gain and linearity of the differential power amplifier.

[0025] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0027] Figure 1 1 is a block diagram of a differential power amplifier provided in an embodiment of the present application; Figure 2 1 is a schematic diagram of a circuit structure corresponding to an implementation manner of a differential power amplifier provided in an embodiment of the present application; Figure 3 1 is a schematic diagram of a circuit structure corresponding to another implementation of a differential power amplifier provided in an embodiment of the present application; Figure 4 This is a block diagram of a modified differential power amplifier provided in an embodiment of the present application; Figure 5 This is a block diagram of another variation of the differential power amplifier provided in an embodiment of the present application; Figure 6 This is a block diagram of another variant of the differential power amplifier provided in an embodiment of the present application; Figure 7 It is a block diagram of the structure of a power amplifier provided in an embodiment of the present application; Figure 8 It is a block diagram schematic diagram of the RF front-end module provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0029] It should be noted that the descriptions of "first", "second", etc. in this application are for descriptive purposes only and should not be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between the various embodiments can be combined with each other, but this must be based on the fact that they can be implemented by ordinary technicians in this field. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0030] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, removable connections, or integral connections. They can refer to mechanical connections or electrical connections. They can refer to direct connections or indirect connections through an intermediary. They can refer to internal communication between two components or interactions between two components. Those skilled in the art will understand the specific meanings of these terms in the present invention based on specific circumstances.

[0031] The flowcharts shown in the accompanying drawings are for illustrative purposes only and do not necessarily include all contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may be decomposed, combined, or partially merged, so the actual execution order may vary depending on the actual situation.

[0032] The following describes some embodiments of the present application in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features therein may be combined with each other.

[0033] See also Figure 1 , Figure 1 A schematic diagram of the circuit structure of a differential power amplifier provided in an embodiment of the present application.

[0034] like Figure 1As shown, the differential power amplifier 100 includes a first amplifying transistor 10, a second amplifying transistor 11, a first varactor circuit 12, and a second varactor circuit 13. The controlled terminal of the first amplifying transistor 10 is used to receive a first input signal in1, the first terminal of the first amplifying transistor 10 is used to output the first input signal in1 after being processed by the first amplifying transistor 10, and the second terminal of the first amplifying transistor 10 is used to be grounded. It will be understood that the second terminal of the first amplifying transistor 10 can be grounded by directly grounding the second terminal of the first amplifying transistor 10, or by connecting the second terminal of the first amplifying transistor 10 to a first target component and grounding through the first target component. For example, the first target component may include an inductor.

[0035] The controlled terminal of the second amplifying transistor 11 is used to receive the second input signal in2. The first terminal of the second amplifying transistor 11 is used to output the second input signal in2 processed by the second amplifying transistor 11. The second terminal of the second amplifying transistor 11 is used to be grounded. It is understood that the second terminal of the second amplifying transistor 11 can be grounded directly, or the second terminal of the second amplifying transistor 11 can be connected to a second target component and grounded through the second target component. For example, the second target component can include an inductor.

[0036] The first input signal in1 and the second input signal in2 are both radio frequency signals, and the first input signal in1 and the second input signal in2 constitute a pair of differential input signals. The input end of the first varactor circuit 12 is connected to the controlled end of the first amplifying transistor 10, the output end of the first varactor circuit 12 is connected to the first end of the second amplifying transistor 11, the bias end of the first varactor circuit 12 is used to receive the first bias voltage Vdc1, the input end of the second varactor circuit 13 is connected to the controlled end of the second amplifying transistor 11, the output end of the second varactor circuit 13 is connected to the first end of the first amplifying transistor 10, and the bias end of the second varactor circuit 13 is used to receive the second bias voltage Vdc2.

[0037] During operation of the differential power amplifier 100, a first parasitic capacitance may be generated between different terminals of the first amplifying transistor 10, and a second parasitic capacitance may be generated between different terminals of the second amplifying transistor 20. Furthermore, as the output power of the differential power amplifier 100 changes, the voltage between different terminals of the first amplifying transistor 10 and the voltage between different terminals of the second amplifying transistor 20 may vary over a wide range, causing the magnitude of the first parasitic capacitance to vary with the voltage between different terminals of the first amplifying transistor 10, and the magnitude of the second parasitic capacitance to vary with the voltage between different terminals of the second amplifying transistor 20. Based on the fact that the differential power amplifier 100 is provided with a first varactor circuit 12 and a second varactor circuit 13, during the operation of the differential power amplifier 100, the first varactor circuit 12 can generate a first variable capacitor to dynamically compensate for the first parasitic capacitance of the first amplifying transistor 10, and the second varactor circuit 13 can generate a second variable capacitor to dynamically compensate for the second parasitic capacitance of the second amplifying transistor 11, thereby providing dynamic compensation adapted to changes in the first parasitic capacitance and the second parasitic capacitance. Compared with the method of compensating for parasitic capacitance using fixed capacitance, the embodiment of the present application can more effectively improve the phase accuracy and gain accuracy between the input power and output power of the differential power amplifier 100, and ultimately more effectively improve the gain and linearity of the differential power amplifier.

[0038] Optionally, the first amplifying transistor 10 may be an HBT transistor, a BJT transistor or a field effect transistor.

[0039] Optionally, the second amplifying transistor 11 may be an HBT transistor, a BJT transistor or a field effect transistor.

[0040] Optionally, the first amplifying transistor 10 and the second amplifying transistor 11 are transistors of the same type. For example, the first amplifying transistor 10 and the second amplifying transistor 11 are both HBT transistors, or the first amplifying transistor 10 and the second amplifying transistor 11 are both BJT transistors.

[0041] For example, the first amplifying transistor 10 and the second amplifying transistor 11 are both HBT transistors. The HBT transistor includes a base, a collector and an emitter, wherein the controlled end of the first amplifying transistor 10 and the second amplifying transistor 11 is the base, the first end is the collector, and the second end is the emitter.

[0042] During operation of the differential power amplifier 100, a base-collector parasitic capacitance Cbc exists between the base and collector of the target transistors (e.g., the first amplifying transistor 10 and the second amplifying transistor 11) in the differential power amplifier 100. When the HBT is operating, as the base-collector voltage Vbc continuously changes, Cbc also changes, resulting in phase imbalance and gain compression between the input power and output power of the differential power amplifier 100.

[0043] In this embodiment, by connecting the input end of the first varactor circuit 12 to the controlled end of the first amplifying transistor 10, connecting the output end of the first varactor circuit 12 to the first end of the second amplifying transistor 11, the bias end of the first varactor circuit 12 is used to receive the first bias voltage Vdc1, and connecting the output end of the second varactor circuit 13 to the first end of the first amplifying transistor 10, and the bias end of the second varactor circuit 13 is used to receive the second bias voltage Vdc2, the signal output by the first amplifying transistor 10 is compensated to the second amplifying transistor 11, and the signal output by the second amplifying transistor 11 is compensated to the first amplifying transistor 10. Since the first input signal The first input signal and the second input signal are differential input signals. After amplification, the signal output by the first amplifier transistor 10 and the signal output by the second amplifier transistor 11 are also a pair of differential signals of equal magnitude and opposite phase. Therefore, the first varactor circuit 12 is equivalent to introducing a first variable negative capacitor into the collector and base of the first amplifier transistor 10 to neutralize the influence of the change of Cbc (parasitic capacitance between the base and the collector) in the first amplifier transistor 10. The second varactor circuit 13 is equivalent to introducing a second variable negative capacitor into the collector and base of the second amplifier transistor 11 to neutralize the influence of the change of Cbc (parasitic capacitance between the base and the collector) in the second amplifier transistor 11. Furthermore, because the voltage difference across the first varactor circuit 12 and the voltage difference across the base-collector electrodes of the first amplifier transistor 10 always remain equal in magnitude and opposite in phase, the change in the first variable negative capacitance generated by the first varactor circuit 12 always tracks the change in the parasitic capacitance Cbc of the first amplifier transistor 10. Consequently, regardless of how the output power of the differential power amplifier 100 changes, the first varactor circuit 12 maintains a good neutralizing effect on the base-collector parasitic capacitance of the first amplifier transistor 10. Similarly, regardless of how the output power of the differential power amplifier 100 changes, the second varactor circuit 12 maintains a good neutralizing effect on the base-collector parasitic capacitance of the second amplifier transistor 11. Since the presence of the parasitic capacitance Cbc between the base and collector electrodes deteriorates the transconductance gm of the HBT during operation of the differential power amplifier 100, neutralizing the parasitic capacitance Cbc can improve the gain of the differential power amplifier 100. At the same time, the parasitic capacitance Cbc will also worsen the phase distortion of the circuit. Therefore, after neutralizing Cbc, the linearity of the differential power amplifier 100 can be effectively improved.

[0044] like Figure 1 As shown, in some embodiments, the controlled end of the first amplifying transistor 10 and the controlled end of the second amplifying transistor 11 are also used to connect to a bias circuit.

[0045] like Figure 1As shown, in some embodiments, the differential power amplifier 100 further includes a balun 14, which includes a primary coil 141 and a secondary coil 142 coupled to the primary coil 141. The first input terminal of the primary coil 141 can be used to receive a signal output by the first terminal of the first amplifying transistor 10, and the second input terminal of the primary coil 141 can be used to receive a signal output by the first terminal of the second amplifying transistor 11. The secondary coil 142 is used to connect to a load. Optionally, the load can be a post-stage circuit of the differential power amplifier 100, such as a switch, filter, or duplexer in an RF front-end module. This application does not limit the specific form of the load.

[0046] See also Figure 2 In some embodiments, the controlled end of the first amplifying transistor 10 and the controlled end of the second amplifying transistor 11 are also used to connect to the impedance matching network 50, and the first input signal in1 is input to the controlled end of the first amplifying transistor 10 through the impedance matching network 50, and the second input signal in2 is input to the controlled end of the second amplifying transistor 11 through the impedance matching network 50.

[0047] See also Figures 2 to 3 In some embodiments, the first varactor circuit 12 includes a first capacitor unit 121 and a first varactor unit 122, the first end of the first capacitor unit 121 is connected to the controlled end of the first amplifying transistor 10, the second end of the first capacitor unit 121 is connected to the anode end of the first varactor unit 122 and is used to receive the first bias voltage Vdc1, and the cathode end of the first varactor unit 122 is connected to the first end of the second amplifying transistor 11.

[0048] The second varactor circuit 13 includes a second capacitor unit 131 and a second varactor unit 132. The first end of the second capacitor unit 131 is connected to the controlled end of the second amplifying transistor 11. The second end of the second capacitor unit 131 is connected to the anode end of the second varactor unit 132 and is used to receive the second bias voltage Vdc2. The cathode end of the second varactor unit 132 is connected to the first end of the first amplifying transistor 10.

[0049] Exemplarily, the first capacitor unit 121 is disposed between the first varactor unit 122 and the controlled terminal of the first amplifying transistor 10. The DC-blocking properties of the first capacitor unit 121 are utilized to prevent the original circuit bias state of the first amplifying transistor 10 from being disrupted by the connection of the first capacitor unit 121 and the first varactor unit 122 to the controlled terminal of the first amplifying transistor 10. Furthermore, the first capacitor unit 121 has a fixed capacitance value C1. During operation of the differential power amplifier 100, the first varactor unit 122 can generate a variable capacitance Cx. When the voltage across the first varactor unit 122 changes with the output power, the variable capacitance Cx generated by the first varactor unit 122 also changes accordingly. Therefore, the capacitance value of the first capacitor unit 121 and the first varactor unit 122 connected in series can also be equivalent to a variable capacitance, thereby reversely compensating for the parasitic capacitance generated by the operation of the first amplifying transistor 10.

[0050] Similarly, the second capacitor unit 131 is positioned between the second varactor unit 132 and the controlled terminal of the second amplifying transistor 11. The DC-blocking properties of the second capacitor unit 131 are utilized to prevent the original circuit bias state of the second amplifying transistor 11 from being disrupted by the connection of the second capacitor unit 131 and the second varactor unit 132 to the controlled terminal of the second amplifying transistor 11. Furthermore, the second capacitor unit 131 has a fixed capacitance value C2. During operation of the differential power amplifier 100, the second varactor unit 132 generates a variable capacitance Cy. As the voltage across the second varactor unit 132 changes with the output power, the variable capacitance Cy generated by the second varactor unit 132 also changes. Therefore, the capacitance of the second capacitor unit 131 and the second varactor unit 132 connected in series can be equivalent to a variable capacitance, which reversely compensates for the parasitic capacitance generated by the operation of the second amplifying transistor 11, thereby effectively improving the linearity and gain of the differential power amplifier 100.

[0051] like Figure 2 and Figure 3 As shown, in some embodiments, the first capacitor unit 121 includes at least one first capacitor, and the capacitance value of the first capacitor unit 121 is less than 0.5pF. Optionally, the capacitance value of the first capacitor unit 121 is greater than 0.05pF and less than 0.3pF. Exemplarily, the first capacitor unit 121 is composed of one first capacitor; or the first capacitor unit 121 includes multiple first capacitors connected in parallel and having a capacitance smaller than the overall capacitance value of the first capacitor unit 121; or the first capacitor unit 121 includes multiple first capacitors connected in series and having a capacitance larger than the overall capacitance value of the first capacitor unit 121.

[0052] In some embodiments, the second capacitor unit 131 includes at least one second capacitor, and the capacitance of the second capacitor unit 131 is less than 0.5 pF. Optionally, the second capacitor unit 131 includes at least one second capacitor, and the capacitance of the second capacitor unit 131 is greater than 0.05 pF and less than 0.3 pF. Exemplarily, the second capacitor unit 131 is composed of one second capacitor; or the second capacitor unit 131 includes multiple second capacitors connected in parallel and having a smaller capacitance than the overall capacitance of the second capacitor unit 131; or the second capacitor unit 131 includes multiple second capacitors connected in series and having a larger capacitance than the overall capacitance of the second capacitor unit 131.

[0053] In this embodiment, by setting the capacitance values of the first capacitor and the second capacitor within a preset range of less than 0.5 pF, preferably greater than 0.05 pF and less than 0.3 pF, the differential amplifier 100 can more appropriately compensate for the parasitic capacitance generated by the first amplifying transistor 10 during operation through the cooperation of the first capacitor and the first varactor unit 122. Simultaneously, the parasitic capacitance generated by the second amplifying transistor 11 can be more appropriately compensated through the cooperation of the second capacitor and the second varactor unit 132. In this embodiment, by setting the capacitance values of the first capacitor and the second capacitor within a range of greater than 0.05 pF and less than 0.3 pF, the total capacitance of the first capacitor and the first varactor unit 122 can be similar to the parasitic capacitance generated by the first amplifying transistor 10, thereby effectively neutralizing the effects of the parasitic capacitance. Simultaneously, the total capacitance of the second capacitor and the second varactor unit 132 can be similar to the parasitic capacitance generated by the second amplifying transistor 11, thereby effectively neutralizing the effects of the parasitic capacitance, thereby effectively improving the linearity and gain of the differential power amplifier 100.

[0054] In some embodiments, during operation of the differential power amplifier 100 , the variable capacitance value generated by the first varactor unit 122 is less than 0.2 pF, and the variable capacitance value generated by the second varactor unit 132 is less than 0.2 pF.

[0055] In this embodiment, because the variable capacitance value generated by the first varactor unit 122 is less than 0.2 pF, and the variable capacitance value generated by the second varactor unit 132 is less than 0.2 pF, the differential amplifier 100 can compensate for the parasitic capacitance generated by the first amplifying transistor 10 during operation through the cooperation of the first capacitor unit 121 and the first varactor unit 122. Simultaneously, the first capacitor unit 131 and the second varactor unit 132 can compensate for the parasitic capacitance generated by the second amplifying transistor 11. In this embodiment, by setting the variable capacitance of the first varactor unit 122 and the second varactor unit 132 to less than 0.2 pF, the total capacitance of the first capacitor and the first varactor unit 122 is closer to the parasitic capacitance generated by the first amplifying transistor 10, thereby better neutralizing the effect of the parasitic capacitance generated by the first amplifying transistor 10. At the same time, the total capacitance of the second capacitor and the second varactor unit 132 is closer to the parasitic capacitance generated by the second amplifying transistor 11, effectively neutralizing the effect of the parasitic capacitance, thereby effectively improving the linearity and gain of the differential power amplifier 100.

[0056] In this embodiment, during operation of the differential power amplifier 100, the difference between the variable capacitance value generated by the first varactor unit 122 and the parasitic capacitance value generated by the first amplifying transistor 10 is less than a first threshold. The difference between the variable capacitance value generated by the second varactor unit 132 and the parasitic capacitance value generated by the second amplifying transistor 11 is less than a second threshold. As a result, the first varactor unit 122 can better compensate for the parasitic capacitance generated by the first amplifying transistor 10, and the second varactor unit 132 can better compensate for the parasitic capacitance generated by the second amplifying transistor 11, ultimately effectively improving the linearity and gain of the differential power amplifier 100.

[0057] It can be understood that the first threshold and the second threshold can be set as needed. For example, the first threshold and the second threshold are both zero, or the first threshold and the second threshold are both 0.05pF, or the first threshold and the second threshold are both 0.03pF, or the first threshold and the second threshold are both 0.01pF, etc., which are not limited here.

[0058] like Figure 2 As shown, in some embodiments, the first variable capacitance unit 122 includes at least one first diode, the second end of the first capacitance unit 121 is connected to the anode end of the first diode, and the cathode end of the first diode is connected to the first end of the second amplifying transistor 11.

[0059] It will be appreciated that the first diode is a varactor diode, which has the characteristic that the junction capacitance varies with the applied voltage when the PN junction is reverse biased. That is, the junction capacitance increases with increasing reverse bias voltage and decreases with increasing reverse bias voltage. Based on the variable capacitance characteristic of the varactor diode, changes in the parasitic capacitance generated by the first amplifying transistor 10 can be effectively compensated during the operation of the differential power amplifier 100.

[0060] like Figure 3 As shown, in some embodiments, the first varactor unit 122 includes at least one first triode, the base of the first triode is connected to the collector and to the second end of the first capacitor unit 121, and the emitter of the first triode is connected to the first end of the second amplifying transistor 11. It can be understood that connecting the base of the triode to the collector makes the triode equivalent to a diode.

[0061] Optionally, when the first varactor unit 122 includes at least one first transistor, the first transistor and the first amplifying transistor 10 are both HBT transistors, or the first transistor and the first amplifying transistor 10 are both BJT transistors.

[0062] like Figure 2 As shown, in some embodiments, the second varactor unit 132 includes at least one second diode, the second end of the second capacitor unit 131 is connected to the anode end of the second diode, and the cathode end of the second diode is connected to the first end of the first amplifying transistor 10.

[0063] It is understood that the second diode is a varactor diode, which has the characteristic that the junction capacitance varies with the applied voltage when the PN junction is reverse biased. That is, the junction capacitance increases with increasing reverse bias voltage and decreases with increasing reverse bias voltage. Based on the variable capacitance characteristic of the varactor diode, the parasitic capacitance generated by the second amplifying transistor 11 can be effectively compensated during the operation of the differential power amplifier 100.

[0064] like Figure 3 As shown, in some embodiments, the second variable capacitance unit 132 includes at least one second triode, the base of the second triode is connected to the collector and to the second end of the second capacitor unit 131, and the emitter of the second triode is connected to the first end of the first amplifying transistor 10.

[0065] Optionally, when the second varactor unit 132 includes at least one second triode, the second triode and the second amplifying transistor 11 are both HBT transistors, or the second triode and the second amplifying transistor 11 are both BJT transistors.

[0066] In some embodiments, during operation of the differential power amplifier 100 , the first bias voltage Vdc1 received by the first varactor circuit 12 and the second bias voltage Vdc2 received by the second varactor circuit 13 are of the same magnitude.

[0067] It is understandable that the first bias voltage Vdc1 and the second bias voltage Vdc2 can be bias voltages output by the same power supply or bias voltages output by different voltage sources, as long as the first bias voltage Vdc1 and the second bias voltage Vdc2 are the same in magnitude.

[0068] like Figures 1 to 3 As shown, in some embodiments, the first terminal of the first amplifying transistor 10 is further used to receive the first power supply voltage Vcc1, and the first terminal of the second amplifying transistor 11 is further used to receive the second power supply voltage Vcc2; wherein Vdc1≥V EG1 + Vcc2, and Vdc2 ≥ V EG2 +Vcc1,V EG1 is the on-state voltage of the first varactor unit 122, V EG2 is the on-state voltage of the second variable capacitance unit 132, Vdc1 is the first bias voltage, and Vdc2 is the second bias voltage. By setting Vdc1≥V EG1 +Vcc2 and Vdc2 ≥ V EG2 + Vcc1 can ensure that the first varactor unit 122 and the second varactor unit 132 are sufficiently conductive under the action of the first bias voltage and the second bias voltage, thereby dynamically compensating for the first parasitic capacitance generated during the operation of the first amplifying transistor 10 and the second parasitic capacitance generated during the operation of the second amplifying transistor 11. Exemplarily, the magnitudes of Vcc1 and Vcc2 are equal, and the magnitudes of Vdc1 and Vdc2 are also equal. Optionally, the voltage of the first bias voltage Vdc1 is adjustable. Optionally, the voltage of the second bias voltage Vdc2 is adjustable. Based on the adjustable voltage of the first bias voltage Vdc1, and the magnitude of the first bias voltage Vdc1 can affect the magnitude of the variable capacitance generated by the first varactor unit 122, the magnitude of the variable capacitance generated by the first varactor unit 122 can be adjusted by adjusting the voltage of the first bias voltage Vdc1. Therefore, the change in the parasitic capacitance generated by the first amplifying transistor 10 can be effectively compensated during the operation of the differential power amplifier 100. Similarly, the voltage of the second bias voltage Vdc2 is adjustable, and the magnitude of the second bias voltage Vdc2 can affect the magnitude of the variable capacitance value generated by the second varactor unit 132. Therefore, the magnitude of the variable capacitance value generated by the second varactor unit 132 can be adjusted by adjusting the voltage of the second bias voltage Vdc2. Therefore, the change of the parasitic capacitance generated by the second amplifying transistor 11 can be effectively compensated during the operation of the differential power amplifier 100.

[0069] See also Figure 4 In some embodiments, the differential power amplifier 100 further includes an unbalanced-balanced conversion circuit 20. The input end of the unbalanced-balanced conversion circuit 20 is used to receive an RF input signal. The first output end of the unbalanced-balanced conversion circuit 20 is used to connect to the controlled end of the first amplifying transistor 10. The second output end of the unbalanced-balanced conversion circuit 20 is used to connect to the controlled end of the second amplifying transistor 11. The unbalanced-balanced conversion circuit 20 is used to convert the input signal into a differential signal pair. For example, the RF input signal Rin is converted into a first input signal in1 and a second input signal in2. The first input signal in1 and the second input signal in2 form a differential signal pair, also referred to as a differential input signal. Optionally, the unbalanced-balanced conversion circuit 20 may include a balun.

[0070] In some embodiments, see Figure 5 The differential power amplifier 100 includes a plurality of first amplifying transistors 10 and a plurality of second amplifying transistors 11. The plurality of first amplifying transistors 10 are connected in parallel and have a first common input terminal and a first common output terminal, and the plurality of second amplifying transistors 11 are connected in parallel and have a second common input terminal and a second common output terminal.

[0071] Among them, multiple parallel-connected first amplifying transistors 10 share a first varactor circuit 12, the input end of the first varactor circuit 12 is connected to the first common input end, and the input end of the first varactor circuit 12 is connected to the second common output end, and multiple parallel-connected second amplifying transistors 11 share a second varactor circuit 13, the input end of the second varactor circuit 13 is connected to the second common input end of the second amplifying transistors 11, and the input end of the second varactor circuit 13 is connected to the first common output end.

[0072] It can be understood that the number of first amplifying transistors 10 and the number of second amplifying transistors 11 in the differential power amplifier 100 are the same, and the multiple first amplifying transistors 10 can be understood as the number of first amplifying transistors 10 in the differential power amplifier 100 is at least two. Similarly, the multiple second amplifying transistors 11 can be understood as the number of second amplifying transistors 11 in the differential power amplifier 100 is at least two.

[0073] like Figure 5 As shown, for ease of understanding, the differential power amplifier 100 is described with the number of the first amplifying transistor 10 and the number of the second amplifying transistor 11 being two each as an example, but is not limited to the number of the first amplifying transistor 10 and the second amplifying transistor 11 being only two.

[0074] In this embodiment, the first varactor circuit 12 is shared by multiple first amplifying transistors 10 , and the first varactor circuit 13 is shared by multiple second amplifying transistors 11 , which can effectively save the area of the differential power amplifier and facilitate miniaturization of the differential power amplifier.

[0075] In some other embodiments, the differential power amplifier 100 includes a plurality of first amplifying transistors 10 and a plurality of second amplifying transistors 11. The plurality of first amplifying transistors 10 are connected in parallel and have a first common input terminal and a first common output terminal, and the plurality of second amplifying transistors 11 are connected in parallel and have a second common input terminal and a second common output terminal.

[0076] Among them, each first amplifying transistor 10 corresponds to a first varactor circuit 12, the input end of each first varactor circuit 12 is connected to the controlled end of the corresponding first amplifying transistor 10, the output end of each first varactor circuit 12 is connected to the first end of the corresponding second amplifying transistor 11, and each second amplifying transistor 11 corresponds to a second varactor circuit 13, the input end of each second varactor circuit 13 is connected to the controlled end of the corresponding second amplifying transistor 11, and the output end of each second varactor circuit 13 is connected to the first end of the corresponding first amplifying transistor 10.

[0077] In this embodiment, each first amplifying transistor 10 corresponds to a first varactor circuit 12 for capacitance compensation, and at the same time, each second amplifying transistor 11 corresponds to a second varactor circuit 13 for capacitance supplementation, thereby achieving more accurate capacitance supplementation during the operation of the differential power amplifier.

[0078] See also Figure 6 In some embodiments, the differential power amplifier 100 further includes a third amplifying transistor 15 and a fourth amplifying transistor 16, wherein the controlled end of the third amplifying transistor 15 is used to receive the first initial input signal, and the first end of the third amplifying transistor 15 is used to connect to the controlled end of the first amplifying transistor 10; the controlled end of the fourth amplifying transistor 16 is used to receive the second initial input signal, and the first end of the fourth amplifying transistor 16 is used to connect to the controlled end of the second amplifying transistor 11.

[0079] Optionally, the third amplifying transistor 15 may be an HBT transistor, a BJT transistor or a field effect transistor.

[0080] Optionally, the fourth amplifying transistor 16 may be an HBT transistor, a BJT transistor or a field effect transistor.

[0081] Optionally, the third amplifying transistor 15 and the fourth amplifying transistor 16 are transistors of the same type. For example, the third amplifying transistor 15 and the fourth amplifying transistor 16 are both HBT transistors, or the third amplifying transistor 15 and the fourth amplifying transistor 16 are both BJT transistors.

[0082] like Figure 6 As shown, the third amplifier transistor 15 and the fourth amplifier transistor 16 constitute a pre-stage amplifier circuit for the input signal, and the first amplifier transistor 10 and the second amplifier transistor 11 constitute a post-stage amplifier circuit for the input signal, which are used to re-amplify the signal after the pre-stage amplification. For example, the first amplifier transistor 10 can re-amplify the signal amplified by the third amplifier transistor 15, and the second amplifier transistor 11 can re-amplify the signal amplified by the fourth amplifier transistor 16.

[0083] like Figure 6 As shown, the differential power amplifier 100 optionally further includes a third varactor circuit 17 and a fourth varactor circuit 18, wherein both the third varactor circuit 17 and the fourth varactor circuit 18 can generate variable capacitance, and the input terminal of the third varactor circuit 17 is connected to the controlled terminal of the third amplifying transistor 15, the output terminal of the third varactor circuit 17 is connected to the first terminal of the fourth amplifying transistor 16, and the bias terminal of the third varactor circuit 17 is used to receive a third bias voltage Vdc3. The input terminal of the fourth varactor circuit 18 is connected to the controlled terminal of the fourth amplifying transistor 16, the output terminal of the fourth varactor circuit 18 is connected to the first terminal of the third amplifying transistor, and the bias terminal of the fourth varactor circuit 18 is used to receive a fourth bias voltage Vdc4.

[0084] During operation of the differential power amplifier 100 , the third varactor circuit 17 can generate a third variable capacitor to compensate for the parasitic capacitance of the third amplifying transistor 15 , and the fourth varactor circuit 18 can generate a fourth variable capacitor to compensate for the parasitic capacitance of the fourth amplifying transistor 16 .

[0085] Optionally, the third varactor circuit 17 has the same circuit structure as the first varactor circuit 12. For example, the third varactor circuit 17 includes a third capacitor unit and a third varactor unit. The first end of the third capacitor unit is connected to the controlled end of the third amplifying transistor 15. The second end of the third capacitor unit is connected to the anode end of the third varactor unit and is used to receive the third bias voltage Vdc3. The cathode end of the third varactor unit is connected to the first end of the fourth amplifying transistor 16.

[0086] The fourth varactor circuit 18 includes a fourth capacitor unit and a fourth varactor unit, the first end of the fourth capacitor unit is connected to the controlled end of the fourth amplifying transistor 16, the second end of the fourth capacitor unit is connected to the anode end of the fourth varactor unit and is used to receive the fourth bias voltage Vdc4, and the cathode end of the fourth varactor unit is connected to the first end of the third amplifying transistor 15.

[0087] Optionally, the third varactor unit has the same circuit structure as the first varactor unit 122 , and the fourth varactor unit has the same circuit structure as the second varactor unit 132 , which will not be described in detail here.

[0088] During operation of the differential power amplifier 100 , the third amplifying transistor 15 generates a corresponding third parasitic capacitance and the fourth amplifying transistor 16 generates a corresponding fourth parasitic capacitance. The magnitudes of the corresponding parasitic capacitances vary with the output power of the differential power amplifier 100 .

[0089] In this embodiment, the differential power amplifier 100 is provided with a third varactor circuit 17 and a fourth varactor circuit 18. During the operation of the differential power amplifier 100, the third varactor circuit 17 can generate a third variable capacitance to dynamically compensate for the third parasitic capacitance of the third amplifying transistor 15, and the fourth varactor circuit 18 can generate a fourth variable capacitance to dynamically compensate for the fourth parasitic capacitance of the fourth amplifying transistor 16, thereby providing dynamic compensation that is adapted to the changes in the third parasitic capacitance and the fourth parasitic capacitance.

[0090] Furthermore, compared with the method of using fixed capacitors to compensate for parasitic capacitance, the embodiment of the present application can more effectively improve the phase accuracy and gain accuracy between the input power and output power of the differential power amplifier 100, and ultimately more effectively improve the gain and linearity of the differential power amplifier.

[0091] like Figure 6 As shown, optionally, in the case where the differential power amplifier 100 has a pre-stage amplifier circuit and a post-stage amplifier circuit, the differential power amplifier 100 further includes a first inter-stage matching circuit 19a and a second inter-stage matching circuit 19b, wherein a first end of the first inter-stage matching circuit 19a is connected to a first end of the third amplifying transistor 15, and a second end of the first inter-stage matching circuit 19a is connected to a controlled end of the first amplifying transistor 10. A first end of the second inter-stage matching circuit 19b is connected to a first end of the fourth amplifying transistor 16, and a second end of the second inter-stage matching circuit 19b is connected to a controlled end of the second amplifying transistor 11.

[0092] In this embodiment, an inter-stage matching circuit is provided between the front-stage amplifier circuit and the rear-stage amplifier circuit of the differential power amplifier 100 to achieve impedance matching between the front-stage and rear-stage circuits, thereby reducing the loss during RF signal transmission.

[0093] See also Figure 7 , Figure 7 A schematic diagram of the circuit structure of a power amplifier provided in an embodiment of the present application.

[0094] like Figure 7 As shown, the power amplifier 200 includes a power distribution circuit 201, a first amplifier circuit 202, a second amplifier circuit 203, and a power combining circuit 204. The power distribution circuit 204 is configured to distribute the power of an input signal and output a first signal and a second signal having a preset phase difference. The first amplifier circuit 202 is configured to amplify the first signal output by the power distribution circuit 204. The second amplifier circuit 203 is configured to amplify the second signal output by the power distribution circuit 204. The power combining circuit 204 is configured to combine and output the first signal amplified by the first amplifier circuit 202 and the second signal amplified by the second amplifier circuit 203. Furthermore, at least one of the first amplifier circuit 202 and the second amplifier circuit 203 includes an unbalanced-balanced converter circuit 20 and a differential power amplifier 100.

[0095] Optionally, the power amplifier 200 further includes an input matching circuit connected to the input end of the power combining circuit 204 , and the input signal is input to the power amplifier 200 through the input matching circuit.

[0096] In some embodiments, the second amplifier circuit 203 is turned on when the output power of the first amplifier circuit 202 reaches a peak. Furthermore, the power combining circuit 204 includes a phase shifting unit 2041 and a combining unit 2042. The phase shifting unit 2041 is configured to phase-shift the second signal amplified by the second amplifier circuit 203 so that the phase of the second signal after the phase shift meets a preset requirement. The combining unit 2042 is configured to combine the first signal amplified by the first amplifier circuit 202 and the phase-shifted second signal and output the combined signal.

[0097] It can be understood that the preset phase difference between the first signal and the second signal can be set as needed. For example, the phase difference between the first signal and the second signal is 90°. The phase difference between the first signal and the second signal can also be 60°, 180°, etc.

[0098] like Figure 7 As shown, for ease of understanding, this embodiment is described by taking the phase difference between the first signal and the second signal as 90° as an example.

[0099] After power distribution by power distribution circuit 201, input signal Rin is generated into first signal Rin1 and second signal Rin2 with a 90° phase difference. First signal Rin1 is amplified by first amplifier circuit 202, and second signal Rin2 is amplified by second amplifier circuit 203. Both first amplifier circuit 202 and second amplifier circuit 203 are equipped with unbalanced-balanced conversion circuit 20 and differential power amplifier 100. Due to the good linearity and gain of differential power amplifier 100, it can effectively amplify the input signal.

[0100] The amplified second signal is phase-shifted by phase shifter 2041 of power combiner circuit 204 so that the phase difference between the amplified first signal and the second signal meets a preset condition, including, but not limited to, a phase difference between the amplified first signal and the second signal of 160°-180°. Combining unit 2042 of power combiner circuit 204 combines the first signal amplified by first amplifier circuit 202 and the phase-shifted second signal, and outputs the combined signal. Ultimately, the output signal can better meet user needs.

[0101] It can be understood that the circuit structure, components or circuit parameters and related beneficial effects of this embodiment that are the same as those in the previous embodiment are not described in detail here. For related detailed descriptions, reference can be made to the previous implementation. For example, the specific circuit structure and function of the differential power amplifier 100 can refer to the related description of the previous implementation and are not described in detail here.

[0102] See also Figure 8 , Figure 8 A block diagram of a radio frequency front-end module is provided in an embodiment of the present application.

[0103] like Figure 8 As shown, the RF front-end module 300 is used to adapt to the antenna module 400 to receive and / or transmit signals. Among them, the RF front-end module is a component that integrates two or more discrete devices such as RF switches, low-noise amplifiers, filters, duplexers, power amplifiers, transformers, etc. into an independent module, thereby improving the integration and hardware performance of the RF front-end module and miniaturizing its size. Specifically, the RF front-end module can be applied to 4G and 5G communication devices such as smartphones, tablets, and smart watches. Optionally, at least two discrete devices in the RF front-end module can form a signal receiving link and / or a signal transmitting link.

[0104] Exemplarily, the RF front-end module 300 includes at least a signal input port 301, a signal output port 302, and an amplifier circuit 303, which is used to amplify the signal. For example, the RF front-end module 300 includes at least a signal transmission link, and the amplifier circuit 303 is a power amplifier in the signal transmission link.

[0105] The amplifier circuit 303 in the signal transmission chain is at least used to amplify the signal input through the signal input port 301 and output the amplified signal to the signal output port 302, and then output it to the antenna module 400 through the signal output port 12, thereby radiating the signal to the external space through the antenna module 400. The amplifier circuit 303 includes at least the differential power amplifier 100 or the power amplifier 200.

[0106] For another example, the RF front-end module 300 includes at least a signal receiving mode. When the RF front-end module 300 operates in the signal receiving mode, the amplification circuit 303 is also used to amplify the signal received through the antenna module 400 and output the amplified signal to the signal input port 301, so that the signal can be transmitted to the corresponding signal processing module through the signal input port 301.

[0107] It is understandable that the key performance goal of the new generation of mobile communication technologies, such as the 5th and 6th generations, is to significantly increase the transmission rate compared to 4G. Therefore, the new generation of communication technologies requires the use of RF front-end modules with higher frequencies, larger bandwidths, and higher-order QAM modulation, which places more stringent requirements on the design of the RF front-end modules. The differential power amplifier, power amplifier, and RF front-end module of the embodiments of the present application, by providing a first varactor circuit and a second varactor circuit, dynamically compensate for the parasitic capacitance of the first amplifying transistor and the parasitic capacitance of the second amplifying transistor of the differential power amplifier, thereby reducing the influence of the parasitic capacitance of the differential power amplifier itself changing with the increase of power due to the increase of power, thereby effectively improving the phase accuracy and gain accuracy between the input power and output power of the differential power amplifier, and ultimately effectively improving the gain and linearity of the differential power amplifier / power amplifier. Therefore, the differential power amplifier, power amplifier, and RF front-end module of the embodiments of the present application can be applied to the new generation of mobile communication technologies, such as the 5th and 6th generations, to improve the quality of mobile communications.

[0108] It should be noted that the circuit structure, components or circuit parameters and related beneficial effects of this embodiment that are the same as those of the previous embodiment are not described in detail here, and the relevant detailed description can refer to the previous implementation method.

[0109] It will also be understood that the term "and / or" used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0110] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present application, and such modifications or substitutions should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A differential power amplifier, characterized in that: include: a first amplifying transistor, a second amplifying transistor, a first varactor circuit, and a second varactor circuit; The controlled end of the first amplifying transistor is used to receive a first input signal, the first end of the first amplifying transistor is used to output the first input signal processed by the first amplifying transistor, and the second end of the first amplifying transistor is used to be grounded; The controlled end of the second amplifying transistor is used to receive a second input signal, the first end of the second amplifying transistor is used to output the second input signal processed by the second amplifying transistor, and the second end of the second amplifying transistor is grounded; The first input signal and the second input signal are differential input signals, the input terminal of the first varactor circuit is connected to the controlled terminal of the first amplifying transistor, the output terminal of the first varactor circuit is connected to the first terminal of the second amplifying transistor, and the bias terminal of the first varactor circuit is used to receive a first bias voltage; The output end of the second varactor circuit is connected to the first end of the first amplifying transistor, and the bias end of the second varactor circuit is used to receive a second bias voltage.

2. The differential power amplifier according to claim 1, wherein: The first varactor circuit includes a first capacitor unit and a first varactor unit, wherein a first end of the first capacitor unit is connected to the controlled end of the first amplifying transistor, a second end of the first capacitor unit is connected to an anode end of the first varactor unit and is configured to receive a first bias voltage, and a cathode end of the first varactor unit is connected to the first end of the second amplifying transistor; In addition, the second varactor circuit includes a second capacitor unit and a second varactor unit, the first end of the second capacitor unit is connected to the controlled end of the second amplifying transistor, the second end of the second capacitor unit is connected to the anode end of the second varactor unit and is used to receive a second bias voltage, and the cathode end of the second varactor unit is connected to the first end of the first amplifying transistor.

3. The differential power amplifier according to claim 2, wherein: During operation of the differential power amplifier, the variable capacitance value generated by the first varactor unit is less than 0.2 pF, and the variable capacitance value generated by the second varactor unit is less than 0.2 pF.

4. The differential power amplifier according to claim 3, wherein: During the operation of the differential power amplifier, the difference between the variable capacitance value generated by the first varactor unit and the parasitic capacitance value generated by the first amplifying transistor is less than a first threshold; the difference between the variable capacitance value generated by the second varactor unit and the parasitic capacitance value generated by the second amplifying transistor is less than a second threshold.

5. The differential power amplifier according to claim 2, wherein: The first variable capacitance unit includes at least one first diode, the second end of the first capacitance unit is connected to the anode end of the first diode, and the cathode end of the first diode is connected to the first end of the second amplifying transistor; Alternatively, the first variable capacitance unit includes at least one first transistor, the base of the first transistor is connected to the collector and to the second end of the first capacitor unit, and the emitter of the first transistor is connected to the first end of the second amplifying transistor.

6. The differential power amplifier according to claim 2, wherein: The second varactor unit includes at least one second diode, the second end of the second capacitor unit is connected to the anode end of the second diode, and the cathode end of the second diode is connected to the first end of the first amplifying transistor; Alternatively, the second varactor unit includes at least one second triode, the base of the second triode is connected to the collector and to the second end of the second capacitor unit, and the emitter of the second triode is connected to the first end of the first amplifying transistor.

7. The differential power amplifier according to claim 2, wherein: The first capacitor unit includes at least one first capacitor, and the capacitance value of the first capacitor unit is less than 0.5 pF; And / or, the second capacitor unit includes at least one second capacitor, and the capacitance value of the second capacitor unit is less than 0.5 pF.

8. The differential power amplifier according to claim 7, wherein: The capacitance value of the first capacitor unit is greater than 0.05 pF and less than 0.3 pF; and / or the capacitance value of the second capacitor unit is greater than 0.05 pF and less than 0.3 pF.

9. The differential power amplifier according to claim 1, wherein: During operation of the differential power amplifier, the first bias voltage received by the first varactor circuit has the same magnitude as the second bias voltage received by the second varactor circuit.

10. The differential power amplifier according to claim 2, wherein: The first terminal of the first amplifying transistor is further used to receive a first power supply voltage Vcc1, and the first terminal of the second amplifying transistor is further used to receive a second power supply voltage Vcc2; Where Vdc1≥V EG1 + Vcc2, and Vdc2 ≥ V EG2 +Vcc1,V EG1 is the on-state voltage of the first variable capacitance unit, V EG2 is the on-state voltage of the second varactor unit, Vdc1 is the first bias voltage, and Vdc2 is the second bias voltage.

11. The differential power amplifier according to claim 10, wherein: The voltage of the first bias voltage is adjustable; and / or the voltage of the second bias voltage is adjustable.

12. The differential power amplifier according to claim 1, wherein: The differential power amplifier includes a plurality of first amplifying transistors and a plurality of second amplifying transistors; the plurality of first amplifying transistors are connected in parallel and have a first common input terminal and a first common output terminal, and the plurality of second amplifying transistors are connected in parallel and have a second common input terminal and a second common output terminal; Each of the first amplifying transistors corresponds to a first varactor circuit, the input end of each of the first varactor circuits is connected to the controlled end of the corresponding first amplifying transistor, the output end of each of the first varactor circuits is connected to the first end of the corresponding second amplifying transistor, and each of the second amplifying transistors corresponds to a second varactor circuit, the input end of each of the second varactor circuits is connected to the controlled end of the corresponding second amplifying transistor, and the output end of each of the second varactor circuits is connected to the first end of the corresponding first amplifying transistor; Alternatively, a plurality of first amplifier transistors connected in parallel share one first varactor circuit, the input end of the first varactor circuit is connected to the first common input end, the input end of the first varactor circuit is connected to the second common output end, and a plurality of second amplifier transistors connected in parallel share one second varactor circuit, the input end of the second varactor circuit is connected to the second common input end of the second amplifier transistor, and the input end of the second varactor circuit is connected to the first common output end.

13. The differential power amplifier according to claim 5 or 6, wherein: The first amplifying transistor is an HBT transistor, a BJT transistor or a field effect transistor; and / or the second amplifying transistor is an HBT transistor, a BJT transistor or a field effect transistor.

14. The differential power amplifier according to claim 13, wherein: In the case where the first varactor unit includes at least one first triode, the first triode and the first amplifying transistor are both HBT transistors, or the first triode and the first amplifying transistor are both BJT transistors; In the case where the second varactor unit includes at least one second triode, the second triode and the second amplifying transistor are both HBT transistors, or the second triode and the second amplifying transistor are both BJT transistors.

15. The differential power amplifier according to claim 1, wherein: The differential power amplifier further includes a balun, wherein the balun includes a primary coil and a secondary coil coupled to the primary coil; The first input end of the primary coil can be used to receive a signal outputted via the first end of the first amplifying transistor, the second input end of the primary coil can be used to receive a signal outputted via the first end of the second amplifying transistor, and the secondary coil is used to connect a load.

16. The differential power amplifier according to claim 1, wherein: The differential power amplifier also includes a third amplifying transistor and a fourth amplifying transistor, wherein the controlled end of the third amplifying transistor is used to receive a first initial input signal, and the first end of the third amplifying transistor is used to connect to the controlled end of the first amplifying transistor; the controlled end of the fourth amplifying transistor is used to receive a second initial input signal, and the first end of the fourth amplifying transistor is used to connect to the controlled end of the second amplifying transistor.

17. The differential power amplifier according to claim 16, wherein: The differential power amplifier also includes the third varactor circuit and the fourth varactor circuit, wherein the third varactor circuit and the fourth varactor circuit can both generate variable capacitance, and the input end of the third varactor circuit is connected to the controlled end of the third amplifying transistor, the output end of the third varactor circuit is connected to the first end of the fourth amplifying transistor, and the bias end of the third varactor circuit is also used to connect the input end of the fourth varactor circuit to the controlled end of the fourth amplifying transistor, and the output end of the fourth varactor circuit is connected to the first end of the third amplifying transistor.

18. The differential power amplifier according to claim 16, wherein: The differential power amplifier also includes a first inter-stage matching circuit and a second inter-stage matching circuit, wherein the first end of the first inter-stage matching circuit is connected to the first end of the third amplifying transistor, and the second end of the first inter-stage matching circuit is connected to the controlled end of the first amplifying transistor; the first end of the second inter-stage matching circuit is connected to the first end of the fourth amplifying transistor, and the second end of the second inter-stage matching circuit is connected to the controlled end of the second amplifying transistor.

19. A differential power amplifier, characterized in that: include: a first amplifying transistor, a second amplifying transistor, a first varactor circuit, and a second varactor circuit; The controlled end of the first amplifying transistor is used to receive a first input signal, the first end of the first amplifying transistor is used to output the first input signal processed by the first amplifying transistor, and the second end of the first amplifying transistor is used to be grounded; The controlled end of the second amplifying transistor is used to receive a second input signal, the first end of the second amplifying transistor is used to output the second input signal processed by the second amplifying transistor, and the second end of the second amplifying transistor is grounded; The first input signal and the second input signal are differential input signals, the input end of the first varactor circuit is connected to the controlled end of the first amplifying transistor, the output end of the first varactor circuit is connected to the first end of the second amplifying transistor, and during operation of the differential power amplifier, the first varactor circuit can generate a first variable capacitance to compensate for the parasitic capacitance of the first amplifying transistor; The input end of the second varactor circuit is connected to the controlled end of the second amplifying transistor, the output end of the second varactor circuit is connected to the first end of the first amplifying transistor, and during the operation of the differential power amplifier, the second varactor circuit can generate a second variable capacitance to compensate for the parasitic capacitance of the second amplifying transistor.

20. A power amplifier, characterized in that: include: A power distribution circuit, configured to distribute the power of an input signal and output a first signal and a second signal with a preset phase difference; a first amplifier circuit, configured to amplify the first signal; a second amplifying circuit, configured to amplify the second signal; a power synthesis circuit, configured to synthesize and output the first signal amplified by the first amplifying circuit and the second signal amplified by the second amplifying circuit; At least one of the first amplifying circuit and the second amplifying circuit includes an unbalanced-balanced conversion circuit and the differential power amplifier according to any one of claims 1 to 19.

21. The power amplifier according to claim 20, wherein: The second amplifying circuit is turned on when the output power of the first amplifying circuit reaches a peak value; The power synthesis circuit includes a phase shift unit and a synthesis unit, wherein the phase shift unit is used to perform phase shift on the second signal amplified by the second amplifying circuit; The synthesis unit is used to synthesize and output the first signal amplified by the first amplifier circuit and the second signal after phase shifting.

22. A radio frequency front-end module, characterized in that: include: The differential power amplifier according to any one of claims 1 to 19, or the power amplifier according to claim 21.

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