Novel SPAD active quenching reset circuit based on positive feedback regulation and control

Abstract

The invention discloses a novel SPAD active quenching reset circuit based on positive feedback regulation and control, and belongs to the technical field of semiconductor photoelectric devices. Through the design of the cross-coupled MOS tube quenching module, the avalanche voltage can be rapidly detected when avalanche occurs in the SPAD device, the avalanche current is rapidly cut off by using a positive feedback mechanism, and rapid quenching of the SPAD device is realized. Compared with a traditional passive quenching circuit, the passive quenching circuit has the advantages that the quenching speed is greatly increased, the dead time of an SPAD device is effectively shortened, the time resolution and the counting rate of the SPAD device are increased, and the passive quenching circuit is simple in structure, does not introduce an integrated module, and has a smaller circuit area and more flexible time sequence regulation and control.

Description

Technical Field

[0001] The present invention relates to a novel SPAD active quenching reset circuit based on positive feedback regulation, belonging to the technical field of semiconductor optoelectronic devices. Background Art

[0002] With the rapid development of autonomous driving, robotic navigation, 3D modeling, and other fields, the performance of laser radar (LiDAR), as a core sensing device, directly determines the accuracy and real-time performance of environmental detection. LiDAR constructs high-resolution 3D point clouds by emitting laser pulses and receiving reflected signals using the time-of-flight (ToF) principle. Single-photon avalanche diodes (SPADs) have become the detector of choice for the new generation of photon-counting LiDARs due to their single-photon sensitivity and picosecond temporal resolution. However, in long-range, high-dynamic scenarios, LiDAR systems place stricter demands on key SPAD device indicators such as detection efficiency and dead time.

[0003] SPADs rely on the avalanche effect to detect single photons. Upon detecting a photon, they generate a macroscopic current in the milliampere range. Due to the self-sustaining nature of avalanches, in the absence of external interference, the SPAD device remains in an avalanche-quenched state until the device burns out. Therefore, a quenching reset circuit is required to dynamically regulate the potential difference across the SPAD device, keeping it in a constant cycle of detection, quenching, and resetting.

[0004] Traditional quenching reset circuits rely primarily on the series resistor of the SPAD device to passively attenuate the avalanche current. While the circuit structure is simple, the reliance on resistance to gradually reduce the current until the avalanche stops results in a slow quenching process, resulting in a long dead time for the SPAD device. This, in turn, fails to meet the high-precision and high-detection efficiency requirements of lidar systems. Subsequently, active quenching circuits with feedback mechanisms have emerged. By adding a switching path to the traditional circuit to actively cut off the avalanche current, the quenching time can be shortened to a few nanoseconds. However, existing solutions generally suffer from high circuit complexity and inflexible timing. A gated quenching reset circuit combines gating technology with a quenching reset function. By applying a gate signal to one end of the SPAD device, the device operates when the gate signal is high and disables it when it is low. In other words, the gate signal controls the device's operating state. However, the design of the gate signal in this circuit requires the knowledge of the photon arrival time, making it suitable only for scenarios where the arrival time of the photon is known.

[0005] The quench reset circuit has a direct impact on the performance of LiDAR. Excessive dead time and insufficient quenching can hinder LiDAR's application in high-speed, high-precision photon detection scenarios. Therefore, developing a fast, efficient, and precisely controllable quench reset circuit is an urgent challenge in this field. Summary of the Invention

[0006] In order to solve the current problems, the present invention provides a new SPAD active quenching and reset circuit based on positive feedback control, which aims to overcome the shortcomings of the existing quenching and reset circuit, realize the rapid quenching and precise reset of the SPAD device, suppress the false triggering caused by post-pulse noise and residual carriers, improve the system's time resolution and counting rate, and enhance its performance in high-speed photon detection applications.

[0007] The first object of the present invention is to provide a novel SPAD active quenching and reset circuit based on positive feedback control, comprising a positive feedback quenching module, an adjustable delay module, a reset module, an output shaping module and a SPAD device;

[0008] Among them, the positive feedback quenching module is used to detect the avalanche voltage and use positive feedback to quench the SPAD device, including a positive feedback loop and a diode-connected NMOS tube, and the positive feedback loop is composed of three PMOS tubes and one NMOS tube cross-coupled; the adjustable delay module is used to delay the quenching signal to ensure that the anode end of the SPAD device is completely quenched before starting the reset module to reset the circuit, including two symmetrically arranged PMOS tubes and two NMOS tubes and an inverter; the reset module is used to reset the cathode level of the SPAD device, including an NMOS tube; the output shaping module is used to output the output signal of the corresponding pulse width, including two PMOS tubes, one NMOS tube and an inverter.

[0009] Optionally, a positive feedback quenching module includes a first NMOS tube MN1, a third NMOS tube MN3, a first PMOS tube MP1, a second PMOS tube MP2, and a third PMOS tube MP3, wherein the first NMOS tube MN1 adopts a diode connection, its gate and drain are simultaneously connected to the anode of the SPAD device, and the source is grounded; the third NMOS tube MN3, the first PMOS tube MP1, the second PMOS tube MP2, and the third PMOS tube MP3 are cross-coupled to form a positive feedback loop.

[0010] Optionally, in the positive feedback quenching module, the source of the first PMOS tube MP1 is connected to the drain of the second PMOS tube MP2; the gate of the first PMOS tube MP1 is connected to the drain of the third PMOS tube MP3 and the third NMOS tube MN3; the drain of the first PMOS tube MP1 is connected to the gate and drain of the first NMOS tube MN1, the gate of the third PMOS tube MP3 and the third NMOS tube MN3, and the anode of the SPAD device; the gate of the second PMOS tube MP2 is connected to the output end of the adjustable delay module; the source of the second PMOS tube MP2 and the third PMOS tube MP3 is connected to the power supply VDD; and the source of the first NMOS tube MN1 and the third NMOS tube MN3 is grounded.

[0011] Optionally, the adjustable delay module includes a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, and a second inverter INV2; wherein the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 are symmetrical with the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6, the source of the seventh PMOS transistor MP7 is connected to the power supply VDD, the gate of the seventh PMOS transistor MP7 is connected to the voltage Vctrlp, the drain of the seventh PMOS transistor MP7 is connected to the source of the sixth PMOS transistor MP6, and the gate of the sixth PMOS transistor MP6 is connected to The gate of the fifth NMOS transistor MN5 is connected to serve as the input of the adjustable delay module. The drain of the sixth PMOS transistor MP6 is connected to the drain of the fifth NMOS transistor MN5 and the input of the second inverter INV2. The output of the second inverter INV2 serves as the output of the adjustable delay module. The source of the fifth NMOS transistor MN5 is connected to the drain of the sixth NMOS transistor MN6. The gate of the sixth NMOS transistor MN6 is connected to the voltage Vctrln. The source of the sixth NMOS transistor MN6 is grounded. The charge and discharge currents are regulated by the external voltages Vctrlp and Vctrln to thereby delay the quenching signal of the positive feedback quenching module.

[0012] Optionally, in the reset module, the drain of the second NMOS tube MN2 is connected to the anode of the SPAD device and the input end of the adjustable delay module, the gate of the second NMOS tube MN2 is connected to the gate of the second PMOS tube MP2 and the output end of the adjustable delay module, and the source of the second NMOS tube MN2 is grounded; the second NMOS tube MN2 and the second PMOS tube MP2 are synchronously driven by the reset signal to ensure timing isolation between the quenching and reset stages.

[0013] Optionally, in the output shaping module, the source of the fifth PMOS tube MP5 is connected to VDD, the gate of the fifth PMOS tube MP5 is connected to the voltage Vq, the drain of the fifth PMOS tube MP5 is connected to the source of the fourth PMOS tube MP4, the gate of the fourth PMOS tube MP4 is connected to the gate of the fourth NMOS tube MN4 and the anode of the SPAD device, the drain of the fourth PMOS tube MP4 is connected to the drain of the fourth NMOS tube MN4 and the input end of the first inverter INV1, the output end of the first inverter INV1 outputs the Vout signal, and the source of the fourth NMOS tube MN4 is grounded.

[0014] Optionally, the second NMOS transistor MN2 is a large-sized transistor with a width-to-length ratio W / L greater than 20 / 1.

[0015] A second object of the present invention is to provide a SPAD active quenching method, which is implemented based on the above-mentioned novel SPAD active quenching reset circuit based on positive feedback control, and the method includes:

[0016] Step 1: At the initial stage of the circuit, the cathode of the SPAD device is connected to the bias voltage V Bias , the anode of the SPAD device is at a low potential, the SPAD device is in Geiger mode, and enters the detection stage; the low potential of the anode of the SPAD device acts on the gates of MP3 and MN3 to output a high level to the gate of MP1, and MP1 is turned off; the low potential of the anode of the SPAD device reaches the gates of MN2 and MP2 after a delay, MN2 is turned off, and MP2 is turned on; MN1 is connected as a resistor using a diode method, and the series branch of the SPAD device and MN1 is used to sense the avalanche current;

[0017] Step 2: At t1, the SPAD device is excited by photons, generating a large current in the milliampere level. After passing through MN1, the voltage of the anode of the SPAD device will be raised. After comparison between MP3 and MN3, a low potential is output to the gate of MP1, and the MP1 tube is turned on. Through the operation of the positive feedback circuit, the anode voltage of the SPAD device is directly pulled to VDD by the quenching branch of MP2 and MP1. At this time, the anode voltage of the SPAD device is V Bias , the cathode voltage of the SPAD device is VDD, exiting the Geiger mode, and the high level of the anode of the SPAD device will output a square wave signal of corresponding pulse width after being processed by the output shaping module for reading by the back-end circuit;

[0018] Step 3: At time t2, after a delay of Delay, the delay time is t2-t1, the SPAD device has been completely quenched, and the high potential of the anode of the SPAD device is transmitted to the gates of MP2 and MN2; although the quenching signal is low, the MP2 tube is cut off and the quenching branch is closed; the MN2 tube is turned on, and the reset branch where MN2 is located is opened, and at time t3, the high potential of the anode of the SPAD device is pulled to ground; at this time, the cathode voltage of the SPAD device is V Bias , the anode potential of the SPAD device is ground, and the SPAD device returns to Geiger mode. At time t4, after a delay of t4-t3, MP2 turns on, and the quenching branch remains closed; MN2 turns off, the reset branch closes, and the SPAD device re-enters the detection phase.

[0019] The third object of the present invention is to provide a laser radar detector, which uses the above-mentioned new SPAD active quenching and reset circuit based on positive feedback control to quench and reset the SPAD device.

[0020] The beneficial effects of the present invention are:

[0021] The cross-coupled MOS transistor quenching module design can quickly detect the avalanche voltage when a SPAD device avalanches, and utilizes a positive feedback mechanism to quickly cut off the avalanche current, achieving rapid quenching of the SPAD device. Compared with traditional passive quenching circuits, the present invention significantly improves the quenching speed, effectively shortening the dead time of the SPAD device and improving the device's time resolution and count rate.

[0022] The coordinated operation of the reset module and the adjustable delay module ensures that the reset operation is performed after the SPAD device is completely quenched, avoiding resetting before the SPAD device is completely quenched, thereby ensuring the stability and reliability of the circuit. By precisely controlling the reset time, the SPAD device can quickly return to the detection state, improving the real-time performance and detection efficiency of the lidar system.

[0023] The output shaping module shapes the anode voltage of the SPAD device, eliminating noise and interference in the signal and ensuring the regularity of the output signal, which is beneficial for reading and processing by the back-end circuit. This improves the quality and stability of the signal and enhances the anti-interference ability of the LiDAR system in complex environments.

[0024] Compared to existing active quenching circuits with feedback mechanisms, the circuit structure of the present invention is relatively simple, reducing circuit complexity and cost. Furthermore, through rational module design and device selection, the circuit's integration and reliability are improved, facilitating large-scale production and application. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0026] Figure 1 This is a schematic diagram of the novel SPAD active quenching and reset circuit based on positive feedback regulation provided by the present invention.

[0027] Figure 2 This is a specific circuit schematic diagram of the adjustable delay module in the novel SPAD active quenching reset circuit based on positive feedback control provided by the present invention.

[0028] Figure 3 This is a flow chart of one working cycle of the novel SPAD active quenching reset circuit based on positive feedback control provided by the present invention.

[0029] Figure 4 This is a simulation result diagram of the working process of the new SPAD active quenching reset circuit based on positive feedback control provided by the present invention. DETAILED DESCRIPTION

[0030] To make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0031] Example 1

[0032] This embodiment provides a novel SPAD active quenching reset circuit based on positive feedback control, such as Figure 1 As shown, the circuit includes a positive feedback quenching module, an adjustable delay module, a reset module, an output shaping module and a SPAD device.

[0033] Among them, the positive feedback quenching module includes a first NMOS tube MN1, a third NMOS tube MN3, a first PMOS tube MP1, a second PMOS tube MP2, and a third PMOS tube MP3, which are used to detect the avalanche voltage and use positive feedback to quench the SPAD device; the reset module includes a second NMOS tube MN2, which is used to reset the cathode level of the SPAD device; the adjustable delay module includes a sixth PMOS tube MP6, a seventh PMOS tube MP7, a fifth NMOS tube MN5, a sixth NMOS tube MN6, and a second inverter INV2, which is used to delay the quenching signal to ensure that the anode end of the SPAD device is completely quenched; the output shaping module includes a fourth NMOS tube MN4, a fourth PMOS tube MP4, a fifth PMOS tube MP4 and a first inverter INV1, which is used to output an output signal corresponding to the pulse width.

[0034] The specific device connection relationship of the positive feedback quenching module is as follows: the source of the first PMOS transistor MP1 is connected to the drain of the second PMOS transistor MP2; the gate of the first PMOS transistor MP1 is connected to the drains of the third PMOS transistor MP3 and the third NMOS transistor MN3; the drain of the first PMOS transistor MP1 is connected to the gate and drain of the first NMOS transistor MN1, the gates of the third PMOS transistor MP3 and the third NMOS transistor MN3, and the anode of the SPAD device; the gate of the second PMOS transistor MP2 is connected to the output end of the adjustable delay module; the sources of the second PMOS transistor MP2 and the third PMOS transistor MP3 are connected to the power supply VDD; and the sources of the first NMOS transistor MN1 and the third NMOS transistor MN3 are grounded. The diode-connected MN1 acts not only as a sensing resistor but also as a quenching resistor, raising the anode voltage in the early stages of an avalanche to prevent the release of large currents. Furthermore, the resistance of the diode-connected MN1 is dynamically modulated by the SPAD anode voltage. As the anode voltage rises, the resistance of the MN1 tube decreases, and the corresponding RC coefficient decreases, facilitating faster charging of the positive feedback circuit. As a result, the positive feedback quenching module helps improve the circuit's quenching response speed. Its rapid quenching response effectively reduces the total charge flowing through the single-photon avalanche diode during an avalanche, thereby reducing the probability of defect-state trapped carriers. Since the thermally excited release of trapped carriers is the primary cause of post-pulse noise, this technology effectively suppresses the post-pulse effect by inhibiting the carrier capture process.

[0035] The reset module's specific connections are as follows: the drain of the second NMOS transistor MN2 is connected to the anode of the SPAD device and the input of the adjustable delay module; the gate of the second NMOS transistor MN2 is connected to the gate of the second PMOS transistor MP2 and the output of the adjustable delay module; and the source of the second NMOS transistor MN2 is grounded. The second NMOS transistor MN2 and the second PMOS transistor MP2 are driven synchronously by the reset signal, ensuring timing isolation between the quenching and reset phases. Furthermore, the second NMOS transistor MN2 is a large-size transistor, which conducts upon receipt of the reset signal to form a low-resistance discharge path. This helps improve the reset response speed of the circuit.

[0036] The output shaping module is specifically connected as follows: the source of the fifth PMOS transistor MP5 is connected to VDD, the gate of the fifth PMOS transistor MP5 is connected to voltage Vq, the drain of the fifth PMOS transistor MP5 is connected to the source of the fourth PMOS transistor MP4, the gate of the fourth PMOS transistor MP4 is connected to the gate of the fourth NMOS transistor MN4 and the anode of the SPAD device, the drain of the fourth PMOS transistor MP4 is connected to the drain of the fourth NMOS transistor MN4 and the input of the first inverter INV1, the output of the first inverter INV1 outputs the Vout signal, and the source of the fourth NMOS transistor MN4 is grounded. Vq is used to control the closing of the fifth PMOS transistor MP5, regulating the current in the charging branch, and can specifically stretch or compress the pulse width. Thanks to this, the voltage value of Vq can be adjusted in the output shaping module to precisely control the output signal pulse width for reading by the back-end circuitry.

[0037] like Figure 2 As shown, the adjustable delay module includes a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, and a second inverter INV2. Specifically, the source of the seventh PMOS transistor MP7 is connected to the power supply VDD, the gate of the seventh PMOS transistor MP7 is connected to the voltage Vctrlp, the drain of the seventh PMOS transistor MP7 is connected to the source of the sixth PMOS transistor MP6, the gate of the sixth PMOS transistor MP6 is connected to the gate of the fifth NMOS transistor MN5, serving as the input of the adjustable delay module, the drain of the sixth PMOS transistor MP6 is connected to the drain of the fifth NMOS transistor MN5 and the input of the second inverter INV2, the output of the second inverter INV2 serves as the output of the adjustable delay module, the source of the fifth NMOS transistor MN5 is connected to the drain of the sixth NMOS transistor MN6, the gate of the sixth NMOS transistor MN6 is connected to the voltage Vctrln, and the source of the sixth NMOS transistor MN6 is grounded. Vctrlp and Vctrln are used to control the charge and discharge currents, thereby delaying the signal. Dual voltage regulation can better balance the symmetry of charge and discharge. Thanks to this, the adjustable delay module can adjust the voltage values of Vctrlp and Vctrln to precisely control the delay from quenching to reset, achieving complete quenching.

[0038] Example 2

[0039] This embodiment provides a method for active quenching of a SPAD device, such as Figure 3 As shown, the working process of the SPAD device is combined with the process timing diagram of a working cycle to make the following explanation:

[0040] Step 1: Before time t1, the SPAD device is in the initial state, and the cathode of the SPAD device is connected to the bias voltage V BiasThe anode of the SPAD device is at a low potential, placing it in Geiger mode and entering the detection phase. The low potential at the anode of the SPAD device acts on the gates of MP3 and MN3, outputting a high level to the gate of MP1, turning off MP1. After a delay, the low potential at the anode of the SPAD device reaches the gates of MN2 and MP2, turning off MN2 and turning on MP2. MN1 is connected as a diode, acting as a resistor. The series branch between the SPAD device and MN1 senses avalanche current.

[0041] Step 2: At t1, the SPAD device is excited by photons, generating a large current in the milliampere range. After passing through MN1, the voltage at the anode of the SPAD device is raised. After comparison between MP3 and MN3, a low potential is output to the gate of MP1, and MP1 turns on. Through the operation of the positive feedback loop, the anode voltage of the SPAD device is directly pulled to VDD by the quenching branch of MP2 and MP1. At this time, the anode voltage of the SPAD device is V Bias , the cathode voltage of the SPAD device is VDD, and the Geiger mode is exited. And the high level of the anode of the SPAD device will output a square wave signal of corresponding pulse width after being processed by the output shaping module for the back-end circuit to read.

[0042] Step 3: At time t2, after a delay of Delay (the delay time is t2-t1), the SPAD device has been completely quenched, and the high potential of the anode of the SPAD device is transmitted to the gates of MP2 and MN2. Although the quenching signal is low, the MP2 tube is cut off and the quenching branch is closed; the MN2 tube is turned on, and the reset branch where MN2 is located is opened, pulling the high potential of the anode of the SPAD device to ground at time t3. At this time, the cathode voltage of the SPAD device is V Bias , the anode potential of the SPAD device is ground, and the SPAD device returns to Geiger mode. At time t4, after a delay of Delay (the delay time is t4-t3), MP2 turns on, and the quenching branch remains closed; MN2 turns off, the reset branch closes, and the SPAD device re-enters the detection phase.

[0043] As can be seen from the circuit structure, before an avalanche occurs, the SPAD device is in Geiger mode, with both the quenching and reset branches closed. Thanks to the diode connection of the first NMOS transistor MN1, MN1 performs the dual functions of sensing avalanche current and providing dynamic quenching resistance. When an avalanche occurs, MN1 senses the avalanche current, opening the quenching branch and closing the reset branch. Thanks to the positive feedback loop coupled with MN1, the quenching branch can be quickly opened after sensing the avalanche current. After the avalanche is quenched, the reset signal is transmitted to MN2 via a controllable delay module, opening the reset branch and closing the quenching branch. Thanks to the adjustable delay module, the SPAD device is thoroughly quenched, minimizing afterpulses. Thanks to the complementary design of the second PMOS transistor MP2 and the second NMOS transistor MN2, the quenching and reset branches of the circuit are always separate, avoiding timing interference between quenching and reset.

[0044] like Figure 4 As shown in the figure, it can be seen that the quenching time of the anode voltage of the SPAD device in this circuit is only 1.7ns, the reset time is 0.8ns, and the dead time is only 2.5ns. Compared with the microsecond dead time of traditional passive quenching circuits, this is a significant improvement. For the same type of active quenching circuit, the dead time is generally above 3ns, and the dead time of the present invention is also slightly improved. In addition, the circuit structure of the present invention is simple, without the introduction of integrated modules, and has a smaller circuit area and more flexible timing control.

[0045] Some steps in the embodiments of the present invention may be implemented using software, and the corresponding software program may be stored in a readable storage medium, such as a CD or a hard disk.

[0046] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A novel SPAD active quenching reset circuit based on positive feedback control, characterized in that: The circuit includes a positive feedback quenching module, an adjustable delay module, a reset module, an output shaping module and a SPAD device; wherein the positive feedback quenching module is used to detect the avalanche voltage and use positive feedback to quench the SPAD device, including a positive feedback loop and an NMOS tube connected in a diode manner, and the positive feedback loop is composed of three PMOS tubes and one NMOS tube cross-coupled; the adjustable delay module is used to delay the quenching signal to ensure that the anode end of the SPAD device is completely quenched before starting the reset module to reset the circuit, including two symmetrically arranged PMOS tubes and two NMOS tubes and an inverter; the reset module is used to reset the cathode level of the SPAD device, including an NMOS tube; the output shaping module is used to output an output signal corresponding to the pulse width, including two PMOS tubes, one NMOS tube and an inverter.

2. The method according to claim 1, characterized in that The positive feedback quenching module includes a first NMOS transistor MN1, a third NMOS transistor MN3, a first PMOS transistor MP1, a second PMOS transistor MP2, and a third PMOS transistor MP3. The first NMOS transistor MN1 adopts a diode connection method, with its gate and drain simultaneously connected to the anode of the SPAD device and the source grounded; the third NMOS transistor MN3, the first PMOS transistor MP1, the second PMOS transistor MP2, and the third PMOS transistor MP3 are cross-coupled to form a positive feedback loop.

3. The method according to claim 2, characterized in that In the positive feedback quenching module, the source of the first PMOS transistor MP1 is connected to the drain of the second PMOS transistor MP2; the gate of the first PMOS transistor MP1 is connected to the drains of the third PMOS transistor MP3 and the third NMOS transistor MN3; the drain of the first PMOS transistor MP1 is connected to the gate and drain of the first NMOS transistor MN1, the gates of the third PMOS transistor MP3 and the third NMOS transistor MN3, and the anode of the SPAD device; the gate of the second PMOS transistor MP2 is connected to the output end of the adjustable delay module; the sources of the second PMOS transistor MP2 and the third PMOS transistor MP3 are connected to the power supply VDD; and the sources of the first NMOS transistor MN1 and the third NMOS transistor MN3 are grounded.

4. The method according to claim 3, characterized in that The adjustable delay module includes a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, and a second inverter INV2; wherein the sixth PMOS transistor MP6 and the seventh PMOS transistor MP7 are symmetrical with the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6, the source of the seventh PMOS transistor MP7 is connected to the power supply VDD, the gate of the seventh PMOS transistor MP7 is connected to the voltage Vctrlp, the drain of the seventh PMOS transistor MP7 is connected to the source of the sixth PMOS transistor MP6, and the gate of the sixth PMOS transistor MP6 is connected to the power supply VDD. The gate of the fifth NMOS transistor MN5 serves as the input of the adjustable delay module. The drain of the sixth PMOS transistor MP6 is connected to the drain of the fifth NMOS transistor MN5 and the input of the second inverter INV2. The output of the second inverter INV2 serves as the output of the adjustable delay module. The source of the fifth NMOS transistor MN5 is connected to the drain of the sixth NMOS transistor MN6. The gate of the sixth NMOS transistor MN6 is connected to the voltage Vctrln, and the source of the sixth NMOS transistor MN6 is grounded. The charge and discharge currents are regulated by the external voltages Vctrlp and Vctrln, thereby delaying the quenching signal of the positive feedback quenching module.

5. The method according to claim 4, characterized in that In the reset module, the drain of the second NMOS transistor MN2 is connected to the anode of the SPAD device and the input end of the adjustable delay module, the gate of the second NMOS transistor MN2 is connected to the gate of the second PMOS transistor MP2 and the output end of the adjustable delay module, and the source of the second NMOS transistor MN2 is grounded; the second NMOS transistor MN2 and the second PMOS transistor MP2 are synchronously driven by the reset signal to ensure timing isolation between the quenching and reset stages.

6. The method according to claim 5, characterized in that In the output shaping module, the source of the fifth PMOS transistor MP5 is connected to VDD, the gate of the fifth PMOS transistor MP5 is connected to the voltage Vq, the drain of the fifth PMOS transistor MP5 is connected to the source of the fourth PMOS transistor MP4, the gate of the fourth PMOS transistor MP4 is connected to the gate of the fourth NMOS transistor MN4 and the anode of the SPAD device, the drain of the fourth PMOS transistor MP4 is connected to the drain of the fourth NMOS transistor MN4 and the input end of the first inverter INV1, the output end of the first inverter INV1 outputs the Vout signal, and the source of the fourth NMOS transistor MN4 is grounded.

7. The method according to claim 6, characterized in that The second NMOS transistor MN2 is a large-sized transistor with a width-to-length ratio W / L greater than 20 / 1.

8. A SPAD active quenching method, characterized in that: The method is implemented based on the circuit according to claim 7, and the method includes: Step 1: At the initial stage of the circuit, the cathode of the SPAD device is connected to the bias voltage V Bias , the anode of the SPAD device is at a low potential, the SPAD device is in Geiger mode, and enters the detection stage; the low potential of the anode of the SPAD device acts on the gates of MP3 and MN3 to output a high level to the gate of MP1, and MP1 is turned off; the low potential of the anode of the SPAD device reaches the gates of MN2 and MP2 after a delay, MN2 is turned off, and MP2 is turned on; MN1 is connected as a resistor using a diode method, and the series branch of the SPAD device and MN1 is used to sense the avalanche current; Step 2: At t1, the SPAD device is excited by photons, generating a large current in the milliampere level. After passing through MN1, the voltage of the anode of the SPAD device will be raised. After comparison between MP3 and MN3, a low potential is output to the gate of MP1, and the MP1 tube is turned on. Through the operation of the positive feedback circuit, the anode voltage of the SPAD device is directly pulled to VDD by the quenching branch of MP2 and MP1. At this time, the anode voltage of the SPAD device is V Bias , the cathode voltage of the SPAD device is VDD, exiting the Geiger mode, and the high level of the anode of the SPAD device will output a square wave signal of corresponding pulse width after being processed by the output shaping module for reading by the back-end circuit; Step 3: At time t2, after a delay of Delay, the delay time is t2-t1, the SPAD device has been completely quenched, and the high potential of the anode of the SPAD device is transmitted to the gates of MP2 and MN2; although the quenching signal is low, the MP2 tube is cut off and the quenching branch is closed; the MN2 tube is turned on, and the reset branch where MN2 is located is opened, and at time t3, the high potential of the anode of the SPAD device is pulled to ground; at this time, the cathode voltage of the SPAD device is V Bias , the anode potential of the SPAD device is ground, and the SPAD device returns to the Geiger mode; after a delay of Delay at time t4, the delay time is t4-t3, MP2 is turned on, and the quenching branch is still closed; MN2 is cut off, the reset branch is closed, and the SPAD device re-enters the detection stage.

9. A laser radar detector, characterized in that: The detector uses the novel SPAD active quenching reset circuit based on positive feedback control as described in any one of claims 1 to 7 to quench and reset the SPAD device.

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