Voltage-current conversion device and current source device

Abstract

A voltage / current conversion device (1A) is provided with a current supply circuit (10A), a differential circuit (20A), a step-up unit (30), a control unit (40A), and the like. A current supply circuit (10A) includes a first NMOS transistor (11), a second NMOS transistor (12), a first resistor (13), and a second resistor (14). The differential circuit (20A) includes a first NPN transistor (21), a second NPN transistor (22), and a tail current source (23). The step-up unit (30) supplies a potential equal to or higher than the power supply potential to the gates of the first NMOS transistor (11) and the second NMOS transistor (12).

Description

Technical Field

[0001] The present disclosure relates to a voltage-to-current conversion device and a current source device. Background Art

[0002] The voltage-to-current conversion device described in Patent Documents 1 and 2 is a device that outputs a current signal corresponding to an input differential voltage signal. In particular, it is a laser driver that supplies a driving current to a laser diode in order to cause the laser diode to emit light. It is a device intended to supply a driving current to a surface-emitting laser diode (Vertical Cavity Surface Emitting Laser, VCSEL) in the laser diode.

[0003] As described in these documents, the voltage-to-current converter generally includes: a differential circuit including two NPN transistors forming an input differential pair for inputting a differential voltage signal; and a current supply circuit provided between the two NPN transistors and a first reference potential supply terminal of a high potential.

[0004] The current supply circuit of the voltage-to-current converter described in Patent Document 1 includes a PMOS transistor operating in the saturation region. The current supply circuit of the voltage-to-current converter described in Patent Document 2 includes a PMOS transistor operating in the linear region. The PMOS transistor is a P-channel metal-oxide-semiconductor (MOS) field-effect transistor (FET).

[0005] The current source device that supplies current to a load circuit is not limited to a voltage-to-current converter that outputs a current signal corresponding to an input differential voltage signal, and also includes a PMOS transistor.

[0006] Prior art literature

[0007] Patent Literature

[0008] Patent Document 1: U.S. Patent Application Publication No. 2022 / 0190554

[0009] Patent Document 2: U.S. Patent No. 9,570,917 Summary of the Invention

[0010] Problems to be solved by the invention

[0011] In PMOS transistors, the capacitance seen from the gate increases due to the mirror effect, resulting in poor frequency characteristics for feedback control and difficulty in high-speed operation. PMOS transistors operating in the saturation region require large transistor sizes to flow the required current, resulting in large parasitic capacitance. This makes high-speed operation even more difficult when operating with large current amplitudes. PMOS transistors operating in the linear region have a strong dependence of the current value on Vds, resulting in low output impedance under feedback control and difficulty operating with large current amplitudes. Consequently, existing voltage-to-current converters and current source devices have difficulty achieving high-speed operation and outputting large current amplitudes.

[0012] The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a voltage-current converter and a current source device that can easily realize high-speed operation and output a large current amplitude.

[0013] Means for solving problems

[0014] A voltage-current conversion device according to a first embodiment of the present invention comprises: (1) a current supply circuit comprising a first NMOS transistor, a second NMOS transistor, a first resistor, and a second resistor, wherein the drains of the first NMOS transistor and the second NMOS transistor are connected to a first reference potential supply terminal for supplying a first reference potential, the first resistor is arranged between the source of the first NMOS transistor and the first node, the second resistor is arranged between the source of the second NMOS transistor and the second node, and the gates of the first NMOS transistor and the second NMOS transistor are connected to each other; and (2) a differential circuit comprising a first NPN transistor, a second NPN transistor, and a first resistor. (1) a body transistor, and a tail current source, wherein the collector of the first NPN transistor is connected to the first node, the collector of the second NPN transistor is connected to the second node, and the tail current source is provided between a second reference potential supply terminal that supplies a second reference potential lower than the first reference potential and the emitters of the first NPN transistor and the second NPN transistor; (2) a booster section that applies a potential greater than the first reference potential to the gates of the first NMOS transistor and the second NMOS transistor; and (3) a control section that controls the potential provided by the booster section to the gates of the first NMOS transistor and the second NMOS transistor based on the current flowing through the first resistor or the potential of the first node. In addition, in the voltage-current conversion device, a differential voltage signal is input to the bases of the first NPN transistor and the second NPN transistor, and a current signal corresponding to the differential voltage signal is output from the first node. In addition, the NMOS transistor is an N-channel metal-oxide-semiconductor (MOS) field effect transistor (FET). The NPN transistor is an NPN bipolar transistor.

[0015] A voltage-current conversion device according to a second embodiment of the present invention comprises: (1) a current supply circuit including a first NMOS transistor and a second NMOS transistor, wherein the drains of the first NMOS transistor and the second NMOS transistor are connected to a first reference potential supply terminal for supplying a first reference potential, and the gates of the first NMOS transistor and the second NMOS transistor are connected to each other; (2) a differential circuit including a first NPN transistor, a second NPN transistor, and a tail current source, wherein the collector of the first NPN transistor is connected to the source of the first NMOS transistor, the collector of the second NPN transistor is connected to the source of the second NMOS transistor, and the tail current source is provided between a second reference potential supply terminal for supplying a second reference potential lower than the first reference potential and the emitters of the first NPN transistor and the second NPN transistor; (3) a first resistor provided between the source of the first NMOS transistor and a first node; (4) a voltage boosting section for providing a potential higher than the first reference potential to the gates of the first NMOS transistor and the second NMOS transistor; and (5) a control section for controlling the potential provided by the voltage boosting section to the gates of the first NMOS transistor and the second NMOS transistor based on the current flowing through the resistor or the potential of the first node. Furthermore, in the voltage-current conversion device, a differential voltage signal is input to the bases of the first NPN transistor and the second NPN transistor, and a current signal corresponding to the differential voltage signal is output from the first node.

[0016] The voltage-current conversion device of the present invention may also be implemented as follows.

[0017] In a third aspect, in addition to the first or second aspect, the voltage-to-current conversion device further includes a third resistor disposed between the source of the first NMOS transistor and the third node, and a current source disposed between the third node and the second reference potential supply terminal. The control unit controls the potential provided by the boosting unit to each of the gates of the first and second NMOS transistors based on a comparison between the current flowing through the first resistor or the potential at the first node and the current flowing through the third resistor or the potential at the third node.

[0018] In a fourth aspect, in addition to the first or second aspect, the voltage-to-current converter further includes a third NMOS transistor having a drain connected to the first reference potential supply terminal, a third resistor provided between the source of the third NMOS transistor and the third node, and a current source provided between the third node and the second reference potential supply terminal. The gates of the first, second, and third NMOS transistors are connected to one another. The control unit controls the potential provided by the boost unit to the gates of the first, second, and third NMOS transistors based on a comparison between the current flowing through the first resistor or the potential at the first node and the current flowing through the third resistor or the potential at the third node.

[0019] In a fifth aspect, in addition to any one of the first to fourth aspects, each of the first NMOS transistor and the second NMOS transistor is an N-type LDMOS transistor.

[0020] In a sixth aspect, in addition to any one of the first to fourth aspects, the first NMOS transistor and the second NMOS transistor each have a triple-well structure, and a resistor is provided between the P-well of each of the first NMOS transistor and the second NMOS transistor and the first node.

[0021] In a seventh aspect, in addition to any one of the first to fourth aspects, the first NMOS transistor and the second NMOS transistor each have a triple-well structure, and a resistor is provided between the P-well of each of the first and second NMOS transistors and the source of the first NMOS transistor.

[0022] In the eighth aspect, based on any one of the first to fourth aspects, the first NMOS transistor and the second NMOS transistor each have a triple-well structure, and a voltage source is provided between the P-well of each of the first NMOS transistor and the second NMOS transistor and the first reference potential supply terminal.

[0023] In a ninth aspect, based on any one of the first to fourth aspects, the first NMOS transistor and the second NMOS transistor each have a triple-well structure, and a diode is provided between the P-well of each of the first NMOS transistor and the second NMOS transistor and the first reference potential supply terminal.

[0024] In the tenth embodiment, based on any one of the first to ninth embodiments, in the differential circuit, a tail current source between the second reference potential supply terminal and the emitter of the first NPN transistor, and a tail current source between the second reference potential supply terminal and the emitter of the second NPN transistor are each separately provided.

[0025] In the eleventh aspect, in addition to the first aspect and any one of the third to tenth aspects including the first aspect, a dummy load is connected to the second node.

[0026] In the twelfth aspect, in addition to the third aspect, the resistance value of the third resistor or the current value of the current source is variable.

[0027] In a thirteenth aspect, in addition to any one of the first to twelfth aspects, the voltage-current conversion device includes a plurality of current supply circuits, and the number of current supply circuits connected to the first reference potential supply terminal is variable.

[0028] The voltage-current conversion device of the fourteenth embodiment of the present invention comprises: (1) a current supply circuit, the current supply circuit comprising a first NPN transistor, a second NPN transistor, a first resistor, and a second resistor, the collectors of the first NPN transistor and the second NPN transistor being connected to a first reference potential supply terminal for supplying a first reference potential, the first resistor being arranged between the emitter of the first NPN transistor and the first node, the second resistor being arranged between the emitter of the second NPN transistor and the second node, the bases of the first NPN transistor and the second NPN transistor being connected to each other; and (2) a differential circuit comprising a third NPN transistor, a fourth NPN transistor, and a first resistor. N-type transistors, and a tail current source, wherein the collector of the third NPN transistor is connected to the first node, the collector of the fourth NPN transistor is connected to the second node, and the tail current source is provided between a second reference potential supply terminal that supplies a second reference potential lower than the first reference potential and the emitters of the third NPN transistor and the fourth NPN transistor; (3) a booster section that provides a potential greater than the first reference potential to the base of each of the first NPN transistor and the second NPN transistor; and (4) a control section that controls the potential provided by the booster section to the base of each of the first NPN transistor and the second NPN transistor based on the current flowing through the first resistor or the potential of the first node. In addition, in the voltage-current converter, a differential voltage signal is input to the base of each of the third NPN transistor and the fourth NPN transistor, and a current signal corresponding to the differential voltage signal is output from the first node.

[0029] A voltage-current conversion device according to a fifteenth aspect of the present invention comprises: (1) a current supply circuit including an NMOS transistor having a drain connected to a first reference potential supply terminal supplying a first reference potential, and a resistor provided between the source of the NMOS transistor and a node; (2) a differential circuit including a first NPN transistor having a collector connected to the node, a second NPN transistor having a collector connected to the first reference potential supply terminal, and a tail current source provided between the second reference potential supply terminal supplying a second reference potential lower than the first reference potential and the emitters of the first and second NPN transistors; (3) a booster section providing a potential greater than the first reference potential to the gate of the NMOS transistor; and (4) a control section controlling the potential provided by the booster section to the gate of the NMOS transistor based on a current flowing through the resistor or the potential of the node. Furthermore, in the voltage-current conversion device, a differential voltage signal is input to the bases of the first and second NPN transistors, and a current signal corresponding to the differential voltage signal is output from the node.

[0030] The current source device of the present invention comprises: (1) an NMOS transistor having a drain connected to a reference potential supply terminal for supplying a reference potential; (2) a boosting unit for supplying a potential higher than the reference potential to the gate of the NMOS transistor; and (3) a control unit for controlling the potential supplied by the boosting unit to the gate of the NMOS transistor based on the current or potential in a load circuit input with the current output from the source of the NMOS transistor.

[0031] Effects of the Invention

[0032] According to the present invention, it is possible to provide a voltage-current conversion device and a current source device that can easily realize high-speed operation and output a large current amplitude. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 1A is a diagram showing the configuration of a voltage-current converter 1A.

[0034] Figure 2 1B is a diagram showing the structure of a voltage-current converter 1B.

[0035] Figure 3 1C is a diagram showing the structure of a voltage-current converter device 1C.

[0036] Figure 4 1 is a diagram showing a circuit configuration example of the voltage boosting unit 30 .

[0037] Figure 5 It is a diagram showing an example of the circuit configuration of the control unit 40B.

[0038] Figure 6 1D is a diagram showing the structure of a voltage-current converter 1D.

[0039] Figure 7 1E is a diagram showing the structure of a voltage-current converter 1E.

[0040] Figure 8 1F is a diagram showing the structure of a voltage-current converter 1F.

[0041] Figure 9 1G is a diagram showing the structure of a voltage-current converter 1G.

[0042] Figure 10 1H is a diagram showing the structure of a voltage-current converter 1H.

[0043] Figure 11 1 is a diagram showing the structure of the voltage-current conversion device 1i.

[0044] Figure 12 1J is a diagram showing the structure of a voltage-current converter 1J.

[0045] Figure 13 1K is a diagram showing the structure of a voltage-current converter 1K.

[0046] Figure 14 1L is a diagram showing the structure of a voltage-current converter 1L.

[0047] Figure 15 1 is a diagram showing a configuration example of the dummy load 60 .

[0048] Figure 16 1M is a diagram showing the structure of a voltage-current converter device 1M.

[0049] Figure 17 1N is a diagram showing the structure of a voltage-current converter device 1N.

[0050] Figure 18 1 is a diagram showing the structure of the voltage-current conversion device 1o.

[0051] Figure 19 1P is a diagram showing the structure of a voltage-current converter 1P.

[0052] Figure 20 1Q is a diagram showing the structure of a current source device 1Q.

[0053] Figure 21 is a diagram showing a cross-sectional structure of a transistor. DETAILED DESCRIPTION

[0054] Hereinafter, the mode for carrying out the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and repeated descriptions are omitted.

[0055] Figure 1This figure shows the structure of a voltage-current converter 1A. The voltage-current converter 1A includes a current supply circuit 10A, a differential circuit 20A, a booster 30, and a control unit 40A. The current supply circuit 10A includes a first NMOS transistor 11, a second NMOS transistor 12, a first resistor 13, and a second resistor 14. The differential circuit 20A includes a first NPN transistor 21, a second NPN transistor 22, and a tail current source 23.

[0056] The drains of the first NMOS transistor 11 and the second NMOS transistor 12 are connected to a first reference potential supply terminal that supplies a first reference potential (e.g., a power supply potential). The gates of the first NMOS transistor 11 and the second NMOS transistor 12 are connected to each other. A first resistor 13 is provided between the source of the first NMOS transistor 11 and the first node N1. A second resistor 14 is provided between the source of the second NMOS transistor 12 and the second node N2. The first NMOS transistor 11 and the second NMOS transistor 12 have the same characteristics. The resistance values of the first resistor 13 and the second resistor 14 are equal to each other.

[0057] The collector of the first NPN transistor 21 is connected to the first node N1. The collector of the second NPN transistor 22 is connected to the second node N2. The tail current source 23 is provided between a second reference potential supply terminal that supplies a second reference potential lower than the first reference potential (e.g., a ground potential) and the emitters of the first NPN transistor 21 and the second NPN transistor 22. The characteristics of the first NPN transistor 21 and the second NPN transistor 22 are the same.

[0058] The booster unit 30 supplies a potential equal to or higher than the first reference potential to the gates of the first and second NMOS transistors 11 and 12. The control unit 40A controls the potential supplied by the booster unit 30 to the gates of the first and second NMOS transistors 11 and 12 based on the current flowing through the first resistor 13 or the potential of the first node N1. Figure 4 A circuit configuration example of the voltage boosting unit 30 is shown.

[0059] Figure 4The booster unit 30 shown includes PMOS transistors Q1 and Q2, NMOS transistors Q3 and Q4, capacitors C1 and C2, diodes D1 and D2, and inverters INV1 and INV2. These circuit components are connected as shown in the figure. The sources of NMOS transistors Q3 and Q4 are connected to the power supply potential VCC. The sources of PMOS transistors Q1 and Q2 are connected to the output terminal of the booster unit 30. A clock signal is input to the input terminal of the first inverter INV1, and the inverted signal of this clock signal is input to capacitor C1. This inverted signal is input to the second inverter INV2 and inverted, and the output signal of the second inverter INV2 is input to capacitor C2.

[0060] exist Figure 1 In the illustrated configuration example, a current source 42 is provided between the output terminal of the boosting unit 30 and the second reference potential supply terminal. The control unit 40A receives the potential of the first node N1 via the low-pass filter 41 and controls the potential supplied to the gates of the first NMOS transistor 11 and the second NMOS transistor 12 by adjusting the current flowing through the current source 42 so that the potential of the first node N1 reaches a desired value (i.e., so that the current flowing through the first resistor 13 reaches a desired value).

[0061] The voltage-to-current converter 1A inputs differential voltage signals INP and INN to the bases of a first NPN transistor 21 and a second NPN transistor 22, respectively, and outputs a current signal corresponding to the input differential voltage signal from a first node N1 (output node) to a load 2. The load 2 may be any type, such as a laser diode, for example, a surface-emitting laser diode.

[0062] The gates of the NMOS transistors 11 and 12 of the current supply circuit 10A are each supplied with a potential equal to or higher than the first reference potential by the booster unit 30, thereby operating the NMOS transistors 11 and 12 in the current supply circuit 10A in the saturation region. Furthermore, the control unit 40A, which adjusts the current extraction amount of the current source 42, performs feedback control to maintain a constant current through the NMOS transistors 11 and 12. Furthermore, a low-pass filter 41 is provided between the first node N1 and the control unit 40A, preventing the load capacitance of the feedback system from being seen at the first node N1 (output node).

[0063] By performing constant current feedback control on the NMOS transistors 11 and 12 operating in the saturation region, the output impedance is high in a wide frequency band from DC to the high frequency band. This is beneficial for large-amplitude operation. That is, the gates of the NMOS transistors 11 and 12 are provided with a potential higher than the first reference potential through the boost unit 3, so that the NMOS transistors 11 and 12 can operate in the saturation region. In addition, the boosting of the boost unit 30 and the current extraction of the current source 42 are used to feedback control the gate potential of the NMOS transistors 11 and 12 so that a constant current flows through each of the NMOS transistors 11 and 12. As a result, the output impedance is increased. Since the output impedance is not increased using an inductor, the output impedance is high even in the low-frequency domain.

[0064] Conventional voltage-to-current converters, including those described in Patent Documents 1 and 2, use PMOS transistors in their current supply circuits. In contrast, in this embodiment, NMOS transistors 11 and 12 are used in current supply circuit 10A. Consequently, this embodiment eliminates mirror effects and minimizes the capacitance seen from the gates of NMOS transistors 11 and 12, making it easier to achieve high speed within the feedback control loop frequency band. Consequently, it is easier to maintain high output impedance up to high frequencies, facilitating high-speed operation and achieving high-current output amplitude.

[0065] Compared to PMOS transistors, NMOS transistors have higher carrier mobility and smaller dimensions for allowing the required amount of current to flow, resulting in smaller parasitic capacitance. Even in high-frequency regions above the loop band of feedback control, the output impedance can be maintained relatively high, which is advantageous for high-speed and large-amplitude operation. Furthermore, due to the large-amplitude operation, even if voltage ripple occurs at the source nodes of the NMOS transistors 11 and 12, the parasitic capacitance is small, resulting in fast charging and discharging, making it less likely to generate ISI (inter-symbol interference), which is advantageous for high-speed and large-amplitude operation. There is also no current path that bypasses the current source and flows to the power supply. The power supply current is determined by the NMOS transistors 11 and 12, so the power supply current has little pattern dependence.

[0066] Figure 2 1B is a diagram showing the structure of the voltage-current converter 1B. The voltage-current converter 1B includes a current supply circuit 10A, a differential circuit 20A, a booster 30, a control unit 40B, a third resistor 52, and a current source 53. Figure 1 ) compared to the voltage-current converter 1B ( Figure 2) differs in that it further includes a third resistor 52 and a current source 53, and in that it includes a control unit 40B instead of the control unit 40A and the current source 42.

[0067] The third resistor 52 is provided between the source of the first NMOS transistor 11 and the third node N3. The current source 53 is provided between the third node N3 and the second reference potential supply terminal.

[0068] The control unit 40B controls the potential provided by the boost unit 30 to the gates of the NMOS transistors 11 and 12 based on a comparison between the current flowing through the first resistor 13, or the potential at the first node N1, and the current flowing through the third resistor 52, or the potential at the third node N3. In the exemplary configuration shown in the figure, the control unit 40B controls the potential provided by the boost unit 30 to the gates of the NMOS transistors 11 and 12 based on a comparison between the potential at the first node N1 and the potential at the third node N3. The control unit 40B can be configured to include a transconductance amplifier (Gm amplifier, current extraction amplifier). The control unit 40B inputs the potential at the node N3 to the non-inverting input terminal and inputs the potential at the first node N1, after passing through the low-pass filter 41, to the inverting input terminal. Figure 5 A circuit configuration example of the control unit 40B is shown.

[0069] The control unit 40B includes a first NMOS transistor Q11, a second NMOS transistor Q12, a current source CS1, a first resistor R11, a second resistor R12, a third NMOS transistor Q13, and a differential amplifier A10. These circuit components are connected as shown in the figure. The gate of the first NMOS transistor Q11 is connected to the gate of the second NMOS transistor Q12, and this connection point is connected to the drain of the second NMOS transistor Q12. The drain of the second NMOS transistor Q12 is connected to the power supply potential VCC via the current source CS1. The drain of the first NMOS transistor Q11 is connected to the power supply potential VCC. The source of the first NMOS transistor Q11 and the source of the second NMOS transistor Q12 are connected to ground potential. The drain of the third NMOS transistor Q13 is connected to the output terminal via a diode D10.

[0070] The resistance values of resistors 13 and 14 are set to R, and the desired value of the current flowing through resistor 13 is set to Ibias. The resistance value of resistor 52 is set to M times R, that is, M*R, and the current flowing through current source 53 is set to 1 / M of Ibias, that is, Ibias / M. The control unit 40B performs feedback control on the potentials supplied to the gates of NMOS transistors 11 and 12 so that the potentials of first node N1 and third node N3 are equal to each other. This allows the potential differences generated across resistors 13 and 52 to be equal, and the current flowing through resistor 13 to be set to the desired value Ibias.

[0071] Figure 3 1C. The voltage-current converter 1B includes a current supply circuit 10A, a differential circuit 20A, a booster 30, a control unit 40B, a third NMOS transistor 51, a third resistor 52, and a current source 53. Figure 1 ) compared to the voltage-current converter 1C ( Figure 3 ) differs in that it further includes a third NMOS transistor 51, a third resistor 52, and a current source 53, and in that it includes a control unit 40B instead of the control unit 40A and the current source 42.

[0072] The drain of the third NMOS transistor 51 is connected to the first reference potential supply terminal. The third resistor 52 is provided between the source of the third NMOS transistor 51 and the third node N3. The current source 53 is provided between the third node N3 and the second reference potential supply terminal. The gates of the NMOS transistors 11, 12, and 51 are connected to each other.

[0073] The control unit 40B controls the potential provided by the boost unit 30 to the gates of the NMOS transistors 11, 12, and 51 based on a comparison between the current flowing through the first resistor 13, or the potential at the first node N1, and the current flowing through the third resistor 52, or the potential at the third node N3. In the exemplary configuration shown in the figure, the control unit 40B controls the potential provided by the boost unit 30 to the gates of the NMOS transistors 11, 12, and 51 based on a comparison between the potential at the first node N1 and the potential at the third node N3. The control unit 40B can be configured to include a transconductance amplifier (current extraction amplifier). The control unit 40B inputs the potential at the node N3 to the non-inverting input terminal and inputs the potential at the first node N1, after passing through the low-pass filter 41, to the inverting input terminal.

[0074] The gate lengths of NMOS transistors 11 and 12 are set to W, the resistance values of resistors 13 and 14 are set to R, and the desired value of the current flowing through resistor 13 is set to Ibias. The gate length of NMOS transistor 51 is set to 1 / M of W, or W / M, the resistance value of resistor 52 is set to M times R, or M*R, and the current flowing through current source 53 is set to 1 / M of Ibias, or Ibias / M. The control unit 40B performs feedback control on the potentials supplied to the gates of NMOS transistors 11, 12, and 51 so that the potentials of first node N1 and third node N3 are equal. This allows the potential difference between NMOS transistor 11 and resistor 13 and the potential difference between NMOS transistor 51 and resistor 52 to be equal, and the current flowing through resistor 13 to be the desired value Ibias.

[0075] Figure 6 1D is a diagram showing the structure of a voltage-current converter 1D. The voltage-current converter 1D includes a current supply circuit 10D, a differential circuit 20A, a booster 30, a control unit 40A, and a resistor 54. Figure 1 ) compared to the voltage-current converter 1D ( Figure 6 ) is different in that a current supply circuit 10D is provided instead of the current supply circuit 10A, and in that a resistor 54 is further provided.

[0076] The current supply circuit 10D includes a first NMOS transistor 11 and a second NMOS transistor 12. The drains of the first NMOS transistor 11 and the second NMOS transistor 12 are connected to a first reference potential supply terminal that supplies a first reference potential (e.g., a power supply potential). The gates of the first NMOS transistor 11 and the second NMOS transistor 12 are connected to each other. The first NMOS transistor 11 and the second NMOS transistor 12 have the same characteristics. The first resistor 13 and the second resistor 14 have the same resistance value.

[0077] The differential circuit 20A includes a first NPN transistor 21, a second NPN transistor 22, and a tail current source 23. The collector of the first NPN transistor 21 is connected to the source of the first NMOS transistor 11. The collector of the second NPN transistor 22 is connected to the source of the second NMOS transistor 12. The tail current source 23 is provided between a second reference potential supply terminal (e.g., ground potential) that supplies a second reference potential lower than the first reference potential and the emitters of the first NPN transistor 21 and the second NPN transistor 22. The first NPN transistor 21 and the second NPN transistor 22 have the same characteristics.

[0078] The resistor 54 is provided between the source of the first NMOS transistor 11 and the first node N1 .

[0079] The booster unit 30 supplies a potential equal to or higher than the first reference potential to the gates of the first and second NMOS transistors 11 and 12. The control unit 40A controls the potential supplied by the booster unit 30 to the gates of the first and second NMOS transistors 11 and 12 based on the current flowing through the resistor 54 or the potential of the first node N1.

[0080] In the configuration example shown in this figure, a current source 42 is provided between the output terminal of the boosting unit 30 and the second reference potential supply terminal. The control unit 40A receives the potential of the first node N1 via the low-pass filter 41 and adjusts the current flowing through the current source 42 so that the potential of the first node N1 reaches a desired value (i.e., the current flowing through the resistor 54 reaches a desired value). This controls the potential provided to each of the gates of the first NMOS transistor 11 and the second NMOS transistor 12.

[0081] The voltage-to-current converter 1D inputs differential voltage signals INP and INN to the bases of first and second NPN transistors 21 and 22, respectively, and outputs a current signal corresponding to the input differential voltage signal from a first node N1 (output node) to a load 2. The load 2 may be any type, such as a laser diode, or a surface-emitting laser diode.

[0082] With the voltage-current converter 1A ( Figure 1 ) compared to the voltage-current converter 1D ( Figure 6 ) differ in that the resistor for detecting the potential is provided at a position. The voltage-current converter 1D ( Figure 6 ) does not detect the current flowing through the NMOS transistor 11, but detects the current output from the first node N1 (output node) to the load 2, so the current value can be controlled more accurately.

[0083] Figure 7 1E is a diagram showing the structure of a voltage-current converter. The voltage-current converter 1E includes a current supply circuit 10D, a differential circuit 20A, a booster 30, a control unit 40B, a third resistor 52, a current source 53, and a resistor 54. Figure 2 ) compared to the voltage-current converter 1E ( Figure 7 ) is different in that it includes a current supply circuit 10D instead of the current supply circuit 10A and in that it also includes a resistor 54. The structure of the current supply circuit 10D and the position of the resistor 54 are similar to those of the voltage-current converter 1D ( Figure 6 ) is the same as the voltage-current converter 1B ( Figure 2 ) compared to the voltage-current converter 1E ( Figure 7 ) differ in that the resistor for detecting the potential is provided at a position. The voltage-current converter 1E ( Figure 7 ) does not detect the current flowing through the NMOS transistor 11, but detects the current output from the first node N1 (output node) to the load 2, so the current value can be controlled more accurately.

[0084] Figure 81F is a diagram showing the structure of a voltage-current converter. The voltage-current converter 1F includes a current supply circuit 10D, a differential circuit 20A, a booster 30, a control unit 40B, a third NMOS transistor 51, a third resistor 52, a current source 53, and a resistor 54. Figure 3 ) compared to the voltage-current conversion device 1F ( Figure 8 ) is different in that it includes a current supply circuit 10D instead of the current supply circuit 10A and in that it also includes a resistor 54. The structure of the current supply circuit 10D and the position of the resistor 54 are similar to those of the voltage-current converter 1D ( Figure 6 ) is the same as the voltage-current converter 1C ( Figure 3 ) compared to the voltage-current conversion device 1F ( Figure 8 ) differ in that the resistor for detecting the potential is provided at a position. The voltage-current converter 1F ( Figure 8 ) does not detect the current flowing through the NMOS transistor 11, but detects the current output from the first node N1 (output node) to the load 2, so the current value can be controlled more accurately.

[0085] The following describes the structures of various modified examples of the voltage-current converter. Figure 1 )、voltage-current conversion device 1B( Figure 2 )、voltage-current conversion device 1C( Figure 3 )、voltage-current conversion device 1D( Figure 6 )、voltage-current conversion device 1E( Figure 7 ) and voltage-current conversion device 1F( Figure 8 ) is described with reference to any one of the structures in the embodiment, but it may also be a structure based on a modification example of another structure. In addition, it is also possible to combine the structures of two or more modification examples of the structures of the multiple modification examples described below.

[0086] The NMOS transistors 11 and 12 (and the NMOS transistor 51) may be of a conventional structure, but may preferably be N-type LDMOS transistors, and may be transistors having a triple-well structure. By using these NMOS transistors, the high voltage resistance characteristics can be improved. The N-type LDMOS transistor has an N-type source region and an N-type drain region, and forms an N channel in a P-type region (P-well) directly below the gate electrode. An N-type drift region is formed around the drain region. The structure of LDMOS is described in, for example, U.S. Patent No. 8,357,986 and U.S. Patent No. 10,833,164, and these documents may be referenced as needed. Various types of LDMOS are known.

[0087] Compared with NMOS transistors with the same degree of withstand voltage, N-type LDMOS transistors can be expected to have low on-resistance and good high-frequency characteristics, which helps to achieve improved characteristics when used in combination with the boost unit 30. The N-type LDMOS transistor has a structure that reduces the electric field gradient per unit length between the drain and the gate. As a result, the withstand voltage is high even with the same gate length. For example, the withstand voltage of CMOS with a gate length of 0.13μm is 1.5V, while the withstand voltage of LDMOS with the same gate length can exceed 5V. CMOS with a withstand voltage exceeding 5V needs to follow design rules of more than 0.4μm, so it will be larger, which will lead to increased parasitic capacitance and parasitic resistance. In applications requiring high withstand voltage, by using LDMOS, a circuit with less parasitic resistance and parasitic capacitance and excellent high-frequency characteristics can be realized compared to CMOS.

[0088] In an NMOS transistor having a triple-well structure (refer to Figure 21 ), a deep N-well 102 and a P-well 103 are sequentially formed on a P-type substrate 101. Within the P-well 103, a drain region DR connected to a drain electrode terminal D and a source region SR connected to a source electrode terminal S are formed. Furthermore, a P-well contact (P-type contact region 104) is formed for electrically connecting the P-well 103 to an external circuit. An N-type contact region 105 is formed within the N-well 102, and a P-type contact region 106 is formed within the surface region of the P-type semiconductor substrate 101. Appropriate bias potentials may be applied to these contact regions. Furthermore, isolation regions 107, 108, and 109 are formed near the surface of each well to isolate the contact regions from electrical conduction. An insulating film 130 is formed on the surface of the semiconductor substrate 1, and a gate electrode 131 is formed on the insulating film 130. Gate electrode 131 is connected to a gate electrode terminal G. Multiple P-wells 103 may be formed within a single N-well 102. A (parasitic) diode is formed between the P-well 103 and the N-well, with the P-well as the anode and the N-well as the cathode. The cathode of the parasitic diode can also be connected to a specific potential via the N-type contact area 105 and the contact terminal B. When a potential difference greater than the power supply voltage is applied between the gate of an NMOS transistor of a conventional structure and the substrate, there is a risk of damaging the gate of the NMOS transistor. In contrast, if an NMOS transistor with a triple-well structure is used, the voltage withstand problem can be avoided. When using a transistor with a triple-well structure as the NMOS transistors 11 and 12 (and the NMOS transistor 51), it is preferred as follows Figures 9 to 12 The structures shown in these figures are based on the voltage-current converter 1B ( Figure 2 ) is a variation of .

[0089] exist Figure 9In the structure of the voltage-current converter 1G shown in FIG. 1 , the P-wells of the NMOS transistors 11 and 12 of the current supply circuit 10G having a triple-well structure (see FIG. Figure 21 The P well 103 of the transistor 104 is connected to the first reference potential supply terminal via the parasitic diodes (DA, DB) formed between the wells, and is also connected to the first node N1 via the resistor 15.

[0090] exist Figure 10 In the structure of the voltage-current converter 1H shown in FIG, the NMOS transistors 11 and 12 of the current supply circuit 10H having a triple-well structure each have a P-well (see FIG. Figure 21 The P well 103 of the transistor 10 is connected to the first reference potential supply terminal via the parasitic diodes (DA, DB) formed between the wells, and is connected to the source of the NMOS transistor 11 via the resistor 16.

[0091] exist Figure 11 In the structure of the voltage-current converter 1i shown in FIG. 1 , the NMOS transistors 11 and 12 of the current supply circuit 10i each have a P-well structure (see FIG. Figure 21 The P well 103 of the transistor 10 is connected to the first reference potential supply terminal via the parasitic diodes (DA, DB) formed between the wells, and is connected to the first reference potential supply terminal via the voltage source 17.

[0092] exist Figure 12 In the structure of the voltage-current converter 1J shown in FIG. 1 , the NMOS transistors 11 and 12 of the current supply circuit 10J having a triple-well structure each have a P-well (see FIG. Figure 21 The P well 103 of the transistor is connected to the first reference potential supply terminal via parasitic diodes (DA, DB) formed between the wells, and is also connected to the first reference potential supply terminal via a diode 18.

[0093] By adopting these Figures 9 to 12 The structure shown can prevent a potential difference exceeding the power supply voltage from being applied between the gates of the NMOS transistors 11 and 12 and the substrate, thereby preventing a withstand voltage problem. Figure 9 Compared to the structure shown in Figure 10 In the structure shown, the substrate potential is higher, which alleviates the increase in Vth caused by the substrate bias effect. In addition, there is no potential between the source and the substrate, which is advantageous in that the parasitic capacitance between the source and the substrate is not visible.

[0094] Figure 13 1K is a diagram showing the structure of the voltage-current converter 1K. Figure 2 ) compared to the voltage-current converter 1K ( Figure 13) differs from the first embodiment in that a differential circuit 20K is provided in place of the differential circuit 20A. Differential circuit 20K includes a tail current source 25 between the second reference potential supply terminal and the emitter of NPN transistor 21, and a tail current source 26 between the second reference potential supply terminal and the emitter of NPN transistor 22. Furthermore, a resistor 24 is provided between the emitters of NPN transistors 21 and 22. This configuration generates emitter degeneration, degrading the transconductance of the differential pair. This suppresses gain, increases the input dynamic range, and enables linear operation of the voltage-to-current converter 1K.

[0095] Figure 14 1L is a diagram showing the structure of the voltage-current converter 1L. Figure 2 ) compared to the voltage-current converter 1L ( Figure 14 ) is that it further includes a dummy load 60. The dummy load 60 is connected to the second node N2 and has the same impedance as the load 2. For example, when the load 2 is a laser diode, Figure 15 As shown, dummy load 60 can be configured by connecting a resistor 601 in series with diodes 602 and 603. Diodes 602 and 603 can be formed by connecting the collector and base of an NPN transistor. This configuration with dummy load 60 improves the bilateral symmetry of circuit operation, suppresses the mode dependency of the power supply current, and is effective in suppressing power supply noise.

[0096] Figure 16 1M is a diagram showing the structure of the voltage-current converter 1M. Figure 2 ) compared to the voltage-current converter 1M ( Figure 16 ) is that the resistance value of the third resistor 52 or the current value of the current source 53 is variable. By adopting such a structure, the current flowing through the NMOS transistors 11 and 12 can be adjusted.

[0097] Figure 17 1N is a diagram showing the structure of the voltage-current converter 1N. Figure 3 ) compared to the voltage-current converter 1N ( Figure 17) is different in that it has multiple current supply circuits 10A. Switches 61 and 62 are provided between each current supply circuit 10A in the multiple current supply circuits 10A and the first reference potential supply terminal. A set of switches 61 and 62 is provided for each current supply circuit 10A. By adjusting the number of sets of switches 61 and 62 set to the on state in the multiple sets of switches 61 and 62, the number of current supply circuits 10A connected to the first reference potential supply terminal in the multiple current supply circuits 10A can be changed. By adopting such a structure, the size ratio between the reference path (third NMOS transistor 51, third resistor 52, current source 53) can be changed, so the total current value flowing through the NMOS transistors 11 and 12 can be adjusted. Even if the current value is adjusted, the operating point of the NMOS transistors 11 and 12 is always kept constant, making it easy to expand the current variable range. In addition, the switch 63 set between the drain of the third NMOS transistor 51 and the first reference potential supply terminal is a replica of the switches 61 and 62 set between the drain of the NMOS transistors 11 and 12 and the first reference potential supply terminal. It is always in the on state when in use and can also be not set.

[0098] Figure 18 1A ( Figure 1 ) compared to the voltage-current conversion device 1o( Figure 18 ) is different in that a current supply circuit 10o is provided instead of the current supply circuit 10A. The current supply circuit 10o includes NPN transistors 111 and 112 and resistors 13 and 14.

[0099] The collectors of NPN transistors 111 and 112 are connected to a first reference potential supply terminal that supplies a first reference potential (e.g., a power supply potential). The bases of NPN transistors 111 and 112 are connected to each other. Resistor 13 is provided between the emitter of NPN transistor 111 and node N1. Resistor 14 is provided between the emitter of NPN transistor 112 and node N2. NPN transistors 111 and 112 have the same characteristics. Resistors 13 and 14 have equal resistance values.

[0100] Boosting unit 30 supplies a potential equal to or higher than the first reference potential to the bases of NPN transistors 111 and 112. Control unit 40A controls the potential supplied by boosting unit 30 to the bases of NPN transistors 111 and 112 based on the current flowing through resistor 13 or the potential of node N1.

[0101] The voltage-current conversion device includes: a current supply circuit 10o, a differential circuit 20A, a boost unit 30, and a control unit 40A. The current supply circuit 10o includes a first NPN transistor 111 and a second NPN transistor 112, a first resistor 13, and a second resistor 14. The collectors of the first NPN transistor 111 and the second NPN transistor 112 are connected to a first reference potential supply terminal V1 that supplies a first reference potential. The first resistor 13 is provided between the emitter of the first NPN transistor 111 and a first node N1. The second resistor 14 is provided between the emitter of the second NPN transistor 112 and a second node N2. The bases of the first NPN transistor 111 and the second NPN transistor 112 are connected to each other. The differential circuit 20A includes a third NPN transistor 21, a fourth NPN transistor 22, and a tail current source 23. The third NPN The collector of the transistor 21 is connected to the first node N1, the collector of the fourth NPN transistor 22 is connected to the second node N2, the tail current source 23 is arranged between the second reference potential supply terminal V2 that supplies a second reference potential lower than the first reference potential and the emitters of the third NPN transistor 21 and the fourth NPN transistor 22, the boost unit 30 provides a potential higher than the first reference potential to the bases of the first NPN transistor 111 and the second NPN transistor 112, the control unit 40A controls the potential provided by the boost unit 30 to the bases of the first NPN transistor 111 and the second NPN transistor 112 based on the current flowing in the first resistor 13 or the potential of the first node N1, a differential voltage signal is input to the bases of the third NPN transistor 21 and the fourth NPN transistor 22, and a current signal corresponding to the differential voltage signal is output from the first node N1.

[0102] Voltage-current converter 1A( Figure 1 ) is a current supply circuit 10A including NMOS transistors 11 and 12. In contrast, the voltage-current conversion device 10 ( Figure 18 ) includes NPN transistors 111 and 112. In the latter configuration, a voltage-to-current converter capable of high-speed operation and easy output of a large current amplitude can be realized.

[0103] Figure 19 1P is a diagram showing the structure of the voltage-current converter 1P. Figure 1 ) compared to the voltage-current converter 1P ( Figure 19 ) is different in that a current supply circuit 10P is provided instead of the current supply circuit 10A. The current supply circuit 10P includes an NMOS transistor 11 and a resistor 13.

[0104] The drain of NMOS transistor 11 is connected to a first reference potential supply terminal that supplies a first reference potential (e.g., a power supply potential). Resistor 13 is provided between the source of NMOS transistor 11 and node N1. The collector of NPN transistor 21 is connected to node N1. The collector of NPN transistor 22 is connected to the first reference potential supply terminal. Boosting unit 30 supplies a potential equal to or greater than the first reference potential to the gate of NMOS transistor 11. Control unit 40A controls the potential supplied by the boosting unit to the gate of the NMOS transistor based on the current flowing through the resistor or the potential of the node.

[0105] Voltage-current converter 1A( Figure 1 ) is a current supply circuit 10A including two NMOS transistors 11 and 12 and two resistors 13 and 14. In contrast, the voltage-current converter 1P ( Figure 19 ) includes an NMOS transistor 11 and a resistor 13. In the latter configuration, a voltage-to-current converter capable of high-speed operation and easy output of a large current amplitude can be realized.

[0106] Figure 20 1 is a diagram showing a configuration of a current source device 1Q. The current source device 1Q includes an NMOS transistor 11, a booster unit 30, a control unit 40A, and the like.

[0107] The drain of the NMOS transistor 11 is connected to a first reference potential supply terminal that supplies a first reference potential (e.g., a power supply potential). The current output from the source of the NMOS transistor 11 is input to the load circuit 3. The booster 30 supplies a potential equal to or greater than the reference potential to the gate of the NMOS transistor 11. The control unit 40A controls the potential supplied by the booster 30 to the gate of the NMOS transistor 11 based on the current or potential at a predetermined node within the load circuit 3 to which the current output from the source of the NMOS transistor is input.

[0108] In the configuration example shown in this figure, a current source 42 is provided between the output terminal of the booster section 30 and a second reference potential supply terminal (e.g., a ground potential supply terminal). The control section 40A controls the potential supplied to the gate of the NMOS transistor 11 by adjusting the current flowing through the current source 42 so that the current or potential at a predetermined node within the load circuit 3 reaches a desired value.

[0109] The load circuit 3 may be any circuit, and may be a circuit requiring high-speed operation. In the current source device 1Q, an NMOS transistor 11 is used to supply current. Since a potential higher than the reference potential is applied to the gate of the NMOS transistor 11, high-speed operation and large current amplitude output are facilitated, making it possible to appropriately supply current to the load circuit 3 requiring high-speed operation.

[0110] The above-mentioned device includes the following exemplary elements.

[0111] (Example 1) The voltage-current conversion device according to Example 1 ( Figures 1 to 17 、 Figure 19 ) comprises: a current supply circuit (10A~10J, 10P), which includes a first NMOS transistor 11 having a drain connected to a first reference potential supply terminal V1; a boosting unit 30 (boosting circuit), which has an output terminal connected to the gate of the first NMOS transistor 11; a first resistor (13, 54), which is arranged downstream of the first NMOS transistor 11; an output terminal OUT, which is connected to a first node N1 located downstream of the first resistor; a control unit 40A, which controls the output potential of the boosting unit 30 according to the potential of the first node N1; and a differential circuit, which includes a first NPN transistor arranged downstream of the first NMOS transistor and a second NPN transistor arranged downstream of the first reference potential supply terminal, and a differential input signal is provided to the first base of the first NPN transistor and the second base of the second NPN transistor.

[0112] (Example 2) Regarding the voltage-current conversion device of Example 2 ( Figures 1 to 17 ) is a device in Example 1, wherein the current supply circuit includes a second NMOS transistor 12, wherein the second NMOS transistor 12 has a gate connected to the gate of the first NMOS transistor 11 and a drain connected to the first reference potential supply terminal V1, the output terminal of the boost unit 30 is connected to the gates of the first and second NMOS transistors, and the second NPN transistor 22 of the differential circuit is arranged downstream of the second NMOS transistor 12.

[0113] (Example 3) Regarding the voltage-current conversion device of Example 3 ( Figures 1 to 17 ), in the device of Example 2, there is also a second resistor 14 arranged downstream of the second NMOS transistor 12, the first NPN transistor 11 is arranged downstream of the first resistor 13, the second NPN transistor 22 is arranged downstream of the second resistor 14, and the first node N1 is located between the first resistor 13 and the first NPN transistor 21.

[0114] (Example 4) Regarding the voltage-current conversion device of Example 4 ( Figures 6 to 8 ) is a device in Example 2, wherein one end of the first resistor 54 is connected to a node between the first NMOS transistor 11 and the first NPN transistor 21, and the other end of the first resistor 54 is connected to the first node N1.

[0115] (Example 5) Regarding the voltage-current conversion device of Example 5 ( Figure 2 、 Figure 3 、 Figures 7 to 14 、 Figure 16 、 Figure 17), in the device of Example 2, there is also provided: a third resistor 52, which is arranged between the source of the first NMOS transistor 11 and the third node N3; and a current source 53, which is arranged between the third node N3 and the second reference potential supply terminal V2, and the control unit controls the output potential of the output terminal of the boost unit 30 based on the comparison between the potential of the first node N1 and the potential of the third node N3.

[0116] (Example 6) Regarding the voltage-current conversion device of Example 6 ( Figure 3 、 Figure 8 ), in the device of Example 2, further comprising: a third NMOS transistor 51 having a drain connected to the first reference potential supply terminal V1 and a gate connected to the gates of the first and second NMOS transistors; a third resistor 52, which is arranged between the source of the third NMOS transistor 51 and the third node N3; and a current source 53, which is arranged between the third node N3 and the second reference potential supply terminal V2, and the control unit controls the output potential of the output terminal of the boost unit 30 based on the comparison between the potential of the first node N1 and the potential of the third node N3.

[0117] (Example 7) Regarding the voltage-current conversion device of Example 7, in the device of Example 2, the first NMOS transistor 11 is an N-type laterally double-diffused metal oxide film semiconductor (LDMOS) field effect transistor, and the second NMOS transistor 12 is an N-type laterally double-diffused metal oxide film semiconductor (LDMOS) field effect transistor.

[0118] (Example 8) Regarding the voltage-current conversion device of Example 8 ( Figure 9 ), in the device of Example 2, the first NMOS transistor 11 has a triple-well structure, the second NMOS transistor 12 has a triple-well structure, and a resistor 15 is provided between the P-well of the first NMOS transistor and the P-well of the second NMOS transistor and the first node N1.

[0119] (Example 9) Regarding the voltage-current conversion device of Example 9 ( Figure 10 ), in the device of Example 2, the first NMOS transistor 11 has a triple-well structure, the second NMOS transistor 12 has a triple-well structure, and a resistor 16 is provided between the P-well of the first NMOS transistor 11 and the P-well of the second NMOS transistor 12 and the source of the first NMOS transistor 11.

[0120] (Example 10) Regarding the voltage-current conversion device of Example 10 ( Figure 11), in the device of Example 2, the first NMOS transistor 11 has a triple-well structure, the second NMOS transistor 12 has a triple-well structure, and a voltage source 17 is provided between the P-well of the first NMOS transistor 11 and the P-well of the second NMOS transistor 12 and the first reference potential supply terminal V1.

[0121] (Example 11) Regarding the voltage-current conversion device of Example 11 ( Figure 12 ) is a device in Example 2, wherein the first NMOS transistor 11 has a triple-well structure, the second NMOS transistor 12 has a triple-well structure, and diodes (DA, DB) are provided between the P-well of the first NMOS transistor 11 and the P-well of the second NMOS transistor 12 and the first reference potential supply terminal.

[0122] (Example 12) Regarding the voltage-current conversion device of Example 12 ( Figures 1 to 3 、 Figures 6 to 12 、 Figure 14 、 Figures 16 and 17 、 Figure 19 ), in the device of Example 2, the differential circuit 20A includes a tail current source 23 provided between the first NPN transistor 21, the second NPN transistor 22 and the second reference potential supply terminal V2.

[0123] (Example 13) Regarding the voltage-current conversion device of Example 13 ( Figure 13 ), in the device of Example 2, the differential circuit 20K has a first tail current source 25 arranged between the first NPN transistor 21 and the second reference potential supply terminal V2, and a second tail current source 26 arranged between the second NPN transistor 22 and the second reference potential supply terminal V2.

[0124] (Example 14) Regarding the voltage-current conversion device of Example 14 ( Figure 14 ), in the device of Example 3, a dummy load 60 is provided which is connected to the second node N2 between the second resistor 14 and the second NPN transistor 22.

[0125] (Example 15) Regarding the voltage-current conversion device of Example 15 ( Figure 16 ), in the device of Example 5, the resistance value of the third resistor 52 or the current value of the current source 53 is variable.

[0126] (Example 16) Regarding the voltage-current conversion device of Example 16 ( Figure 17 ) is a device in Example 2 that includes a plurality of current supply circuits 10A, and the number of the plurality of current supply circuits 10A connected to the first reference potential supply terminal V1 is variable.

[0127] (Example 17) The voltage-current conversion device of Example 17 ( Figure 18) comprises: a current supply circuit (10o), which includes a first upstream side NPN transistor 111 having a collector connected to a first reference potential supply terminal V1; a boosting unit 30, which has an output terminal connected to the base of the first upstream side NPN transistor 111; a first resistor 13, which is provided downstream of the first upstream side NPN transistor 111; an output terminal OUT, which is connected to a first node N1 located downstream of the first resistor 13; a control unit 40A, which controls the output potential of the boosting unit 30 according to the potential of the first node N1; and a differential circuit 20A, which includes a first NPN transistor 21 arranged downstream of the first upstream side NPN transistor 111 and a second NPN transistor 22 arranged downstream of the first reference potential supply terminal V1, and the first base of the first NPN transistor 21 and the second base of the second NPN transistor 22 are provided with a differential input signal.

[0128] (Example 18) Regarding the voltage-current conversion device of Example 18 ( Figure 18 ), in the device of Example 17, the current supply circuit 10o includes a second upstream side NPN transistor 112, which has a gate connected to the gate of the first upstream side NPN transistor 111 and a drain connected to the first reference potential supply terminal V1, the output terminal of the boost unit 30 is connected to the gates of the first and second upstream side NMOS transistors, and the second NPN transistor 22 of the differential circuit 20A is arranged downstream of the second upstream side NPN transistor 12.

[0129] (Example 19) Regarding the voltage-current conversion device of Example 19 ( Figure 18 ), in the device of Example 18, there is also a second resistor 14 arranged downstream of the second upstream side NPN transistor 112, the first upstream side NPN transistor 111 is arranged downstream of the first resistor 13, the second NPN transistor 22 is arranged downstream of the second resistor 14, and the first node N1 is located between the first resistor 13 and the first NPN transistor 21.

[0130] (Example 20) Current source device ( Figure 20 ) comprises: a first NMOS transistor 11 having a drain connected to a first reference potential supply terminal V1; a boosting unit 30, which provides a potential higher than the first reference potential to the gate of the first NMOS transistor 11; and a control unit 40A, which controls the potential provided by the boosting unit 30 to the gate of the first NMOS transistor 11 based on the current or potential in the load circuit 3 inputted with the current outputted from the source of the first NMOS transistor 11.

[0131] Various modifications to the above-described embodiments will be readily apparent to those skilled in the art, and the principles defined in this specification can be applied to other embodiments without departing from the scope of this disclosure. The various features of the described embodiments and illustrations may be combined. Individual features are included in different claims, but they may also be combined in advantageous ways. The present invention is not limited to the above-described illustrations, but is set forth in the claims, which are intended to include all modifications within the meaning and scope equivalent to the claims.

[0132] Description of labels

[0133] 1A to 1P: voltage-to-current converter; 1Q: current source; 2: load; 3: load circuit; 10A, 10D, 10G to 10J, 10O, 10P: current supply circuit; 11: first NMOS transistor; 12: second NMOS transistor; 13: first resistor; 14: second resistor; 15: fourth resistor; 16: fifth resistor; 17: voltage source; 18: diode; 111, 112: NPN transistors; 20A, 20K: differential circuit; 2 1: First NPN transistor; 22: Second NPN transistor; 23: Tail current source; 24: Resistor; 25, 26: Tail current source; 30: Boost unit; 40A: Control unit; 40B: Control unit (current extraction amplifier); 41: Low-pass filter; 42: Current source; 51: Third NMOS transistor; 52: Third resistor; 53: Current source; 54: Resistor; 60: Dummy load; 61-63: Switches; N1: First node; N2: Second node; N3: Third node.

Claims

1. A voltage-to-current conversion device comprising: a current supply circuit comprising a first NMOS transistor, a second NMOS transistor, a first resistor, and a second resistor, wherein the drains of the first NMOS transistor and the second NMOS transistor are connected to a first reference potential supply terminal for supplying a first reference potential, the first resistor is provided between the source of the first NMOS transistor and a first node, the second resistor is provided between the source of the second NMOS transistor and a second node, and the gates of the first NMOS transistor and the second NMOS transistor are connected to each other; a differential circuit comprising a first NPN transistor, a second NPN transistor, and a tail current source, wherein the collector of the first NPN transistor is connected to the first node, the collector of the second NPN transistor is connected to the second node, and the tail current source is provided between a second reference potential supply terminal that supplies a second reference potential lower than the first reference potential and the emitters of the first NPN transistor and the second NPN transistor; a booster configured to provide a potential equal to or higher than the first reference potential to each gate of the first NMOS transistor and the second NMOS transistor; as well as a control unit configured to control a potential provided by the boosting unit to each gate of the first NMOS transistor and the second NMOS transistor based on a current flowing through the first resistor or a potential of the first node; A differential voltage signal is input to the base of each of the first NPN transistor and the second NPN transistor, and a current signal corresponding to the differential voltage signal is output from the first node.

2. A voltage-to-current conversion device comprising: a current supply circuit comprising a first NMOS transistor and a second NMOS transistor, wherein the drain of each of the first NMOS transistor and the second NMOS transistor is connected to a first reference potential supply terminal that supplies a first reference potential, and the gates of each of the first NMOS transistor and the second NMOS transistor are connected to each other; a differential circuit comprising a first NPN transistor, a second NPN transistor, and a tail current source, wherein the collector of the first NPN transistor is connected to the source of the first NMOS transistor, the collector of the second NPN transistor is connected to the source of the second NMOS transistor, and the tail current source is provided between a second reference potential supply terminal that supplies a second reference potential lower than the first reference potential and the emitters of the first NPN transistor and the second NPN transistor; a first resistor disposed between a source of the first NMOS transistor and a first node; a booster configured to provide a potential equal to or higher than the first reference potential to each gate of the first NMOS transistor and the second NMOS transistor; as well as a control unit configured to control a potential provided by the boosting unit to each gate of the first NMOS transistor and the second NMOS transistor based on a current flowing through the resistor or a potential of the first node; A differential voltage signal is input to the base of each of the first NPN transistor and the second NPN transistor, and a current signal corresponding to the differential voltage signal is output from the first node.

3. The voltage-current conversion device according to claim 1 or 2, wherein: The voltage-current conversion device further includes a third resistor provided between the source of the first NMOS transistor and a third node, and a current source provided between the third node and the second reference potential supply terminal. The control unit controls the potential provided by the boosting unit to each gate of the first NMOS transistor and the second NMOS transistor based on a comparison between the current flowing through the first resistor or the potential of the first node and the current flowing through the third resistor or the potential of the third node.

4. The voltage-current conversion device according to claim 1 or 2, wherein: The voltage-current conversion device further includes a third NMOS transistor having a drain connected to the first reference potential supply terminal, a third resistor provided between the source of the third NMOS transistor and a third node, and a current source provided between the third node and the second reference potential supply terminal. The gates of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are connected to each other. The control unit controls the potential provided by the boost unit to the gates of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor based on a comparison between the current flowing through the first resistor or the potential of the first node and the current flowing through the third resistor or the potential of the third node.

5. The voltage-current conversion device according to claim 1 or 2, wherein: The first NMOS transistor and the second NMOS transistor are respectively N-type LDMOS transistors.

6. The voltage-current conversion device according to claim 1 or 2, wherein: The first NMOS transistor and the second NMOS transistor each have a triple-well structure, and a resistor is provided between a P-well of each of the first NMOS transistor and the second NMOS transistor and the first node.

7. The voltage-current conversion device according to claim 1 or 2, wherein: The first NMOS transistor and the second NMOS transistor each have a triple-well structure, and a resistor is provided between a P-well of each of the first NMOS transistor and the second NMOS transistor and a source of the first NMOS transistor.

8. The voltage-current conversion device according to claim 1 or 2, wherein: The first NMOS transistor and the second NMOS transistor each have a triple-well structure, and a voltage source is provided between the P-well of each of the first NMOS transistor and the second NMOS transistor and the first reference potential supply terminal.

9. The voltage-current conversion device according to claim 1 or 2, wherein: The first NMOS transistor and the second NMOS transistor each have a triple-well structure, and a diode is provided between the P-well of each of the first NMOS transistor and the second NMOS transistor and the first reference potential supply terminal.

10. The voltage-current conversion device according to claim 1 or 2, wherein: In the differential circuit, a tail current source between the second reference potential supply terminal and the emitter of the first NPN transistor and a tail current source between the second reference potential supply terminal and the emitter of the second NPN transistor are independently provided.

11. The voltage-current conversion device according to claim 1, wherein: A dummy load is connected to the second node.

12. The voltage-current conversion device according to claim 3, wherein: The resistance value of the third resistor or the current value of the current source may be variable.

13. The voltage-current conversion device according to claim 1 or 2, wherein: The voltage-current conversion device includes a plurality of the current supply circuits, and the number of the current supply circuits connected to the first reference potential supply terminal among the plurality of the current supply circuits is variable.

14. A voltage-current conversion device comprising: a current supply circuit comprising a first NPN transistor, a second NPN transistor, a first resistor, and a second resistor, wherein the collectors of the first NPN transistor and the second NPN transistor are connected to a first reference potential supply terminal that supplies a first reference potential, the first resistor is provided between the emitter of the first NPN transistor and a first node, the second resistor is provided between the emitter of the second NPN transistor and a second node, and the bases of the first NPN transistor and the second NPN transistor are connected to each other; a differential circuit comprising a third NPN transistor, a fourth NPN transistor, and a tail current source, wherein the collector of the third NPN transistor is connected to the first node, the collector of the fourth NPN transistor is connected to the second node, and the tail current source is provided between a second reference potential supply terminal that supplies a second reference potential lower than the first reference potential and the emitters of the third NPN transistor and the fourth NPN transistor; a voltage boosting unit configured to provide a potential equal to or greater than the first reference potential to the bases of the first NPN transistor and the second NPN transistor; as well as a control unit that controls a potential provided by the boosting unit to the bases of the first and second NPN transistors based on a current flowing through the first resistor or a potential of the first node; A differential voltage signal is input to the base of each of the third NPN transistor and the fourth NPN transistor, and a current signal corresponding to the differential voltage signal is output from the first node.

15. A voltage-current conversion device comprising: a current supply circuit comprising an NMOS transistor having a drain connected to a first reference potential supply terminal for supplying a first reference potential, and a resistor provided between a source of the NMOS transistor and a node; a differential circuit comprising a first NPN transistor having a collector connected to the node, a second NPN transistor having a collector connected to the first reference potential supply terminal, and a tail current source provided between a second reference potential supply terminal supplying a second reference potential lower than the first reference potential and emitters of the first NPN transistor and the second NPN transistor; a voltage boosting unit configured to provide a potential higher than the first reference potential to the gate of the NMOS transistor; as well as a control unit that controls a potential provided by the boosting unit to the gate of the NMOS transistor based on the current flowing through the resistor or the potential of the node; A differential voltage signal is input to the base of each of the first NPN transistor and the second NPN transistor, and a current signal corresponding to the differential voltage signal is output from the node.

16. A current source device comprising: An NMOS transistor, a drain of which is connected to a reference potential supply terminal for supplying a reference potential; a booster configured to provide a potential higher than the reference potential to the gate of the NMOS transistor; and A control unit controls a potential provided by the boosting unit to the gate of the NMOS transistor based on a current or a potential in a load circuit input with the current output from the source of the NMOS transistor.

17. A voltage-to-current conversion device comprising: a current supply circuit comprising a first NMOS transistor having a drain connected to a first reference potential supply terminal; a boosting unit having an output terminal connected to the gate of the first NMOS transistor; a first resistor disposed downstream of the first NMOS transistor; an output terminal connected to a first node downstream of the first resistor; a control unit configured to control an output potential of the boost unit according to a potential of the first node; as well as The differential circuit includes a first NPN transistor arranged downstream of a first NMOS transistor and a second NPN transistor arranged downstream of a first reference potential supply terminal, wherein a differential input signal is provided to a first base of the first NPN transistor and a second base of the second NPN transistor.

18. The voltage-current conversion device according to claim 17, wherein: The current supply circuit includes a second NMOS transistor having a gate connected to the gate of the first NMOS transistor and a drain connected to the first reference potential supply terminal. The output terminal of the boost unit is connected to the gate of the first NMOS transistor and the gate of the second NMOS transistor. The second NPN transistor of the differential circuit is arranged downstream of the second NMOS transistor.

19. The voltage-current conversion device according to claim 18, wherein: The voltage-current conversion device further includes a second resistor disposed downstream of the second NMOS transistor. The first NPN transistor is arranged downstream of the first resistor, The second NPN transistor is arranged downstream of the second resistor, The first node is located between the first resistor and the first NPN transistor.

20. The voltage-current conversion device according to claim 18, wherein: One end of the first resistor is connected to a node between the first NMOS transistor and the first NPN transistor, The other end of the first resistor is connected to the first node.

21. The voltage-current conversion device according to claim 18, wherein: The voltage-current conversion device further comprises: a third resistor provided between the source of the first NMOS transistor and a third node; and a current source, which is provided between the third node and the second reference potential supply terminal, The control unit controls an output potential of an output terminal of the boosting unit based on a comparison between a potential of the first node and a potential of the third node.

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