A manufacturing method and related device for high-precision intelligent instrument measurement chip

Abstract

The present invention discloses a method for manufacturing a high-precision intelligent instrument measurement chip and related devices. The method first performs multi-stage vacuum annealing and atomic layer reduction etching on the lower copper interconnect, introducing thermo-electric synergistic stress to transform the vacancy-rich layer into <111> preferred grains, thereby obtaining a bonding preparation surface with consistent crystal orientation. Low-temperature copper-copper hot-press bonding is then performed in a controlled inert atmosphere, and the initial thermoelectric potential of the interconnect is captured in real time. Vertical heat flow is established by driving the upper functional area according to a spatially mapped power consumption sequence, and the interface voltage response is collected. The interconnect Seebeck deviation is extracted through timing alignment and differential processing. Based on the deviation results, programmable metal segments in the rewiring layer are used to implement synchronous fusing and parallel connection, constructing a thermoelectrically balanced interconnect network and writing zero-drift calibration values. This scheme eliminates directionally dependent thermoelectric potentials at the material, measurement, and interconnect reconstruction levels, thereby ensuring long-term zero-drift stability of the measurement chain under nanovolt-level noise conditions.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a method for manufacturing a high-precision intelligent instrument measurement chip and related devices. Background Art

[0002] High-precision intelligent instrument measurement chips are system-level integrated circuits (SIICs) specifically designed for precise sensing of weak physical quantities. These chips integrate an ultra-low-noise analog front end, a high-resolution analog-to-digital converter, an on-chip self-calibration network, and a real-time digital algorithm processing unit within a single silicon wafer or a multi-chip stack. Through a highly matched reference power supply and temperature compensation mechanism, the measurement chain maintains long-term linearity and zero-point stability at nanovolt-level noise levels. Compared to traditional instrumentation amplifiers or discrete measurement modules, these chips not only pursue extremely low noise and offset control in hardware design, but also rely on on-chip self-diagnostics and intelligent algorithms to continuously correct for environmental changes and device aging, thereby meeting the high-precision requirements of applications such as industrial process control and precision metering equipment.

[0003] To meet the demands for both analog precision and digital processing power, the current mainstream manufacturing approach utilizes three-dimensional heterogeneous integration technology. Specifically, the bottom chip is fabricated using a high-voltage bipolar complementary metal oxide semiconductor (BCD) process, forming low-noise amplifier circuits and high-linearity analog-to-digital conversion circuits. The top chip, fabricated using an advanced FinFET process, implements digital signal processing and data interface functions. The two layers are vertically connected using low-temperature copper-to-copper hybrid bonding technology, and the overall packaging and heat dissipation design are completed using fan-out wafer-level packaging technology. However, during the low-temperature thermocompression bonding process, a thin film of cuprous oxide (CuO) with a thickness of several nanometers remains on the copper interconnect interface, and the orientation of the copper grains is randomly distributed. During chip operation, the difference in power consumption between the analog and digital circuits generates a thermal gradient in the vertical direction. Due to the different Seebeck coefficients of copper grains in different orientations, coupled with the uneven thickness of the CuO film, heat flow through these non-uniform bonding interfaces generates a direction-dependent thermoelectromotive force. These microvolt-level DC offsets directly affect the measurement system's zero reference, causing unpredictable long-term drift. Because interface thermoelectric potentials don't affect DC resistance, traditional resistance and short-term functional testing can't detect this issue. This makes thermal EMF mismatch at the bond interface a key technical challenge affecting the long-term stability of high-precision smart instrument measurement chips. Summary of the Invention

[0004] The main purpose of the present invention is to solve the technical problem that the existing copper-copper hybrid bonding interface generates direction-dependent thermoelectromotive force under the action of vertical heat flow, which makes it difficult to suppress the measurement zero-point drift.

[0005] A first aspect of the present invention provides a method for manufacturing a high-precision intelligent instrument measurement chip, the method comprising:

[0006] Performing vacuum activation and preferential crystal orientation reconstruction on the exposed copper interconnects of the underlying silicon wafer to remove the oxide film and orient the copper grains along the <111> crystal plane to obtain a processed bonding preparation surface;

[0007] Performing low-temperature hot-press bonding of the copper interconnect of the upper silicon wafer to the bonding preparation surface in an inert atmosphere to form a copper-copper bonding interface, and collecting initial thermoelectric potential data;

[0008] A vertical heat flow is generated by driving the upper functional area to work according to a preset power consumption sequence, collecting thermoelectric potential response data at the copper-copper bonding interface, and generating a thermoelectric potential response curve;

[0009] performing a differential operation based on the initial thermoelectric potential data and the thermoelectric potential response curve to obtain an interconnect Seebeck deviation parameter set;

[0010] The interconnection network is selectively fused or connected in parallel according to the interconnection Seebeck deviation parameter set to form a thermoelectric balance interconnection network and record the zero drift calibration value.

[0011] Preferably, the process of performing vacuum activation and preferential crystal orientation reconstruction on the copper interconnect exposed on the lower silicon wafer to remove the oxide film and orient the copper grains along the <111> crystal plane to obtain a processed bonding preparation surface includes:

[0012] Perform multi-stage gradient vacuum annealing on the exposed copper interconnects of the underlying silicon wafer to remove adsorbed water vapor and weakly adsorbed oxygen molecules by gradually reducing the pressure and increasing the temperature, forming a pre-treated copper interconnect without adsorption components.

[0013] Applying controlled atomic layer reduction etching on the pretreated copper interconnect to remove the surface oxide film and introduce a vacancy-rich layer near the surface to form an activated copper interconnect;

[0014] Applying a directional thermal-electric coupled stress field to the activated copper interconnect to drive the vacancy-rich layer to recrystallize and transform into <111> preferentially oriented grains to obtain preferentially oriented copper interconnects;

[0015] The preferentially oriented copper interconnect is subjected to low-temperature planarization annealing to reduce surface roughness and eliminate residual stress through lateral grain annealing and interface locking, thereby forming a flat bonding preparation surface with consistent crystal orientation.

[0016] Preferably, applying a directional thermo-electric coupled stress field to the activated copper interconnect to drive the vacancy-rich layer to recrystallize and transform into <111> preferentially oriented grains to obtain preferentially oriented copper interconnects comprises:

[0017] Performing a zoned temperature increase process on the activated copper interconnect, establishing an in-plane temperature gradient and limiting the temperature difference amplitude by setting temperature difference zones along the radial direction of the wafer;

[0018] injecting alternating polarity current pulses into the activated copper interconnect during the presence of the vacancy-rich layer, adjusting the pulse amplitude and duty cycle so that the electromigration direction is consistent with the temperature gradient direction;

[0019] Orientation determination processing is performed between current pulse injections, and the degree of grain orientation migration is evaluated in real time based on surface diffraction signal comparison;

[0020] When the orientation determination process indicates that the <111> orientation deviation is lower than a set threshold, the thermal-electrical coordinated processing is terminated and a preferentially oriented copper interconnect is output.

[0021] Preferably, the copper interconnect of the upper silicon wafer is bonded to the bonding preparation surface by performing low-temperature hot-pressing bonding in an inert atmosphere to form a copper-copper bonding interface, and collecting initial thermoelectric potential data, including:

[0022] Performing a spatial six-degree-of-freedom alignment process on the upper silicon wafer in an inert atmosphere controlled chamber, obtaining target alignment gap data through gap monitoring, so that the copper interconnection of the upper silicon wafer and the bonding preparation surface remain in a plane-parallel state;

[0023] performing a pre-press contact process on the upper silicon wafer according to the target alignment gap data, generating a pre-bonded copper interconnect array under a defined pre-press pressure, so that each copper interconnect establishes continuous metal contact with the bonding preparation surface;

[0024] Performing a stepwise temperature-pressure synchronous loading process on the pre-bonded copper interconnect array, increasing the temperature and pressure in stages within a temperature range not exceeding 300 degrees Celsius, completing the formation of a copper-copper bonding interface and recording real-time temperature-pressure process data;

[0025] At the moment when the copper-copper bonding interface is formed, a reference circuit interception process is triggered, and the output voltage of the interconnect array is synchronously collected to obtain the original data of the initial thermoelectric potential of the interconnect;

[0026] According to the real-time temperature-pressure process data, debiasing and filtering processing is performed on the original data of the initial thermoelectric potential of the interconnection, so as to eliminate background stress noise and normalize the data into the initial thermoelectric potential data.

[0027] Preferably, the method of generating a vertical heat flow by driving the upper functional area to operate according to a preset power consumption sequence, collecting thermoelectric potential response data at the copper-copper bonding interface, and generating a thermoelectric potential response curve includes:

[0028] Performing spatial mapping processing on the preset power consumption sequence, allocating the power consumption pulses to the logic blocks corresponding to the interconnect array positions in the upper functional area, and generating a power consumption trigger time stamp set;

[0029] Driving the upper functional area to perform alternating power consumption pulse processing according to the power consumption trigger time scale set, establishing a periodically varying vertical heat flow in the copper-copper bonding structure, and recording power consumption output time history data;

[0030] During the vertical heat flow establishment process, multi-channel acquisition and processing of interface microvoltage are performed synchronously to obtain the original sequence data of interconnected thermoelectric potential;

[0031] Performing time series registration processing on the interconnection thermoelectric potential original sequence data according to the power consumption output time series data, extracting the interconnection Seebeck response window, and forming an interconnection thermoelectric potential time series matrix;

[0032] The interconnected thermoelectric potential time series matrix is ​​subjected to periodic accumulation vector superposition processing to eliminate random noise and retain the main component of heat flow coupling to obtain a thermoelectric potential response curve.

[0033] Preferably, performing a differential operation based on the initial thermoelectric potential data and the thermoelectric potential response curve to obtain an interconnect Seebeck deviation parameter set includes:

[0034] Perform channel mapping index processing on the interconnect initial thermoelectric potential data and the thermoelectric potential response curve, establish a one-to-one correspondence between the initial thermoelectric potential value of the same interconnect and the full cycle response curve, and construct an interconnect thermoelectric potential pairing matrix;

[0035] Performing baseline offset differential processing on each interconnect according to the interconnect thermoelectric potential pairing matrix, subtracting the initial thermoelectric potential value from the corresponding response curve point by point, and obtaining an interconnect thermoelectric differential sequence;

[0036] Performing multi-cycle window function integration processing on the interconnected thermoelectric differential sequence, integrating and averaging the positive and negative segments of each cycle respectively, and extracting the interconnected Seebeck response amplitude vector and polarity vector;

[0037] performing symmetric reference normalization processing based on the interconnection Seebeck response amplitude vector and the polarity vector, eliminating common mode drift with the interconnection array geometric symmetry axis as a reference, and obtaining a normalized Seebeck offset vector;

[0038] Threshold segmentation and arrangement processing are performed on the normalized Seebeck offset vector, the amplitude and direction levels are calibrated, and an interconnected Seebeck deviation parameter set is output.

[0039] Preferably, the selectively fusing or parallel connecting the interconnection network according to the interconnection Seebeck deviation parameter set to form a thermoelectric balance interconnection network and recording the zero drift calibration value includes:

[0040] Performing threshold classification processing on the interconnect Seebeck deviation parameter set to divide the interconnects into a positive deviation group, a negative deviation group, and a negligible group, and generating an interconnect compensation mapping table;

[0041] Performing polarity pairing matching processing on the positive deviation group and the negative deviation group according to the interconnection compensation mapping table, determining the corresponding combination of the target bridge wire to be blown and the parallel connection bridge wire, and obtaining the interconnection topology adjustment plan;

[0042] Performing programmable metal segment selective fusing processing on the rewiring layer according to the interconnection topology adjustment scheme, cutting off the fusing target bridge wire, and generating an intermediate interconnection topology;

[0043] performing an additive metal closing process based on the intermediate interconnection topology to close the parallel connection bridge lines and obtain a thermoelectrically balanced interconnection network;

[0044] A zero point calibration sampling process is performed on the thermoelectric balance interconnection network, the residual thermoelectric potential is measured and written into a storage array, and a zero point drift calibration value is recorded.

[0045] Preferably, performing programmable metal segment selective fusing processing on the rewiring layer according to the interconnection topology adjustment scheme, cutting off the fusing target bridge wire, and generating an intermediate interconnection topology includes:

[0046] forming an isolation protection pattern on the redistribution layer according to the interconnection topology adjustment scheme, depositing a barrier film on the unselected metal bridge lines, and leaving the target metal bridge lines for melting exposed;

[0047] Applying a local energy pulse to the exposed target metal bridge wire, using instantaneous Joule heat to cause electromigration disconnection of the metal bridge wire, thereby generating an open circuit gap;

[0048] After the energy pulse ends, the residue self-shrinkage process is performed, using the metal droplet retraction effect to gather the melted residue to the end of the bridge wire to avoid the retention of metal fragments;

[0049] Connectivity confirmation processing is performed on the open gap, and the intermediate interconnection topology is updated after determining that the disconnection is successful through resistance measurement.

[0050] A second aspect of the present invention provides a manufacturing device for a high-precision intelligent instrument measurement chip, the manufacturing device for a high-precision intelligent instrument measurement chip comprising:

[0051] A crystal orientation reconstruction module is used to perform vacuum activation and preferential crystal orientation reconstruction on the copper interconnects exposed on the underlying silicon wafer, removing the oxide film and orienting the copper grains along the <111> crystal plane to obtain a processed bonding preparation surface;

[0052] A low-temperature bonding module is used to perform low-temperature hot-press bonding of the copper interconnect of the upper silicon wafer to the bonding preparation surface in an inert atmosphere to form a copper-copper bonding interface and collect initial thermoelectric potential data;

[0053] a heat flow excitation measurement module, configured to generate a vertical heat flow by driving the upper functional area to operate according to a preset power consumption sequence, collect thermoelectric potential response data at the copper-copper bonding interface, and generate a thermoelectric potential response curve;

[0054] a differential calculation module, configured to perform a differential operation based on the initial thermoelectric potential data and the thermoelectric potential response curve to obtain a set of interconnection Seebeck deviation parameters;

[0055] The interconnection compensation module is used to selectively fuse or parallel connect the interconnection network according to the interconnection Seebeck deviation parameter set to form a thermoelectric balance interconnection network and record the zero drift calibration value.

[0056] A third aspect of the present invention provides a manufacturing device for a high-precision intelligent meter measuring chip, comprising: a memory and at least one processor, wherein the memory stores instructions, and the memory and the at least one processor are interconnected via a circuit; the at least one processor calls the instructions in the memory to enable the manufacturing device for the high-precision intelligent meter measuring chip to execute the steps of the above-mentioned method for manufacturing the high-precision intelligent meter measuring chip.

[0057] A fourth aspect of the present invention provides a computer-readable storage medium having instructions stored therein. When the computer-readable storage medium is run on a computer, the computer is caused to execute the steps of the above-mentioned method for manufacturing a high-precision intelligent meter measuring chip.

[0058] Zero-point drift within the chip stems from the coupling of an extremely thin oxide film and random grain orientation at the copper-copper bonding interface. When perpendicular heat flows through the interconnect network, the anisotropic Seebeck coefficient generates microvolt-level DC voltages in different directions, causing the zero point of the measurement link to continuously shift. Based on this, the technical solution provided in the embodiments of this application begins with vacuum activation and crystal orientation reconstruction of the underlying copper interconnects. Water vapor and weakly adsorbed oxygen molecules are removed through staged vacuum evacuation and temperature increase. The residual oxide film is then stripped away using controlled atomic layer reduction etching, resulting in a vacancy-rich layer of surface copper atoms. An in-plane temperature gradient and alternating polarity pulsed current are then introduced to align the vacancy migration direction with the temperature gradient. Vacancy aggregation promotes recrystallization toward the <111> crystal plane. The <111> crystal orientation has minimal Seebeck anisotropy and the lowest surface energy. This process compresses the interface base electromotive force differences into a measurable range, creating a uniform starting point for subsequent fine-grained compensation.

[0059] The reconstructed prepared surface and the upper copper interconnect were hot-pressed at low temperature in a controlled inert atmosphere. Temperature, pressure, and voltage profiles were recorded simultaneously during the pressing process. The static thermoelectric potential of the interconnect was captured at the moment when the copper-copper atoms diffused to establish a continuous lattice. This static baseline locked onto the initial Seebeck state after interface deoxidation and crystal orientation alignment, providing a zero reference for dynamic measurements.

[0060] Next, through a pre-planned power consumption sequence, the upper-level logic blocks are spatially rotated into peak operation. This periodic localized heating creates a controlled heat flow in the vertical direction. As the heat flows across the interface, real-time multi-channel sampling captures minute fluctuations in the interconnect voltage. By aligning the sampled waveforms with the power consumption time standard, the pure Seebeck response vector driven by the heat flow can be isolated in the timing matrix. Using a differential operation, the static baseline is subtracted point by point from the dynamic waveform to obtain the net thermoelectric potential of each interconnect in the specific heat flow direction. This result is then normalized to the chip's geometric symmetry axis, eliminating common-mode errors caused by global temperature drift and obtaining accurate deviation polarity and amplitude levels.

[0061] Finally, programmable fusing and paralleling operations are performed on the rewiring layer based on the deviation vector. Interconnects with opposite polarity are bridged into differential pairs, and channels with excessive amplitude are blown and replaced by redundant channels with similar amplitudes. The fusing residues are condensed by the droplet retraction effect, eliminating parasitics. After adjustment, the interface voltage is measured again. If the residual offset falls within the set window, it is written to the memory array as a zero-drift calibration. Through this structural reconstruction performed in situ on the chip, the directionally dependent thermoelectromotive force is converted into a mutually canceling differential pattern, leaving the remaining random components below the noise floor, and fundamentally eliminating the zero-drift problem. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0063] Figure 1 Schematic diagram of an embodiment of a method for manufacturing a high-precision intelligent instrument measurement chip according to an embodiment of the present invention;

[0064] Figure 2 Schematic diagram of an embodiment of a manufacturing device for a high-precision intelligent instrument measurement chip according to an embodiment of the present invention;

[0065] Figure 3 FIG1 is a schematic diagram of an embodiment of a manufacturing device for a high-precision intelligent instrument measurement chip according to an embodiment of the present invention.

[0066] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0067] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0068] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture. If the specific posture changes, the directional indications will also change accordingly.

[0069] In addition, the descriptions of "first", "second", etc. in the present invention are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, "and / or" in the full text includes three solutions. Taking A and / or B as an example, it includes technical solution A, technical solution B, and technical solution that satisfies both A and B. In addition, the technical solutions between the various embodiments can be combined with each other, and must be based on the ability of ordinary technicians in this field to implement. When the combination of technical solutions is mutually contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0070] An embodiment of the present application provides a method for manufacturing a high-precision intelligent instrument measurement chip. Figure 1 A flow chart of a method for manufacturing a high-precision intelligent meter measurement chip according to an embodiment of the present application. In this embodiment, the method includes:

[0071] See also Figure 1 , performing vacuum activation and preferential crystal orientation reconstruction on the copper interconnect exposed on the underlying silicon wafer, removing the oxide film and orienting the copper grains along the <111> crystal plane to obtain a processed bonding preparation surface;

[0072] In one embodiment of the present invention, the step of performing vacuum activation and preferential crystal orientation reconstruction on the copper interconnect exposed on the underlying silicon wafer to remove the oxide film and orient the copper grains along the <111> crystal plane to obtain a processed bonding preparation surface includes:

[0073] Perform multi-stage gradient vacuum annealing on the exposed copper interconnects of the underlying silicon wafer to remove adsorbed water vapor and weakly adsorbed oxygen molecules by gradually reducing the pressure and increasing the temperature, forming a pre-treated copper interconnect without adsorption components.

[0074] Applying controlled atomic layer reduction etching on the pretreated copper interconnect to remove the surface oxide film and introduce a vacancy-rich layer near the surface to form an activated copper interconnect;

[0075] Applying a directional thermal-electric coupled stress field to the activated copper interconnect to drive the vacancy-rich layer to recrystallize and transform into <111> preferentially oriented grains to obtain preferentially oriented copper interconnects;

[0076] The preferentially oriented copper interconnect is subjected to low-temperature planarization annealing to reduce surface roughness and eliminate residual stress through lateral grain annealing and interface locking, thereby forming a flat bonding preparation surface with consistent crystal orientation.

[0077] The following is a detailed description of the steps involved in the above embodiment:

[0078] In the ultra-high vacuum step annealing stage, the wafer loader fixes the lower silicon wafer on the quartz carrier and pushes it into the composite vacuum furnace chamber. The furnace chamber is first evacuated to 1×10 -3 Pa, then the temperature was raised to 120°C at a rate of 2°C per minute and maintained for ten minutes to remove physically adsorbed water vapor; then the temperature was continuously pumped to 1×10 -5 Pa and the temperature was raised to 180℃, the weakly adsorbed oxygen molecules were desorbed by the heat and taken away by the molecular pump. The last evacuation was reduced to 5×10 -6 Pa, while slowly raising the temperature to 230°C. At this pressure-temperature combination, it's difficult for a new oxide layer to form. The loss of H2O and O2 on the copper surface reduces contamination to sub-monomolecule levels, resulting in a pretreated copper interconnect free of adsorbed components. This is easy to understand: if the initial temperature is raised, high-pressure water vapor will recondense in local cold traps. Once the water vapor and oxygen molecules are completely removed, entering a deeper vacuum prevents secondary adsorption and provides a clean interface for subsequent atomic layer etching.

[0079] When the vacuum environment stabilizes, the furnace chamber is switched to a slightly positive pressure of 95% Ar + 5% H2, and the remote radio frequency cracking source is turned on to generate a ≈0.3eV active hydrogen atom beam. The hydrogen atoms react with Cu2O on the copper surface to generate volatile H2O and are immediately extracted without destroying the metal lattice. -1 The low-speed atomic layer etching pulse can evenly remove about 3nm of oxide film without etching the base copper. At the same time, the near-surface layer forms 10 18 cm -3 This vacancy-rich layer is a defect-rich layer with a vacancy concentration greater than one order of magnitude higher than the bulk within the atomic layer thickness. Vacancies provide diffusion sites for subsequent grain rotation; if the defect concentration is insufficient, the efficiency of recrystallization rotation will be significantly reduced. Real-time reflection high-energy electron diffraction (RHEED) monitoring shows that the surface lattice constant remains stable, indicating that the etching process did not produce coarse etch pits.

[0080] Then, in the same cavity, a tungsten wire grid array on a pulsed heating plate was used to construct a radial 20°C cm -1 The in-plane temperature gradient is simultaneously injected into the interconnecting channel with a duty ratio of 50% and an amplitude of 0.8 MA cm -2 Alternating polarity DC pulses. The temperature gradient provides the driving force for thermal migration, and the current pulse provides the directional momentum for electromigration. The superposition of the two fields forms a thermal-electric coupling stress field. This stress field is defined as a composite field in which reversible thermal diffusion potential and electromigration potential exist simultaneously and in the same direction. It can induce the sequential movement of vacancies in the vacancy-rich layer, and promote the orderly expansion of the recrystallization core toward the low end of the temperature difference. Real-time surface electron backscatter diffraction (EBSD) scanning found that the volume fraction of the <111> orientation increased from 25% to 92%, and the reverse pole figure concentration was less than 6°, indicating that the crystal orientation was highly consistent. If the temperature difference is too large, thermal cracks are easily introduced; if the current density exceeds 1MA cm -2 It will also trigger electromigration voids, so the upper limits of the two parameters are given by the copper electromigration critical curve and the stress-relaxation model.

[0081] After the orientation is completed, the temperature is lowered to 150°C and kept for ten minutes to enter the low-temperature flattening annealing stage. This temperature is about 40°C lower than the recrystallization temperature of copper, which can prevent the grains from re-orienting randomly; at the same time, driven by surface tension, adjacent 〈111〉 grains are laterally swallowed to form large sheet-like grains, and the dislocation pairs at the interface are locked, which is called interface locking. After the swallowing is completed, the height of the surface atomic steps is less than 0.8nm, and the average roughness Ra=0.2nm measured by atomic force microscopy (AFM) is one order of magnitude lower than the original oxidized surface; micro-Raman residual stress test shows that the shear stress peak is reduced from 80MPa to 12MPa. The core consideration of this flattening annealing is to obtain extremely low surface energy and extremely low Seebeck anisotropy by suppressing high-temperature regeneration oxidation and maintaining the crystal orientation unchanged, while eliminating the risk of warping during subsequent pressing. The final bonding preparation surface is 10mm 2 Thermocouple voltage dispersion within the region is less than 20nV, fully meeting the zero-drift requirements of the nanovolt measurement chain.

[0082] In one embodiment of the present invention, applying a directional thermo-electric coupled stress field to the activated copper interconnect to drive the vacancy-rich layer to recrystallize and transform into <111> preferentially oriented grains to obtain a preferentially oriented copper interconnect comprises:

[0083] Performing a zoned temperature increase process on the activated copper interconnect, establishing an in-plane temperature gradient and limiting the temperature difference amplitude by setting temperature difference zones along the radial direction of the wafer;

[0084] injecting alternating polarity current pulses into the activated copper interconnect during the presence of the vacancy-rich layer, adjusting the pulse amplitude and duty cycle so that the electromigration direction is consistent with the temperature gradient direction;

[0085] Orientation determination processing is performed between current pulse injections, and the degree of grain orientation migration is evaluated in real time based on surface diffraction signal comparison;

[0086] When the orientation determination process indicates that the <111> orientation deviation is lower than a set threshold, the thermal-electrical coordinated processing is terminated and a preferentially oriented copper interconnect is output.

[0087] The following is a detailed description of the steps involved in the above embodiment:

[0088] When performing zoned heating on activated copper interconnects, an array of independently addressable quartz lamps and a backplane water cooling plate are used to form concentric ring-shaped "temperature difference zones" on the wafer surface. A "temperature difference zone" refers to a band-shaped area where the surface temperature difference between adjacent radial rings is constant. In this embodiment, the temperature difference is 20°C cm -1 The in-plane gradient is: 260°C for the outermost ring, 220°C for the innermost ring, and 2mm for the bandwidth. The gradient value is lower than the activation energy upper limit of copper reoxidation, which can avoid the formation of a new oxide layer; if it is higher than 10°C cm -1 The driving force for spatiotemporal vacancy migration is sufficient to achieve recrystallization orientation within a limited timeframe. Closed-loop temperature control utilizes real-time feedback from an embedded thin-film thermocouple array, with the lamp array adjusting power every 0.5 seconds to ensure that temperature fluctuations within each ring zone do not exceed ±2°C. This step establishes a stable thermal diffusion potential within the wafer plane, directing vacancies toward the radially cooler end. This provides a heat flow reference coordinate for subsequent alignment of electromigration directions, improving orientation consistency and suppressing lateral thermal warpage.

[0089] While the vacancy-rich layer is still in an effective diffusion state, an alternating polarity current pulse is injected into the activated copper interconnect via a multi-channel pulse source. An alternating polarity current pulse is a rectangular current wave with alternating positive and negative polarities within a fixed beat. In this embodiment, the pulse width is set to 20μs, the interval is 20μs, the duty cycle is 50%, and the peak current density is 0.8mA cm -2 The pulse amplitude is lower than the critical density of copper electromigration 1MAcm -2 , which can provide directional momentum without introducing voids; the alternating polarity design makes the average charge flux zero, which can avoid net heating, and at the same time keep the electromigration direction in the same direction as the previously set temperature gradient direction, thus achieving dual-field coupling of thermal diffusion and electromigration. Under this condition, the vacancy moves at an axial speed of 0.2 nm s -1 Orderly movement promotes the radial parallel growth of recrystallization cores, shortens the orientation consistency time and reduces residual stress.

[0090] Current pulses are injected into the gap, using surface diffraction to determine the degree of grain orientation migration in real time. This orientation determination process utilizes 25keV electron backscatter diffraction (EBSD) scanning and a fast Fourier transform matching algorithm. The electron beam scans the top surface of the interconnect at a 5μm grid pitch. The system instantly cross-correlates the resulting diffraction Kikuchi pattern with a <111> standard template, outputting the orientation error angle for each measurement point. The software highlights grid cells with an error angle greater than 5° in red and generates a heat map. The process controller dynamically adjusts the pulse amplitude and temperature difference for the next cycle based on this information. When the local error angle exceeds the target, the current density is increased by 5%, while when it falls below the target, the parameters remain unchanged. This closed-loop determination reduces statistical orientation deviation to an average of 3° within the batch, avoiding under-orientation at the edges or excessive migration in the center due to fixed parameters.

[0091] When real-time statistics show that the orientation deviation of the entire sheet is less than 3° and there is no rebound for three scanning cycles (about 3s), the thermal-electric collaborative processing is terminated and the preferentially oriented copper interconnect is output. Preferentially oriented copper interconnect refers to a copper interconnect layer with a <111> surface fraction of not less than 90% and an in-plane mismatch angle of not more than 3°. After the treatment is completed, the system automatically cools down to 150°C and switches to nitrogen protection to prevent residual heat oxidation; at the same time, the final orientation distribution map is recorded and archived along with the batch number for subsequent quality traceability. This termination judgment can ensure both crystal orientation consistency and low residual stress, and the interface Seebeck anisotropy is controlled at 0.05µVK during subsequent low-temperature hot pressing bonding. -1 Within, it lays the material foundation for the zero drift stability of the entire measurement chain.

[0092] Please continue reading Figure 1 , performing low-temperature hot-press bonding of the copper interconnect of the upper silicon wafer to the bonding preparation surface in an inert atmosphere to form a copper-copper bonding interface, and collecting initial thermoelectric potential data;

[0093] In one embodiment of the present invention, the step of performing low-temperature hot-press bonding of the copper interconnect of the upper silicon wafer to the bonding preparation surface in an inert atmosphere to form a copper-copper bonding interface and collecting initial thermoelectric potential data includes:

[0094] Performing a spatial six-degree-of-freedom alignment process on the upper silicon wafer in an inert atmosphere controlled chamber, obtaining target alignment gap data through gap monitoring, so that the copper interconnection of the upper silicon wafer and the bonding preparation surface remain in a plane-parallel state;

[0095] performing a pre-press contact process on the upper silicon wafer according to the target alignment gap data, generating a pre-bonded copper interconnect array under a defined pre-press pressure, so that each copper interconnect establishes continuous metal contact with the bonding preparation surface;

[0096] Performing a stepwise temperature-pressure synchronous loading process on the pre-bonded copper interconnect array, increasing the temperature and pressure in stages within a temperature range not exceeding 300 degrees Celsius, completing the formation of a copper-copper bonding interface and recording real-time temperature-pressure process data;

[0097] At the moment when the copper-copper bonding interface is formed, a reference circuit interception process is triggered, and the output voltage of the interconnect array is synchronously collected to obtain the original data of the initial thermoelectric potential of the interconnect;

[0098] According to the real-time temperature-pressure process data, debiasing and filtering processing is performed on the original data of the initial thermoelectric potential of the interconnection, so as to eliminate background stress noise and normalize the data into the initial thermoelectric potential data.

[0099] The following is a detailed description of the steps involved in the above embodiment:

[0100] A six-degree-of-freedom (DOF) alignment process is first performed within an inert atmosphere chamber. The upper silicon wafer is secured to a vacuum gripper mounted on a six-axis nanometer displacement stage. The six degrees of freedom (DOF) refer to linear displacement in X, Y, and Z, plus triangular displacement in pitch, yaw, and roll. The stage uses a closed-loop probe consisting of a laser interferometer and a capacitively coupled displacement meter as a positional reference. The in-plane flatness of the lower wafer's bond preparation surface is measured using a white-light interferometer, serving as a static reference. The air gap between the upper copper interconnect and the bond preparation surface is scanned in real time using a multi-band confocal displacement probe with a resolution of 20nm, capable of generating a thermal map of the gap across the entire wafer within 0.2s. The control system automatically calculates the minimum mean square deviation (MSS) posture based on the thermal map and drives the stage for nanometer-level adjustments until the maximum gap across the wafer is below 200nm, with in-plane parallelism error within 2µrad. This process ensures synchronized contact of the copper array during subsequent press-bonding, preventing single-point overpressure from causing localized voids or residual oxide interlayers, and improving overall bonding uniformity.

[0101] When the target alignment gap reaches the set threshold, the upper silicon wafer is moved at 1Ns -1 Pre-pressing is performed with a slope loading until the pressure reaches 4 MPa and enters a steady state. The purpose of the pre-pressing contact stage is to cause all copper bumps to produce an elastic deformation of 1–2%, establishing initial contact between metal atoms without plastic flow; this is called a pre-bonded copper interconnect array. The pre-pressing pressure is selected based on the average roughness of the copper paste end surface and the wafer warpage value. It can smooth out the micro-peaks of large-grained grains while ensuring that fine-grained areas do not shrink excessively. At this stage, online reflection acoustic microscopy is used to verify contact continuity: if the acoustic echo shows the presence of micropores or non-contact areas, the local indenter compensation is adjusted. This allows a continuous metal path to be established without increasing the temperature load, saving a time window for subsequent hot pressing diffusion.

[0102] After completing the pre-pressing, it enters the step-by-step temperature-pressing and synchronous loading; the temperature zone is divided into three platforms: 230℃, 260℃, and 290℃. Each platform is kept warm for two minutes and the pressure is increased from 4MPa to 25MPa simultaneously. The reason for the step setting is that the diffusion rate in the low-temperature section is limited, and it is necessary to activate atomic migration by delayed heat preservation; further large-scale temperature increase above the medium-temperature section is likely to promote abnormal grain growth and cause warping. Synchronous loading ensures that the strain rate matches the diffusion rate, suppressing macroscopic warping and micro-void generation. During the process, a piezoelectric film pressure plate and a thin film thermocouple are embedded between the hot pressing head and the back plate, and the pressure and temperature are recorded every 10ms respectively to generate real-time temperature-pressing process data. This data is subsequently used to filter out pseudo-thermoelectric signals introduced by mechanical oscillations or temperature drifts to ensure detection reliability.

[0103] At the end of the last holding period, when the copper-copper bond interface is formed, synchronous voltage capture is performed via a reference circuit pre-installed in the wiring layer. This reference circuit is a closed copper ring surrounding the outer ring of the interconnect array and connected to a high-speed sampling ADC. The cessation of pressure triggers the photosensor, which samples all channels in parallel within 1µs and latches the interconnect voltage. This voltage represents the initial interconnect thermoelectric potential raw data. The sampling window is designed to be an order of magnitude shorter than the mechanical rebound process, effectively shielding the stress potential caused by pressure relief, ensuring that the measured signal corresponds to the interface thermocouple voltage, rather than strain voltage or parasitic potential.

[0104] The original potential sequence is then debiased and filtered using the recorded real-time temperature and pressure process data. This filtering process is performed in two steps: first, a first-order temperature slope regression is performed on the original sequence using the temperature curve as a reference to deduct the temperature-dependent thermoelectric potential of the copper resistance; then, double exponential smoothing is performed using the pressure curve as a reference to remove voltage glitches introduced by micro-vibration of the indenter. Parameter settings include a temperature regression window of 500ms and a smoothing coefficient of 0.2, which take into account the characteristics of both the transition and steady-state sections. The processed sequence, representing the initial thermoelectric potential data, has its random fluctuations compressed to below the decanovolt level, achieving the high confidence level required for the baseline in the subsequent Seebeck deviation calculation.

[0105] Please continue reading Figure 1 , generating a vertical heat flow by driving the upper functional area to work according to a preset power consumption sequence, collecting thermoelectric potential response data at the copper-copper bonding interface, and generating a thermoelectric potential response curve;

[0106] In one embodiment of the present invention, the method of generating a vertical heat flow by driving the upper functional area to operate according to a preset power consumption sequence, collecting thermoelectric potential response data at the copper-copper bonding interface, and generating a thermoelectric potential response curve includes:

[0107] Performing spatial mapping processing on the preset power consumption sequence, allocating the power consumption pulses to the logic blocks corresponding to the interconnect array positions in the upper functional area, and generating a power consumption trigger time stamp set;

[0108] Driving the upper functional area to perform alternating power consumption pulse processing according to the power consumption trigger time scale set, establishing a periodically varying vertical heat flow in the copper-copper bonding structure, and recording power consumption output time history data;

[0109] During the vertical heat flow establishment process, multi-channel acquisition and processing of interface microvoltage are performed synchronously to obtain the original sequence data of interconnected thermoelectric potential;

[0110] Performing time series registration processing on the interconnection thermoelectric potential original sequence data according to the power consumption output time series data, extracting the interconnection Seebeck response window, and forming an interconnection thermoelectric potential time series matrix;

[0111] The interconnected thermoelectric potential time series matrix is ​​subjected to periodic accumulation vector superposition processing to eliminate random noise and retain the main component of heat flow coupling to obtain a thermoelectric potential response curve.

[0112] The following is a detailed description of the steps involved in the above embodiment:

[0113] After the inert packaging is completed, the preset power consumption sequence is first spatially mapped. The power consumption sequence is output by the on-chip power consumption scheduler and is a set of rectangular pulses with a duty cycle of 50%, each with a pulse width of 10µs. The scheduler calls the back-end physical design database to map the two-dimensional coordinates of the interconnect array to the logic blocks of the upper functional area, and establishes a logic block-interconnect comparison table. The mapping principle adopts nearest neighbor matching: each interconnect corresponds to the logic block with the highest power consumption density within a radius of 50µm, ensuring that the heat source is directly opposite the interconnect throttling point. After the comparison table is downloaded to the on-chip power consumption control unit, a power consumption trigger time stamp set is generated. The time stamp set records the start and end time of each logic block pulse for subsequent heat flow synchronization. This step directly establishes the heat source-interconnect mapping with the help of physical design coordinates to ensure that the thermal excitation positioning accuracy is within ±10µm, thereby reducing the in-plane diffusion error of the temperature gradient.

[0114] When driving the upper functional area to implement alternating power pulses based on the power trigger time stamp set, the power control unit alternately activates logic blocks in row and column parity order, ensuring that adjacent logic blocks operate in opposite phases. The pulse amplitude is limited to 80% of full-load power consumption by an on-chip voltage regulator to prevent instantaneous power supply collapse. The pulse interval is 10µs to ensure that the temperature rise at the underlying copper-copper bond interface remains stable below 12K. This alternating power pulse establishes a periodic heat flow in the vertical direction, with the period determined by the pulse width and interval, forming a repetitive 20µs heat flow waveform. The power output time history data is fed into an off-chip logic analyzer in real time through the power control unit port. The logic analyzer has a time resolution of 1ns and can fully record the power consumption waveform of each logic block. This alternating pulse method repeatedly reverses the direction of heat flow in the same area, amplifying the Seebeck voltage modulation depth without increasing the average temperature.

[0115] During the vertical heat flow establishment process, multi-channel acquisition and processing of interface microvoltages are performed synchronously. A high-speed microvoltage sampling array with a bandwidth of 1kHz is arranged around the bonding interface, with each interconnection occupying a dedicated channel. The sampling array uses a Σ-Δ ADC, outputting 24-bit quantized results at a 128x oversampling rate. The sampling clock is provided by the power control unit to ensure phase alignment with the power sequence. Synchronous sampling lasts for 2ms, and a 1×10 5 The sampling arrays are wired with equal lengths, and the delay difference between channels is less than 100 ps, ​​effectively suppressing the impact of timing jitter on amplitude measurements.

[0116] Timing alignment is performed on the raw sequence data of the interconnect thermoelectric potential based on the power output time series data. The data processing unit uses the time stamp set as an anchor point to segment the power and voltage waveforms into segments of equal length. The end of each segment is aligned, and alignment is considered successful when the maximum cross-correlation peak within the segment reaches or exceeds 0.9. Voltage data within the 0-10µs window along the rising edge of the power pulse is then extracted to obtain the interconnect Seebeck response window. All windows are arranged sequentially by interconnect number to form the interconnect thermoelectric potential timing matrix. Timing alignment eliminates internal delays and signal path variations within the logic blocks, ensuring a strict one-to-one correspondence between the thermal flow stimulus and the voltage response, thus avoiding amplitude attenuation and phase drift.

[0117] When performing periodic cumulative vector superposition on the interconnect thermoelectric potential time series matrix, the algorithm first performs parity grouping on each interconnect's window sequence, sign-reversing sequences with opposite phases before summing the results and taking the arithmetic average across all cycles. This superposition operation is equivalent to extracting the main vector component with the same excitation fundamental frequency in the frequency domain, while simultaneously canceling out white noise and anharmonic components. After 20 iterations, the random noise variance is reduced to 1 / 20 of the initial value, and the final thermoelectric potential response curve is output. The peak-to-peak value of the response curve directly reflects the Seebeck voltage of the interconnect under maximum heat flow conditions. The curve is phase-locked to the power consumption pulse time scale, facilitating subsequent differential operations. The entire process uses integer sampling points and sign reversal, eliminating the need for floating-point convolution operations. This process can be completed in real time on the on-chip digital signal processor, ensuring that the data is formatted in a standard, directly comparable format before leaving the test bench.

[0118] Please continue reading Figure 1 , performing a differential operation based on the initial thermoelectric potential data and the thermoelectric potential response curve to obtain a set of interconnect Seebeck deviation parameters;

[0119] In one embodiment of the present invention, performing a differential operation based on the initial thermoelectric potential data and the thermoelectric potential response curve to obtain a set of interconnect Seebeck deviation parameters includes:

[0120] Perform channel mapping index processing on the interconnect initial thermoelectric potential data and the thermoelectric potential response curve, establish a one-to-one correspondence between the initial thermoelectric potential value of the same interconnect and the full cycle response curve, and construct an interconnect thermoelectric potential pairing matrix;

[0121] Performing baseline offset differential processing on each interconnect according to the interconnect thermoelectric potential pairing matrix, subtracting the initial thermoelectric potential value from the corresponding response curve point by point, and obtaining an interconnect thermoelectric differential sequence;

[0122] Performing multi-cycle window function integration processing on the interconnected thermoelectric differential sequence, integrating and averaging the positive and negative segments of each cycle respectively, and extracting the interconnected Seebeck response amplitude vector and polarity vector;

[0123] performing symmetric reference normalization processing based on the interconnection Seebeck response amplitude vector and the polarity vector, eliminating common mode drift with the interconnection array geometric symmetry axis as a reference, and obtaining a normalized Seebeck offset vector;

[0124] Threshold segmentation and arrangement processing are performed on the normalized Seebeck offset vector, the amplitude and direction levels are calibrated, and an interconnected Seebeck deviation parameter set is output.

[0125] The following is a detailed description of the steps involved in the above embodiment:

[0126] When performing channel mapping and indexing of the interconnect's initial thermoelectric potential data and thermoelectric potential response curves, the data processing unit first calls the interconnect number-sampling channel comparison table generated during the bond test phase to bind each interconnect's initial thermoelectric potential value to the full-cycle response curve of the sampling channel with the same number. The two types of data are then populated into a single two-dimensional array, using the interconnect number as the row index and the sampling point number as the column index, thus forming a thermoelectric potential pairing matrix. Within this matrix, each row contains the complete voltage waveform and corresponding static baseline sampled for that interconnect between time 0 and time T, ensuring point-by-point comparison within a unified coordinate system for subsequent operations. The matrix format utilizes a double-buffered storage structure, enabling conflict-free row and column parallel reads and writes within the on-chip SRAM (static random access memory array integrated on the same silicon die), avoiding timing jitter caused by bus contention. This mapping and indexing ensures a strict one-to-one correspondence between the static baseline and the dynamic response, eliminating the risk of mismatches caused by inconsistent sampling timing among multiple ADCs.

[0127] When performing baseline-offset differential processing on each interconnect based on the interconnect thermoelectric potential pairing matrix, the algorithm, within the hardware pipeline, subtracts the static baseline value of the same interconnect from the response value of each sampling point, outputting a sequence of interconnect thermoelectric differentials. This operation utilizes a fixed-point subtraction circuit combined with overflow detection logic to preserve microvolt-level differential information with a 24-bit width. The subtraction eliminates the inherent static thermoelectric potential of the copper-copper interface and the op amp input offset on a point-by-point basis. After differentiation, the waveform remains only with the AC component generated by the periodic heat flow modulation, providing a clean signal source for subsequent amplitude and polarity extraction. The hardware implementation latches the constant baseline into a register array, allowing parallel subtraction to be completed within a single clock cycle, avoiding the introduction of additional noise from moving large matrices off-chip.

[0128] When applying a multi-cycle window function integration to the interconnect's thermoelectric differential sequence, the processor segments the differential sequence using a 20µs rectangular window. Within each segment, the positive and negative half-waves are weighted and integrated using a 10µs symmetrical Hanning window. The difference between the two integrated results yields the single-cycle net Seebeck voltage. This multi-cycle integration, performed by accumulating and averaging 100 adjacent cycles, reduces the random noise variance to one-tenth of its original value according to the 1 / √N law. The integration window width is equal to the pulse period, ensuring that all useful power frequency energy is captured without introducing phase distortion. The weighting function mitigates sudden changes along the window edge and prevents the expansion of spectral sidelobes. The output is stored as a vector, representing the Seebeck response amplitude and polarity vectors. The amplitude component captures the peak-to-valley difference, while the polarity component uses the sign bit to indicate the direction. This resulting vector contains both amplitude and direction information, directly reflecting the interconnect's thermoelectric sensitivity under maximum heat flux.

[0129] When performing symmetric reference normalization on the interconnect Seebeck response amplitude and polarity vectors, the system averages the amplitudes of symmetrically positioned interconnects, using the geometric symmetry axis of the interconnect array as a reference. Each interconnect amplitude is then divided by the corresponding average to produce a dimensionless ratio. For interconnects with opposite orientations, the sign is maintained to preserve polarity. Symmetric reference normalization offsets low-order temperature distortion and common-mode power supply perturbations across the wafer through spatial pairing, ensuring that the normalized Seebeck offset vector reflects only local anomalies caused by orientation differences and micro-interface defects within the interconnects themselves. This normalization step does not require an external reference temperature field and is accomplished directly using the array's inherent geometric characteristics, eliminating the need for additional thermal noise injection.

[0130] When performing threshold segmentation and sorting on the normalized Seebeck offset vector, amplitude thresholds ε1 and ε2 are first set, where ε1 is the upper limit of the negligible region and ε2 is the lower limit of the compensation region. The processor traverses the vector, marking interconnects with amplitudes less than ε1 as zero offset, interconnects between ε1 and ε2 as slight offset, and interconnects exceeding ε2 as large offset. The vector is then sorted by polarity, from largest to smallest, to form a list of positive and negative offsets, respectively. These lists are then combined to generate a set of interconnect Seebeck offset parameters. The threshold range is determined by statistical analysis: ε1 is 1.5 times the standard deviation of the median of the full-chip amplitude distribution to filter out random noise; ε2 is the 90th percentile of the amplitude distribution to identify significantly abnormal interconnects. The output parameter set provides the deviation level and direction for each interconnect, providing an accurate, recalibration-free data foundation for subsequent fusing and shunt compensation.

[0131] Please continue reading Figure 1 , selectively fusing or parallel connecting the interconnection network according to the interconnection Seebeck deviation parameter set to form a thermoelectric balance interconnection network and record the zero drift calibration value.

[0132] In one embodiment of the present invention, the selectively fusing or parallel connecting the interconnection network according to the interconnection Seebeck deviation parameter set to form a thermoelectric balance interconnection network and recording the zero drift calibration value includes:

[0133] Performing threshold classification processing on the interconnect Seebeck deviation parameter set to divide the interconnects into a positive deviation group, a negative deviation group, and a negligible group, and generating an interconnect compensation mapping table;

[0134] Performing polarity pairing matching processing on the positive deviation group and the negative deviation group according to the interconnection compensation mapping table, determining the corresponding combination of the target bridge wire to be blown and the parallel connection bridge wire, and obtaining the interconnection topology adjustment plan;

[0135] Performing programmable metal segment selective fusing processing on the rewiring layer according to the interconnection topology adjustment scheme, cutting off the fusing target bridge wire, and generating an intermediate interconnection topology;

[0136] performing an additive metal closing process based on the intermediate interconnection topology to close the parallel connection bridge lines and obtain a thermoelectrically balanced interconnection network;

[0137] A zero point calibration sampling process is performed on the thermoelectric balance interconnection network, the residual thermoelectric potential is measured and written into a storage array, and a zero point drift calibration value is recorded.

[0138] The following is a detailed description of the steps involved in the above embodiment:

[0139] The threshold classification process takes a normalized Seebeck shift vector as input. The processor first performs an absolute value operation on the vector to obtain an amplitude array, then applies off-chip fixed thresholds ε1 and ε2. ε1 corresponds to the upper bound of 1.5 times the standard deviation of the statistical distribution and is used to determine the negligible region of measurement noise; ε2 corresponds to the 9th decile of the distribution and is used to capture significantly mismatched interconnects. After a line-by-line comparison, the algorithm writes interconnects with amplitudes less than ε1 to the negligible group, those with amplitudes between the two thresholds to the slight deviation buffer, and those with amplitudes ≥ ε2 to either the positive deviation group or the negative deviation group, depending on polarity. The interconnect number, amplitude, and polarity of each interconnect are stored in a three-column structure and separated by polarity to form an interconnect compensation mapping table. The thresholds are soft registers that can be updated based on test piece statistics, rather than being fixed in the logic. This ensures that the classification criteria consistently align with the actual drift distribution across different batches and measurement environments. The classification results present a large number of interconnects in three labeled states. Subsequent logic only needs to compensate for the "positive" and "negative" categories, significantly reducing iteration time.

[0140] Polarity pairing is performed within the on-chip DMA controller. The controller reads the positive and negative deviation lists in descending order of amplitude, searching for complementary pairs using the closest amplitude principle: If the amplitude difference between two interconnects does not exceed 10%, the larger-amplitude number is recorded as the target bridge line for the fuse, and the other number is recorded as the parallel-connected bridge line. Both are written into the interconnect topology adjustment plan. If no match exists, the remaining single-sided interconnect is paired with the negligible group of interconnects with the smallest amplitude to ensure the minimum Seebeck sum of the network. This pairing logic does not require floating-point operations and relies only on absolute value comparison of amplitude differences, making it suitable for hardware pipeline implementation. The output adjustment plan is sent to the rewiring layer reconstruction unit in the form of a fuse number-close number key-value pair, providing a clear action list for subsequent programmable operations.

[0141] Programmable metal segment selective fusing is performed using a femtosecond UV laser processing machine, which directly illuminates the rewiring layer through a window in the glass cover. The target bridge wire for fusing is a pre-placed 8µm-wide, 2µm-thin, high-aluminum copper alloy wire; a 2µm x 1µm "thinned neck" is designed in the center as a fusible zone. The laser system positions each wire point according to the adjustment plan. A single pulse energy of 5µJ is sufficient to vaporize the neck and create an open circuit gap of ≥3µm. After fusing, the open circuit resistance is immediately measured with a microresistance meter, ensuring a value >1MΩ to determine a successful disconnection. The measurement result is recorded along with the bridge wire number in the intermediate interconnect topology. The femtosecond laser heat-affected zone is less than 0.1µm deep, avoiding contact with the underlying copper pillars and preventing remelting contamination. After fusing, the intermediate interconnect topology exhibits multiple open circuits, geometrically breaking the original Seebeck mismatch path and providing space for the next parallel connection.

[0142] Additive metal closure is achieved by area electroplating. A 3µm gap is reserved for the parallel connection bridge line and covered with photoresist; the corresponding photoresist is removed by exposure according to the adjustment scheme, and then the 5mA cm -2A 1.5µm thick layer of copper is electroplated at a current density of 100 nm. The copper solution self-aligns and fills the bridge wire sidewalls until the metal ends make contact, forming a low-resistance connection. A plating time of 30 seconds ensures resistance drops to the 10mΩ level. After closing, the DC impedance is measured again to verify the parallel connection is successful, and the measured value is stored in the thermoelectric balance interconnection network database. Symmetrical parallel connection cancels out the positive and negative Seebeck electromotive forces at the physical circuit level, theoretically paving the way for zero-drift stability.

[0143] The fifth stage of zero-point calibration sampling uses an on-chip 24-bit Σ-Δ ADC to scan the entire interconnect after reconstruction. This sampling is repeated three times at a constant temperature of 25°C and averaged to produce a residual thermoelectric potential matrix. After the system determines that the residual amplitude of all interconnects is less than ε1, the average residual value is written to the on-chip fuse array as the zero-point drift calibration value. This calibration value is used for compensation during final product self-test, ensuring a fixed reference for closed-loop temperature drift control during field operation. After sampling is complete, the processor shuts down the power sequence generator and enters low-power standby mode, completing the closed-loop compensation chain. By the time the chip leaves the factory, the direction-dependent thermoelectric drift has been suppressed to within the detection noise floor.

[0144] In one embodiment of the present invention, performing programmable metal segment selective fusing processing on the rewiring layer according to the interconnection topology adjustment scheme, cutting off the fusing target bridge wire, and generating an intermediate interconnection topology includes:

[0145] forming an isolation protection pattern on the redistribution layer according to the interconnection topology adjustment scheme, depositing a barrier film on the unselected metal bridge lines, and leaving the target metal bridge lines for melting exposed;

[0146] Applying a local energy pulse to the exposed target metal bridge wire, using instantaneous Joule heat to cause electromigration disconnection of the metal bridge wire, thereby generating an open circuit gap;

[0147] After the energy pulse ends, the residue self-shrinkage process is performed, using the metal droplet retraction effect to gather the melted residue to the end of the bridge wire to avoid the retention of metal fragments;

[0148] Connectivity confirmation processing is performed on the open gap, and the intermediate interconnection topology is updated after determining that the disconnection is successful through resistance measurement.

[0149] The following is a detailed description of the steps involved in the above embodiment:

[0150] When forming the isolation protection pattern in the redistribution layer, a list of target metal bridges is first generated based on the interconnect topology adjustment plan. These metal bridges are 8µm-wide, 2µm-high aluminum-copper alloy branches designed specifically for programmable reconfiguration and located on the outermost layer of the redistribution layer. After vacuum plasma cleaning, the wafer is spin-coated with 3µm photoresist. A 248nm deep UV exposure process is used to transfer the protection pattern, covering all bridges except for the listed target metal bridges. Subsequently, a 200nm silicon nitride barrier film is deposited in a -30°C evaporation chamber. Silicon nitride has high dielectric strength and low thermal conductivity, protecting adjacent metal from heating caused by laser or pulse energy. After development, only the target bridges remain exposed. The isolation protection pattern ensures that energy is concentrated in the highly fusible areas during localized energy processing, preventing heat coupling to functional interconnects or underlying copper pillars. This reduces the risk of electromigration of non-target lines and improves the predictability of blown holes.

[0151] When applying a localized energy pulse to the exposed metal bridge wire, a femtosecond fiber laser coupled with a 0.5NA microscope objective is focused at the center of the bridge wire's "thinned neck." The "thinned neck" is designed to have a depth of 1µm and a width of 2µm, resulting in a cross-sectional area that is only 50% of the bridge wire's bulk, significantly reducing the melting threshold. The laser outputs a single pulse energy of 5µJ with a pulse width of 300fs. This transient Joule heating elevates the local temperature to approximately 1100K, exceeding the melting point of the Al-Cu alloy. Electromigration rapidly occurs under this temperature-electric field coupling, with atoms migrating in the direction of the electron flow. The metal in the neck liquefies and is driven outward by surface tension, forming an approximately 3µm open-circuit gap in the center. The femtosecond laser heat-affected zone (HAZ) is less than 100nm deep, leaving the surrounding metal lattice intact. This parameter selection allows for complete material migration within a single pulse without generating melt pool splash, thus preventing impurity craters from entering the functional area.

[0152] Immediately after the energy pulse ends, the residue undergoes a self-shrinkage process. This process exploits the retraction effect of a metal droplet: driven by surface tension, the molten metal shrinks toward the end of the bridge line, forming two hemispherical metal beads upon cooling. To accelerate this retraction, a continuous flow of 60 sccm of dry nitrogen and a chamber pressure of 0.9 atm are maintained within 1 ms of the melt completion, reducing the ambient heat dissipation impedance and shortening the solidification time to <5 ms. Optical microscopy confirms that the spherical residue is less than 3 µm in diameter and remains within a defined area. The retraction operation eliminates metal splashing and prevents conductive particles from floating in the gaps between the redistribution layers, potentially causing short circuits.

[0153] Connectivity verification utilizes a four-wire resistance measurement method. Probe card pins apply a 2mA test current simultaneously to both ends of the fuse bridge wire through contact pads. A digital milliohmmeter with a resolution of 10µΩ is used; a reading above 1MΩ is considered a successful disconnect. The detection software compares the measurement results with the programmed list in real time. If any bridge wire fails to meet the threshold, it is marked as "fuse failure" and the laser is re-fired. Once all bridge wires pass verification, the system writes a new connection matrix to the on-chip SRAM, updating the intermediate interconnect topology. This connectivity verification not only verifies electrical opens but also ensures that debris has not formed metal bridges across the open gaps, improving the matching accuracy of the subsequent additive closure process.

[0154] The above describes the manufacturing method of the high-precision intelligent instrument measurement chip according to the embodiment of the present invention. The following describes the manufacturing device of the high-precision intelligent instrument measurement chip according to the embodiment of the present invention. Figure 2 An embodiment of a manufacturing device for a high-precision intelligent instrument measurement chip according to an embodiment of the present invention includes:

[0155] The crystal orientation reconstruction module 101 is used to perform vacuum activation and preferential crystal orientation reconstruction on the copper interconnects exposed on the underlying silicon wafer, remove the oxide film and orient the copper grains along the <111> crystal plane to obtain a processed bonding preparation surface;

[0156] A low-temperature bonding module 102 is used to perform low-temperature hot-press bonding of the copper interconnect of the upper silicon wafer to the bonding preparation surface in an inert atmosphere to form a copper-copper bonding interface and collect initial thermoelectric potential data;

[0157] a heat flow excitation measurement module 103 for generating a vertical heat flow by driving the upper functional area to operate according to a preset power consumption sequence, collecting thermoelectric potential response data at the copper-copper bonding interface, and generating a thermoelectric potential response curve;

[0158] a differential calculation module 104 for performing a differential operation based on the initial thermoelectric potential data and the thermoelectric potential response curve to obtain a set of interconnection Seebeck deviation parameters;

[0159] The interconnection compensation module 105 is used to selectively fuse or parallel connect the interconnection network according to the interconnection Seebeck deviation parameter set to form a thermoelectric balance interconnection network and record the zero drift calibration value.

[0160] above Figure 2 The manufacturing device of the high-precision intelligent meter measurement chip in the embodiment of the present invention is described in detail from the perspective of modular functional entities. The manufacturing equipment of the high-precision intelligent meter measurement chip in the embodiment of the present invention is described in detail from the perspective of hardware processing.

[0161] Figure 3This is a schematic diagram of the structure of a high-precision smart meter measurement chip manufacturing apparatus provided by an embodiment of the present invention. The high-precision smart meter measurement chip manufacturing apparatus 200 may vary significantly depending on configuration or performance. It may include one or more processors 210 (e.g., one or more processors), memory 220, and one or more storage media 230 (e.g., one or more mass storage devices) storing application programs 233 or data 232. The memory 220 and storage medium 230 may be either transient or persistent storage. The program stored in the storage medium 230 may include one or more modules (not shown), each of which may include a series of instructions for operating on the high-precision smart meter measurement chip manufacturing apparatus 200. Furthermore, the processor 210 may be configured to communicate with the storage medium 230, executing the series of instructions stored in the storage medium 230 on the high-precision smart meter measurement chip manufacturing apparatus 200 to implement the steps of the above-described method for manufacturing a high-precision smart meter measurement chip.

[0162] The manufacturing equipment 200 for high-precision intelligent meter measurement chips may further include one or more power supplies 240, one or more wired or wireless network interfaces 250, one or more input and output interfaces 260, and / or one or more operating systems 231, such as Windows Server, Mac OS X, Unix, Linux, FreeBSD, etc. It will be understood by those skilled in the art that Figure 3 The structure of the manufacturing equipment for the high-precision smart meter measurement chip shown does not limit the manufacturing equipment for the high-precision smart meter measurement chip provided by the present invention, and may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0163] The present invention also provides a computer-readable storage medium, which can be a non-volatile computer-readable storage medium or a volatile computer-readable storage medium. The computer-readable storage medium stores instructions. When the instructions are executed on a computer, the computer executes the steps of the method for manufacturing the high-precision intelligent instrument measurement chip.

[0164] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems, devices, and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0165] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes various media that can store program code, such as a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0166] The above description is only a preferred embodiment of the present invention and does not limit the patent scope of the present invention. All equivalent structural transformations made by using the contents of the present invention description and drawings under the inventive concept of the present invention, or direct / indirect application in other related technical fields are included in the patent protection scope of the present invention.

Claims

1. A method for manufacturing a high-precision intelligent instrument measurement chip, characterized in that: include: Performing vacuum activation and preferential crystal orientation reconstruction on the exposed copper interconnects of the underlying silicon wafer to remove the oxide film and orient the copper grains along the <111> crystal plane to obtain a processed bonding preparation surface; Performing low-temperature hot-press bonding of the copper interconnect of the upper silicon wafer to the bonding preparation surface in an inert atmosphere to form a copper-copper bonding interface, and collecting initial thermoelectric potential data; A vertical heat flow is generated by driving the upper functional area to work according to a preset power consumption sequence, collecting thermoelectric potential response data at the copper-copper bonding interface, and generating a thermoelectric potential response curve; performing a differential operation based on the initial thermoelectric potential data and the thermoelectric potential response curve to obtain an interconnect Seebeck deviation parameter set; According to the interconnection Seebeck deviation parameter set, the interconnection network is selectively fused or connected in parallel to form a thermoelectrically balanced interconnection network and record the zero-point drift calibration value, specifically including: performing threshold classification processing on the interconnection Seebeck deviation parameter set, dividing the interconnection into a positive deviation group, a negative deviation group and a negligible group, and generating an interconnection compensation mapping table; performing polarity pairing matching processing on the positive deviation group and the negative deviation group according to the interconnection compensation mapping table, determining the corresponding combination of the fused target bridge line and the parallel-connected bridge line, and obtaining an interconnection topology adjustment scheme; performing programmable metal segment selective fusing processing on the rewiring layer according to the interconnection topology adjustment scheme, cutting off the fused target bridge line, and generating an intermediate interconnection topology; performing additive metal closure processing on the intermediate interconnection topology, closing the parallel-connected bridge line, and obtaining a thermoelectrically balanced interconnection network; performing zero-point calibration sampling processing on the thermoelectrically balanced interconnection network, measuring the residual thermoelectric potential and writing it into a storage array, and recording the zero-point drift calibration value.

2. The method for manufacturing a high-precision intelligent instrument measurement chip according to claim 1, characterized in that: The method of performing vacuum activation and preferential crystal orientation reconstruction on the copper interconnect exposed on the lower silicon wafer to remove the oxide film and orient the copper grains along the <111> crystal plane to obtain a processed bonding preparation surface includes: Perform multi-stage gradient vacuum annealing on the exposed copper interconnects of the underlying silicon wafer to remove adsorbed water vapor and weakly adsorbed oxygen molecules by gradually reducing the pressure and increasing the temperature, forming a pre-treated copper interconnect without adsorption components. Applying controlled atomic layer reduction etching on the pretreated copper interconnect to remove the surface oxide film and introduce a vacancy-rich layer near the surface to form an activated copper interconnect; Applying a directional thermal-electric coupled stress field to the activated copper interconnect to drive the vacancy-rich layer to recrystallize and transform into <111> preferentially oriented grains to obtain preferentially oriented copper interconnects; The preferentially oriented copper interconnect is subjected to low-temperature planarization annealing to reduce surface roughness and eliminate residual stress through lateral grain annealing and interface locking, thereby forming a flat bonding preparation surface with consistent crystal orientation.

3. The method for manufacturing a high-precision intelligent instrument measurement chip according to claim 2, characterized in that: The step of applying a directional thermo-electric coupling stress field to the activated copper interconnect to drive the vacancy-rich layer to recrystallize and transform it into <111> preferentially oriented grains to obtain a preferentially oriented copper interconnect comprises: Performing a zoned temperature increase process on the activated copper interconnect, establishing an in-plane temperature gradient and limiting the temperature difference amplitude by setting temperature difference zones along the radial direction of the wafer; injecting alternating polarity current pulses into the activated copper interconnect during the presence of the vacancy-rich layer, adjusting the pulse amplitude and duty cycle so that the electromigration direction is consistent with the temperature gradient direction; Orientation determination processing is performed between current pulse injections, and the degree of grain orientation migration is evaluated in real time based on surface diffraction signal comparison; When the orientation determination process indicates that the <111> orientation deviation is lower than a set threshold, the thermal-electrical coordinated processing is terminated and a preferentially oriented copper interconnect is output.

4. The method for manufacturing a high-precision intelligent instrument measurement chip according to claim 1, characterized in that: The copper interconnect of the upper silicon wafer is bonded to the bonding preparation surface by performing low-temperature hot-pressing bonding in an inert atmosphere to form a copper-copper bonding interface, and initial thermoelectric potential data is collected, including: Performing a spatial six-degree-of-freedom alignment process on the upper silicon wafer in an inert atmosphere controlled chamber, obtaining target alignment gap data through gap monitoring, so that the copper interconnection of the upper silicon wafer and the bonding preparation surface remain in a plane-parallel state; performing a pre-press contact process on the upper silicon wafer according to the target alignment gap data, generating a pre-bonded copper interconnect array under a defined pre-press pressure, so that each copper interconnect establishes continuous metal contact with the bonding preparation surface; Performing a stepwise temperature-pressure synchronous loading process on the pre-bonded copper interconnect array, increasing the temperature and pressure in stages within a temperature range not exceeding 300 degrees Celsius, completing the formation of a copper-copper bonding interface and recording real-time temperature-pressure process data; At the moment when the copper-copper bonding interface is formed, a reference circuit interception process is triggered, and the output voltage of the interconnect array is synchronously collected to obtain the original data of the initial thermoelectric potential of the interconnect; According to the real-time temperature-pressure process data, debiasing and filtering processing is performed on the original data of the initial thermoelectric potential of the interconnection, so as to eliminate background stress noise and normalize the data into the initial thermoelectric potential data.

5. The method for manufacturing a high-precision intelligent instrument measurement chip according to claim 1, characterized in that: The method generates a vertical heat flow by driving the upper functional area to operate according to a preset power consumption sequence, collects thermoelectric potential response data at the copper-copper bonding interface, and generates a thermoelectric potential response curve, including: Performing spatial mapping processing on the preset power consumption sequence, allocating the power consumption pulses to the logic blocks corresponding to the interconnect array positions in the upper functional area, and generating a power consumption trigger time stamp set; Driving the upper functional area to perform alternating power consumption pulse processing according to the power consumption trigger time scale set, establishing a periodically varying vertical heat flow in the copper-copper bonding structure, and recording power consumption output time history data; During the vertical heat flow establishment process, multi-channel acquisition and processing of interface microvoltage are performed synchronously to obtain the original sequence data of interconnected thermoelectric potential; Performing time series registration processing on the interconnection thermoelectric potential original sequence data according to the power consumption output time series data, extracting the interconnection Seebeck response window, and forming an interconnection thermoelectric potential time series matrix; The interconnected thermoelectric potential time series matrix is ​​subjected to periodic accumulation vector superposition processing to eliminate random noise and retain the main component of heat flow coupling to obtain a thermoelectric potential response curve.

6. The method for manufacturing a high-precision intelligent instrument measurement chip according to claim 1, characterized in that: The performing a differential operation based on the initial thermoelectric potential data and the thermoelectric potential response curve to obtain an interconnect Seebeck deviation parameter set includes: Perform channel mapping index processing on the interconnect initial thermoelectric potential data and the thermoelectric potential response curve, establish a one-to-one correspondence between the initial thermoelectric potential value of the same interconnect and the full cycle response curve, and construct an interconnect thermoelectric potential pairing matrix; Performing baseline offset differential processing on each interconnect according to the interconnect thermoelectric potential pairing matrix, subtracting the initial thermoelectric potential value from the corresponding response curve point by point, and obtaining an interconnect thermoelectric differential sequence; Performing multi-cycle window function integration processing on the interconnected thermoelectric differential sequence, integrating and averaging the positive and negative segments of each cycle respectively, and extracting the interconnected Seebeck response amplitude vector and polarity vector; performing symmetric reference normalization processing based on the interconnection Seebeck response amplitude vector and the polarity vector, eliminating common mode drift with the interconnection array geometric symmetry axis as a reference, and obtaining a normalized Seebeck offset vector; Threshold segmentation and arrangement processing are performed on the normalized Seebeck offset vector, the amplitude and direction levels are calibrated, and an interconnected Seebeck deviation parameter set is output.

7. The method for manufacturing a high-precision intelligent instrument measurement chip according to claim 1, characterized in that: The method of performing programmable metal segment selective fusing processing on the rewiring layer according to the interconnection topology adjustment scheme, cutting off the fusing target bridge line, and generating an intermediate interconnection topology includes: forming an isolation protection pattern on the redistribution layer according to the interconnection topology adjustment scheme, depositing a barrier film on the unselected metal bridge lines, and leaving the target metal bridge lines for melting exposed; Applying a local energy pulse to the exposed target metal bridge wire, using instantaneous Joule heat to cause electromigration disconnection of the metal bridge wire, thereby generating an open circuit gap; After the energy pulse ends, the residue self-shrinkage process is performed, using the metal droplet retraction effect to gather the melted residue to the end of the bridge wire to avoid the retention of metal fragments; Connectivity confirmation processing is performed on the open gap, and the intermediate interconnection topology is updated after determining that the disconnection is successful through resistance measurement.

8. A manufacturing device for a high-precision intelligent instrument measurement chip, characterized in that: The manufacturing device of the high-precision intelligent instrument measurement chip adopts the manufacturing method of the high-precision intelligent instrument measurement chip according to any one of claims 1 to 7, and the manufacturing device of the high-precision intelligent instrument measurement chip comprises: A crystal orientation reconstruction module is used to perform vacuum activation and preferential crystal orientation reconstruction on the copper interconnects exposed on the underlying silicon wafer, removing the oxide film and orienting the copper grains along the <111> crystal plane to obtain a processed bonding preparation surface; A low-temperature bonding module is used to perform low-temperature hot-press bonding of the copper interconnect of the upper silicon wafer to the bonding preparation surface in an inert atmosphere to form a copper-copper bonding interface and collect initial thermoelectric potential data; a heat flow excitation measurement module, configured to generate a vertical heat flow by driving the upper functional area to operate according to a preset power consumption sequence, collect thermoelectric potential response data at the copper-copper bonding interface, and generate a thermoelectric potential response curve; a differential calculation module, configured to perform a differential operation based on the initial thermoelectric potential data and the thermoelectric potential response curve to obtain a set of interconnection Seebeck deviation parameters; An interconnection compensation module is used to selectively fuse or connect in parallel the interconnection network according to the interconnection Seebeck deviation parameter set to form a thermoelectrically balanced interconnection network and record a zero-point drift calibration value, specifically comprising: performing threshold classification processing on the interconnection Seebeck deviation parameter set to divide the interconnection into a positive deviation group, a negative deviation group and a negligible group, and generating an interconnection compensation mapping table; performing polarity pairing matching processing on the positive deviation group and the negative deviation group according to the interconnection compensation mapping table to determine the corresponding combination of the fuse target bridge line and the parallel connection bridge line to obtain an interconnection topology adjustment scheme; performing programmable metal segment selective fusing processing on the rewiring layer according to the interconnection topology adjustment scheme to cut off the fuse target bridge line and generate an intermediate interconnection topology; performing additive metal closure processing on the intermediate interconnection topology to close the parallel connection bridge line and obtain a thermoelectrically balanced interconnection network; performing zero-point calibration sampling processing on the thermoelectrically balanced interconnection network to measure the residual thermoelectric potential and write it into a storage array, and record the zero-point drift calibration value.

9. A manufacturing device for high-precision intelligent instrument measurement chips, characterized in that: The manufacturing equipment of the high-precision intelligent instrument measurement chip includes: a memory and at least one processor, wherein the memory stores instructions; The at least one processor calls the instructions in the memory to enable the manufacturing equipment of the high-precision smart meter measurement chip to execute the steps of the method for manufacturing the high-precision smart meter measurement chip according to any one of claims 1 to 7.

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