Charge pump circuit with over-temperature and latch protection functions

Abstract

The invention discloses a charge pump circuit with over-temperature and latch protection functions, and belongs to the technical field of integrated circuits. According to the circuit, logic judgment is carried out through the logic circuit module according to the output of the over-temperature protection circuit, the latch protection circuit and the clock generation module, so that over-temperature protection and latch protection of a core circuit are realized; the phenomena that a residual heat source is not completely eliminated and parasitic double transistors are kept on can be avoided, and the working stability of the circuit is improved.

Description

Technical Field

[0001] The invention relates to a charge pump circuit with over-temperature and latch protection functions, belonging to the technical field of integrated circuits. Background Art

[0002] With the advancement of process technology in recent years, more and more portable devices have become part of people's lives. This advancement in process technology has also led to increasingly stringent requirements for System-on-Chip (SoCs). These requirements include the need for the smallest possible chip size, lower power consumption, lower cost, and minimal maintenance. Therefore, an efficient and stable power management unit (PMU) is crucial for SoCs. As a key component of PMUs, the charge pump requires optimized design to meet these growing demands.

[0003] A charge pump is an electronic device widely used in electronics and electrical engineering. Its basic principle is to store and transfer charge by periodically switching the connection of capacitors, thereby increasing, decreasing, or reversing the voltage. The core idea is to charge, discharge, and reconfigure capacitors, controlling the energy transfer path through switches. It is not only used for power management and signal processing, but also plays a key role in various fields such as communications, medical equipment, and scientific research.

[0004] A traditional charge pump, also known as a Dickson charge pump, is a voltage boost circuit based on series capacitors. During operation, the switch in each stage switches periodically, transferring charge from one capacitor to the next. Through multiple stages of charge transfer, the output voltage gradually increases. Although the Dickson charge pump has certain advantages in certain application scenarios, it also has some disadvantages and limitations. For example, the efficiency of the voltage boost is reduced due to the loss of capacitors. Due to the influence of the transistor body effect, the Dickson charge pump is prone to significant threshold loss in the case of multi-stage voltage boost, thereby reducing the boost efficiency.

[0005] A cross-coupled charge pump is an improved type of charge pump. During operation, the charge of each capacitor in each stage is transferred between the cross-capacitors, gradually increasing the output voltage. Cross-coupled charge pumps generally have higher voltage boost efficiency and can more effectively utilize input power. However, since both Dickson and cross-coupled charge pumps provide high-voltage analog power to the entire analog circuit, inrush current increases dramatically when the chip switches modes or experiences abnormal operating conditions, raising the chip temperature. Excessive power and high chip temperatures can degrade the performance of electronic equipment, shorten its lifespan, and even damage the chip.

[0006] Common charge pump circuits may overheat or latch up when the chip switches modes or operates abnormally. The charge pump circuit of a conventional integrated protection circuit generally works by turning off the main switch and power tube of the back-end circuit without turning off the charge pump. A circuit that can turn off the charge pump during mode switching or abnormal conditions requires redesigning and optimizing the power management architecture of the entire chip. Turning off the charge pump will cause the voltage in the chip to drop rapidly, causing voltage fluctuations; and prolonging the time required for the chip to return to normal working state. In addition, if the charge pump is turned off, the conduction of the parasitic bipolar transistor cannot be effectively controlled, thereby aggravating the parasitic effect. In some cases, turning off the charge pump requires additional control circuits and power devices, which will also increase the power loss of the chip. Not turning off the charge pump may result in residual heat sources not being completely eliminated and parasitic bipolar transistors remaining on, which may cause the performance of the electronic equipment to decline, shorten its life, and even burn out the chip. Summary of the Invention

[0007] In order to be able to shut down the charge pump to stop the power supply to the back-end circuit when the chip temperature exceeds a set safety threshold, thereby reducing the chip temperature and achieving the effect of over-temperature protection; and to shut down the charge pump to stop the power supply to the back-end circuit when a latch-up phenomenon occurs inside the chip, thereby eliminating the latch-up current and achieving the effect of latch-up protection; the present invention provides a charge pump circuit with over-temperature and latch-up protection functions, the circuit comprising a main circuit and a protection object; wherein the main circuit comprises: a charge pump boost module, an over-temperature protection circuit, a latch-up protection circuit, a bandgap reference voltage source, a voltage stabilizing comparator, a feedback resistor network, a clock generation module and a logic circuit module; the protection object comprises a core circuit;

[0008] The outputs of the over-temperature protection circuit, the latch protection circuit, the clock generation module and the voltage regulator comparator are simultaneously connected to the logic circuit module; the output of the logic circuit module is connected to the charge pump boost module; the output of the charge pump boost module is simultaneously connected to the core circuit and the feedback network resistor; the outputs of the feedback resistor network and the bandgap reference voltage source are respectively connected to the positive input terminal and the negative input terminal of the voltage regulator comparator.

[0009] The over-temperature protection circuit is used to detect the chip temperature. When the chip temperature exceeds the set safety threshold, the logic level is output to the logic circuit module; Figure 3 As shown, the circuit includes a temperature-independent current source I generated by a bandgap reference voltage source. Bias , bipolar transistor PNP1, first NMOS transistor MN1, first comparator, first resistor RW1, second resistor RW2, first PMOS transistor MP1, second PMOS transistor MP2 and third PMOS transistor MP3; according to V in bipolar transistor PNP1 BEThe negative temperature coefficient characteristic, as the temperature increases V BE will gradually become smaller, wherein the first resistor RW1 and the second resistor RW2 can flexibly take values in [10KΩ, 20KΩ] and [50KΩ, 60KΩ] respectively according to actual conditions, so that the first comparator outputs the desired logic level within the corresponding temperature range;

[0010] The source of the first PMOS transistor MP1 is connected to the source of the second PMOS transistor MP2 and the source of the third PMOS transistor MP3. The gate of the first PMOS transistor MP1 is connected to the gate of the second PMOS transistor MP2 and the gate of the third PMOS transistor MP3. The gate of the first PMOS transistor MP1 is connected to the drain and the current source I Bias The input terminal is connected to the current source I Bias The output end of the first transistor is simultaneously connected to the base and emitter of the bipolar transistor PNP1; the drain of the second PMOS transistor MP2 is simultaneously connected to the collector of the bipolar transistor PNP1 and the positive input end of the first comparator, and the emitter and base of the bipolar transistor PNP1 are connected; the drain of the third PMOS transistor MP3 is connected to one end of the first resistor RW1 and is also connected to the negative input end of the first comparator; the source and drain of the first NMOS transistor MN1 are respectively connected to the two ends of the first resistor RW1, and the gate of the first NMOS transistor MN1 is connected to the output end of the first comparator; one end of the second resistor RW2 is connected to the source of the first NMOS transistor MN1 and the other end of the first resistor RW1, and the other end of the second resistor RW2 is simultaneously connected to the base and emitter of the bipolar transistor PNP1.

[0011] When the chip temperature is lower than TH, the positive input terminal of the first comparator is greater than the negative input terminal, and the output VSW1 is high. At this time, the first NMOS tube MN1 is turned on and the resistor RW1 is short-circuited. Therefore, the output flip voltage of the first comparator is RW2×I Bias When the chip temperature drops below TL, the positive input of the first comparator is greater than (RW1+RW2)×I Bias , the output VSW1 is high, at this time the first NMOS tube MN1 is turned on, RW1 is shorted again, so the output flip voltage of the first comparator is RW2×I Bias The above shows the hysteresis characteristic of the output voltage of the over-temperature protection circuit, which avoids frequent adjustment of the charge pump working state when the chip is operating near the set temperature threshold.

[0012] The latch protection circuit is used to protect the internal current of the core circuit. When the core circuit current exceeds the set safety threshold, the logic level is output to the logic circuit module and the core circuit path is cut off. Figure 4As shown, the latch protection circuit includes: a second NMOS transistor MN2, a third NMOS transistor MN3, a first PMOS transistor MP1, a first NOT gate, a second NOT gate, a third resistor RW3 and a core circuit;

[0013] The input end of the first NOT gate is connected to the drain of the second NMOS transistor MN2 and one end of the third resistor RW3 respectively; the input end of the second NOT gate is connected to the output end of the first NOT gate and the gate end of the fourth PMOS transistor MP4; the gate end of the third NMOS transistor MN3 is connected to the gate end of the second NMOS transistor MN2; and the gate end and drain end of the third NMOS transistor MN3 are connected;

[0014] According to the current replication characteristics of the second NMOS transistor MN2 and the third NMOS transistor MN3, as the core circuit current increases, the Va potential decreases. The third resistor RW3 can be set to a value between [10KΩ, 20KΩ] according to actual conditions, so that the second NOT gate input terminal outputs the desired logic level within the corresponding current range;

[0015] When the core circuit current is lower than Ith, the latch-up protection circuit outputs a logic level "0" on the first NOT gate. At this time, the first PMOS transistor MP1 is turned on, and the core circuit operates normally. When the core circuit current rises to greater than Ith, the input end of the first NOT gate is less than VDD-RW3×Ith, and the first NOT gate outputs a logic level "1". At this time, the first PMOS transistor MP1 is turned off, the core circuit path is cut off, and the latch-up current is eliminated. After the latch-up phenomenon ends, the core circuit returns to normal operation mode.

[0016] The charge pump boost module is used to provide Vout potential for the feedback resistor network and provide power higher than the power supply voltage for the core circuit;

[0017] The bandgap reference voltage source is used to provide bias current for the over-temperature protection circuit and bias voltage and bias current for the voltage stabilization comparator;

[0018] The clock generation module is used to generate the clock required by the charge pump boost module;

[0019] The feedback resistor network includes a first feedback resistor R1 and a second feedback resistor R2, which modulates the clock signal frequency according to the voltage of the bandgap reference voltage source, thereby controlling the output voltage of the charge pump module;

[0020] The voltage stabilization comparator is used to stabilize the potential generated by the charge pump boost module;

[0021] The logic circuit module includes a NAND gate and a three-input AND gate, which implements over-temperature and latch-up protection for the core circuit through the output of the input over-temperature protection circuit, the output of the latch protection circuit, and the clock generation module;

[0022] The over-temperature protection circuit detects the chip temperature. When the chip temperature is within the set safety threshold, it gives a logic level "1" and the three-input AND gate outputs a normal clock signal. When the chip temperature exceeds the set safety threshold, it gives a logic level "0" and the three-input AND gate outputs a logic level "0" signal, suspending the power supply to the charge pump and suspending the operation of the core circuit, thereby reducing the chip temperature and realizing the over-temperature protection function.

[0023] The latch protection circuit is used to detect the current of the core circuit. When the core circuit current is within the set safety threshold, a logic level "1" is given, and the three-input AND gate outputs a normal clock signal. When the core circuit current exceeds the set safety threshold, a logic level "0" is given, and the three-input AND gate outputs a logic level "0" signal, suspending the power supply of the charge pump and cutting off the current path of the core circuit, thereby eliminating the latch phenomenon and realizing the latch protection function.

[0024] The beneficial effects of the present invention are:

[0025] First, the charge pump circuit with overtemperature and latch-up protection provided by the present invention provides overtemperature and latch-up protection for the power supply circuit provided by the circuit, compared to conventional charge pump circuits. It automatically activates protection in the event of overtemperature or latch-up; after an overtemperature or latch-up event occurs, it can resume normal operation. Compared to conventional charge pump circuits, this circuit has higher reliability.

[0026] Second, the present invention provides a charge pump circuit with overtemperature and latch-up protection, integrated with a protection circuit capable of outputting logic levels. The detection circuit detects chip temperature and latch-up current. When the temperature and current exceed set thresholds, the detection circuit outputs the corresponding logic level to the logic circuit module, which processes the signal to shut off the power supply to the back-end circuit. Compared to traditional protection circuits that shut off the main switch or power transistor in the back-end circuit, this method can avoid residual heat sources that are not completely eliminated and parasitic bipolar transistors that remain on.

[0027] Therefore, the present invention can effectively protect the high-voltage power supply module in the chip and greatly improve the stability and robustness of the chip during operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1A block diagram of a charge pump circuit structure with over-temperature and latch-up protection functions provided in the first embodiment of the present invention;

[0030] Figure 2 A circuit diagram of a charge pump circuit example with over-temperature and latch-up protection functions provided in the second embodiment of the present invention;

[0031] Figure 3 A schematic diagram of an over-temperature protection circuit in a charge pump circuit with over-temperature and latch protection functions provided in a first embodiment of the present invention;

[0032] Figure 4 A schematic diagram of a latch protection circuit in a charge pump circuit with over-temperature and latch protection functions provided in a first embodiment of the present invention;

[0033] Figure 5 Schematic diagram of output waveforms of the over-temperature protection circuit having hysteresis characteristics in different temperature ranges in a charge pump circuit with over-temperature and latch-up protection functions provided in the second embodiment of the present invention;

[0034] Figure 6 Schematic diagram of output waveforms of a latch protection circuit in different current ranges in a charge pump circuit with over-temperature and latch protection functions provided by the second embodiment of the present invention. DETAILED DESCRIPTION

[0035] To make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0036] Example 1

[0037] This embodiment provides a charge pump circuit with over-temperature and latch protection functions. The structure of the circuit is as follows: Figure 1 As shown, it includes a main circuit and a protection object; wherein the main circuit includes: a charge pump boost module, an over-temperature protection circuit, a latch protection circuit, a bandgap reference voltage source, a voltage regulator comparator, a feedback resistor network, a clock generation module and a logic circuit module; the protection object includes a core circuit;

[0038] The outputs of the over-temperature protection circuit, the latch protection circuit, the clock generation module and the voltage regulator comparator are simultaneously connected to the logic circuit module; the output of the logic circuit module is connected to the charge pump boost module; the output of the charge pump boost module is simultaneously connected to the core circuit and the feedback network resistor; the outputs of the feedback resistor network and the bandgap reference voltage source are respectively connected to the positive input terminal and the negative input terminal of the voltage regulator comparator.

[0039] The over-temperature protection circuit is used to detect the chip temperature. When the chip temperature exceeds the set safety threshold, the logic level is output to the logic circuit module; Figure 3As shown, the circuit includes a temperature-independent current source I generated by a bandgap reference voltage source. Bias , bipolar transistor PNP1, first NMOS transistor MN1, first comparator, first resistor RW1, second resistor RW2, first PMOS transistor MP1, second PMOS transistor MP2, third PMOS transistor MP3; according to V in bipolar transistor PNP1 BE The negative temperature coefficient characteristic, as the temperature increases V BE It will gradually become smaller, and by setting the appropriate resistance values of the first resistor RW1 and the second resistor RW2, the first comparator can output the desired logic level within the corresponding temperature range;

[0040] The source of the first PMOS transistor MP1 is connected to the source of the second PMOS transistor MP2 and the source of the third PMOS transistor MP3, the gate of the first PMOS transistor MP1 is connected to the gate of the second PMOS transistor MP2 and the gate of the third PMOS transistor MP3, the gate and drain of the first PMOS transistor MP1 are connected, the second PMOS transistor MP2 is connected to the collector of the bipolar transistor PNP1 and the positive input terminal of the first comparator, the emitter and base of the bipolar transistor PNP1 are connected, and the third PMOS transistor MP3 is connected to the first resistor RW1 and the negative input terminal of the first comparator. The first comparator is connected to the input terminal, the source and drain of the first NMOS transistor MN1 are respectively connected to the two ends of the first resistor RW1, and the output terminal of the first comparator is connected to the gate of the first NMOS transistor MN1; the second resistor RW2 is connected to the source of the first NMOS transistor MN1 and the first resistor RW1; the positive input terminal and the negative input terminal of the first comparator are respectively connected to the emitter of the bipolar transistor PNP1 and the first resistor RW1 and the second resistor RW2, and the gate and source of the first NMOS transistor MN1 are respectively connected to the two ends of the first resistor RW1; the output of the first comparator is connected to the gate of the first NMOS transistor MN1;

[0041] The latch protection circuit is used to protect the internal current of the core circuit. When the core circuit current exceeds the set safety threshold, the logic level is output to the logic circuit module and the core circuit path is cut off. Figure 4 As shown, the latch protection circuit includes: a second NMOS transistor MN2, a third NMOS transistor MN3, a first PMOS transistor MP1, a first NOT gate, a second NOT gate, a third resistor RW3 and a core circuit;

[0042] The input end of the first NOT gate is connected to the drain of the second NMOS transistor MN2 and one end of the third resistor RW3 respectively; the input end of the second NOT gate is connected to the output end of the first NOT gate and the gate end of the fourth PMOS transistor MP4; the gate end of the third NMOS transistor MN3 is connected to the gate end of the second NMOS transistor MN2; and the gate end and drain end of the third NMOS transistor MN3 are connected;

[0043] According to the current replication characteristics of the second NMOS transistor MN2 and the third NMOS transistor MN3, as the core circuit current increases, the Va potential decreases. By setting the appropriate resistance value of the resistor RW3, the second NOT gate input terminal can output the desired logic level within the corresponding current range.

[0044] The charge pump boost module is used to provide Vout potential for the feedback resistor network and provide power higher than the power supply voltage for the core circuit;

[0045] The bandgap reference voltage source is used to provide bias current for the over-temperature protection circuit and bias voltage and bias current for the voltage stabilization comparator;

[0046] The clock generation module is used to generate the clock required by the charge pump boost module;

[0047] The feedback resistor network includes a first feedback resistor R1 and a second feedback resistor R2, which modulates the clock signal frequency according to the voltage of the bandgap reference voltage source, thereby controlling the output voltage of the charge pump module;

[0048] The voltage stabilization comparator is used to stabilize the potential generated by the charge pump boost module;

[0049] The logic circuit module includes a three-input AND gate, which implements over-temperature and latch-up protection for the core circuit by inputting the output of the over-temperature protection circuit, the output of the latch-up protection circuit, and the clock generation module;

[0050] The over-temperature protection circuit detects the chip temperature. When the chip temperature is within the set safety threshold, it gives a logic level "1" and the three-input AND gate outputs a normal clock signal. When the chip temperature exceeds the set safety threshold, it gives a logic level "0" and the three-input AND gate outputs a logic level "0" signal, suspending the power supply to the charge pump and suspending the operation of the core circuit, thereby reducing the chip temperature and realizing the over-temperature protection function.

[0051] The latch protection circuit is used to detect the current of the core circuit. When the core circuit current is within the set safety threshold, a logic level "1" is given, and the three-input AND gate outputs a normal clock signal. When the core circuit current exceeds the set safety threshold, a logic level "0" is given, and the three-input AND gate outputs a logic level "0" signal, suspending the power supply of the charge pump and cutting off the current path of the core circuit, thereby eliminating the latch phenomenon and realizing the latch protection function.

[0052] Example 2

[0053] This embodiment provides a charge pump circuit with over-temperature and latch-up protection functions, such as Figure 2As shown, it includes: a charge pump boost module, an over-temperature protection circuit, a latch protection circuit, a bandgap reference voltage source, a voltage regulator comparator, a feedback resistor network, a clock generation module, and a logic circuit module;

[0054] The logic circuit module includes a three-input AND gate, and the feedback resistor network includes a first feedback resistor R1 and a second feedback resistor R2;

[0055] The outputs of the over-temperature protection circuit, the latch protection circuit, and the clock generation module serve as the three inputs of a three-input AND gate. The output of the three-input AND gate is connected to the charge pump boost module. The other end of the charge pump boost module is sequentially connected to the first feedback resistor R1 and the second feedback resistor R2 in the feedback resistor network. The potential Vp between the first feedback resistor R1 and the second feedback resistor R2 is connected to the non-inverting input of the voltage regulator comparator. The inverting input of the voltage regulator comparator is connected to a bandgap reference voltage source. The output of the voltage regulator comparator is connected to one of the inputs of the clock generation module.

[0056] The bandgap reference voltage source provides a bias current for the over-temperature protection circuit and provides a bias voltage and a bias current for the voltage stabilization comparator;

[0057] The voltage stabilizing comparator is used to stabilize the Vout potential generated by the charge pump boost module; the bandgap reference voltage source is used to provide a bias current for the over-temperature protection circuit and provide a bias voltage and bias current for the voltage stabilizing comparator;

[0058] The voltage stabilizing comparator is used to stabilize the Vout potential generated by the charge pump boost module;

[0059] The waveforms output by the over-temperature protection circuit of the charge pump circuit provided in this embodiment under different temperature ranges are as follows: Figure 5 As shown in the figure; when the chip temperature is lower than TH, the positive input terminal of the first comparator is greater than the negative input terminal, and the output VSW1 is high. At this time, the first NMOS tube MN1 is turned on and the first resistor RW1 is short-circuited. Therefore, the output flip voltage of the first comparator is RW2×I Bias When the chip temperature drops below TL, the positive input of the first comparator is greater than (RW1+RW2)×I Bias , the output VSW1 is high, at this time the first NMOS tube MN1 is turned on, the first resistor RW1 is short-circuited again, so the output flip voltage of the first comparator is RW2×I Bias The above shows the hysteresis characteristic of the output voltage of the over-temperature protection circuit, which avoids frequent adjustment of the charge pump working state when the chip is operating near the set temperature threshold.

[0060] The waveforms output by the latch protection circuit of the charge pump circuit provided in this embodiment under different current ranges are as follows: Figure 6As shown in the figure, when the core circuit current is lower than Ith, the first NOT gate outputs a logic level "0", at which point the first PMOS transistor MP1 is turned on and the core circuit operates normally. When the core circuit current rises to greater than Ith, the input end of the first NOT gate is less than VDD-RW3×Ith, and the first NOT gate outputs a logic level "1". At this time, the first PMOS transistor MP1 is turned off, the core circuit path is cut off, and the latch-up current is eliminated. After the latch-up phenomenon ends, the core circuit returns to normal operating mode.

[0061] The over-temperature protection circuit detects the chip temperature. Figure 3 According to the working principle of the three-input AND gate, when the chip temperature is within the set safety threshold, a logic level "1" is given, and the three-input AND gate outputs a normal clock signal. When the chip temperature exceeds the set safety threshold, a logic level "0" is given, and the three-input AND gate outputs a logic level "0" signal, suspending the power supply to the charge pump and suspending the operation of the back-end core circuit, thereby reducing the chip temperature and realizing the over-temperature protection function.

[0062] The latch protection circuit detects the current of the core circuit. Figure 4 According to the working principle of the three-input AND gate, when the core circuit current is within the set safety threshold, a logic level "1" is given, and the three-input AND gate outputs a normal clock signal. When the core circuit current exceeds the set safety threshold, a logic level "0" is given, and the three-input AND gate outputs a logic level "0" signal, suspending the power supply to the charge pump and cutting off the core circuit current path, thereby eliminating the latch-up phenomenon and realizing the latch-up protection function.

[0063] The three-input AND gate judges the output logic of the over-temperature protection circuit and the latch protection circuit. When the chip temperature is within the set safety threshold and the core circuit current is within the set safety threshold, a normal clock signal will be output. Otherwise, the output logic level "0" stops the charge pump power supply and protects the back-end core circuit.

[0064] Some steps in the embodiments of the present invention may be implemented using software, and the corresponding software program may be stored in a readable storage medium, such as a CD or a hard disk.

[0065] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A charge pump circuit with over-temperature and latch-up protection functions, characterized in that: The circuit includes: a charge pump boost module, an over-temperature protection circuit, a latch protection circuit, a bandgap reference voltage source, a voltage stabilizing comparator, a feedback resistor network, a clock generation module and a logic circuit module; The outputs of the over-temperature protection circuit, latch protection circuit, clock generation module and voltage regulator comparator are simultaneously connected to the logic circuit module; the output of the logic circuit module is connected to the charge pump boost module; the output of the charge pump boost module is simultaneously connected to the core circuit and the feedback resistor network; the outputs of the feedback resistor network and the bandgap reference voltage source are respectively connected to the positive input and negative input of the voltage regulator comparator.

2. The circuit according to claim 1, wherein: The over-temperature protection circuit includes: a current source I Bias , bipolar transistor PNP1, first NMOS transistor MN1, first comparator, first resistor RW1, second resistor RW2, first PMOS transistor MP1, second PMOS transistor MP2 and third PMOS transistor MP3; The source of the first PMOS transistor MP1 is connected to the source of the second PMOS transistor MP2 and the source of the third PMOS transistor MP3. The gate of the first PMOS transistor MP1 is connected to the gate of the second PMOS transistor MP2 and the gate of the third PMOS transistor MP3. The gate of the first PMOS transistor MP1 is connected to the drain and the current source I Bias The input terminal is connected to the current source I Bias The output end of the first transistor is simultaneously connected to the base and emitter of the bipolar transistor PNP1; the drain of the second PMOS transistor MP2 is simultaneously connected to the collector of the bipolar transistor PNP1 and the positive input end of the first comparator, and the emitter and base of the bipolar transistor PNP1 are connected; the drain of the third PMOS transistor MP3 is connected to one end of the first resistor RW1 and is also connected to the negative input end of the first comparator; the source and drain of the first NMOS transistor MN1 are respectively connected to the two ends of the first resistor RW1, and the gate of the first NMOS transistor MN1 is connected to the output end of the first comparator; one end of the second resistor RW2 is connected to the source of the first NMOS transistor MN1 and the other end of the first resistor RW1, and the other end of the second resistor RW2 is simultaneously connected to the base and emitter of the bipolar transistor PNP1.

3. The circuit according to claim 2, characterized in that The latch protection circuit includes: a second NMOS transistor MN2, a third NMOS transistor MN3, a first PMOS transistor MP1, a first NOT gate, a second NOT gate, a third resistor RW3 and a core circuit; The input end of the first NOT gate is respectively connected to the drain of the second NMOS transistor MN2 and one end of the third resistor RW3; the other end of the third resistor RW3 is connected to the source of the fourth PMOS transistor MP4, and the gate of the fourth PMOS transistor MP4 is connected to both the output end of the first NOT gate and the input end of the second AND gate; the drain of the fourth PMOS transistor MP4 is connected to the core circuit, and the other end of the core circuit is simultaneously connected to the drain and gate of the third NMOS transistor MN3; the source and gate of the third NMOS transistor MN3 are respectively connected to the second NMOS transistor MN2, and the drain of the second NMOS transistor MN2 is connected to one end of the third resistor RW3 and also to the input end of the first AND gate.

4. The circuit according to claim 3, characterized in that When the chip temperature is lower than TH, the positive input terminal of the first comparator is greater than the negative input terminal, and the output VSW1 is high. At this time, the first NMOS tube MN1 is turned on, the resistor RW1 is short-circuited, and the output flip voltage of the first comparator is RW2×I Bias ; When the chip temperature drops below TL, the positive input of the first comparator is greater than (RW1+RW2)×I Bias , the output VSW1 is high, at this time the first NMOS tube MN1 is turned on, RW1 is shorted again, and the output flip voltage of the first comparator is RW2×I Bias .

5. The circuit according to claim 4, characterized in that When the core circuit current of the latch protection circuit is lower than Ith, the output of the first NOT gate is logic level "0", at which time the first PMOS transistor MP1 is turned on and the core circuit operates normally; When the voltage of the core circuit rises to greater than Ith, the input of the first NOT gate is less than VDD-RW3×Ith, and the output of the first NOT gate is logic level "1". At this time, the first PMOS transistor MP1 is turned off, the core circuit path is cut off, and the latch-up current is eliminated. After the latch-up phenomenon ends, the core circuit returns to normal operating mode.

6. The circuit according to claim 5, characterized in that The charge pump boost module is used to provide a Vout potential for the feedback resistor network and provide a power supply higher than the power supply voltage for the core circuit.

7. The circuit according to claim 6, characterized in that The bandgap reference voltage source is used to provide a bias current for the over-temperature protection circuit and to provide a bias voltage and a bias current for the voltage stabilization comparator.

8. The circuit according to claim 7, characterized in that The clock generating module is used to generate the clock required by the charge pump boost module.

9. The circuit according to claim 8, characterized in that The feedback resistor network includes a first feedback resistor R1 and a second feedback resistor R2, which modulates the clock signal frequency according to the voltage of the bandgap reference voltage source, thereby controlling the output voltage of the charge pump module.

10. The circuit according to claim 9, characterized in that The voltage stabilizing comparator is used to stabilize the potential generated by the charge pump boost module.

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