Transistor test system, test method, device and medium

Abstract

The invention discloses a test system, a test method and equipment of a transistor and a medium. The test system comprises a heating device used for adjusting the temperature of transistors, wherein each transistor is connected in series with a high-voltage power supply through a non-inductive resistor; the plurality of driving circuits are used for controlling the on-off of the transistors through a preset switching rate; the data measuring circuit is used for collecting the transistor temperature of each transistor and collecting the transistor output current of the transistor at the transistor temperature and the switching rate; the controller is used for generating a temperature adjusting instruction and a transistor control instruction according to the target transistor temperature and the target switching rate, receiving the transistor temperature and the transistor output current detected by the data measuring circuit, analyzing the transistor temperature and the transistor output current, and outputting the analyzed transistor temperature and the analyzed transistor output current. And generating a test result for testing the current sharing characteristic of the transistor. According to the scheme provided by the invention, the accuracy of transistor parallel current sharing characteristic testing can be improved.

Description

Technical Field

[0001] The present application belongs to the field of power conversion technology, and in particular relates to a transistor testing system, testing method, equipment and medium. Background Art

[0002] SiC (Silicon Carbide) MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) feature excellent switching characteristics and low conduction losses. They are typically used in high-voltage, high-power applications, employing multiple transistors in parallel for power conversion to reduce product costs. The positive temperature characteristics of SiC MOSFET on-resistance enable current sharing when multiple transistors are connected in parallel. However, different devices have different positive temperature characteristics, resulting in varying current sharing effects when multiple transistors are connected in parallel. Therefore, testing the parallel current sharing characteristics of SiC MOSFETs is necessary to ensure product reliability during circuit design while also controlling costs and avoiding waste.

[0003] In related technologies, only static testing of the parallel current-sharing characteristics of SiC MOSFETs is usually performed. However, during the test, the on-resistance, temperature, etc. of the SiC MOSFET are changing. Therefore, the static test cannot accurately reflect the test results of the parallel current-sharing characteristics of the SiC MOSFET, thereby reducing the test accuracy of the parallel current-sharing characteristics of the SiC MOSFET. Summary of the Invention

[0004] The embodiments of the present application provide a transistor testing system, testing method, equipment and medium, which can improve the accuracy of parallel current sharing characteristic testing of transistors.

[0005] In a first aspect, an embodiment of the present application provides a transistor testing system, the testing system comprising: a heating device connected to a plurality of parallel transistors for adjusting the temperature of the transistors, wherein each transistor is connected in series with a high-voltage power supply via a non-inductive resistor; a plurality of drive circuits, each drive circuit connected to a transistor for controlling the on / off state of the transistor by a target switching rate corresponding to the transistor; a data measurement circuit connected to the output end of each transistor for collecting a first transistor temperature of each transistor and collecting a transistor output current of the transistor at the first transistor temperature and the switching rate; a controller connected to the heating device, the plurality of drive circuits, and the data measurement circuit for generating a temperature adjustment instruction for controlling the heating device and a transistor control instruction for controlling the plurality of transistors based on the target transistor temperature and the target switching rate corresponding to the transistor, and receiving the first transistor temperature and the transistor output current detected by the data measurement circuit, and determining a test result of the current sharing characteristic of the transistor based on the first transistor temperature and the transistor output current, wherein the target transistor temperature is a temperature at which the output current of the transistor is within a preset current range, the target switching rate is a switching rate at which the output current of the transistor is within a preset current range, and the preset current range is a current range at which the plurality of parallel transistors are in a current sharing state.

[0006] In a second aspect, an embodiment of the present application provides a transistor testing method, which is applied to a transistor testing system such as the first aspect, and the testing method includes: a controller obtains test requirement information for performing a current sharing characteristic test on multiple transistors connected in parallel, wherein the test requirement information includes at least a target transistor temperature corresponding to each transistor and a switching rate of each transistor, the target transistor temperature is a temperature that makes the output current of the transistor within a preset current range, the target switching rate is a switching rate that makes the output current of the transistor within a preset current range, and the preset current range is a current range when multiple parallel transistors are in a current sharing state; the controller generates a temperature adjustment instruction including the target transistor temperature, and controls the heating device to adjust the transistor temperature of the multiple transistors, and obtains a first transistor temperature detected by the data measurement circuit; the controller generates a transistor control instruction including the target switching rate, and controls the drive circuit to adjust the on and off of the multiple transistors, and obtains the transistor output current detected by the data measurement circuit; the controller determines the test result of the transistor's current sharing characteristic based on the first transistor temperature and the transistor output current.

[0007] In a third aspect, an embodiment of the present application provides an electronic device comprising: a processor and a memory storing computer program instructions; when the processor executes the computer program instructions, the transistor testing method as described in the second aspect is implemented.

[0008] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium having computer program instructions stored thereon. When the computer program instructions are executed by a processor, the transistor testing method as described in the second aspect is implemented.

[0009] In a fifth aspect, an embodiment of the present application provides a computer program product. When the instructions in the computer program product are executed by a processor of an electronic device, the electronic device executes the transistor testing method as described in the second aspect.

[0010] As can be seen from the above, in the embodiment of the present application, by connecting a non-inductive resistor in series in the parallel branch where each transistor is located, the on-resistance of the transistor can be simulated by adjusting the resistance value of the non-inductive resistor when the performance test of the transistor is performed, thereby solving the problem of inaccurate test results due to the inability to change the on-resistance of the transistor in the related art. In addition, in the embodiment of the present application, a drive circuit is used to control the on and off of the transistor to achieve dynamic testing of the transistor. Moreover, a heating device is used to heat the transistor to change the temperature of the transistor, thereby simulating the change of the chip temperature of the transistor, solving the problem of inaccurate parallel current sharing characteristic test results of the transistor in the related art due to the failure to consider the influence of chip temperature change on the transistor.

[0011] It can be seen that the solution proposed in the embodiment of the present application can realize dynamic testing of the parallel current sharing characteristics of transistors, and can simulate the changes in the on-resistance of the transistor and the changes in the chip temperature during the test process, so that the state of the transistor during the test process is more consistent with the actual scenario, thereby improving the accuracy of the parallel current sharing characteristic test of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0013] Figure 1 1 is a schematic structural diagram of a transistor testing system provided by one embodiment of the present application;

[0014] Figure 2 This is a schematic structural diagram of a heating unit provided in one embodiment of the present application;

[0015] Figure 3 This is a schematic diagram of the structure of a heat source temperature control circuit provided by an embodiment of the present application;

[0016] Figure 4 This is a schematic diagram of the structure of a driving circuit provided by an embodiment of the present application;

[0017] Figure 5 is a flow chart of a transistor testing method provided by another embodiment of the present application;

[0018] Figure 6 is a flow chart of a method for adjusting transistor temperature provided by another embodiment of the present application;

[0019] Figure 7 This is a structural diagram of an electronic device provided in yet another embodiment of the present application. DETAILED DESCRIPTION

[0020] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present application by illustrating the examples of the present application.

[0021] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, the elements defined by the phrase "comprising..." do not exclude the presence of other identical elements in the process, method, article, or device comprising the elements.

[0022] For ease of understanding, before explaining the solution provided in this application, the background of the solution provided in this application is first explained.

[0023] The development of power conversion technology is limited by the material properties of power electronic devices. The emergence of third-generation semiconductor technology has broken the limitations of traditional silicon materials in high-frequency, high-voltage and high-power applications.

[0024] Currently, power conversion applications are trending toward high power-to-density and power-to-weight ratios. SiC MOSFETs are widely used due to their excellent switching characteristics and low conduction losses. This is particularly true in high-voltage, high-power applications, where the use of multiple transistors in parallel can significantly reduce product costs. However, due to differences among SiC MOSFETs, the current passing through multiple parallel SiC MOSFETs is not identical, resulting in uneven heating of the SiC MOSFETs, which in turn affects their electrical lifespan and reliability.

[0025] Typically, the positive temperature characteristics of SiC MOSFET on-resistance can be exploited to achieve current sharing across multiple parallel transistors. However, different SiC MOSFETs have different positive temperature characteristics, resulting in varying current sharing results when connected in parallel. Therefore, circuit design margins must be determined based on the parallel current sharing performance of SiC MOSFETs to ensure product reliability, control costs, and avoid waste. This means that before using SiC MOSFETs, it is usually necessary to test their parallel current sharing characteristics.

[0026] As can be seen from the above, in high-voltage, high-power applications, SiC MOSFETs use multiple transistors in parallel to increase current capacity, relying on their inherent characteristics to achieve current distribution and achieve parallel current sharing. Testing the parallel current sharing performance of SiC MOSFETs requires solving the following key issues:

[0027] (1) Limited by the current manufacturing process, the electrical parameters of different SiC MOSFETs are inconsistent. As the device life increases, the electrical parameters of SiC MOSFETs will also change. Therefore, the parallel connection of multiple transistors faces a greater challenge. It is necessary to test the extreme current sharing effect of SiC MOSFETs, that is, to test the current sharing effect of multiple parallel SiC MOSFETs under their respective electrical parameters, so as to ensure the long-term reliability of power conversion products through design.

[0028] (2) When multiple SiC MOSFETs are used in parallel, the current flowing through the SiC MOSFET is negatively correlated with its on-resistance, decreasing as the on-resistance increases. Typically, the on-resistance of a SiC MOSFET is very small, determined by its own characteristics. In practical applications, it is not possible to evaluate the parallel current sharing performance by changing the on-resistance of the SiC MOSFET.

[0029] (3) The on-resistance of SiC MOSFET is positively correlated with the temperature of the chip. When the parallel SiC MOSFETs have uneven current distribution, the SiC MOSFETs are dynamically adjusted. However, static testing can no longer meet the requirements of parallel current distribution testing. It is necessary to test the dynamic current distribution characteristics of SiC MOSFETs.

[0030] In summary, in the related art, it is impossible to dynamically adjust the characteristics of SiC MOSFETs, and it is impossible to meet the test requirements of the parallel current sharing performance of SiC MOSFETs, and there are certain defects and shortcomings.

[0031] To address the problems of the prior art, the present invention provides a transistor testing system, testing method, device, and medium. The transistor testing method provided in the present invention can be applied to a transistor testing system. Before introducing the transistor testing method provided in the present invention, the transistor testing system provided in the present invention is first introduced.

[0032] Figure 1 FIG. 1 shows a schematic diagram of a transistor test system according to an embodiment of the present application. Figure 1 As shown, the transistor test system includes a heating device 10 , a plurality of driving circuits 20 , a data measurement circuit 30 and a controller 40 .

[0033] like Figure 1 As shown, the heating device 10 is connected to a plurality of transistors connected in parallel for adjusting the temperature of the transistors.

[0034] In an embodiment of the present application, the transistor may be a MOSFET, which may be a P-channel field effect transistor or an N-channel field effect transistor, specifically a SiC MOSFET. SiC MOSFET is a switching device that is sensitive to parasitic parameters of circuit design. In this regard, in an embodiment of the present application, each transistor is connected in series with a high-voltage power supply via a non-inductive resistor, wherein the non-inductive resistor is a purely resistive device that can minimize the impact on the switching characteristics of the SiC MOSFET. The change in the on-resistance of the SiC MOSFET is simulated by changing the resistance value of the series non-inductive resistor.

[0035] In one example, if Figure 1 As shown, each transistor (such as Figure 1 TP1, TP2, ..., TPN) through non-inductive resistors (such as Figure 1The R1, R2, ..., RN in the figure are connected in series with a high-voltage power supply, which is then connected in series with the load via a non-inductive resistor and a transistor. By connecting non-inductive resistors in series, different resistance values can be inserted in the parallel SiC MOSFET branches to simulate changes in the on-resistance of the SiC MOSFET. This effectively solves the problem of dynamic testing being unable to change the on-resistance of the SiC MOSFET.

[0036] In addition, in the embodiment of the present application, the heating device 10 is used to provide a heat source to the transistor to simulate the temperature change of the chip where the transistor is located, so as to test the current sharing performance of the transistor at different chip temperatures. Therefore, it can be seen that in the embodiment of the present application, the use of external heating method to conduct heat to the SiC MOSFET chip and simulate the change of the SiC MOSFET chip temperature can effectively solve the problem of being unable to dynamically adjust the SiC MOSFET chip temperature.

[0037] In one embodiment, the heating device 10 may include a plurality of heating units, each of which is connected to a transistor for regulating the temperature of the connected transistor. Figure 2 Shows a schematic diagram of the structure of the heating unit, consisting of Figure 2 It can be seen that the heating unit includes a transistor heating source 101 , a heat conducting unit 102 and a temperature sensor 103 .

[0038] The transistor heating source 101 is connected to the controller 40 and is used to heat the transistor placed on the transistor heating source. In the embodiment of the present application, multiple transistor heating sources 101 can be deployed in the heating device 10, and each heating unit is provided with a transistor heating source 101 to heat one transistor. In the embodiment of the present application, the transistor heating source 101 can be set as a planar heat source so that the transistors placed on the transistor heating source 101 can be heated evenly, avoiding uneven heating of the transistors and reducing the accuracy of the parallel current sharing characteristic test of the transistors.

[0039] like Figure 2 As shown, the heat transfer unit 102 is disposed between the transistor heating source 101 and the transistor placed on the transistor heating source, and is in contact with the transistor heating source 101 and the transistor. The heat transfer unit 102 is used to transfer the heat generated by the transistor heating source 101 to the transistor, thereby preventing the transistor heating source 101 from directly contacting the transistor and causing damage to the transistor. As an example, the heat transfer unit 102 may be, but is not limited to, a thermal pad, a thermal sheet, or the like.

[0040] In addition, if Figure 2 As shown, the temperature sensor 103 is disposed on a side of the heat conducting unit 102 close to the transistor to monitor the temperature of the transistor.

[0041] It should be noted that in the embodiment of the present application, the transistor heating source 101 heats the transistor through temperature control, thereby simulating the change in the temperature of the transistor; the high conductivity of the heat conduction unit 102 is utilized to improve the thermal conductivity between the transistor heating source 101 and the transistor; and the temperature sensor 103 is placed in close contact with the transistor to achieve real-time monitoring of the transistor temperature.

[0042] In one embodiment, Figure 1 As shown, the transistor test system also includes: a heat source temperature control circuit 50. The heat source temperature control circuit 50 is connected between the controller 40 and the heating device 10, and is used to control the heating device 10 to heat the transistor according to the temperature adjustment instruction. In the embodiment of the present application, the temperature adjustment instruction can be set by the controller 40 according to the test requirements. The temperature adjustment instruction can include parameters such as the temperature to be output by each transistor heating source 101 and the heating time. Therefore, after receiving the temperature modulation instruction, the heat source temperature control circuit 50 can adjust the output temperature of the corresponding transistor heating source 101.

[0043] In one embodiment, Figure 3 The heat source temperature control circuit 50 is shown in FIG. Figure 3 It can be seen that the heat source temperature control circuit 50 includes: a temperature feedback circuit 501 , a logic control circuit 502 , a relay 503 , and a control power supply 504 .

[0044] Specifically, the temperature feedback circuit 501 is connected to the output terminals of the temperature sensors 103 of the multiple heating units and is configured to transmit the second transistor temperature detected by each temperature sensor 103 to the controller 40. The temperature feedback circuit 501 conditions the collected signals from all the temperature sensors 103 built into the heating device 10 and transmits them to the logic control circuit 502 for logic processing. The logic control circuit 502 then transmits the processed signals to the controller 40, allowing the controller 40 to adjust the test strategy.

[0045] The logic control circuit 502 is connected to the output end of the temperature feedback circuit 501 and is used to control the heating operation of the heating device 10 on the transistor according to the target transistor temperature and the second transistor temperature fed back by the temperature feedback circuit 501 .

[0046] In one embodiment, the logic control circuit 502 includes: a first input end, a second input end, and multiple signal output ends, wherein the logic control circuit 502 is connected to the controller 40 through the first input end to receive the temperature adjustment instruction issued by the controller 40; the logic control circuit 502 is connected to the temperature feedback circuit 501 through the second input end to obtain the second transistor temperature detected by the temperature sensor 103; the logic control circuit 502 is respectively connected to multiple relays 503 through multiple signal output ends, and controls the heating device to heat the transistor by controlling the on and off of the multiple relays 503.

[0047] Specifically, the logic control circuit 502 receives the temperature adjustment instruction issued by the controller 40, gives the target transistor temperature of the transistor heating source 101, compares the target transistor temperature of the given heat source and the feedback temperature of the heating device 101, and controls the switch of the relay 503, thereby switching the power supply circuit of the heating device 10 to achieve temperature regulation of the transistor heating source 101.

[0048] like Figure 3 As shown, multiple relays 503 are connected between the logic control circuit 502 and the heating device 10, and are used to control the heating device 10 to perform heating operations on the transistors, wherein each relay 503 is connected to a signal output port of the logic control circuit 502; each relay 503 is connected to a transistor, and when the relay 503 is in the on state, power is supplied to the corresponding transistor heating source 101, so that the transistor heating source 101 generates heat to perform heating operations on the transistors.

[0049] like Figure 3 As shown, the heat source temperature control circuit 50 also includes a control power supply 504. The control power supply 504 is connected to the power input terminals of the multiple relays 503 and supplies power to the transistor heating source when the relays 503 are turned on. In this embodiment of the present application, the control power supply 504 can provide multiple +12V power supplies to the heating device 10 to meet the device's heating requirements for the SiC MOSFET chip.

[0050] This concludes the introduction of the heating device 10 and the heat source temperature control circuit 50 .

[0051] In one embodiment, Figure 1 As shown, each driving circuit 20 is connected to a transistor and is used to control the on and off of the transistor through a target switching rate corresponding to the transistor, wherein the target switching rate is a switching rate that makes the output current of the transistor within a preset current range, and the preset current range is a current range when multiple parallel transistors are in a current sharing state.

[0052] In one embodiment, Figure 4The schematic diagram of the driving circuit 20 is shown. Figure 4 It can be seen that the driving circuit 20 includes a gate driving circuit 201 , a gate clamping circuit 202 , a driving chip 203 and a driving power circuit 204 .

[0053] Specifically, the gate drive circuit 201 is connected to the gate of the transistor for controlling the on and off of the transistor; the gate clamping circuit 202 is connected to the output end of the gate drive circuit 201 for transmitting the output signal of the gate drive circuit 201; the driving chip 203 is connected to the input end of the gate drive circuit 201 and to the output end of the gate clamping circuit 202 for performing Miller clamping processing on the output signal of the gate drive circuit 201 according to the output signal of the gate drive circuit 201; the driving power supply circuit 204 is connected to the output end of the controller 40 and to the input end of the driving chip 203 for outputting the on and off voltage for controlling the on and off of the transistor according to the transistor control instruction.

[0054] Depend on Figure 4 As can be seen, the driver power circuit 204 includes: a first output terminal and a second output terminal; the driver chip includes a third input terminal and a fourth input terminal. The driver power circuit 204 is connected to the third input terminal of the driver chip 203 via the first output terminal, for inputting a transistor turn-on voltage to the driver chip 203 to turn on the transistor; the driver power circuit 204 is connected to the fourth input terminal of the driver chip 203 via the second output terminal, for inputting a transistor turn-off voltage to the driver chip 203 to turn off the transistor. As an example, the first output terminal of the driver power circuit 204 can output a +18V voltage to power the driver chip 203 to turn on the transistor; the second output terminal of the driver power circuit 204 can output a -4V voltage to power the driver chip 203 to turn off the transistor.

[0055] In an embodiment of the present application, the drive circuit 20 amplifies the control signal of the controller 40 and drives the SiC MOSFET to turn on and off. Each SiC MOSFET test unit branch is configured with an independent drive circuit to ensure that there is no crosstalk between the gate-source loops of the parallel tubes. The drive circuit 20 can provide a turn-on voltage of +18V and a turn-off voltage of -4V, which can ensure the stable turn-on and reliable turn-off of the SiC MOSFET. By adjusting the gate drive circuit parameters, the switching speed can be controlled. At the same time, the drive circuit 20 has a Miller clamping function, which cooperates with the gate clamping circuit 202 to suppress the crosstalk and oscillation problems of the gate-source voltage during the switching of the SiC MOSFET. The drive circuit 20 is also equipped with a drive current desaturation protection function. When the SiC MOSFET current is higher than a certain value, the drive circuit 20 can implement hardware protection, and the protection will automatically recover within 7ms to ensure that the transistor is not damaged.

[0056] This completes the introduction of the driving circuit 20 .

[0057] In one embodiment, Figure 1 As shown, the transistor test system further includes: a first conditioning circuit 60, which is used to convert the transistor control instruction into a pulse width modulation PWM signal. Specifically, as Figure 1 As shown, the input end of the first conditioning circuit 60 is connected to the controller 40 for receiving the transistor control instruction output by the controller 40; the multiple output ends of the first conditioning circuit 60 are respectively connected to the driving power circuit 204 in the multiple driving circuits 20 for transmitting the PWM signal to the driving power circuit 204.

[0058] This completes the introduction of the first conditioning circuit 60 .

[0059] In one embodiment, Figure 1 As shown, the transistor test system further includes a data measurement circuit 30. The data measurement circuit 30 is connected to the output terminal of each transistor and is used to collect the first transistor temperature of each transistor and the transistor output current of the transistor at the first transistor temperature and the target switching rate.

[0060] Specifically, such as Figure 1 As shown, the data measurement circuit 30 includes a current acquisition circuit 301, a temperature acquisition circuit 302, and a second conditioning circuit 303. The current acquisition circuit 301 is connected to the output terminal of the transistor to acquire the transistor output current of the transistor; the temperature acquisition circuit 302 is connected to the temperature sensor 103 to acquire the first transistor temperature of the transistor; the second conditioning circuit 303 is connected to the current acquisition circuit 301, the temperature acquisition circuit 302, and the controller 40 to convert the format of the transistor output current and the first transistor temperature. The second conditioning circuit 303 includes a fifth input terminal, a sixth input terminal, and a third output terminal. The second conditioning circuit 303 is connected to the output terminal of the current acquisition circuit 301 via the fifth input terminal; the second conditioning circuit 303 is connected to the output terminal of the temperature acquisition circuit 302 via the sixth input terminal; and the second conditioning circuit 303 is connected to the input terminal of the controller 40 via the third output terminal.

[0061] The temperature data and current data of the transistors can be fed back to the controller 40 through the data measurement circuit 30, so that the controller 40 can test the parallel current sharing characteristics of the transistors according to the temperature data and current data of the transistors to improve the accuracy of the test results.

[0062] In one embodiment, Figure 1As shown, the controller 40 is connected to the heating device 10, multiple drive circuits 20 and the data measurement circuit 30, and is used to generate a temperature adjustment instruction for controlling the heating device 10 and a transistor control instruction for controlling the transistor according to the target transistor temperature and target switching rate corresponding to the transistor, and receive the first transistor temperature and transistor output current detected by the data measurement circuit 30, and determine the test result of the transistor's current sharing characteristic according to the first transistor temperature and transistor output current. Wherein, the target transistor temperature is the temperature at which the output current of the transistor is within a preset current range, and the preset current range is the current range in which multiple parallel transistors are in a current sharing state. The target transistor temperature can be calculated by the controller. For example, the controller can determine whether the multiple transistors are in a current sharing state based on the current value and temperature value of the multiple transistors detected by the second conditioning circuit. If the battery value of a certain transistor is detected to be outside the preset current range, it can be determined that the multiple transistors are in a non-current sharing state. At this time, the controller can adjust the temperature of the transistor whose current value is outside the preset current range to adjust the on-resistance of the transistor, thereby adjusting the output current of the transistor to achieve a current sharing effect of multiple transistors in parallel.

[0063] In an embodiment of the present application, the controller 40 may include a master DSP (Digital Signal Processing) and a logic operation circuit. The controller 40 dynamically adjusts the heating device 10 based on the set target transistor temperature and temperature data fed back by the data measurement circuit 30, simulating changes in the SiC MOSFET chip temperature. Based on test instructions, the controller 40 issues PWM signals to control the on-off process of the SiC MOSFET under test. The first conditioning circuit 60 and the drive circuit 20 control the on-off of the SiC MOSFET under test by receiving control signals from the controller 40. The second conditioning circuit 303, the temperature acquisition circuit 302, and the current acquisition circuit 301 use temperature sensors and current sensors to measure the temperature and current of the sample under test. After signal conditioning, the signals are uploaded to the controller 40 for status monitoring. By configuring the high-voltage power supply and load, the on-off voltage and on-current of the SiC MOSFET under test can be adjusted, thereby adjusting the test conditions of the SiC MOSFET under test. A non-inductive resistor is connected in series with the SiC MOSFET test unit branch to simulate changes in the on-resistance of the SiC MOSFET.

[0064] In summary, the parallel current sharing capability of transistors can be evaluated by controlling and monitoring the controller 40 .

[0065] This concludes the introduction to the transistor testing system provided in the embodiments of the present application.

[0066] As can be seen from the above content, by programming a control algorithm through the controller 40, dynamic regulation and control of the on-resistance and chip temperature of the SiC MOSFET can be achieved to meet the requirements of the parallel current sharing performance test of the SiC MOSFET.

[0067] The transistor test system described above is based on the concept of equivalent simulation. By connecting a non-inductive resistor in series and using external heating, the internal resistance and temperature of the SiC MOSFET are changed. The ultimate current sharing effect of multiple transistors in parallel is tested, thereby evaluating the parallel current sharing performance of the SiC MOSFET, verifying the circuit selection design, and ensuring the long-term reliability of the product.

[0068] Based on the above, the transistor testing method provided by the embodiment of the present application is introduced. The method can be executed by the above-mentioned transistor testing system.

[0069] Figure 5 FIG1 shows a flow chart of a transistor testing method provided by an embodiment of the present application. Figure 5 As shown, the method includes the following steps S501 to S504:

[0070] In step S501 , the controller obtains test requirement information for performing a current sharing characteristic test on a plurality of transistors connected in parallel.

[0071] In step S501, the test requirement information includes at least a target transistor temperature corresponding to each transistor and a target switching rate for each transistor. The target transistor temperatures and corresponding switching rates may be different for multiple transistors. The target transistor temperature is the temperature at which the output current of the transistor falls within a preset current range, and the target switching rate is the switching rate at which the output current of the transistor falls within a preset current range. The preset current range is the current range for multiple parallel-connected transistors in a current-sharing state.

[0072] In one example, a user can set the target transistor temperature and target switching rate corresponding to each transistor, and input them into the transistor test system through a controller in the transistor test system, so that the transistor test system can test the current sharing characteristics of multiple transistors in parallel according to the above test requirement information.

[0073] In another example, the target transistor temperature and target switching rate can also be calculated by the controller. For example, for the target transistor temperature, the controller can determine whether the multiple transistors are in a current-sharing state based on the current values and temperature values of the multiple transistors detected by the second conditioning circuit. If the battery value of a certain transistor is detected to be outside the preset current range, it can be determined that the multiple transistors are in a non-current-sharing state. At this time, the controller can adjust the temperature of the transistor whose current value is outside the preset current range to adjust the on-resistance of the transistor, thereby adjusting the output current of the transistor to achieve a current-sharing effect of multiple transistors in parallel. The calculation method of the target switching rate is similar to the calculation method of the target transistor temperature, and no further examples are given here.

[0074] In step S502 , the controller generates a temperature adjustment instruction including a target transistor temperature, and controls the heating device to adjust the transistor temperatures of the plurality of transistors, thereby obtaining a first transistor temperature detected by the data measurement circuit.

[0075] In step S502, after receiving the target transistor temperature corresponding to each transistor, the controller generates a temperature adjustment instruction and sends the temperature adjustment instruction to the heating device, so that the heating device adjusts the temperature of the transistor so that the temperature of the transistor reaches the target transistor temperature. During this process, the controller can also obtain the first transistor temperature detected by the data measurement circuit in real time to determine whether the transistor has reached the target transistor temperature, thereby avoiding problems such as transistor damage caused by excessively high transistor temperature or inaccurate test results caused by substandard transistor temperature.

[0076] In step S503 , the controller generates a transistor control instruction including a target switching rate, and controls the driving circuit to adjust the on and off of the plurality of transistors, and obtains the transistor output current detected by the data measurement circuit.

[0077] In step S503, after receiving the target switching rate corresponding to each transistor, the controller generates a transistor control instruction and sends it to the driver circuit, which controls the transistor to switch at the target switching rate. During this process, the controller can also obtain the transistor output current detected by the data measurement circuit in real time to analyze the transistor output current and determine whether the transistor's current sharing characteristics meet the requirements.

[0078] In step S504 , the controller determines a test result of the current sharing characteristic of the transistor according to the first transistor temperature and the transistor output current.

[0079] In step S504, the controller may perform data analysis on the first transistor temperature and the transistor output current to determine the current sharing characteristics of the transistor. For example, the controller may analyze whether the transistor output current meets the preset requirements at the first transistor temperature. If the preset requirements are met, it may be determined that the current sharing characteristics of the transistor meet the standards at the first transistor temperature.

[0080] The following introduces the implementation process of the transistor measurement method provided in the embodiment of the present application.

[0081] In one embodiment, during the process of adjusting the transistor temperatures of a plurality of transistors, when a first transistor temperature is less than a target transistor temperature, the controller controls the heating device to perform heating operations on the transistors until the first transistor temperature detected by the data measurement circuit reaches the target transistor temperature; when the first transistor temperature is greater than or equal to the target transistor temperature, the controller controls the heating device to stop heating the transistors.

[0082] In one example, Figure 6 shows a method for adjusting the transistor temperature, in Figure 6 In the data measurement circuit, Tg is the target transistor temperature, and Tc is the transistor temperature detected by the data measurement circuit. Specifically, the controller receives control instructions, sets the target transistor temperature of the SiC MOSFET under test to Tg, and the logic control circuit compares the set target transistor temperature Tg with the transistor temperature Tc collected by the data measurement circuit. When Tg>Tc, the relay is turned on and the heating device operates; when Tc>temperature threshold T0, the heating device stops operating; when Tc≤T0, the heating device operates normally; when Tg≤Tc and Tc>T0, the heating device stops operating; when Tg≤Tc and Tc≤T0, only temperature collection feedback is performed, and the heating device does not operate.

[0083] It should be noted that in the above embodiment, temperature threshold T0 is the target transistor temperature, which is a temperature warning value. This temperature warning value is lower than the upper temperature limit for normal operation of the transistor. For example, temperature threshold T0 may be 125°C, while the upper temperature limit for normal operation of the transistor is 127°C. The heat source temperature control circuit uses the above control logic to simulate the change of the SiC MOSFET chip temperature.

[0084] In one embodiment, each transistor is connected in series with a non-inductive resistor, and the test requirement information also includes a target resistance value of the non-inductive resistor. In this scenario, after obtaining the test requirement information for performing a current sharing characteristic test on multiple transistors connected in parallel, the controller can further adjust the resistance value of the non-inductive resistor connected in series with each transistor to the target resistance value.

[0085] It should be noted that the non-inductive resistor in the test unit can be replaced based on test requirements to simulate changes in the SiC MOSFET's on-resistance. By adjusting the SiC MOSFET's on-resistance, the current flowing through each parallel branch is altered. Under the dynamic regulation of the SiC MOSFET's thermal characteristics, each branch will experience a dynamic current sharing effect. Using temperature and current acquisition feedback circuits for status monitoring, the parallel current sharing performance of SiC MOSFETs can be tested. Furthermore, by replacing non-inductive resistors with different resistance values, the ultimate current sharing effect of multiple parallel transistors can be evaluated.

[0086] In one embodiment, the test requirement information also includes a test scenario. In this scenario, after obtaining the test requirement information for performing a current sharing characteristic test on multiple transistors connected in parallel, the controller can also obtain the transistor turn-off voltage and transistor on-current corresponding to the test scenario, and adjust the high-voltage power supply and load connected to the multiple transistors according to the transistor turn-off voltage and transistor on-current.

[0087] It should be noted that by setting the load of the high-voltage power supply through the control instructions of the controller, for example, controlling the connection or disconnection of the load of the high-voltage power supply, it is possible to dynamically adjust the cut-off voltage and current of the SiC MOSFET under test, enriching the test scenarios of SiC MOSFET and improving the test accuracy of SiC MOSFET.

[0088] This concludes the introduction to the transistor testing method provided in the embodiments of the present application.

[0089] As can be seen from the above introduction, in the embodiment of the present application, by connecting non-inductive resistors in series, non-inductive resistors of different resistance values are connected in series in the SiC MOSFET parallel branch to simulate the change of the on-resistance of the SiC MOSFET, which can effectively solve the problem that the dynamic test cannot change the on-resistance of the SiC MOSFET. The external heating method is used to conduct heat to the SiC MOSFET chip to simulate the change of the chip temperature of the SiC MOSFET, which can effectively solve the problem that the temperature of the SiC MOSFET chip cannot be dynamically adjusted. The main control MCU is used to control and monitor the test to test the extreme current sharing effect, so as to achieve the purpose of meeting the parallel current sharing performance test of the SiC MOSFET.

[0090] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0091] Figure 7 A schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present application is shown.

[0092] The electronic device may include a processor 701 and a memory 702 storing computer program instructions.

[0093] Specifically, the processor 701 may include a central processing unit (CPU), or an application-specific integrated circuit (ASIC), or may be configured to implement one or more integrated circuits of the embodiments of the present application.

[0094] The memory 702 may include a large capacity memory for data or instructions. By way of example and not limitation, the memory 702 may include a hard disk drive (HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a universal serial bus (USB) drive, or a combination of two or more of these. Where appropriate, the memory 702 may include removable or non-removable (or fixed) media. Where appropriate, the memory 702 may be inside or outside the integrated gateway disaster recovery device. In a specific embodiment, the memory 702 is a non-volatile solid-state memory.

[0095] The memory may include read-only memory (ROM), random access memory (RAM), magnetic disk storage media devices, optical storage media devices, flash memory devices, electrical, optical or other physical / tangible memory storage devices. Thus, generally, the memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., memory devices) encoded with software including computer-executable instructions, and when the software is executed (e.g., by one or more processors), it is operable to perform the operations described with reference to the method according to an aspect of the present disclosure.

[0096] The processor 701 reads and executes computer program instructions stored in the memory 702 to implement any one of the transistor testing methods in the above embodiments.

[0097] In one example, the electronic device may further include a communication interface 703 and a bus 710. Figure 7 As shown, the processor 701, the memory 702, and the communication interface 703 are connected via a bus 710 and communicate with each other.

[0098] The communication interface 703 is mainly used to implement communication between various modules, devices, units and / or equipment in the embodiments of the present application.

[0099] Bus 710 comprises hardware, software or both, couples the parts of electronic equipment to each other.For example, and not limitation, bus can comprise accelerated graphics port (AGP) or other graphics bus, enhanced industry standard architecture (EISA) bus, front side bus (FSB), hypertransport (HT) interconnection, industry standard architecture (ISA) bus, infinite bandwidth interconnection, low pin count (LPC) bus, memory bus, micro channel architecture (MCA) bus, peripheral component interconnection (PCI) bus, PCI-Express (PCI-X) bus, serial advanced technology attachment (SATA) bus, video electronics standard association local (VLB) bus or other suitable bus or two or more of these combinations.In suitable cases, bus 710 can comprise one or more buses.Although the present application embodiment describes and shows specific bus, the application considers any suitable bus or interconnection.

[0100] In addition, in conjunction with the transistor testing method in the above embodiments, embodiments of the present application may provide a computer-readable storage medium for implementation. The computer-readable storage medium stores computer program instructions; when the computer program instructions are executed by a processor, any of the transistor testing methods in the above embodiments is implemented.

[0101] In addition, in combination with the transistor testing method in the above embodiments, the present application can provide a computer program product for implementation. When the instructions in the computer program product are executed by a processor of an electronic device, the electronic device executes and implements any of the transistor testing methods in the above embodiments.

[0102] It should be understood that the present application is not limited to the specific configurations and processes described above and illustrated in the figures. For the sake of brevity, a detailed description of known methods is omitted here. In the above embodiments, several specific steps are described and illustrated as examples. However, the method process of the present application is not limited to the specific steps described and illustrated. Those skilled in the art can make various changes, modifications, and additions, or change the order of the steps after understanding the spirit of the present application.

[0103] The functional modules shown in the above-described block diagram can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application specific integrated circuit (ASIC), appropriate firmware, a plug-in unit, a function card or the like. When implemented in software, the elements of the present application are programs or code segments that are used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or a communication link by a data signal carried in a carrier wave. "Machine-readable medium" can include any medium that can store or transmit information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROMs, flash memories, erasable ROMs (EROMs), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (RF) links, etc. The code segment can be downloaded via a computer network such as the Internet, an intranet, etc.

[0104] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, this application is not limited to the order of the above steps. In other words, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0105] The above describes various aspects of the present disclosure with reference to the flowcharts and / or block diagrams of the test systems, test methods, devices and media of transistors according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of boxes in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine so that these instructions executed by the processor of the computer or other programmable data processing device enable the implementation of the functions / actions specified in one or more boxes in the flowchart and / or block diagram. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor or a field programmable logic circuit. It can also be understood that each box in the block diagram and / or flowchart and the combination of boxes in the block diagram and / or flowchart can also be implemented by dedicated hardware that performs the specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0106] The above description is only a specific embodiment of the present application. Those skilled in the art will clearly understand that for the convenience and brevity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the scope of protection of the present application.

Claims

1. A transistor testing system, characterized in that: include: a heating device connected to a plurality of transistors connected in parallel, for adjusting the temperature of the transistors, wherein each of the transistors is connected in series with a high-voltage power supply via a non-inductive resistor; a plurality of driving circuits, each of the driving circuits being connected to one of the transistors and configured to control the on and off of the transistors according to a target switching rate corresponding to the transistor; a data measurement circuit connected to the output terminal of each of the transistors, configured to collect a first transistor temperature of each of the transistors and collect a transistor output current of the transistor at the first transistor temperature and the target switching rate; A controller is connected to the heating device, the multiple drive circuits, and the data measurement circuit, and is used to generate a temperature adjustment instruction for controlling the heating device and a transistor control instruction for controlling the transistor based on a target transistor temperature and a target switching rate corresponding to the transistor, and receives a first transistor temperature and a transistor output current detected by the data measurement circuit, and determines a test result of a current sharing characteristic of the transistor based on the first transistor temperature and the transistor output current, wherein the target transistor temperature is a temperature at which the output current of the transistor is within a preset current range, the target switching rate is a switching rate at which the output current of the transistor is within the preset current range, and the preset current range is a current range when multiple parallel transistors are in a current sharing state.

2. The test system according to claim 1, wherein: The test system further comprises: The heat source temperature control circuit is connected between the controller and the heating device, and is used to control the heating device to heat the transistor according to the temperature adjustment instruction.

3. The test system according to claim 2, wherein: The heating device comprises: a plurality of heating units, each of the heating units being connected to one of the transistors; Each of the heating units includes a transistor heating source, a heat conducting unit and a temperature sensor; The transistor heating source is connected to the controller and is used to perform a heating operation on the transistor placed on the transistor heating source; The heat conduction unit is provided between the transistor heating source and the transistor placed on the transistor heating source, and is in contact with the transistor heating source and the transistor; The temperature sensor is arranged on a side of the heat conducting unit close to the transistor.

4. The test system according to claim 3, characterized in that: The heat source temperature control circuit includes: a temperature feedback circuit connected to output ends of the temperature sensors of the plurality of heating units, and configured to transmit the second transistor temperature detected by each temperature sensor to the controller; a logic control circuit connected to the output end of the temperature feedback circuit, and configured to control the heating operation of the heating device on the transistor according to the target transistor temperature and the second transistor temperature fed back by the temperature feedback circuit; a plurality of relays connected between the logic control circuit and the heating device, for controlling the heating device to perform a heating operation on the transistor; A control power supply is connected to the power input terminals of the plurality of relays and supplies power to the transistor heating source when the relays are turned on.

5. The test system according to claim 4, characterized in that: The logic control circuit includes: a first input terminal, a second input terminal and a plurality of signal output terminals. The logic control circuit is connected to the controller via the first input terminal to receive a temperature adjustment instruction issued by the controller; The logic control circuit is connected to the temperature feedback circuit via the second input terminal to obtain the second transistor temperature detected by the temperature sensor; The logic control circuit is connected to the plurality of relays respectively through the plurality of signal output terminals, and controls the heating device to heat the transistor by controlling the on and off of the plurality of relays.

6. The test system according to claim 1, wherein: The driving circuit includes: A gate drive circuit connected to the gate of the transistor and used to control the on and off of the transistor; a gate clamping circuit connected to the output terminal of the gate driving circuit and configured to transmit an output signal of the gate driving circuit; a driving chip connected to the input end of the gate driving circuit and to the output end of the gate clamping circuit, and configured to perform Miller clamping on the output signal of the gate driving circuit according to the output signal of the gate driving circuit; The driving power supply circuit is connected to the output end of the controller and the input end of the driving chip, and is used to output an on-off voltage for controlling the on-off of the transistor according to the transistor control instruction.

7. The test system according to claim 6, characterized in that: The driving power circuit includes: a first output terminal and a second output terminal; the driving chip includes a third input terminal and a fourth input terminal; The driving power circuit is connected to the third input terminal of the driving chip via the first output terminal, and is used to input a transistor turn-on voltage to the driving chip to turn on the transistor; The driving power circuit is connected to the fourth input terminal of the driving chip via the second output terminal, and is used for inputting a transistor-off voltage to the driving chip to turn off the transistor.

8. The test system according to claim 6, wherein: The test system further includes: a first conditioning circuit for converting the transistor control instruction into a pulse width modulation (PWM) signal; The input end of the first conditioning circuit is connected to the controller and is used to receive the transistor control instruction output by the controller; The multiple output terminals of the first conditioning circuit are respectively connected to the driving power circuits in the multiple driving circuits, and are used to transmit the PWM signal to the driving power circuits.

9. The test system according to claim 3, wherein: The data measurement circuit includes: a current collection circuit connected to the output end of the transistor and used for collecting the transistor output current of the transistor; a temperature acquisition circuit, connected to the temperature sensor, for acquiring a first transistor temperature of the transistor; The second conditioning circuit is connected to the current acquisition circuit, the temperature acquisition circuit and the controller, and is used for performing format conversion on the transistor output current and the first transistor temperature.

10. A method for testing a transistor, characterized in that: In the transistor test system according to any one of claims 1 to 9, the method comprises: The controller obtains test requirement information for performing a current sharing characteristic test on a plurality of transistors connected in parallel, wherein the test requirement information includes at least a target transistor temperature corresponding to each of the transistors and a target switching rate of each of the transistors, the target transistor temperature being a temperature at which an output current of the transistor falls within a preset current range, the target switching rate being a switching rate at which an output current of the transistor falls within the preset current range, and the preset current range being a current range at which the plurality of transistors connected in parallel are in a current sharing state; The controller generates a temperature adjustment instruction including the target transistor temperature, and controls the heating device to adjust the transistor temperatures of the plurality of transistors, and obtains the first transistor temperature detected by the data measurement circuit; The controller generates a transistor control instruction including the target switching rate, and controls the driving circuit to adjust the on and off of the plurality of transistors, and obtains the transistor output current detected by the data measurement circuit; The controller determines a test result of a current sharing characteristic of the transistor according to the temperature of the first transistor and the output current of the transistor.

11. The method according to claim 10, characterized in that The controlling the heating device to adjust the transistor temperature of the plurality of transistors comprises: When the first transistor temperature is lower than the target transistor temperature, the controller controls the heating device to heat the transistor until the first transistor temperature detected by the data measurement circuit reaches the target transistor temperature. When the first transistor temperature is greater than or equal to the target transistor temperature, the controller controls the heating device to stop heating the transistor.

12. The method according to claim 10 or 11, characterized in that Each of the transistors is connected in series with a non-inductive resistor, and the test requirement information further includes a target resistance value of the non-inductive resistor. After the controller obtains the test requirement information for performing a current sharing characteristic test on the plurality of transistors connected in parallel, the method further includes: The controller adjusts the resistance of the non-inductive resistor connected in series with each of the transistors to the target resistance.

13. The method according to claim 10 or 11, characterized in that The test requirement information further includes a test scenario, wherein, after the controller obtains the test requirement information for performing a current sharing characteristic test on a plurality of transistors connected in parallel, the method further includes: The controller obtains a transistor off-voltage and a transistor on-current corresponding to the test scenario; The controller adjusts the high-voltage power supply and the load connected to the plurality of transistors according to the transistor turn-off voltage and the transistor turn-on current.

14. An electronic device, characterized in that: The electronic device includes: a processor and a memory storing computer program instructions; When the processor executes the computer program instructions, the transistor testing method according to any one of claims 10 to 13 is implemented.

15. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer program instructions, and when the computer program instructions are executed by a processor, the transistor testing method according to any one of claims 10 to 13 is implemented.

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