Floating ground generation circuit in high voltage application and control method thereof

Abstract

The invention discloses a floating ground generation circuit in high-voltage application and a control method thereof, and the floating ground generation circuit comprises a coarse tuning ground generation circuit, a reference voltage circuit, a feedback resistance network, a low-voltage error amplifier EA, an adjusting tube NM1 and a current self-adaptive adjusting circuit, the coarse tuning ground generation circuit generates a voltage HVSS based on a power supply voltage VDD; the reference voltage circuit generates a reference voltage VREF based on a power supply voltage VDD and a voltage HVSS, a normal-phase input end of the low-voltage error amplifier EA is connected with the reference voltage VREF, an inverted-phase input end of the low-voltage error amplifier EA is connected with an output end of the feedback resistance network, an output end of the error amplifier EA is connected with a grid electrode of the adjusting tube NM1 and an input end of the current self-adaptive adjusting circuit, and the current self-adaptive adjusting circuit is connected with the grid electrode of the adjusting tube NM1. And the output end of the current self-adaptive regulation circuit generates an output voltage VOUT. The floating ground generation circuit provided by the invention simultaneously meets the design requirements of small area and low power consumption.

Description

Technical Field

[0001] The present invention relates to a floating ground generating circuit and a control method thereof, in particular to a floating ground generating circuit and a control method thereof in high voltage applications, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] In applications such as automotive electronics and industrial control, systems often need to handle high input voltages (such as 12V or 48V DC power). However, the functional modules within the chip often cannot directly operate in such a high voltage range. Therefore, power supply voltage conversion circuits are particularly important. Depending on the requirements, two approaches to power supply voltage conversion are available: one is to generate a lower supply voltage, denoted as LVDD, with internal modules operating between LVDD and system ground; the other is to generate a ground voltage with a fixed voltage differential from the supply voltage, denoted as HVSS, with internal modules operating between the system supply and HVSS. For example, in a high-side switch application, when the switch is on, the output voltage approaches the supply voltage. If the internal modules use a low supply voltage, they still face voltage withstand issues. In this case, the operating voltage range of the internal circuits needs to be converted to a higher rail, that is, between the supply voltage and internal ground. Therefore, a floating reference ground generation circuit is more efficient.

[0003] Figure 3 This is an existing high-voltage domain ground voltage generation circuit. This structure is converted from a low-dropout linear regulator (LDO). The input voltage VDD is usually a high-voltage power supply voltage, and VREF is a temperature-independent reference voltage generated by the reference. M0 is a high-voltage adjustment tube, and EA is an error amplifier, which operates between VDD and GND. The output voltage VOUT can be determined by feedback resistors R1 and R2. Although this structure is simple to implement, because VDD is a high-voltage power supply with a wide input range, the reference and bias circuits and the error amplifier require many high-voltage components to implement, which undoubtedly increases the area. In order to reduce the use of high-voltage components, it can be used. Figure 4 The circuit shown. In this circuit, the error amplifier operates in a voltage range between VDD and VOUT, so no high-voltage devices are required, which can greatly save area. NM1 is a pass transistor, NM4 is a high-voltage transistor, and the voltage between its drain and source can withstand is higher than the maximum voltage of VDD. NM2 and NM3 are current mirrors, and the size of NM3 is n times that of NM2. If the current flowing through NM2 is I0, the current flowing through NM3 is theoretically n*I0. Although this circuit is similar to Figure 3 Compared with the circuit, the number of high-voltage tubes used is significantly reduced, but when the load circuit is not working, the current on NM3 is still equal to n*I0, which will generate a lot of power consumption, which is contrary to the current low-power design of the circuit.

[0004] Therefore, in order to simultaneously meet the design requirements of small area and low power consumption, a high-voltage domain floating ground generation circuit is needed that has low requirements for high-voltage tubes and whose power consumption can be adjusted according to the load current. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a floating ground generating circuit and a control method thereof in high voltage applications, which simultaneously meet the design requirements of small area and low power consumption.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is: A floating ground generation circuit for high-voltage applications includes a coarse ground generation circuit, a reference voltage circuit, a feedback resistor network, a low-voltage error amplifier EA, an adjustment tube NM1, and a current adaptive adjustment circuit. The coarse ground generation circuit generates a voltage HVSS based on a power supply voltage VDD. The reference voltage circuit generates a reference voltage VREF based on the power supply voltage VDD and the voltage HVSS. A non-inverting input of the low-voltage error amplifier EA is connected to the reference voltage VREF. An inverting input of the low-voltage error amplifier EA is connected to the output of the feedback resistor network. The output of the error amplifier EA is connected to the gate of the adjustment tube NM1 and the input of the current adaptive adjustment circuit. The drain of the adjustment tube NM1 is connected to the power supply voltage VDD. The source of the adjustment tube NM1 is connected to the output of the current adaptive adjustment circuit to generate an output voltage VOUT. The feedback resistor network divides the power supply voltage VDD and the output voltage VOUT and outputs them.

[0007] Furthermore, the coarse adjustment ground generation circuit includes a PMOS transistor PM2, a PMOS transistor PM3, an NMOS transistor NM6, a high-voltage NMOS transistor NM7, a high-voltage NMOS transistor NM8, a current source I1, and a current source I2. The source of the PMOS transistor PM2 and the drain of the NMOS transistor NM6 are connected to the power supply voltage VDD, the gate of the PMOS transistor PM2 is connected to the drain of the PMOS transistor PM2 and the source of the PMOS transistor PM3, the gate of the PMOS transistor PM3 is connected to the drain of the PMOS transistor PM3, The gate of the NMOS transistor NM6 is connected to the drain of the high-voltage NMOS transistor NM7, the source of the NMOS transistor NM6 is connected to the drain of the high-voltage NMOS transistor NM8 and generates a voltage HVSS, the gate of the high-voltage NMOS transistor NM7 and the gate of the high-voltage NMOS transistor NM8 are connected to an enable signal EN, the source of the high-voltage NMOS transistor NM7 is connected to one end of the current source I1, the source of the high-voltage NMOS transistor NM8 is connected to one end of the current source I2, and the other end of the current source I1 and the other end of the current source I2 are grounded.

[0008] Furthermore, the current adaptive regulation circuit includes an NMOS tube NM2, a high-voltage PMOS tube PM1, an NMOS tube NM3, an NMOS tube NM4, a high-voltage NMOS tube NM5 and a current source I0, one end of the current source I0 is connected to the power supply voltage VDD, the other end of the current source I0 is connected to the drain of the NMOS tube NM2 and the source of the high-voltage PMOS tube PM1, the gate of the NMOS tube NM2 is connected as the input end of the current adaptive regulation circuit to the output end of the low-voltage error amplifier EA and the gate of the adjustment tube NM1, and the source of the NMOS tube NM2 is connected to the output end of the low-voltage error amplifier EA and the gate of the adjustment tube NM1. The output voltage VOUT is generated by connecting the high-voltage PMOS transistor PM1 to the drain of the high-voltage NMOS transistor NM5 and serving as the output end of the current adaptive regulation circuit. The gate of the high-voltage PMOS transistor PM1 is connected to the voltage HVSS. The drain of the high-voltage PMOS transistor PM1 is connected to the drain of the NMOS transistor NM3, the gate of the NMOS transistor NM3, and the gate of the NMOS transistor NM4. The gate of the high-voltage NMOS transistor NM5 is connected to the enable signal EN. The source of the high-voltage NMOS transistor NM5 is connected to the drain of the NMOS transistor NM4. The source of the NMOS transistor NM3 and the source of the NMOS transistor NM4 are grounded.

[0009] Furthermore, the ratio of the width to length of the adjustment transistor NM1 and the NMOS transistor NM2 is m:1.

[0010] Furthermore, the width-to-length ratio of the NMOS transistor NM4 to the NMOS transistor NM3 is n:1.

[0011] Furthermore, the feedback resistor network includes a resistor R1 and a resistor R2, one end of the resistor R1 is connected to the power supply voltage VDD, the other end of the resistor R1 is connected to one end of the resistor R2 and serves as the output end of the feedback resistor network, and the other end of the resistor R2 is connected to the output voltage VOUT.

[0012] A method for controlling a floating ground generating circuit in a high voltage application comprises the following steps: The coarse ground generation circuit provides a ground voltage for the reference voltage circuit and the low-voltage error amplifier EA. That is, when the enable signal EN becomes high, the NMOS transistors NM7 and NMOS transistors NM8 are turned on, the gate-source voltage of the PMOS transistor PM2 is |VGS1|, the gate-source voltage of the PMOS transistor PM3 is |VGS2|, and the gate-source voltage of the NMOS transistor NM6 is VGS3. Then the voltage HVSS is expressed as: HVSS=VDD-|VGS1|-|VGS2|-VGS3; The reference voltage circuit provides a precise reference voltage VREF for the low-voltage error amplifier EA. The reference voltage VREF is connected to the non-inverting input of the low-voltage error amplifier EA. The precise output voltage VOUT is obtained through the feedback resistor network composed of resistors R1 and R2 and the adjustment tube NM1. The output voltage VOUT is expressed as: ; When the power supply voltage VDD is powered on, the enable signal EN becomes high, first coarsely adjusting the circuit output voltage HVSS. The voltage HVSS provides the ground voltage for the reference voltage circuit. Then the feedback resistor network, low-voltage error amplifier EA, pass transistor NM1, and current adaptive regulation circuit start working. The final output voltage VOUT is a precise floating reference ground voltage with a fixed voltage difference from the power supply voltage VDD. The working range of the reference voltage circuit is from the power supply voltage VDD to the voltage HVSS, and the working range of the low-voltage error amplifier EA is from the power supply voltage VDD to the output voltage VOUT. The voltage difference between the working ranges of the reference voltage circuit and the low-voltage error amplifier EA is low voltage, and no high-voltage tube is required. The current I0 generated by the current source I0 is divided into two paths and flows to the NMOS transistor NM2 and the high-voltage PMOS transistor PM1 respectively. Assuming that the current flowing through the NMOS transistor NM2 is I1 and the current flowing through the high-voltage PMOS transistor PM1 is I2, then I0=I1+I2. Since the ratio of the width to length of the adjustment transistor NM1 and the NMOS transistor NM2 is m:1, the current flowing through the adjustment transistor NM1 is m*I1. The current flowing through the NMOS transistor NM3 is equal to the current I2 flowing through the high-voltage PMOS transistor PM1. At the same time, since the ratio of the width to length of the NMOS transistor NM4 and the NMOS transistor NM3 is n:1, the current flowing through the NMOS transistor NM4 is n*I2. The load operates between the power supply voltage VDD and the output voltage VOUT. The load current is IL. The current flowing through the NMOS transistor NM4 is equal to the sum of the current I1 flowing through the NMOS transistor NM2, the current m*I1 flowing through the adjustment transistor NM1, and the load current IL. Therefore, the current flowing through the NMOS transistor NM4 is expressed as: ; If the load current increases, the current flowing through the NMOS transistor NM4 increases, that is, I2 increases. Since I0=I1+I2, the current I1 flowing through the NMOS transistor NM2 decreases, realizing that the power consumption changes with the load current. When the load is not working, that is, the load current IL=0, the current on the NMOS tube NM4 is only: .

[0013] Compared with the prior art, the present invention has the following advantages and effects: 1. The present invention provides a floating ground generation circuit and control method for high-voltage applications, which simultaneously meet the design requirements of small area and low power consumption; 2. The operating range of the reference voltage circuit and the low-voltage error amplifier EA of the present invention is between VDD and HVSS and between VDD and VOUT. This is a low-voltage domain, so no high-voltage tube is required, which reduces the area; 3. The circuit of the present invention has a current adaptive regulation circuit, so the power consumption of the circuit can change with the current consumed by the external load. When the load is not working, the power consumption is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 FIG. 1 is a schematic diagram of a floating ground generating circuit in a high voltage application according to the present invention.

[0015] Figure 2 FIG. 1 is a schematic diagram of a coarse adjustment ground generating circuit of the present invention.

[0016] Figure 3 This is a schematic diagram of a ground voltage generating circuit in a high-voltage domain in the prior art.

[0017] Figure 4 This is a schematic diagram of another high-voltage domain ground voltage generating circuit in the prior art. DETAILED DESCRIPTION

[0018] In order to elaborate on the technical solutions adopted by the present invention to achieve the predetermined technical purpose, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0019] like Figure 1 As shown, a floating ground generation circuit for high-voltage applications of the present invention includes a coarse ground generation circuit, a reference voltage circuit, a feedback resistor network, a low-voltage error amplifier EA, an adjustment tube NM1, and a current adaptive adjustment circuit. The coarse ground generation circuit generates a voltage HVSS based on a power supply voltage VDD, and the reference voltage circuit generates a reference voltage VREF based on the power supply voltage VDD and the voltage HVSS. The non-inverting input terminal of the low-voltage error amplifier EA is connected to the reference voltage VREF, the inverting input terminal of the low-voltage error amplifier EA is connected to the output terminal of the feedback resistor network, the output terminal of the error amplifier EA is connected to the gate of the adjustment tube NM1 and the input terminal of the current adaptive adjustment circuit, the drain terminal of the adjustment tube NM1 is connected to the power supply voltage VDD, the source terminal of the adjustment tube NM1 is connected to the output terminal of the current adaptive adjustment circuit and generates an output voltage VOUT, and the feedback resistor network divides the power supply voltage VDD and the output voltage VOUT for output.

[0020] like Figure 2As shown, the coarse adjustment ground generating circuit includes a PMOS transistor PM2, a PMOS transistor PM3, an NMOS transistor NM6, a high-voltage NMOS transistor NM7, a high-voltage NMOS transistor NM8, a current source I1 and a current source I2. The source of the PMOS transistor PM2 and the drain of the NMOS transistor NM6 are connected to the power supply voltage VDD, the gate of the PMOS transistor PM2 is connected to the drain of the PMOS transistor PM2 and the source of the PMOS transistor PM3, the gate of the PMOS transistor PM3 is connected to the drain of the PMOS transistor PM3, and the NMOS transistor NM6 is connected to the drain of the PMOS transistor PM3. The gate of the OS transistor NM6 is connected to the drain of the high-voltage NMOS transistor NM7, the source of the NMOS transistor NM6 is connected to the drain of the high-voltage NMOS transistor NM8 and generates a voltage HVSS, the gate of the high-voltage NMOS transistor NM7 and the gate of the high-voltage NMOS transistor NM8 are connected to an enable signal EN, the source of the high-voltage NMOS transistor NM7 is connected to one end of the current source I1, the source of the high-voltage NMOS transistor NM8 is connected to one end of the current source I2, and the other ends of the current source I1 and the other ends of the current source I2 are grounded.

[0021] The current adaptive regulation circuit includes an NMOS tube NM2, a high-voltage PMOS tube PM1, an NMOS tube NM3, an NMOS tube NM4, a high-voltage NMOS tube NM5 and a current source I0. One end of the current source I0 is connected to the power supply voltage VDD, and the other end of the current source I0 is connected to the drain of the NMOS tube NM2 and the source of the high-voltage PMOS tube PM1. The gate of the NMOS tube NM2 is connected to the output of the low-voltage error amplifier EA and the gate of the adjustment tube NM1 as the input end of the current adaptive regulation circuit. The source of the NMOS tube NM2 is connected to the high-voltage The drain of the NMOS transistor NM5 is connected and serves as the output end of the current adaptive regulation circuit to generate an output voltage VOUT. The gate of the high-voltage PMOS transistor PM1 is connected to the voltage HVSS. The drain of the high-voltage PMOS transistor PM1 is connected to the drain of the NMOS transistor NM3, the gate of the NMOS transistor NM3, and the gate of the NMOS transistor NM4. The gate of the high-voltage NMOS transistor NM5 is connected to the enable signal EN. The source of the high-voltage NMOS transistor NM5 is connected to the drain of the NMOS transistor NM4. The source of the NMOS transistor NM3 and the source of the NMOS transistor NM4 are grounded.

[0022] The ratio of the width to length of the adjustment transistor NM1 to the NMOS transistor NM2 is m:1, and the ratio of the width to length of the NMOS transistor NM4 to the NMOS transistor NM3 is n:1.

[0023] The feedback resistor network includes resistors R1 and R2. One end of resistor R1 is connected to the power supply voltage VDD. The other end of resistor R1 is connected to one end of resistor R2 and serves as the output end of the feedback resistor network. The other end of resistor R2 is connected to the output voltage VOUT.

[0024] A method for controlling a floating ground generating circuit in a high voltage application comprises the following steps: The coarse ground generation circuit provides a ground voltage for the reference voltage circuit and the low-voltage error amplifier EA. That is, when the enable signal EN becomes high, the NMOS transistors NM7 and NMOS transistors NM8 are turned on, the gate-source voltage of the PMOS transistor PM2 is |VGS1|, the gate-source voltage of the PMOS transistor PM3 is |VGS2|, and the gate-source voltage of the NMOS transistor NM6 is VGS3. Then the voltage HVSS is expressed as: HVSS=VDD-|VGS1|-|VGS2|-VGS3.

[0025] The reference voltage circuit provides a precise reference voltage VREF for the low-voltage error amplifier EA. The reference voltage VREF is connected to the non-inverting input of the low-voltage error amplifier EA. The precise output voltage VOUT is obtained through the feedback resistor network composed of resistors R1 and R2 and the adjustment tube NM1. The output voltage VOUT is expressed as: .

[0026] When the power supply voltage VDD is powered on, the enable signal EN goes high, first generating a coarse ground voltage HVSS. HVSS provides the ground voltage for the reference voltage circuit. Then, the feedback resistor network, low-voltage error amplifier EA, pass transistor NM1, and current adaptive regulation circuit begin to operate. The final output voltage VOUT is a precise floating reference ground voltage with a fixed voltage differential from the power supply voltage VDD.

[0027] The working range of the reference voltage circuit is from the power supply voltage VDD to the voltage HVSS, and the working range of the low-voltage error amplifier EA is from the power supply voltage VDD to the output voltage VOUT. The voltage difference between the working ranges of the reference voltage circuit and the low-voltage error amplifier EA is low voltage, and no high-voltage tube is required, which greatly saves area.

[0028] The current I0 generated by the current source I0 is divided into two paths and flows to the NMOS transistor NM2 and the high-voltage PMOS transistor PM1 respectively. Assuming that the current flowing through the NMOS transistor NM2 is I1 and the current flowing through the high-voltage PMOS transistor PM1 is I2, then I0=I1+I2. Since the width-to-length ratio of the adjustment transistor NM1 and the NMOS transistor NM2 is m:1, the current flowing through the adjustment transistor NM1 is m*I1. The current flowing through the NMOS transistor NM3 is equal to the current I2 flowing through the high-voltage PMOS transistor PM1. At the same time, since the width-to-length ratio of the NMOS transistor NM4 and the NMOS transistor NM3 is n:1, the current flowing through the NMOS transistor NM4 is n*I2.

[0029] The load operates between the power supply voltage VDD and the output voltage VOUT. The load current is IL. The current flowing through the NMOS transistor NM4 is equal to the sum of the current I1 flowing through the NMOS transistor NM2, the current m*I1 flowing through the adjustment transistor NM1, and the load current IL. Therefore, the current flowing through the NMOS transistor NM4 is expressed as: .

[0030] If the load current increases, the current flowing through the NMOS tube NM4 increases, that is, I2 increases. Since I0=I1+I2, the current I1 flowing through the NMOS tube NM2 decreases, realizing that the power consumption changes with the load current.

[0031] When the load is not working, that is, the load current IL=0, the current on the NMOS tube NM4 is only: .

[0032] Compared to Figure 4 The current in the circuit structure is reduced , thereby reducing circuit power consumption when the load is not working.

[0033] The present invention provides a floating ground generation circuit and control method for high-voltage applications, which simultaneously meet design requirements of small area and low power consumption. The reference voltage circuit and low-voltage error amplifier EA of the present invention operate between VDD and HVSS and between VDD and VOUT, which is a low-voltage domain. Therefore, no high-voltage tube is required, reducing the area. The circuit of the present invention includes a current adaptive regulation circuit, so the power consumption of the circuit can vary with the current consumed by the external load. When the load is not working, the power consumption is reduced.

[0034] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment as above, it is not intended to limit the present invention. Any technician familiar with the present profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical content disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement of the above embodiments made according to the technical essence of the present invention, within the spirit and principles of the present invention, without departing from the content of the technical solution of the present invention, shall still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A floating ground generating circuit for high voltage applications, characterized in that: The invention comprises a coarse ground generation circuit, a reference voltage circuit, a feedback resistor network, a low-voltage error amplifier EA, an adjustment tube NM1 and a current adaptive adjustment circuit. The coarse ground generation circuit generates a voltage HVSS based on a power supply voltage VDD. The reference voltage circuit generates a reference voltage VREF based on the power supply voltage VDD and the voltage HVSS. The non-inverting input terminal of the low-voltage error amplifier EA is connected to the reference voltage VREF. The inverting input terminal of the low-voltage error amplifier EA is connected to the output terminal of the feedback resistor network. The output terminal of the error amplifier EA is connected to the gate of the adjustment tube NM1 and the input terminal of the current adaptive adjustment circuit. The drain terminal of the adjustment tube NM1 is connected to the power supply voltage VDD. The source terminal of the adjustment tube NM1 is connected to the output terminal of the current adaptive adjustment circuit and generates an output voltage VOUT. The feedback resistor network divides the power supply voltage VDD and the output voltage VOUT and outputs them.

2. The floating ground generating circuit for high voltage applications according to claim 1, wherein: The coarse adjustment ground generating circuit includes a PMOS transistor PM2, a PMOS transistor PM3, an NMOS transistor NM6, a high-voltage NMOS transistor NM7, a high-voltage NMOS transistor NM8, a current source I1 and a current source I2. The source of the PMOS transistor PM2 and the drain of the NMOS transistor NM6 are connected to the power supply voltage VDD. The gate of the PMOS transistor PM2 is connected to the drain of the PMOS transistor PM2 and the source of the PMOS transistor PM3. The gate of the PMOS transistor PM3 is connected to the drain of the PMOS transistor PM3 and the NMOS transistor NM6. The gate of the S transistor NM6 is connected to the drain of the high-voltage NMOS transistor NM7, the source of the NMOS transistor NM6 is connected to the drain of the high-voltage NMOS transistor NM8 and generates a voltage HVSS, the gate of the high-voltage NMOS transistor NM7 and the gate of the high-voltage NMOS transistor NM8 are connected to an enable signal EN, the source of the high-voltage NMOS transistor NM7 is connected to one end of the current source I1, the source of the high-voltage NMOS transistor NM8 is connected to one end of the current source I2, and the other ends of the current source I1 and the other ends of the current source I2 are grounded.

3. The floating ground generating circuit for high voltage applications according to claim 1, wherein: The current adaptive regulation circuit comprises an NMOS transistor NM2, a high-voltage PMOS transistor PM1, an NMOS transistor NM3, an NMOS transistor NM4, a high-voltage NMOS transistor NM5 and a current source I0. One end of the current source I0 is connected to the power supply voltage VDD, and the other end of the current source I0 is connected to the drain of the NMOS transistor NM2 and the source of the high-voltage PMOS transistor PM1. The gate of the NMOS transistor NM2 is connected to the output of the low-voltage error amplifier EA and the gate of the adjustment transistor NM1 as the input end of the current adaptive regulation circuit. The source of the NMOS transistor NM2 is connected to the high-voltage error amplifier EA and the gate of the adjustment transistor NM1. The drain of the high-voltage NMOS transistor NM5 is connected to the output end of the current adaptive regulation circuit to generate the output voltage VOUT. The gate of the high-voltage PMOS transistor PM1 is connected to the voltage HVSS. The drain of the high-voltage PMOS transistor PM1 is connected to the drain of the NMOS transistor NM3, the gate of the NMOS transistor NM3, and the gate of the NMOS transistor NM4. The gate of the high-voltage NMOS transistor NM5 is connected to the enable signal EN. The source of the high-voltage NMOS transistor NM5 is connected to the drain of the NMOS transistor NM4. The source of the NMOS transistor NM3 and the source of the NMOS transistor NM4 are grounded.

4. The floating ground generating circuit for high voltage applications according to claim 3, wherein: The ratio of the width to length of the adjustment transistor NM1 and the NMOS transistor NM2 is m:

1.

5. The floating ground generating circuit for high voltage applications according to claim 3, wherein: The width-to-length ratio of the NMOS transistor NM4 to the NMOS transistor NM3 is n:

1.

6. The floating ground generating circuit for high voltage applications according to claim 1, wherein: The feedback resistor network includes a resistor R1 and a resistor R2. One end of the resistor R1 is connected to the power supply voltage VDD. The other end of the resistor R1 is connected to one end of the resistor R2 and serves as the output end of the feedback resistor network. The other end of the resistor R2 is connected to the output voltage VOUT.

7. A method for controlling a floating ground generating circuit in a high voltage application according to any one of claims 1 to 6, characterized in that The following steps are involved: The coarse ground generation circuit provides a ground voltage for the reference voltage circuit and the low-voltage error amplifier EA. That is, when the enable signal EN becomes high, the NMOS transistors NM7 and NMOS transistors NM8 are turned on, the gate-source voltage of the PMOS transistor PM2 is |VGS1|, the gate-source voltage of the PMOS transistor PM3 is |VGS2|, and the gate-source voltage of the NMOS transistor NM6 is VGS3. Then the voltage HVSS is expressed as: HVSS=VDD-|VGS1|-|VGS2|-VGS3; The reference voltage circuit provides a precise reference voltage VREF for the low-voltage error amplifier EA. The reference voltage VREF is connected to the non-inverting input of the low-voltage error amplifier EA. The precise output voltage VOUT is obtained through the feedback resistor network composed of resistors R1 and R2 and the adjustment tube NM1. The output voltage VOUT is expressed as: ； When the power supply voltage VDD is powered on, the enable signal EN becomes high, first coarsely adjusting the circuit output voltage HVSS. The voltage HVSS provides the ground voltage for the reference voltage circuit. Then the feedback resistor network, low-voltage error amplifier EA, pass transistor NM1, and current adaptive regulation circuit start working. The final output voltage VOUT is a precise floating reference ground voltage with a fixed voltage difference from the power supply voltage VDD. The working range of the reference voltage circuit is from the power supply voltage VDD to the voltage HVSS, and the working range of the low-voltage error amplifier EA is from the power supply voltage VDD to the output voltage VOUT. The voltage difference between the working ranges of the reference voltage circuit and the low-voltage error amplifier EA is low voltage, and no high-voltage tube is required. The current I0 generated by the current source I0 is divided into two paths and flows to the NMOS transistor NM2 and the high-voltage PMOS transistor PM1 respectively. Assuming that the current flowing through the NMOS transistor NM2 is I1 and the current flowing through the high-voltage PMOS transistor PM1 is I2, then I0=I1+I2. Since the ratio of the width to length of the adjustment transistor NM1 and the NMOS transistor NM2 is m:1, the current flowing through the adjustment transistor NM1 is m*I1. The current flowing through the NMOS transistor NM3 is equal to the current I2 flowing through the high-voltage PMOS transistor PM1. At the same time, since the ratio of the width to length of the NMOS transistor NM4 and the NMOS transistor NM3 is n:1, the current flowing through the NMOS transistor NM4 is n*I2. The load operates between the power supply voltage VDD and the output voltage VOUT. The load current is IL. The current flowing through the NMOS transistor NM4 is equal to the sum of the current I1 flowing through the NMOS transistor NM2, the current m*I1 flowing through the adjustment transistor NM1, and the load current IL. Therefore, the current flowing through the NMOS transistor NM4 is expressed as: ； If the load current increases, the current flowing through the NMOS transistor NM4 increases, that is, I2 increases. Since I0=I1+I2, the current I1 flowing through the NMOS transistor NM2 decreases, realizing that the power consumption changes with the load current. When the load is not working, that is, the load current IL=0, the current on the NMOS tube NM4 is only: 。

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