High-precision band-gap reference circuit with second-order temperature compensation

Abstract

The invention discloses a high-precision band-gap reference circuit with second-order temperature compensation, which comprises field effect transistors M1 to M18, Mi, 1 to Mi, 4, bipolar transistors Q1 to Q3, Qi, 1 to Qi, 2, resistors R1 to R5 and a current mirror array, and i ranges from 1 to 8. On the basis of a traditional band-gap reference circuit, additional negative temperature coefficient current is introduced, and control over the second-order temperature coefficient of reference voltage is achieved. The reference voltage shows an S-shaped change curve along with temperature rise, has small temperature drift, and is suitable for high-precision analog-to-digital converter design.

Description

Technical Field

[0001] The invention relates to a high-precision bandgap reference circuit with second-order temperature compensation, belonging to the technical field of integrated circuits. Background Art

[0002] In hybrid digital-analog integrated circuits, modules such as power management, oscillators, and analog-to-digital converters require a reference voltage that is invariant to temperature, power supply voltage, and other factors. Bandgap references are widely used due to their low temperature coefficient, simple structure, and wide operating temperature range. Traditional bandgap references utilize the negative temperature coefficient of a bipolar transistor's emitter junction voltage and the positive temperature coefficient of the emitter junction voltage difference at two different current densities. Using an appropriate voltage summing circuit, these positive and negative temperature coefficients cancel each other out, resulting in a reference voltage with zero temperature coefficient. However, traditional bandgap reference sources have the following shortcomings: 1. The mutual cancellation of positive and negative temperature coefficients is only effective at one temperature point. At other temperature points, especially at more extreme temperature points, the reference voltage still has a large temperature coefficient. Therefore, traditional bandgap reference sources are difficult to use in high-precision occasions; 2. Voltage summing circuits usually require op amps, which require stable bias current to maintain normal operation. In particular, high-gain op amps usually require a large quiescent current. Therefore, traditional bandgap reference sources are difficult to use in low-power occasions; at the same time, the offset and noise of the op amp are amplified by the feedback loop and directly superimposed on the reference output, which will lead to a decrease in accuracy and deterioration of noise performance. Summary of the Invention

[0003] The technical problem solved by the present invention is to overcome the deficiencies of the prior art and provide a high-precision bandgap reference circuit with second-order temperature compensation and smaller temperature drift.

[0004] The technical solution of the present invention is:

[0005] The present invention discloses a high-precision bandgap reference circuit with second-order temperature compensation, comprising: a positive temperature coefficient current generation module, a negative temperature coefficient current generation module, a current mirror array and a reference voltage generation module; wherein,

[0006] The positive temperature coefficient current generation module uses the positive temperature characteristic of the voltage difference between the emitter junctions of the BJT tube under different current densities to generate a positive temperature coefficient current and output it to the current mirror array;

[0007] The negative temperature coefficient current generation module uses the negative temperature characteristic of the BJT tube emitter junction voltage to generate a negative temperature coefficient current and output it to the current mirror array;

[0008] The reference voltage generation module uses the positive temperature coefficient current and negative temperature coefficient current output by the current mirror array to bias the BJT tube so that the emitter junction voltages of each BJT tube compensate each other and generate a reference voltage.

[0009] Furthermore, in the above-mentioned reference circuit, the positive temperature coefficient current generation module includes MOS transistors M1-M6, M13-M17, BJT transistors Q1-Q2, and resistors R1, R3-R4, wherein the drain of M1 is connected to the source of M2, the drain of M3 is connected to the source of M4, and the drain of M5 is connected to the source of M6; the gates of M2, M4, and M6 are commonly connected to the drain of M14, the gates of M1, M3, and M5 are commonly connected to the drain of M4, and R1 is connected across the drain of M4 and the drain of M14; the drain of M2, the drain of M13, and the gate of M13 are commonly connected to the gate of M14; the source of M13 is connected to the collector of Q1, the source of M14 is connected to the collector of Q2, and the base of Q1 is connected to the base of Q2 through R3; the drain of M6 is connected to the current mirror array; the emitter of Q1 is grounded, the emitter of Q2 is grounded through R4, and the sources of M1, M3, and M5 are connected to the power supply.

[0010] Furthermore, in the above-mentioned reference circuit, the negative temperature coefficient current generation module includes MOS tubes M7-M12, M18, BJT tube Q3, and resistors R2 and R5; wherein, the drain of M7 is connected to the source of M8, the drain of M9 is connected to the source of M10, and the drain of M11 is connected to the source of M12; the gates of M9 and M11 are commonly linked to the drain of M10, the gates of M10 and M12 are commonly connected to the drain of M18, and R2 is connected across the drain of M10 and the drain of M18; the drain of M8 and the gate of M18 are commonly connected to the collector of Q3, and the source of M18 is connected to the base of Q3; the drain of M12 is connected to the current mirror array; the emitter of Q3 is grounded, the source of M18 is grounded through R5, and the sources of M7, M9, and M11 are connected to the power supply.

[0011] Furthermore, in the above-mentioned reference circuit, the reference voltage generation module includes a multi-stage cascade circuit, each stage of the cascade circuit includes MOS tubes Mi,1-Mi,4 and BJT tubes Qi,1-Qi,2, where i=1-8; Mi,1 gate, Mi,1 drain and Mi,2 gate are commonly connected to Mi,3 drain, Mi,3 source and Mi,4 source are connected; Mi,3 gate is connected to Qi,1 collector; Mi,2 drain is connected to Qi,1 and Qi,2 The base provides base current for it; the sources of Mi,1 and Mi,2 are connected to the power supply; the emitter of Qi,1 is connected to the source of Mi,4, the emitter of Qi,2 is connected to the drain of Mi,4, and the collector of Qi,2 is connected to the gate of Mi,4; the drain of Mi,4 serves as the output of this stage, and the source of Mi,4 serves as the input of this stage; the input of the first stage is grounded, and the inputs of the 2nd to 8th stages are connected to the output of the previous stage in sequence; Mi,4 is used to conduct the bias current of each stage to the ground, and at the same time connects each stage to achieve voltage summation;

[0012] The collectors of Qi,1 and Qi,2 are connected to the current mirror array respectively; the base voltage of Q8,2 is output as the reference voltage.

[0013] Furthermore, in the above reference circuit, the gate of M17 is connected to the collector of Q1, the drain of M17, the drain of M16 and the gate of M16 are commonly connected to the gate of M15; the drain of M15 is connected to the base of Q2; the source of M17 is grounded, and the sources of M15 and M16 are connected to the power supply.

[0014] Furthermore, in the above reference circuit, the gate of M5 is connected to the gate of M7; and the gate of M6 is connected to the gate of M8.

[0015] The beneficial effects of the present invention and the prior art are:

[0016] (1) The present invention achieves control of the second-order temperature coefficient of the reference voltage by introducing an additional negative temperature coefficient current. The reference voltage shows an S-shaped change curve as the temperature rises, and has a small temperature drift.

[0017] (2) The present invention realizes voltage summation by cascading the emitter junctions of multiple bipolar transistors, does not require a high-performance operational amplifier, and thus has lower power consumption, while avoiding the influence of operational amplifier offset voltage and noise on the reference voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 The high-precision reference voltage generating circuit of the present invention;

[0019] Figure 2 is a curve diagram showing the variation of the second-order derivative of the reference voltage with temperature according to the present invention;

[0020] Figure 3 This is a curve diagram showing the change of the first-order derivative of the reference voltage with temperature according to the present invention;

[0021] Figure 4 This is a curve diagram of the reference voltage changing with temperature in the present invention. DETAILED DESCRIPTION

[0022] The present invention will be further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0023] like Figure 1 As shown, this embodiment provides a high-precision bandgap reference circuit with second-order temperature compensation, comprising: field-effect transistors M1-M18, Mi,1-Mi,4, bipolar transistors Q1-Q3, Qi,1-Qi,2, resistors R1-R5, and a current mirror array, wherein the value of i ranges from 1 to 8;

[0024] The drain of the field effect transistor M1 is connected to the source of the field effect transistor M2, the drain of the field effect transistor M2 is connected to the drain and gate of the field effect transistor M13, the source of the field effect transistor M13 is connected to the collector of the bipolar transistor Q1, the emitter of the bipolar transistor Q1 is connected to the ground, the drain of the field effect transistor M3 is connected to the source of the field effect transistor M4, the drain of the field effect transistor M4 is connected to the drain of the field effect transistor M14 through the resistor R1, the gate of the field effect transistor M14 is connected to the gate of the field effect transistor M13, the source of the field effect transistor M14 is connected to the collector of the bipolar transistor Q2, the emitter of the bipolar transistor Q2 is connected to the ground through the resistor R4, and the base of the bipolar transistor Q2 is connected to the base of the bipolar transistor Q1 through the resistor R3. The drain of field-effect transistor M5 is connected to the source of field-effect transistor M6, the drain of field-effect transistor M6 is connected to the current mirror array, the gates of field-effect transistors M1, M3, and M5 are connected to the drain of field-effect transistor M4, the gates of field-effect transistors M2, M4, and M6 are connected to the drain of field-effect transistor M14, the drain of field-effect transistor M15 is connected to the base of bipolar transistor Q2, the gate of field-effect transistor M15 is connected to the gate and drain of field-effect transistor M16, the drain of field-effect transistor M16 is connected to the drain of field-effect transistor M17, the source of field-effect transistor M17 is connected to ground, the gate of field-effect transistor M17 is connected to the collector of bipolar transistor Q1, and the drains of field-effect transistors M1, M3, M5, M15, and M16 are connected to a power supply.

[0025] The drain of the field effect transistor M7 is connected to the source of the field effect transistor M8, the gate of the field effect transistor M7 is connected to the gate of the field effect transistor M3, the drain of the field effect transistor M8 is connected to the collector of the bipolar transistor Q3, the gate of the field effect transistor M8 is connected to the gate of the field effect transistor M4, the emitter of the bipolar transistor Q3 is connected to the ground, the drain of the field effect transistor M9 is connected to the source of the field effect transistor M10, the drain of the field effect transistor M10 is connected to the drain of the field effect transistor M18 through the resistor R2, and the gate of the field effect transistor M18 is connected to the The collector of the bipolar transistor Q3 is connected, the source of the field effect transistor M18 is connected to the base of the bipolar transistor Q3, the source of the field effect transistor M18 is connected to the ground through the resistor R5, the drain of the field effect transistor M11 is connected to the source of the field effect transistor M12, the drain of the field effect transistor M12 is connected to the current mirror array, the gates of the field effect transistors M9 and M11 are connected to the drain of the field effect transistor M10, and the gates of the field effect transistors M10 and M12 are connected to the drain of the field effect transistor M18.

[0026] Field effect transistors Mi,1~Mi,4 and bipolar transistors Qi,1~Qi,2 form an 8-stage circuit. In the first stage circuit, the sources of field effect transistors M1,1 and M1,2 are connected to the power supply, the gate and drain of field effect transistor M1,1 are connected to the drain of field effect transistor M1,3, the source of field effect transistor M1,3 is connected to the emitter of bipolar transistor Q1,1, the gate of field effect transistor M1,2 is connected to the gate of field effect transistor M1,1, the drain of field effect transistor M1,2 is connected to the base of bipolar transistors Q1,1 and Q1,2, the collectors of bipolar transistors Q1,1 and Q1,2 are connected to the current mirror array respectively, and the collector of bipolar transistor Q1,1 is connected to The gates of field effect transistors M1,3 are connected, the collectors of bipolar transistors Q1,2 are connected to the gates of M1,4, the emitters of bipolar transistors Q1,1 are connected to the sources of field effect transistors M1,4, the emitters of bipolar transistors Q1,2 are connected to the drains of field effect transistors M1,4, the sources of field effect transistors M1,4 are the inputs of the first stage circuit, and the drains of field effect transistors M1,4 are the outputs of the first stage circuit. The circuit structures of stages 2 to 8 are the same as those of the first stage circuit and will not be described in detail here. Except for the input of the first stage circuit being connected to the ground, the inputs of all other stage circuits are connected to the outputs of the previous stage circuit. The base voltage of bipolar transistor Q8,2 is used as the reference voltage V REF Output.

[0027] Based on the traditional bandgap reference circuit, the present invention introduces an additional negative temperature coefficient current to achieve control of the second-order temperature coefficient of the reference voltage. The reference voltage shows an S-shaped change curve as the temperature rises, with a small temperature drift.

[0028] For a bipolar transistor, its emitter junction voltage V BE =V T ln(I C / I S )=(kT / q)ln(I C / I S ), where k is the Boltzmann constant, T is the absolute temperature, q is the electron charge, and I C is the transistor collector current, I S is the saturation current. Figure 1 As shown, the sum of the emitter junction voltage of the bipolar transistor Q1 and the voltage across the resistor R3 is equal to the sum of the emitter junction voltage of Q2 and the voltage across R4, that is,

[0029] V T ln(I C1 / I S1 )+I B1 R3=V T ln(I C2 / I S2 )+(I C2 +IB2 )R4

[0030] Among them I B is the transistor base current. The current mirror formed by field effect transistors M1 to M8 has a replication ratio of 1:1, the size ratio of Q2 to Q1 is a:1, and the resistance values of R3 and R4 are equal, so the positive temperature coefficient current I P for

[0031] I P =I C1 =(V T lna) / R3

[0032] By adding the voltage of Q3 emitter junction to R5, a negative temperature coefficient current I can be obtained. N for

[0033]

[0034] The current mirror converts the current I P and I N After being copied in a certain proportion, it is injected into Q 1～8,1 and Q 1～8,2 Collector, where Q 1～8,1 Collector current b 1～8 I P , Q 1～8,2 Collector current I C =I P +I N .Q 1～8,2 With Q 1～8,1 The size ratio is a:1, and the reference voltage V REF for

[0035]

[0036] Where Q = clna + V BE3 / V T , c=R5 / R3.

[0037] Let V REF The second derivative of T=(T H +T L ) / 2 is equal to zero, where T H and T L are the highest and lowest operating temperatures of the circuit respectively, we can get

[0038]

[0039] At this time V REF The second-order derivative of is approximately a linear function of temperature. H +TL ) / 2, there is a zero point, such as Figure 2 As shown; V REF The first-order derivative of is approximately a parabolic function. H +T L ) / 2, there is a maximum value, such as Figure 3 As shown. At V REF In the expression, parameter b i It is only related to the first-order term of temperature T, so adjust b i Only V REF The first derivative of moves up and down. By adjusting b i make Figure 3 When the areas of regions Ⅰ, Ⅱ, and Ⅲ are approximately equal, V REF It shows an S-shaped temperature change curve with minimal temperature drift, such as Figure 4 shown.

[0040] Although the present invention has been described in detail through the above preferred embodiments, it should be understood that the above description is not intended to limit the present invention. After reading the above description, various modifications and substitutions of the present invention will become apparent to those skilled in the art. Therefore, the scope of protection of the present invention should be defined by the appended claims.

[0041] The contents not described in detail in the specification of the present invention belong to the common knowledge of professionals in this field.

Claims

1. A high-precision bandgap reference circuit with second-order temperature compensation, characterized in that: include: A positive temperature coefficient current generation module, a negative temperature coefficient current generation module, a current mirror array and a reference voltage generation module; wherein, The positive temperature coefficient current generation module uses the positive temperature characteristic of the voltage difference between the emitter junctions of the BJT tube under different current densities to generate a positive temperature coefficient current and output it to the current mirror array; The negative temperature coefficient current generation module uses the negative temperature characteristic of the BJT tube emitter junction voltage to generate a negative temperature coefficient current and output it to the current mirror array; The reference voltage generation module uses the positive temperature coefficient current and negative temperature coefficient current output by the current mirror array to bias the BJT tube so that the emitter junction voltages of each BJT tube compensate each other and generate a reference voltage.

2. The bandgap reference circuit according to claim 1, wherein: The positive temperature coefficient current generation module includes MOS transistors M1-M6, M13-M17, BJT transistors Q1-Q2, and resistors R1, R3-R4, wherein the drain of M1 is connected to the source of M2, the drain of M3 is connected to the source of M4, and the drain of M5 is connected to the source of M6; the gates of M2, M4, and M6 are commonly connected to the drain of M14, the gates of M1, M3, and M5 are commonly connected to the drain of M4, and R1 is connected across the drain of M4 and the drain of M14; the drain of M2, the drain of M13, and the gate of M13 are commonly connected to the gate of M14; the source of M13 is connected to the collector of Q1, the source of M14 is connected to the collector of Q2, and the base of Q1 is connected to the base of Q2 via R3; the drain of M6 is connected to the current mirror array; the emitter of Q1 is grounded, the emitter of Q2 is grounded via R4, and the sources of M1, M3, and M5 are connected to a power supply.

3. The bandgap reference circuit according to claim 1, wherein: The negative temperature coefficient current generation module includes MOS tubes M7-M12, M18, BJT tube Q3, and resistors R2 and R5. Among them, the drain of M7 is connected to the source of M8, the drain of M9 is connected to the source of M10, and the drain of M11 is connected to the source of M12; the gates of M9 and M11 are commonly linked to the drain of M10, the gates of M10 and M12 are commonly connected to the drain of M18, and R2 is connected across the drain of M10 and M18; the drain of M8 and the gate of M18 are commonly connected to the collector of Q3, and the source of M18 is connected to the base of Q3; the drain of M12 is connected to the current mirror array; the emitter of Q3 is grounded, the source of M18 is grounded through R5, and the sources of M7, M9, and M11 are connected to a power supply.

4. The bandgap reference circuit according to claim 1, wherein: The reference voltage generation module includes a multi-stage cascade circuit, each stage of the cascade circuit includes MOS transistors Mi,1-Mi,4 and BJT transistors Qi,1-Qi,2, where i=1-8; The gate of Mi,1, the drain of Mi,1 and the gate of Mi,2 are connected to the drain of Mi,3, and the source of Mi,3 is connected to the source of Mi,4; the gate of Mi,3 is connected to the collector of Qi,1; the drain of Mi,2 is connected to the base of Qi,1 and Qi,2 to provide base current for them; the sources of Mi,1 and Mi,2 are connected to the power supply; The emitter of Qi,1 is connected to the source of Mi,4, the emitter of Qi,2 is connected to the drain of Mi,4, and the collector of Qi,2 is connected to the gate of Mi,4; Mi,4 drain is used as the output terminal of this stage, and Mi,4 source is used as the input terminal of this stage; the input terminal of the first stage is grounded, and the input terminals of the 2nd to 8th stages are connected to the output terminals of the previous stages in sequence; Mi,4 is used to conduct the bias current of each stage to the ground, and at the same time connects each stage to realize voltage summation; The collectors of Qi,1 and Qi,2 are connected to the current mirror array respectively; the base voltage of Q8,2 is output as the reference voltage.

5. The bandgap reference circuit according to claim 1, wherein: The gate of M17 is connected to the collector of Q1, and the drain of M17, the drain of M16 and the gate of M16 are connected to the gate of M15; the drain of M15 is connected to the base of Q2; the source of M17 is grounded, and the sources of M15 and M16 are connected to the power supply.

6. The bandgap reference circuit according to claim 1, wherein: The gate of M5 is connected to the gate of M7; the gate of M6 is connected to the gate of M8.

Images