Digital circuit for chip power-on detection

Abstract

The invention provides a digital circuit for chip power-on detection, the circuit comprises a fast counter, a clock frequency dividing circuit, a slow counter and a comparator, the counting bit width of the slow counter is marked as X, and the counting bit width of the fast counter is greater than X; the comparator is used for comparing a high X-bit value of the fast counter with a value of the slow counter when the slow counter counts to certain verification values; and if the value of the high X bit of the fast counter is equal to the value of the slow counter at all the verification values, it is considered that power-on is completed. The circuit can accurately judge whether the voltage reaches the voltage level at which the chip can work stably when the chip is powered on, can assist in prolonging reset, and ensures that the chip enters a normal working state when the reset is released.

Description

Technical Field

[0001] The present invention relates to the field of chips, and in particular to a digital circuit for on-chip electrical detection. Background Art

[0002] When the chip is powered on, the reset circuit generates a power-on reset signal, initializing the chip's internal circuits to a preset state. External chip reset refers to the process of restoring the chip's internal circuit state to its initial set value using an external input signal when the chip requires initialization. This reset mechanism, triggered by external circuitry or user operation, offers strong controllability and fast response speed. In practical applications, it's often used for chip debugging, fault recovery, power-on initialization, and in systems where multiple chips work together, achieving synchronized reset of each chip to ensure the orderly operation of the entire system.

[0003] However, the voltage is unstable during chip power-up. When the external reset is released, the power supply voltage may not yet have reached a stable operating voltage level for the chip. In this case, the chip's internal circuits cannot function properly, and the chip's initialization process is likely to fail, leading to chip malfunction or, in severe cases, even damage, posing a significant challenge to system stability and reliability. Summary of the Invention

[0004] In order to prevent the reset from being released when the chip voltage is low when the chip is powered on, the present invention provides a digital circuit for chip power-on detection, the digital circuit comprising:

[0005] A fast counter for counting according to an external input clock signal;

[0006] A clock frequency dividing circuit, used for dividing the frequency of the externally input clock signal;

[0007] A slow counter, configured to count according to the divided clock signal; the counting bit width of the slow counter is denoted as X, and the counting bit width of the fast counter is greater than X;

[0008] The comparator is used to compare the value of the high X bits of the fast counter with the value of the slow counter when the slow counter counts to a certain test value;

[0009] If the value of the high X bit of the fast counter is not equal to the value of the slow counter at the calibration value, it is considered that the power-on is not complete and the voltage has not reached the normal working threshold;

[0010] If the high X bits of the fast counter are equal to the slow counter values at all test values, it is considered that power-on is complete and the voltage has reached a level at which the chip can operate stably.

[0011] In some embodiments, the external input clock signal is an RC oscillator clock signal.

[0012] In some embodiments, the clock frequency dividing circuit is a traveling wave clock frequency dividing circuit.

[0013] In some more specific embodiments, the ripple clock frequency division circuit includes three cascaded D flip-flops, with the output signal of the third D flip-flop serving as the clock input of the slow counter. The counting bit width X of the slow counter is 9, and the counting bit width of the fast counter is 12. The calibration values include: 0x0FF, 0x100, and 0x1FF.

[0014] In some embodiments, the clock frequency dividing circuit is further configured to convert an external input signal into a comparator clock signal.

[0015] In some embodiments, after comparing the value of the high X bits of the fast counter with the value of the slow counter:

[0016] If the high X bits of the fast counter are equal to the slow counter at all test values, the comparator outputs a comparison success signal to the chip, which serves as the reset source inside the chip and controls the circuit inside the chip to cancel the reset. If the high X bits of the fast counter are not equal to the slow counter, the comparator outputs a comparison failure signal, which serves as the reset signal for the two counters and controls the counters to reset and count again.

[0017] The digital circuit for on-chip power-on detection provided by the present invention accurately determines whether the power supply voltage has reached the voltage level required for stable chip operation by comparing the values of two counters: a fast counter and a slow counter. It also assists in extending the reset period, ensuring that the chip is fully operational when the reset is released. The digital circuit has a simple structure and strong compatibility, allowing direct porting across different process technologies and integration into digital reset circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 A digital circuit for on-chip electrical detection provided by the present invention is shown;

[0020] Figure 2 A clock frequency division circuit provided by the present invention;

[0021] Figure 3FIG. 1 is a schematic diagram of bits compared by a comparator in an embodiment of the present invention. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings.

[0023] The present invention provides a chip power-on detection circuit for preventing the reset from being released when the chip is powered on due to unstable voltage. When the reset of the chip's external pin is released, the circuit activates and detects the voltage. The circuit only releases the chip's internal reset when it determines that the voltage has reached a level at which the chip can operate stably.

[0024] The present invention performs power-on detection based on whether the components in the detection circuit are functioning properly. All components in the detection circuit provided by the present invention operate at the power supply voltage (i.e., the voltage to be detected), and the circuit's operating voltage is consistent with the chip's normal operating voltage. When all components in the circuit are functioning properly, the voltage is considered to have reached a level at which the chip can operate stably.

[0025] Figure 1 The present invention provides a circuit diagram of a digital circuit for on-chip power detection. The circuit includes: a fast counter cnt_f, a slow counter cnt_s, a clock frequency division circuit clk_div, and a comparator cmp. Figure 1 , introduces the various components in the circuit, their main functions and connection methods.

[0026] The fast counter cnt_f is used to count according to the external clock signal rc_osc_clk. The clock input of the fast counter cnt_f is connected to the external clock signal, and the reset input is connected to the output signal of the comparator and the external power-on reset signal por_rstn through an AND gate.

[0027] Exemplarily, the fast counter cnt_f may be a synchronous binary fast counter. Figure 1The counting bit width of a medium-sized fast counter is 12. A synchronous binary fast counter consists of 12 D flip-flops, each corresponding to a binary digit. The D flip-flops are arranged sequentially from low to high. The clock input CLK of all D flip-flops is connected to the external clock signal. The D terminal of the higher-order D flip-flop is connected to the Q output of the lower-order D flip-flop via a logic gate circuit. When the falling edge of the clock signal arrives, all D flip-flops in the counter simultaneously update their outputs based on the current state of the counter. Specifically, the D input of the higher-order D flip-flop is the result of the AND gate connection of the Q outputs of all the lower-order D flip-flops below it. Only when the Q outputs of all the lower-order D flip-flops below it are all 1 will the D value of the higher-order D flip-flop be 1. Only then will the higher-order D flip-flop change from 0 to 1 on the falling edge of the clock, generating a carry. Therefore, a synchronous fast counter simultaneously flips the flip-flops that need to flip on each valid edge of the clock signal, thereby increasing counting speed. However, its counting process relies on complex logic gate circuits, and voltage instability significantly affects counting delays, causing counting confusion.

[0028] The external input clock signal is generated by an external clock source, which can be a main clock source for sending clock signals to the entire chip, or a local clock source. In terms of type, the clock source can be an RC oscillator, an LC oscillator, a crystal oscillator, etc. For example, Figure 1 The RC oscillator clock rc_osc_clk generated by the RC oscillator is used as the external input clock signal.

[0029] The slow counter cnt_s is used to count according to the slow clock signal obtained after frequency division. Figure 1 The counting bit width of the medium slow counter is 9. The clock signal input of the slow counter cnt_s is connected to the output of the clock frequency divider circuit, and the reset input of the slow counter cnt_s is consistent with the reset input of the fast counter.

[0030] Exemplarily, the slow counter can be an asynchronous binary slow counter. The asynchronous binary slow counter consists of nine JK flip-flops, each representing a corresponding digit of a binary number. The JK flip-flops are arranged from the lowest digit to the highest digit, with both the J and K terminals of the JK flip-flops connected to 1, implementing a counting function based on falling clock edge flipping. For the lowest-order JK flip-flop, its clock input CLK is connected to the slow clock signal obtained after frequency division. For the highest-order JK flip-flop, its clock input CLK is connected to the output Q of the next-lowest-order JK flip-flop. The counting logic is as follows: when the falling edge of the slow clock signal arrives, the lowest-order JK flip-flop flips, and output Q changes from 0 to 1. When the rising edge of the slow clock signal arrives again, the lowest-order JK flip-flop flips, and output Q changes from 1 to 0. At this time, because the clock input CLK of the next-lowest-order JK flip-flop is connected to the output of the lowest-order JK flip-flop, a falling edge is generated on the clock input CLK of the next-lowest-order JK flip-flop, causing the state of the next-lowest-order JK flip-flop to flip, thereby implementing a carry. As can be seen, the asynchronous slow counter uses the output of the low-order flip-flop as the clock pulse input for the adjacent high-order flip-flop, implementing counting according to the "carry one every two" principle. The flip-flop of the high-order flip-flop depends on the carry signal of the low-order flip-flop, which causes a certain delay. However, the slow counter does not rely on complex logic gate circuits to count, and voltage instability has minimal impact on counting delay.

[0031] The clock divider circuit clk_div is used to divide the external input clock signal rc_osc_clk into a slow clock signal clk_cnt_s and a comparator clock signal clk_cmp. The reset terminal of the clock divider circuit is connected to the external reset signal por_rstn.

[0032] The clock frequency division circuit here can be used as Figure 2 The traveling wave clock frequency division circuit shown in the figure includes three cascaded D flip-flops. The D terminal of each D flip-flop is connected to its own output terminal QN. The external input clock signal rc_osc_clk is input from the clock input terminal CLK of the first D flip-flop. The clock input terminal CLK of the subsequent D flip-flop is connected to the output terminal QN of the previous D flip-flop, thereby achieving clock signal frequency division. Figure 2 In the embodiment, the signal at the output terminal QN of the second D flip-flop is used as the comparator clock signal clk_cmp, and the signal at the output terminal QN of the third D flip-flop is used as the slow clock signal clk_cnt_s.

[0033] The comparator cmp is used to compare the high bit of the fast counter with the count value of the slow counter when the slow counter counts to certain calibration values. For example, the calibration values can be set to 0x0FF, 0x100, and 0x1FF.

[0034] The comparison process of the comparator is described in detail below. Figure 1 In the power-on detection circuit shown in FIG, the counting bit width of the slow counter is 9, and the maximum counting value is 0x1FF; the counting bit width of the fast counter is 12, and the maximum counting value is 0xFFF; the bits compared by the comparator are as follows Figure 3 As shown in the figure, when the slow counter counts to 0x0FF, 0x100, and 0x1FF, the comparator compares the high-order 9-bit value of the fast counter with all the bits of the slow counter. If the high-order 9-bit value of the fast counter matches the slow counter value in each of the three comparisons, the comparison is considered successful; otherwise, the comparison is considered unsuccessful. This can be achieved by using three comparators to perform three comparisons, each with the comparison results serving as the inputs to an AND gate, and the AND gate output serving as the comparison result for the entire comparator.

[0035] The verification value can be set according to the bit width of the counter. To ensure the accuracy of the detection, there should be multiple verification values, and the comparison can only be considered successful if all the bits compared by the comparator are equal at all verification values.

[0036] The comparator's two inputs are connected to the fast counter and the slow counter, respectively. The comparator's reset terminal is connected to the external reset signal por_rstn. The comparator has two output terminals, both of which are low when the comparison is not completed. One output terminal is connected to the chip internally. After a successful comparison, its output signal goes high, outputting the comparison success signal cmp_done. This signal serves as the internal reset source of the chip and controls the internal reset of the chip. The other output terminal goes high when the comparison is unsuccessful, serving as the count reset signal cnt_rstn. Together with the external power-on reset signal por_rstn, it is connected to the reset input terminals of the two counters through an AND gate, controlling the reset of the two counters after a comparison failure.

[0037] The following combination Figure 1 , the working process of the circuit is introduced in detail.

[0038] When the chip's external reset is released, the power-on reset signal por_rstn goes high, and the circuit begins operating. The fast counter cnt_f counts based on the external clock signal rc_osc_clk. The clock divider circuit clk_div divides the external clock signal rc_osc_clk, and the divided signal is input as the clock signal clk_cnt_s to the slow counter. The slow counter cnt_s counts based on this slow clock signal clk_cnt_s. When the slow counter counts to 0x0FF, 0x100, and 0x1FF, the comparator clk_cmp compares the high-order 9 bits of the fast counter with all the bits of the slow counter. If the high-order 9 bits of the fast counter match the slow counter value in each of the three comparisons, the comparison is considered successful, the counter is operating normally, and the voltage has reached a stable operating voltage level for the chip, and the chip reset can be released. Otherwise, the comparison is considered unsuccessful.

[0039] If the comparison is successful, the comparator outputs a comparison success signal, which serves as the reset source inside the chip to control the chip to cancel the reset and enter the working state.

[0040] If the comparison is unsuccessful, the output terminal of the comparator connected to the reset input of the counter controls the count reset signal cnt_rstn to become valid; when the count reset signal cnt_rstn and the external power-on reset signal por_rstn are valid at the same time, the two counters will reset the count, and then count and compare again after reset until the comparison is successful.

[0041] The detection principle of this circuit is:

[0042] The signal propagation delay of logic gates in digital circuits is related to the power supply voltage. Unstable or insufficient voltage can change the operating characteristics of the logic gate's internal transistors, causing changes in the signal propagation speed in the logic gate and causing transmission delay in the counter.

[0043] Asynchronous slow counters don't rely on complex logic gates for counting, and their internal combinational logic is shallow, so voltage instability has a relatively small impact on the slow counter's counting delay. In contrast, synchronous fast counters rely on complex logic gates and deep internal combinational logic, so voltage instability has a greater impact on counting delay and can cause counting confusion. By comparing the values of the two counters, it's possible to accurately determine whether a stable voltage has been reached. This circuit performs multiple checks, and only outputs a success signal if each check is correct. This helps delay the reset, ensuring that the reset is not released until the voltage reaches stability. The circuit's operating voltage matches the chip's internal circuitry. If the voltage falls below the normal operating voltage, the circuit outputs a comparison failure signal, ensuring that the reset is not released when the voltage falls below the chip's normal operating voltage.

[0044] It can be seen that the digital circuit for on-chip electrical detection provided by the present invention has the following beneficial effects:

[0045] 1. It is realized through digital circuits, has strong compatibility, can be directly transplanted under different processes, and can also be directly integrated into digital reset circuits.

[0046] 2. Simple structure, no need for complex voltage detection circuit and delay circuit.

[0047] 3. By comparing the values of the fast and slow counters, it is possible to accurately determine whether the voltage has reached the voltage level at which the chip can operate stably.

[0048] 4. The circuit passes multiple checks, and each check is correct before it outputs a success signal. This can help delay the reset and ensure that the chip can work normally when the reset is released.

[0049] In the description of the embodiments of the present application, words such as "exemplary," "for example," or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary," "for example," or "for example" in the embodiments of the present application should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary," "for example," or "for example" is intended to present the relevant concepts in a concrete manner.

[0050] In the description of the embodiments of this application, the term "and / or" is merely a description of an association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B can represent the following three situations: A exists alone, B exists alone, and A and B exist at the same time. In addition, unless otherwise specified, the term "plurality" means two or more.

[0051] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly identifying the technical features being referred to. Thus, features specified as "first" or "second" may explicitly or implicitly include one or more of such features. The terms "include," "comprising," "having," and their variations all mean "including but not limited to," unless otherwise specifically emphasized.

[0052] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent replacements, improvements, etc. made on the basis of the technical solution of the present invention should be included in the scope of protection of the present invention.

Claims

1. A digital circuit for on-chip electrical detection, characterized in that: include: A fast counter for counting according to an external input clock signal; A clock frequency dividing circuit, used for dividing the frequency of the externally input clock signal; A slow counter, configured to count according to the divided clock signal; the counting bit width of the slow counter is denoted as X, and the counting bit width of the fast counter is greater than X; The comparator is used to compare the value of the high X bits of the fast counter with the value of the slow counter when the slow counter counts to a certain test value; If the value of the high X bit of the fast counter is not equal to the value of the slow counter at the calibration value, it is considered that the power-on is not complete and the voltage has not reached the normal working threshold; If the high X bits of the fast counter are equal to the slow counter values at all test values, it is considered that power-on is complete and the voltage has reached a level at which the chip can operate stably.

2. The digital circuit according to claim 1, wherein: The external input clock signal is an RC oscillator clock signal.

3. The digital circuit according to claim 1, wherein: The clock frequency dividing circuit is a traveling wave clock frequency dividing circuit.

4. The digital circuit according to claim 3, wherein: The traveling wave clock frequency dividing circuit includes three cascaded D flip-flops, and the signal output by the third D flip-flop is used as the clock input of the slow counter.

5. The digital circuit according to claim 4, characterized in that The counting bit width X of the slow counter is 9, and the counting bit width X of the fast counter is 12.

6. The digital circuit according to claim 5, characterized in that The verification values include: 0x0FF, 0x100, and 0x1FF.

7. The digital circuit according to claim 1, wherein: If the high X bits of the fast counter are equal to the slow counter values at all test values, the comparator outputs a comparison success signal to the chip, which serves as the reset source inside the chip and controls the circuit inside the chip to cancel the reset.

8. The digital circuit according to claim 1, wherein: If the value of the high X bit of the fast counter is not equal to the value of the slow counter, the comparator outputs a comparison failure signal, which serves as the reset signal of the fast counter and the slow counter, controlling the counter to reset and recount.

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