Bandgap reference circuit

Abstract

The band-gap reference circuit comprises first, second and third current sources, first and second amplifiers, a temperature coefficient adjusting unit and a resistor. The first current source, the second current source and the third current source each comprise two spliced PMOS transistors and are used for reducing the voltage applied to each PMOS transistor when receiving the high supply voltage. The first amplifier controls the PMOS transistors in the first current source and the second current source so as to ensure that the PMOS transistors have enough margin when receiving low power supply voltage. The second amplifier provides a gain boosting loop to prevent mismatching of PMOS transistors in the first current source, the second current source and the third current source. The temperature coefficient adjusting unit introduces a positive temperature coefficient and a negative temperature coefficient into current generated by the first current source and the second current source, and the resistor generates reference voltage according to current copied by the third current source.

Description

Technical Field

[0001] The present disclosure relates to a bandgap reference circuit, and more particularly to a bandgap reference circuit capable of operating over a wide voltage range. Background Art

[0002] A bandgap reference circuit is a voltage reference circuit that provides a stable and accurate reference voltage for use in various electronic systems. It is designed to produce a constant output voltage that is relatively unaffected by changes in temperature, supply voltage, and other environmental factors.

[0003] One of the main challenges facing bandgap reference circuits is achieving high accuracy and stability over a wide range of operating conditions. For example, a bandgap reference circuit may need to be able to operate at a supply voltage ranging from 1.5V to 0.9V to meet the requirements of various applications. However, in order for the bandgap reference circuit to operate at a higher voltage (such as 1.5V), additional protection measures may be required to ensure that the core components of the bandgap reference circuit remain in the safe operating area (SOA). However, these protection measures may cause the bandgap reference circuit to not operate properly at low voltages (such as 0.9V). Therefore, designing a bandgap reference circuit that can support different voltage ranges and output a stable reference voltage has become an urgent problem to be solved.

[0004] This prior art section provides background information only. Statements in this prior art section are not an admission that the subject matter disclosed in this section constitutes prior art to the present disclosure, and no part of this prior art section shall be construed as an admission that any part of this application (including this prior art section) constitutes prior art to the present disclosure. Summary of the Invention

[0005] One aspect of the present disclosure provides a bandgap reference circuit for generating a reference voltage and outputting the reference voltage via an output node. The bandgap reference circuit includes a first current source, a second current source, a third current source, a first amplifier, a second amplifier, a resistor, and a temperature coefficient adjustment unit. The first current source outputs a first current flowing through a first node and includes a first P-type metal-oxide-semiconductor (PMOS) transistor and a second PMOS transistor connected in a cascaded manner between a power supply voltage terminal and the first node. The second current source outputs a second current flowing through a second node and includes a third PMOS transistor and a fourth PMOS transistor connected in a cascaded manner between the power supply voltage terminal and the second node. The third current source outputs a third current flowing through the output node and includes a fifth PMOS transistor and a sixth PMOS transistor connected in a cascaded manner between the power supply voltage terminal and the output node. The first amplifier has a first input terminal coupled to the first node, a second input terminal coupled to the second node, and an output terminal coupled to the control terminal of the first PMOS transistor and the control terminal of the third PMOS transistor. The second amplifier has a first input terminal coupled to a third node connecting the fifth PMOS transistor and the sixth PMOS transistor, a second input terminal coupled to a fourth node connecting the first PMOS transistor and the second PMOS transistor, and an output terminal coupled to the control terminal of the sixth PMOS transistor. A resistor is coupled to the output node and is configured to receive a third current. The temperature coefficient adjustment unit includes a first bipolar junction transistor (BJT) configured to receive the first current and a second BJT configured to receive the second current. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] A more complete understanding of the present disclosure can be obtained by referring to the detailed description and claims in conjunction with the accompanying drawings, in which like reference numerals in different drawings refer to like elements.

[0007] Figure 1 FIG2 shows a bandgap reference circuit according to a comparative example of the present disclosure.

[0008] Figure 2 A bandgap reference circuit according to an embodiment of the present disclosure is shown.

[0009] Figure 3 A bandgap reference circuit according to another embodiment of the present disclosure is shown.

[0010] Figure 4 A bandgap reference circuit according to another embodiment of the present disclosure is shown.

[0011] Figure 5 An amplifier according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0012] This application claims priority to and the benefit of U.S. regular application No. 63 / 554,164, filed on February 16, 2024, the contents of which are incorporated herein by reference in their entirety.

[0013] Figure 1 A bandgap reference circuit 100 according to a comparative example of the present disclosure is shown, and includes P-type metal oxide semiconductor (PMOS) transistors P1A, P2A, and P3A, an amplifier 110, resistors R1A, R2A, R3A, and R4A, and bipolar junction transistors (BJTs) B1A and B2A.

[0014] PMOS transistor P1A includes a first terminal coupled to a power supply voltage terminal to receive power supply voltage VDD, a second terminal, and a control terminal. PMOS transistor P2A includes a first terminal coupled to a power supply voltage terminal to receive power supply voltage VDD, a second terminal, and a control terminal coupled to the control terminal of PMOS transistor P1A. PMOS transistor P3A includes a first terminal coupled to a power supply voltage terminal to receive power supply voltage VDD, a second terminal, and a control terminal coupled to the control terminal of PMOS transistor P1A.

[0015] The amplifier 110 has a first input terminal coupled to the second terminal of the PMOS transistor P1A, a second input terminal coupled to the second terminal of the PMOS transistor P2A, and an output terminal coupled to the control terminal of the PMOS transistor P1A and the control terminal of the PMOS transistor P2A.

[0016] BJT B1A has an emitter coupled to the second terminal of PMOS transistor P1A, a collector coupled to ground, and a base coupled to the collector of BJT B1A. BJT B2A has an emitter, a collector coupled to ground, and a base coupled to the collector of BJT B2A.

[0017] Resistor R1A has a first end coupled to the second end of PMOS transistor P1A and a second end coupled to ground. Resistor R2A has a first end coupled to the second end of PMOS transistor P2A and a second end coupled to the emitter of BJT B2A. Resistor R3A has a first end coupled to the second end of PMOS transistor P2A and a second end coupled to ground. Resistor R4A has a first end coupled to the second end of PMOS transistor P3A and a second end coupled to ground.

[0018] The bandgap reference circuit 100 can output a reference voltage VBGR through the second terminal of the PMOS transistor P3A. The reference voltage VBGR can be expressed as I3·R4A, where I3 is the current conducted by the PMOS transistor P3A and flowing through the resistor R4A.

[0019] Furthermore, since PMOS transistors P1A, P2A, and P3A can be connected to form a current mirror, the current I3 conducted by transistor P3A should be equal to the current I1 conducted by transistor P1A and the current I2 conducted by transistor P2A (when PMOS transistors P1A, P2A, and P3A have the same width-to-length ratio). Furthermore, current I1 is equal to the sum of current I1A flowing through resistor R1A and current I1B flowing through BJT B1A. Current I1A is proportional to the base-emitter voltage VBE of BJT B1A and has a negative temperature coefficient, while current I1B is proportional to the absolute temperature and has a positive temperature coefficient. Therefore, by properly selecting resistor R1A, current I1 can be made substantially unaffected by temperature variations, and thus, the reference voltage VBGR provided by bandgap reference circuit 100 can be made unaffected by temperature variations.

[0020] However, as the temperature increases, the voltage VC at the second terminal of the PMOS transistor P3A may become different from the voltage VA at the second terminal of the PMOS transistor P1A and the voltage VB at the second terminal of the PMOS transistor P2A. In other words, as the temperature increases, mismatch may occur between the PMOS transistors P1A, P2A, and P3A. This problem may become more severe when the bandgap reference circuit 100 operates at a low power supply voltage. For example, in some cases, the bandgap reference circuit 100 may be configured to provide a reference voltage VBGR below 1V, while the power supply voltage VDD may range from 0.9V to 1.5V. In this case, when the power supply voltage VDD is approximately 0.9V, the mismatch may become more significant and unacceptable.

[0021] Furthermore, when the bandgap reference circuit 100 operates at a high power supply voltage (e.g., 1.5V), the PMOS transistors P1A, P2A, and P3A may need to withstand a higher voltage. Therefore, the PMOS transistors P1A, P2A, and P3A may not be suitable for manufacturing using advanced processes that require thin gate oxides, hindering the application of advanced processes.

[0022] Figure 2 A bandgap reference circuit 200 according to an embodiment of the present disclosure is shown, comprising current sources 210 , 220 , and 230 , amplifiers 240 , 250 , a temperature coefficient adjustment unit 260 , and a resistor R1B.

[0023] Current source 210 generates an output current I1 flowing through node N1. Current source 210 includes PMOS transistors P1B and P2B, which are connected in cascade between a power supply voltage terminal and node N1. Current source 220 generates an output current I2 flowing through node N2. Current source 220 includes PMOS transistors P3B and P4B, which are connected in cascade between a power supply voltage terminal and node N2. Current source 230 generates an output current I3 flowing through node NO1 (i.e., the output node of bandgap reference circuit 200). Current source 230 includes PMOS transistors P5B and P6B, which are connected in cascade between a power supply voltage terminal and node NO1. In some embodiments, when the power supply voltage VDD is relatively high, the stacked structure of the current sources 210 , 220 , and 230 helps reduce the voltage applied to each PMOS transistor, thereby enabling the use of advanced process nodes with thin gate oxide devices and ensuring that the PMOS transistors P1B, P2B, P3B, P4B, P5B, and P6B ​​can operate in an SOA.

[0024] like Figure 2 As shown, PMOS transistor P1B has a first terminal coupled to the power supply voltage terminal to receive the power supply voltage VDD, a second terminal, and a control terminal. PMOS transistor P2B has a first terminal coupled to the second terminal of PMOS transistor P1B, a second terminal coupled to node N1, and a control terminal. PMOS transistor P3B has a first terminal coupled to the power supply voltage terminal to receive the power supply voltage VDD, a second terminal, and a control terminal. PMOS transistor P4B has a first terminal coupled to the second terminal of PMOS transistor P3B, a second terminal coupled to node N2, and a control terminal. PMOS transistor P5B has a first terminal coupled to the power supply voltage terminal to receive the power supply voltage VDD, a second terminal, and a control terminal. PMOS transistor P6B has a first terminal coupled to the second terminal of PMOS transistor P5B, a second terminal coupled to node N3, and a control terminal.

[0025] Amplifier 240 has a first input terminal coupled to node N1, a second input terminal coupled to node N2, and an output terminal coupled to the control terminal of PMOS transistor P1B and the control terminal of third PMOS transistor P3B. In some embodiments, the first input terminal of amplifier 240 is a negative input terminal, and the second input terminal of amplifier 240 is a positive input terminal. However, the present disclosure is not limited to this. The output of amplifier 240 can be used to control current sources 210 and 220 to equalize the voltages at nodes N1 and N2.

[0026] In this embodiment, the bandgap reference circuit 200 may further include a capacitor C1B having a first terminal coupled to the power supply voltage terminal and a second terminal coupled to the output terminal of the amplifier 240. The capacitor C1B may help stabilize the output of the amplifier 240. However, the present disclosure is not limited thereto. In some embodiments, the capacitor C1B may be omitted.

[0027] Amplifier 250 has a first input terminal coupled to node N3, a second input terminal coupled to node N4, and an output terminal coupled to the control terminal of PMOS transistor P6B. Node N3 is connected to PMOS transistors P5B and P6B, and node N4 is connected to PMOS transistors P1B and P2B. In some embodiments, the first input terminal of amplifier 250 is a negative input terminal, and the second input terminal of amplifier 250 is a positive input terminal. However, the present disclosure is not limited thereto. In some embodiments, the second input terminal of amplifier 250 may instead be coupled to another node connected to PMOS transistors P3B and P4B.

[0028] In this embodiment, amplifier 250 functions as a source follower and maintains the voltage at node N3 (connected to the second terminal of PMOS transistor P5B and the first terminal of PMOS transistor P6B) equal to the voltage at node N4 (connected to the second terminal of PMOS transistor P1B and the first terminal of PMOS transistor P2B). Consequently, the drain-source voltages of PMOS transistors P1B, P3B, and P5B are the same, and PMOS transistors P1B, P3B, and P5B can operate under the same conditions regardless of temperature variations, significantly reducing mismatching. Furthermore, the gain boost provided by amplifier 250 also helps increase output resistance, thereby improving the performance of bandgap reference circuit 200.

[0029] Temperature coefficient adjustment unit 260 includes BJTs B1B and B2B. BJT B1B receives at least a portion of current I1 generated by current source 210, and BJT B2B receives at least a portion of current I2 generated by current source 220. BJT B1B has an emitter coupled to node N1 to receive at least a portion of current I1, a collector coupled to ground, and a base coupled to ground. In this embodiment, temperature coefficient adjustment unit 260 further includes a resistor R2B. Resistor R2B has a first terminal coupled to first node N1 and a second terminal coupled to ground.

[0030] BJT B2B has an emitter for receiving at least a portion of current I2, a collector coupled to ground, and a base coupled to ground. Furthermore, temperature coefficient adjustment unit 260 further includes resistors R3B and R4B. Resistor R3B has a first terminal coupled to node N2 and a second terminal coupled to the emitter of BJT B2B. Resistor R4B has a first terminal coupled to node N2 and a second terminal coupled to ground.

[0031] By appropriately selecting resistors R2B, R3B, and R4B, temperature coefficient adjustment unit 260 can adjust the temperature coefficients of currents I1 and I2 to reduce the effects of temperature variations. Because current sources 210, 220, and 230 can be connected to form a current mirror, currents I1 and I2 can be mirrored to generate current I3. Resistor R1B can receive current I3 to generate reference voltage VBGR. In this embodiment, resistor R1B has a first terminal coupled to node NO1 and a second terminal coupled to ground. In this case, reference voltage VBGR can be output via node NO1.

[0032] Furthermore, in this embodiment, bandgap reference circuit 200 may further include capacitor C2B. Capacitor C2B has a first terminal coupled to node NO1 and a second terminal coupled to ground. Capacitor C2B may be used to stabilize the output of reference voltage VBGR. However, the present disclosure is not limited thereto. In some embodiments, capacitor C2B may be omitted.

[0033] In this embodiment, the temperature coefficient adjustment unit 260 may include resistors R2B, R3B, and R4B to adjust the temperature coefficient. However, the present disclosure is not limited thereto. In some embodiments, certain resistors may be omitted or other resistors may be added.

[0034] Figure 3 A bandgap reference circuit 300 according to an embodiment of the present disclosure is shown. The difference between the bandgap reference circuit 300 and the bandgap reference circuit 200 is that the temperature coefficient adjustment unit 360 of the bandgap reference circuit 300 omits the resistor R2B.

[0035] Figure 4 FIG4 illustrates a bandgap reference circuit 400 according to an embodiment of the present disclosure. Bandgap reference circuit 400 differs from bandgap reference circuit 300 in that temperature coefficient adjustment unit 460 of bandgap reference circuit 400 further includes resistor R5B. Resistor R5B has a first end coupled to the second end of PMOS transistor P4B and the second input end of amplifier 250, and a second end coupled to the first end of resistor R3B and the first end of resistor R4B.

[0036] In the bandgap reference circuits 200, 300, and 400, when receiving a high power supply voltage VDD (e.g., 1.5V), the stacked structure of current sources 210, 220, and 230 can distribute the high voltage experienced by the PMOS transistors therein, thereby allowing the PMOS transistors P1B, P2B, P3B, P4B, P5B, and P6B ​​to operate within their SOA. However, when receiving a low power supply voltage VDD (e.g., 0.9V), the PMOS transistors P2B and P4B require appropriate bias voltages to provide sufficient voltage margin for the PMOS transistors P1B and P3B to operate normally.

[0037] In some embodiments, the control terminal of PMOS transistor P2B and the control terminal of PMOS transistor P4B can receive the same bias voltage VBP. In some embodiments, bias voltage VBP can be substantially equal to VDD-2Vt, where VDD is the power supply voltage and Vt is the threshold voltage of PMOS transistor P1B. In this case, when power supply voltage VDD is high (e.g., greater than a threshold voltage of 1.2V or 1.5V), PMOS transistors P1B, P2B, P3B, and P4B can operate in saturation mode. Furthermore, when power supply voltage VDD is low (e.g., less than a threshold voltage of 0.9V), PMOS transistors P2B and P4B can be fully turned on and operate in linear mode, thereby facilitating the operation of PMOS transistors P1B and P3B.

[0038] In some embodiments, the bandgap reference circuits 200, 300, and 400 may further include a voltage generator specifically for providing a bias voltage VBP for the PMOS transistors P2B and P4B. However, the present disclosure is not limited thereto. In some embodiments, the bias voltage VBP used to control the PMOS transistors P2B and P4B may be the same as the bias voltage used by the amplifier 240. In other words, the bias voltage VBP used by the amplifier 240 may also be used to control the PMOS transistors P2B and P4B.

[0039] Figure 5 An amplifier 240 according to an embodiment of the present disclosure is shown. In this embodiment, the amplifier 240 is a folded amplifier including NMOS transistors N1B, N2B, and N3B, PMOS transistors P7B, P8B, P9B, and P10B, and load units 242 and 244.

[0040] The NMOS transistor N1B has a first terminal, a second terminal, and a control terminal coupled to the first input terminal of the amplifier 240, that is, coupled to the node N1 of the bandgap reference circuit 200, 300, or 400. The second NMOS transistor N2B has a first terminal, a second terminal, and a control terminal coupled to the second input terminal of the amplifier 240, that is, coupled to the node N2 of the bandgap reference circuit 200, 300, or 400. The NMOS transistor N3B has a first terminal coupled to the second terminal of the NMOS transistor N1B and the second terminal of the NMOS transistor N2B, a second terminal coupled to the ground terminal, and a control terminal for receiving the bias voltage VBN1.

[0041] The PMOS transistor P7B has a first terminal coupled to the power supply voltage terminal, a second terminal coupled to the first terminal of the NMOS transistor N1B, and a control terminal. The PMOS transistor P8B has a first terminal coupled to the second terminal of the PMOS transistor P7B, a second terminal coupled to the output terminal AO of the amplifier 240, and a control terminal for receiving the bias voltage VBP.

[0042] The PMOS transistor P9B has a first terminal coupled to the power supply voltage terminal, a second terminal coupled to the first terminal of the NMOS transistor N2B, and a control terminal coupled to the control terminal of the PMOS transistor P7B. The PMOS transistor P10B has a first terminal coupled to the second terminal of the PMOS transistor P9B, a second terminal coupled to the control terminal of the PMOS transistor P9B, and a control terminal coupled to the control terminal of the PMOS transistor P8B.

[0043] The load unit 242 is coupled to the second terminal of the PMOS transistor P8B, and the load unit 244 is coupled to the second terminal of the PMOS transistor P10B. In this embodiment, the load unit 242 includes NMOS transistors N4B and N5B, and the load unit 244 includes NMOS transistors N6B and N7B.

[0044] NMOS transistor N4B has a first terminal coupled to the second terminal of PMOS transistor P8B, a second terminal, and a control terminal for receiving bias voltage VBN2. NMOS transistor N5B has a first terminal coupled to the second terminal of NMOS transistor N4B, a second terminal coupled to ground, and a control terminal for receiving bias voltage VBN1.

[0045] NMOS transistor N6B has a first terminal coupled to the second terminal of PMOS transistor P10B, a second terminal, and a control terminal for receiving bias voltage VBN2. NMOS transistor N7B has a first terminal coupled to the second terminal of NMOS transistor N6B, a second terminal coupled to ground, and a control terminal for receiving bias voltage VBN1.

[0046] In this embodiment, since the connection method of the PMOS transistors P7B, P8B, P9B, and P10B is the same as the connection method of the PMOS transistors P1B, P2B, P3B, and P4B, the bias voltage VBP received by the PMOS transistors P8B and P10B can also be provided to the control terminals of the PMOS transistors P2B and P4B. In other words, the control terminal of the PMOS transistor P2B and the control terminal of the PMOS transistor P4B can be coupled to the control terminal of the PMOS transistor P8B. In some embodiments, to further ensure that the bias voltage VBP can be applied to both the amplifier 240 and the current sources 210 and 220, the PMOS transistors P7B, P8B, P9B, and P10B may have the same size factor as the PMOS transistors P1B, P2B, P3B, and P4B, such that the current I4 flowing through the PMOS transistors P7B and P8B is equal to the currents I1 and I2 (i.e., I1=I2=I4), and the current I5 flowing through the PMOS transistors P9B and P10B is equal to the currents I1 and I2 (i.e., I1=I2=I5). Specifically, the PMOS transistors P1B, P3B, P5B, P7B, and P9B may all have the same size factor. Furthermore, the PMOS transistors P2B, P4B, P6B, P8B, and P10B may all have the same size factor.

[0047] Furthermore, in some embodiments, PMOS transistors P1B, P3B, P5B, P7B, and P9B may have different size factors than PMOS transistors P2B, P4B, P6B, P8B, and P10B. For example, the width-to-length ratio of PMOS transistor P2B may be greater than the width-to-length ratio of PMOS transistor P1B. However, the present disclosure is not limited thereto.

[0048] By making PMOS transistors P7B, P8B, P9B, and P10B have the same size factor and the same connection relationship as PMOS transistors P1B, P2B, P3B, and P4B, bias voltage VBP ensures that PMOS transistors P2B and P4B operate in a linear mode when power supply voltage VDD is low (e.g., below a threshold). Consequently, the drain-source voltage of PMOS transistors P2B and P4B can be reduced, and PMOS transistors P2B and P4B can be treated as pass gates, thereby leaving more voltage margin for PMOS transistors P1B and P3B. Consequently, bandgap reference circuits 200, 300, and 400 can provide a stable reference voltage VBGR regardless of whether they are receiving a low or high power supply voltage.

[0049] In summary, the bandgap reference circuit provided by the embodiments of the present disclosure utilizes a stacked structure within the current source to mitigate the voltage applied to the transistors within the current source when receiving a high power supply voltage. Furthermore, the bandgap reference circuit further includes an amplifier acting as a source follower to mitigate mismatches among the transistors within the current source. As such, the bandgap reference circuit of the present disclosure is capable of generating a stable and accurate reference voltage over a wide power supply voltage range.

[0050] Explanation of symbols

[0051] 100, 200, 300, 400: Bandgap reference circuit

[0052] 110:Amplifier

[0053] P1A, P2A, P3A: PMOS transistors

[0054] VDD: power supply voltage

[0055] VA, VB, VC: voltage

[0056] I1, I2, I3, I1A, I1B: current

[0057] R1A, R2A, R3A, R4A: resistors

[0058] B1A,B2A:BJT

[0059] VBE: Base-Emitter Voltage

[0060] VBGR: reference voltage

[0061] 210, 220, 230: Current source

[0062] 240,250:Amplifier

[0063] 260,360,460: Temperature coefficient adjustment unit

[0064] P1B, P2B, P3B, P4B, P5B, P6B: PMOS transistors

[0065] N1, N2, N3, N4, NO1: nodes

[0066] C1B, C2B: capacitors

[0067] R1B, R2B, R3B, R4B, R5B: resistors

[0068] B1B,B2B:BJT

[0069] VBP: Bias voltage

[0070] 242,244: Load cell

[0071] N1B, N2B, N3B, N4B, N5B, N6B, N7B: NMOS transistors

[0072] P7B, P8B, P9B, P10B: PMOS transistors

[0073] VBN1, VBN2, VBP: bias voltage

[0074] AO: output terminal

Claims

1. A bandgap reference circuit for generating a reference voltage and outputting the reference voltage via an output node, the bandgap reference circuit comprising: a first current source for generating a first current flowing through a first node, the first current source comprising a first PMOS transistor and a second PMOS transistor connected in cascade between a power supply voltage terminal and the first node; a second current source for generating a second current flowing through a second node, the second current source comprising a third PMOS transistor and a fourth PMOS transistor connected in cascade between the power voltage terminal and the second node; a third current source for generating a third current flowing through an output node, the third current source comprising a fifth PMOS transistor and a sixth PMOS transistor connected in cascade between the power voltage terminal and the output node; a first amplifier having a first input terminal coupled to the first node, a second input terminal coupled to the second node, and an output terminal coupled to a control terminal of the first PMOS transistor and a control terminal of the third PMOS transistor; a second amplifier having a first input terminal coupled to a third node, a second input terminal coupled to a fourth node, and an output terminal coupled to a control terminal of the sixth PMOS transistor, wherein the third node is connected to the fifth PMOS transistor and the sixth PMOS transistor, and the fourth node is connected to the first PMOS transistor and the second PMOS transistor; a first resistor coupled to the output node and configured to receive the third current; as well as A temperature coefficient adjustment unit includes a first BJT for receiving the first current and a second BJT for receiving the second current. 2 . The bandgap reference circuit as claimed in claim 1 , wherein a control terminal of the second PMOS transistor and a control terminal of the fourth PMOS transistor are used to receive a first bias voltage. 3 . The bandgap reference circuit as claimed in claim 2 , wherein the first bias voltage is equal to a power voltage received from the power voltage terminal minus twice a threshold voltage of the first PMOS transistor.

4. The bandgap reference circuit of claim 2 , wherein the first bias voltage is set according to a potential of a power voltage received from the power voltage terminal, such that when the power voltage is lower than a threshold, the second PMOS transistor operates in a linear mode, and when the power voltage is higher than the threshold, the second PMOS transistor operates in a saturation mode.

5. The bandgap reference circuit of claim 2 , wherein the first amplifier comprises: a first NMOS transistor having a first terminal, a second terminal, and a control terminal coupled to the first input terminal of the first amplifier; a second NMOS transistor having a first terminal, a second terminal, and a control terminal coupled to the second input terminal of the first amplifier; a third NMOS transistor having a first terminal coupled to the second terminal of the first NMOS transistor and the second terminal of the second NMOS transistor, a second terminal coupled to a ground terminal, and a control terminal for receiving a second bias voltage; a seventh PMOS transistor having a first terminal coupled to the power voltage terminal, a second terminal coupled to the first terminal of the first NMOS transistor, and a control terminal; an eighth PMOS transistor having a first terminal coupled to the second terminal of the seventh PMOS transistor, a second terminal coupled to the output terminal of the first amplifier, and a control terminal for receiving the first bias voltage; a ninth PMOS transistor having a first terminal coupled to the power supply voltage terminal, a second terminal coupled to the first terminal of the second NMOS transistor, and a control terminal coupled to the control terminal of the seventh PMOS transistor; a tenth PMOS transistor having a first terminal coupled to the second terminal of the ninth PMOS transistor, a second terminal coupled to the control terminal of the ninth PMOS transistor, and a control terminal coupled to the control terminal of the eighth PMOS transistor; a first load unit coupled to the second terminal of the eighth PMOS transistor; and A second load unit is coupled to the second terminal of the tenth PMOS transistor. 6 . The bandgap reference circuit as claimed in claim 5 , wherein a control terminal of the second PMOS transistor and a control terminal of the fourth PMOS transistor are coupled to the control terminal of the eighth PMOS transistor.

7. The bandgap reference circuit of claim 5 , wherein the first PMOS transistor, the third PMOS transistor, the fifth PMOS transistor, the seventh PMOS transistor, and the ninth PMOS transistor have the same size factor, and the second PMOS transistor, the fourth PMOS transistor, the sixth PMOS transistor, the eighth PMOS transistor, and the tenth PMOS transistor have the same size factor.

8. The bandgap reference circuit as claimed in claim 1 , wherein a first terminal of the first PMOS transistor is coupled to the power supply voltage terminal, a second terminal of the first PMOS transistor is coupled to the fourth node, a first terminal of the second PMOS transistor is coupled to the fourth node, and a second terminal of the second PMOS transistor is coupled to the first node.

9. The bandgap reference circuit as claimed in claim 1 , wherein a first terminal of the fifth PMOS transistor is coupled to the power supply voltage terminal, a second terminal of the fifth PMOS transistor is coupled to the third node, a first terminal of the sixth PMOS transistor is coupled to the third node, and a second terminal of the sixth PMOS transistor is coupled to the output node. 10 . The bandgap reference circuit as claimed in claim 1 , wherein the first input terminal of the first amplifier is a negative input terminal, and the second input terminal of the first amplifier is a positive input terminal. 11 . The bandgap reference circuit as claimed in claim 1 , wherein the first input terminal of the second amplifier is a negative input terminal, and the second input terminal of the second amplifier is a positive input terminal. 12 . The bandgap reference circuit as claimed in claim 1 , further comprising a first capacitor having a first terminal coupled to the power supply voltage terminal and a second terminal coupled to the output terminal of the first amplifier. 13 . The bandgap reference circuit as claimed in claim 1 , wherein the first resistor has a first terminal coupled to the output node and a second terminal coupled to a ground terminal. 14 . The bandgap reference circuit as claimed in claim 1 , further comprising a second capacitor having a first terminal coupled to the output node and a second terminal coupled to a ground terminal. 15 . The bandgap reference circuit of claim 1 , wherein the first BJT has an emitter for receiving at least a portion of the first current, a collector coupled to a ground terminal, and a base coupled to the ground terminal. 16 . The bandgap reference circuit as claimed in claim 15 , wherein the temperature coefficient adjustment unit further comprises a second resistor having a first end coupled to the first node and a second end coupled to the ground. 17 . The bandgap reference circuit of claim 1 , wherein the second BJT has an emitter for receiving at least a portion of the second current, a collector coupled to a ground terminal, and a base coupled to the ground terminal. 18 . The bandgap reference circuit as claimed in claim 17 , wherein the temperature coefficient adjustment unit further comprises a third resistor having a first end coupled to the second node and a second end coupled to the emitter of the second BJT. 19 . The bandgap reference circuit as claimed in claim 17 , wherein the temperature coefficient adjustment unit further comprises a fourth resistor having a first end coupled to the second node and a second end coupled to the ground. 20 . The bandgap reference circuit of claim 1 , wherein a width-to-length ratio of the second PMOS transistor is greater than a width-to-length ratio of the first PMOS transistor.

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