Method for recording accumulated working time of equipment by using NorFlash
The embedded device itself Nor Flash records the accumulated working time of the device, which solves the problems of high hardware costs and indefinitely reliable timing in the prior art, and realizes the timing function of saving costs and improving reliability, and only 64K Flash storage space is required.
Patent Information
- Application Number
- CN202510607674.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-13
- Publication Date
- 2025-08-26
AI Technical Summary
In the prior art, when using Nor Flash to record the equipment to accumulate working hours, additional hardware accumulation timing circuit is required, resulting in high hardware cost, large circuit board area, and ineffective timing function under complex working conditions. Flash block erasing operation is prone to data errors due to power outage.
Using Nor Flash for embedded devices' own program storage, the device's cumulative working time recording is realized through two NorFlash blocks, and fault detection and fault recovery functions are introduced to avoid additional hardware accumulation timing circuits. Only 64K Flash storage space can meet the long-term timing requirements.
Save hardware costs, reduce circuit board area, improve the reliability of timing functions under complex conditions, reduce the number of electronic components, and meet the timing requirements for long-term work.
Smart Images
Figure CN120540586A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of chip design, and in particular to a method for recording the accumulated working time of a device using NorFlash. Background Art
[0002] Embedded devices generally require additional hardware cumulative timing circuits to record the cumulative operating time of the device. The typical operating characteristics of Nor Flash chips are as follows:
[0003] On Nor Flash, data needs to be erased block by block before being written to ensure reliable writing.
[0004] After the block is erased, each data bit of each storage unit in the block is set to 1, and each byte value is 0xFF.
[0005] For a block that has been erased, after writing arbitrary data once to each storage address space, if you need to write arbitrary data again, you need to complete the block erase again to execute it correctly.
[0006] Each data block in a typical Nor Flash chip has a capacity of 65,536 bytes. Using Nor Flash to record cumulative operating time requires writing and erasing data to the Flash block. If a sudden power outage occurs during these operations, the data in the corresponding data block storage area will be lost.
[0007] Block erasure is a process of erasing 65536 bytes of data, which takes a long time and has a high probability of causing errors due to power failure during execution.
[0008] The byte write operation takes a short time and has a low probability of error caused by power failure during execution.
[0009] This method utilizes the embedded device's own Nor Flash memory, used for program storage, to record the device's cumulative operating time. This avoids the need for additional hardware-based cumulative timing circuitry, saving hardware costs, reducing circuit board area, and reducing the number of electronic components. This method also incorporates fault detection and recovery capabilities, improving the reliability of the timing function under complex operating conditions. Using only two 64KB of Flash memory, this method can meet the device's timing requirements for long-term operation, taking up minimal storage space. Summary of the Invention
[0010] (1) Technical problems solved
[0011] To address the shortcomings of the existing technology, the present invention provides a method for recording device cumulative operating time using NorFlash. This method utilizes the embedded device's own NorFlash program storage to implement the device's cumulative operating time recording function, avoiding the need for additional hardware cumulative timing circuitry, saving hardware costs, reducing circuit board area, and reducing the number of electronic components. This method incorporates fault detection and recovery capabilities, improving the reliability of the timing function under complex operating conditions. This method utilizes only two 64KB Flash memory slots to meet the timing requirements of long-term device operation, thus taking up less storage space.
[0012] (2) Technical solution
[0013] To achieve the above objectives, the present invention is implemented through the following technical solution: a method for recording the accumulated working time of a device using NorFlash, specifically comprising the following steps:
[0014] S1. The Flash initialization process is completed during the device production phase. The manufacturer needs to ensure the correctness of the process and does not need to consider its troubleshooting issues.
[0015] S2, fault detection and parameter recovery are completed during the parameter loading process;
[0016] S3. After the device is powered on and initialized, two NorFlash blocks are used to perform a timing accumulation process with the ability to recover after a sudden power outage.
[0017] Preferably, a single-byte Flash operation will affect the Flash content of the byte, and a block Flash operation failure will affect the Flash content of the block.
[0018] Preferably, the Flash initialization process in step S1 specifically includes the following steps:
[0019] T1. Set PosL=0, StL=0, and erase the H block of Flash;
[0020] T2, then perform the WH0 operation, that is, write 0 to a byte at the StL*2 address in the H block of the Flash, and erase the L block of the Flash;
[0021] T3. Perform WH1 operation, that is, write 0 to a byte at address StL*2+1 in the H block of the Flash, and write 0 to a byte at address PosL in the L block of the Flash.
[0022] Preferably, the parameter loading process in step S2 specifically includes the following steps:
[0023] E1. When power is lost after the WL0 operation begins, the Flash data required for the preceding operation comes from the H block. The next power-on will not be affected. The only consequence of this operation failure is that the WL0 operation will be repeated during the parameter loading process after the next power-on. It has no effect on the next correct execution of this process.
[0024] E2. When power is lost after the start of this WH1 operation, the Flash bytes corresponding to odd addresses in the H block will have two conditions: A1, 0xFF and B1, non-0xFF;
[0025] E3. After the next power-on, the A1 condition will cause the parameter loading process to enter the branch process where PosH is an odd number and is not satisfied, which is equivalent to continuing the current process and has no effect on the next correct execution of the current process;
[0026] E4. After the next power-on, the B1 situation will cause the parameter loading process to enter the branch process where PosH is an odd number. Since the L block is erased at this time and the content is all 0xFF, and no 0 is written to the first byte, it will enter the branch process where the L block is all 0xFF and continue the PosL=0 and WL1 operations. This has no effect on the next correct execution of this process.
[0027] Preferably, when the power is cut off after the WL1 operation of step E2 is started, the Flash bytes of the corresponding addresses in the L block will have two situations: A2, 0xFF and B2, non-0xFF. Since the parameter loading process of this power-on has completed the WL0 and WH1 operations, after the next power-on, the parameter loading process enters the branch where PosH is an odd number, and then enters the conditional judgment that all L blocks are 0xFF.
[0028] Preferably, situation A2 will cause the parameter loading process to enter the branch where all L blocks are 0xFF, and continue the PosL=0 and WL1 operations, which will have no effect on the next correct execution of this process. At this time, situation B2 will cause the parameter loading process to enter the branch where all L blocks are 0xFF and are not satisfied, which will have no effect on the next correct execution of this process. When a Flash-related operation failure occurs in the parameter loading process, it will have no effect on the next correct execution of this process.
[0029] Preferably, the timing accumulation process in step S3 specifically includes the following steps:
[0030] P1,When the power is lost after the start of this WH0 operation, the Flash bytes corresponding to the even addresses in the H block will have two situations: A3, 0xFF and B3, non-0xFF;
[0031] P2. After the next power-on, the A3 situation will be equivalent to the WH0 operation of the timing accumulation process not being executed, that is, only a ΔT time is accumulated less, which has no effect on the next correct execution of the parameter loading process;
[0032] P3. After the next power-on, the B3 situation will cause the parameter loading process to enter the branch process where PosH is an odd number and is not satisfied. The subsequent WL0, WH1 and WL1 operations of the parameter loading process are the same as the corresponding operations of the timing accumulation process, and have no effect on the next correct execution of the parameter loading process;
[0033] P4. When the power is cut off after the WL0 operation starts, the parameter loading process will enter the branch process where PosH is an odd number and is not satisfied after the next power-on. The subsequent WL0, WH1 and WL1 operations are the same as those in the timing accumulation process, and have no effect on the correct execution of the parameter loading process next time;
[0034] P5,When the power is lost after the start of this WH1 operation, the Flash bytes corresponding to odd addresses in the H block will have two situations: A4, 0xFF and B4, non-0xFF;
[0035] P6. After the next power-on, the A4 condition will cause the parameter loading process to enter the branch process where PosH is an odd number and is not satisfied. The subsequent WL0, WH1, and WL1 operations of the parameter loading process are the same as those of the timing accumulation process, and have no effect on the next correct execution of the parameter loading process.
[0036] P7. After the next power-on, the B4 situation will cause the parameter loading process to enter the branch process where PosH is an odd number. Since the L block is erased at this time and the content is all 0xFF, and no 0 is written to the first byte, it will enter the branch process where the L block is all 0xFF and continue the PosL=0 and WL1 operations. This has no effect on the next correct execution of the parameter loading process.
[0037] When power is lost after the WL1 operation begins, the Flash bytes at the corresponding addresses in the L block may appear in two situations: A5, 0xFF, and B5, non-0xFF. After the next power-on, the parameter loading process enters the branch where PosH is an odd number, and then enters the conditional judgment where the L block is all 0xFF. At this time, the A5 situation will cause the parameter loading process to enter the branch where the L block is all 0xFF, and continue the PosL = 0 and WL1 operation. This has no effect on the next correct execution of this process. At this time, the B5 situation will cause the parameter loading process to enter the branch where the L block is all 0xFF is not satisfied, which has no effect on the next correct execution of this process.
[0038] (3) Beneficial effects
[0039] The present invention provides a method for recording the accumulated working time of a device using NorFlash. Compared with the prior art, the method has the following advantages: the method for recording the accumulated working time of a device using NorFlash implements the function of recording the accumulated working time of the device by utilizing the Nor Flash used for program storage of the embedded device itself, avoiding the introduction of additional hardware cumulative timing circuits, saving hardware costs, reducing the circuit board area, and reducing the number of electronic components. The method introduces fault detection and fault recovery functions, improving the reliability of the timing function under complex working conditions. The method only utilizes two 64K Flash storage spaces to meet the timing requirements of the device for long-term operation, and has the advantage of occupying less storage space. BRIEF DESCRIPTION OF THE DRAWINGS
[0040] Figure 1 This is the Flash initialization flow chart of the present invention;
[0041] Figure 2 Loading flow chart for parameters of the present invention;
[0042] Figure 3 This is a timing accumulation flow chart of the present invention. DETAILED DESCRIPTION
[0043] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.
[0044] See also Figure 1-3 The present invention provides two technical solutions: a method for recording the accumulated working time of a device using NorFlash, specifically including the following embodiments:
[0045] Example 1: A method for recording the accumulated working time of a device using NorFlash, specifically comprising the following steps:
[0046] S1. The Flash initialization process is completed during the device production phase. The manufacturer needs to ensure the correctness of the process and does not need to consider its troubleshooting issues.
[0047] S2. Fault detection and parameter recovery are completed during the parameter loading process. The parameter loading process is a necessary process for users, and the effectiveness of its Flash operation fault handling needs to be considered.
[0048] S3. After the device is powered on and initialized, two NorFlash blocks are used to perform a timing accumulation process with the ability to recover after a sudden power outage. The timing accumulation process is a necessary process for user use, and the effectiveness of its Flash operation fault handling needs to be considered.
[0049] In the embodiment of the present invention, a single-byte Flash operation will affect the Flash content of the byte, and a block Flash operation failure will affect the Flash content of the block.
[0050] In the embodiment of the present invention, the Flash initialization process in step S1 specifically includes the following steps:
[0051] T1. Set PosL=0, StL=0, and erase the H block of Flash;
[0052] T2, then perform the WH0 operation, that is, write 0 to a byte at the StL*2 address in the H block of the Flash, and erase the L block of the Flash;
[0053] T3. Perform WH1 operation, that is, write 0 to a byte at address StL*2+1 in the H block of the Flash, and write 0 to a byte at address PosL in the L block of the Flash.
[0054] In the embodiment of the present invention, the parameter loading process in step S2 specifically includes the following steps:
[0055] E1. When power is lost after the WL0 operation begins, the Flash data required for the preceding operation comes from the H block. The next power-on will not be affected. The only consequence of this operation failure is that the WL0 operation will be repeated during the parameter loading process after the next power-on. It has no effect on the next correct execution of this process.
[0056] E2. When power is lost after the start of this WH1 operation, the Flash bytes corresponding to odd addresses in the H block will have two conditions: A1, 0xFF and B1, non-0xFF;
[0057] E3. After the next power-on, the A1 condition will cause the parameter loading process to enter the branch process where PosH is an odd number and is not satisfied, which is equivalent to continuing the current process and has no effect on the next correct execution of the current process;
[0058] E4. After the next power-on, the B1 situation will cause the parameter loading process to enter the branch process where PosH is an odd number. Since the L block is erased at this time and the content is all 0xFF, and no 0 is written to the first byte, it will enter the branch process where the L block is all 0xFF and continue the PosL=0 and WL1 operations. This has no effect on the next correct execution of this process.
[0059] In an embodiment of the present invention, when power is lost after the WL1 operation in step E2 is started, two situations may occur for the Flash bytes at the corresponding addresses in the L block: A2, 0xFF and B2, non-0xFF. Since the parameter loading process for this power-on has completed the WL0 and WH1 operations, after the next power-on, the parameter loading process enters the branch where PosH is an odd number, and then enters the conditional judgment of whether the L block is all 0xFF. The A2 situation will cause the parameter loading process to enter the branch where the L block is all 0xFF, and continue the PosL=0 and WL1 operations, which has no effect on the next correct execution of the current process. At this time, the B2 situation will cause the parameter loading process to enter the branch where the L block is not all 0xFF, which has no effect on the next correct execution of the current process. When a Flash-related operation failure occurs in the parameter loading process, it has no effect on the next correct execution of the current process.
[0060] Embodiment 2: The technical solution of the embodiment of the present invention is different from that of embodiment 1 in that the timing accumulation process in step S3 specifically includes the following steps:
[0061] P1,When the power is lost after the start of this WH0 operation, the Flash bytes corresponding to the even addresses in the H block will have two situations: A3, 0xFF and B3, non-0xFF;
[0062] P2. After the next power-on, the A3 situation will be equivalent to the WH0 operation of the timing accumulation process not being executed, that is, only a ΔT time is accumulated less, which has no effect on the next correct execution of the parameter loading process;
[0063] P3. After the next power-on, the B3 situation will cause the parameter loading process to enter the branch process where PosH is an odd number and is not satisfied. The subsequent WL0, WH1 and WL1 operations of the parameter loading process are the same as the corresponding operations of the timing accumulation process, and have no effect on the next correct execution of the parameter loading process;
[0064] P4. When the power is cut off after the WL0 operation starts, the parameter loading process will enter the branch process where PosH is an odd number and is not satisfied after the next power-on. The subsequent WL0, WH1 and WL1 operations are the same as those in the timing accumulation process, and have no effect on the correct execution of the parameter loading process next time;
[0065] P5,When the power is lost after the start of this WH1 operation, the Flash bytes corresponding to odd addresses in the H block will have two situations: A4, 0xFF and B4, non-0xFF;
[0066] P6. After the next power-on, the A4 condition will cause the parameter loading process to enter the branch process where PosH is an odd number and is not satisfied. The subsequent WL0, WH1, and WL1 operations of the parameter loading process are the same as those of the timing accumulation process, and have no effect on the next correct execution of the parameter loading process.
[0067] P7. After the next power-on, the B4 situation will cause the parameter loading process to enter the branch process where PosH is an odd number. Since the L block is erased at this time and the content is all 0xFF, and no 0 is written to the first byte, it will enter the branch process where the L block is all 0xFF and continue the PosL=0 and WL1 operations. This has no effect on the next correct execution of the parameter loading process.
[0068] In the embodiment of the present invention, when power is lost after the WL1 operation starts, two situations will occur in the Flash bytes at the corresponding addresses in the L block: A5, 0xFF and B5, non-0xFF. After the next power-on, the parameter loading process enters the branch where PosH is an odd number, and then enters the conditional judgment of whether the L block is all 0xFF. At this time, the A5 situation will cause the parameter loading process to enter the branch where the L block is all 0xFF, and continue PosL=0 and WL1 operations, which has no effect on the next correct execution of this process. At this time, the B5 situation will cause the parameter loading process to enter the branch where the L block is all 0xFF, which is not satisfied, and has no effect on the next correct execution of this process.
[0069] Flash initialization process is as follows Figure 1 As shown, its purpose is to complete the initialization of the device storage parameters, which is mainly used in the production process before the device leaves the factory.
[0070] The parameter loading process is as follows Figure 2 As shown in the figure, this process is executed during each power-on initialization process after the device leaves the factory. It correctly reads the parameters after power-on and recovers the relevant Flash block data from a fault. The straight line between the beginning and the end of this process represents the normal parameter initialization process when there is no fault. The process on the right side of the two conditional judgments represents the processing flow when a fault occurs in the previous Flash operation.
[0071] The timing accumulation process is as follows Figure 3 As shown, this process is executed repeatedly after each power-on initialization of the device after shipment, completing the device's time accumulation functions, including background accumulation and recording of working time. In this process, if power is lost during any of the WH0, WL0, WH1, or WL1 operations, the contents stored in the corresponding Flash memory will change, requiring the right-hand fault handling branch of the parameter loading process to restore the correct data. If power is lost during any other operation in this process, the Flash memory contents will not be affected. The next time power is turned on, the parameter loading process will proceed as it would if no faults were present.
[0072] In the timing accumulation process, each delay of ΔT can be implemented through interrupt calls to avoid invalid CPU usage during the delay period. The cumulative working time of the device is calculated using the following formula:
[0073] Sum(T)=ΔT×(PosL+StL*65536).
[0074] Analysis of the longest recording time: The analysis of the longest recording time allowed by this method is as follows:
[0075] The longest operation used in this method is the Flash block erase operation, which takes at least milliseconds to complete. To reduce CPU usage in embedded devices, ΔT is typically set to ≥ 1 minute.
[0076] If ΔT = 1 minute, the maximum cumulative working time that can be recorded by this method is:
[0077]
[0078] This cumulative time recording range fully meets the needs of cumulative recording of equipment working time.
[0079] At the same time, even during this longest recorded time, there is no Flash erase operation on the H block, and the L block erase count is 32,768 times, which is lower than the maximum secure erase count of 100,000 times guaranteed in the Nor Flash chip data sheets of many manufacturers. There is no limit on the number of Flash erase times in the engineering implementation of this method.
[0080] In summary, the present invention utilizes the embedded device's own Nor Flash memory for program storage to record the device's cumulative operating time, avoiding the need for additional hardware cumulative timing circuitry. This reduces hardware costs, circuit board area, and the number of electronic components. This method also incorporates fault detection and recovery capabilities, improving the reliability of the timing function under complex operating conditions. This method utilizes only two 64KB Flash memories to meet the device's timing requirements for long-term operation, thus taking up minimal storage space.
[0081] Meanwhile, the contents not described in detail in this specification belong to the prior art known to those skilled in the art.
[0082] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus.
[0083] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.
Claims
1. A method for recording the accumulated working time of a device using NorFlash, characterized in that: The specific steps include: S1. The Flash initialization process is completed during the device production phase. The manufacturer needs to ensure the correctness of the process and does not need to consider its troubleshooting issues. S2, fault detection and parameter recovery are completed during the parameter loading process; S3. After the device is powered on and initialized, two NorFlash blocks are used to perform a timing accumulation process with the ability to recover after a sudden power outage.
2. The method of using NorFlash to record the accumulated working time of a device according to claim 1, characterized in that: Single-byte Flash operations affect the Flash contents of that byte, and block Flash operation failures affect the Flash contents of that block.
3. The method of using NorFlash to record the accumulated working time of a device according to claim 1, characterized in that: The Flash initialization process in step S1 specifically includes the following steps: T1. Set PosL=0, StL=0, and erase the H block of Flash; T2, then perform the WH0 operation, that is, write 0 to a byte at the StL*2 address in the H block of the Flash, and erase the L block of the Flash; T3. Perform WH1 operation, that is, write 0 to a byte at address StL*2+1 in the H block of the Flash, and write 0 to a byte at address PosL in the L block of the Flash.
4. The method of using NorFlash to record the accumulated working time of a device according to claim 1, characterized in that: The parameter loading process in step S2 specifically includes the following steps: E1. When power is lost after the WL0 operation begins, the Flash data required for the preceding operation comes from the H block. The next power-on will not be affected. The only consequence of this operation failure is that the WL0 operation will be repeated during the parameter loading process after the next power-on. It has no effect on the next correct execution of this process. E2. When power is lost after the start of this WH1 operation, the Flash bytes corresponding to odd addresses in the H block will have two conditions: A1, 0xFF and B1, non-0xFF; E3. After the next power-on, the A1 condition will cause the parameter loading process to enter the branch process where PosH is an odd number and is not satisfied, which is equivalent to continuing the current process and has no effect on the next correct execution of the current process; E4. After the next power-on, the B1 situation will cause the parameter loading process to enter the branch process where PosH is an odd number. Since the L block is erased at this time and the content is all 0xFF, and no 0 is written to the first byte, it will enter the branch process where the L block is all 0xFF and continue the PosL=0 and WL1 operations. This has no effect on the next correct execution of this process.
5. The method for recording the accumulated working time of a device using NorFlash according to claim 4, characterized in that: When the power is lost after the WL1 operation in step E2 is started, the Flash bytes at the corresponding addresses in the L block will have two situations: A2, 0xFF and B2, non-0xFF. Since the parameter loading process has completed the WL0 and WH1 operations during this power-on, after the next power-on, the parameter loading process enters the branch where PosH is an odd number, and then enters the conditional judgment that all the values in the L block are 0xFF.
6. The method for recording the accumulated working time of a device using NorFlash according to claim 5, characterized in that: In case A2, the parameter loading process will enter the branch where all L blocks are 0xFF, and continue the PosL=0 and WL1 operations. This will not affect the next correct execution of this process. At this time, in case B2, the parameter loading process will enter the branch where all L blocks are 0xFF, which is not satisfied. This will not affect the next correct execution of this process. If a Flash-related operation failure occurs in the parameter loading process, this will not affect the next correct execution of this process.
7. The method of using NorFlash to record the accumulated working time of a device according to claim 1, characterized in that: The timing accumulation process in step S3 specifically includes the following steps: P1,When the power is lost after the start of this WH0 operation, the Flash bytes corresponding to the even addresses in the H block will have two situations: A3, 0xFF and B3, non-0xFF; P2. After the next power-on, the A3 situation will be equivalent to the WH0 operation of the timing accumulation process not being executed, that is, only a ΔT time is accumulated less, which has no effect on the next correct execution of the parameter loading process; P3. After the next power-on, the B3 situation will cause the parameter loading process to enter the branch process where PosH is an odd number and is not satisfied. The subsequent WL0, WH1 and WL1 operations of the parameter loading process are the same as the corresponding operations of the timing accumulation process, and have no effect on the next correct execution of the parameter loading process; P4. When the power is cut off after the WL0 operation starts, the parameter loading process will enter the branch process where PosH is an odd number and is not satisfied after the next power-on. The subsequent WL0, WH1 and WL1 operations are the same as those in the timing accumulation process, and have no effect on the correct execution of the parameter loading process next time; P5,When the power is lost after the start of this WH1 operation, the Flash bytes corresponding to odd addresses in the H block will have two situations: A4, 0xFF and B4, non-0xFF; P6. After the next power-on, the A4 condition will cause the parameter loading process to enter the branch process where PosH is an odd number and is not satisfied. The subsequent WL0, WH1, and WL1 operations of the parameter loading process are the same as those of the timing accumulation process, and have no effect on the next correct execution of the parameter loading process. P7. After the next power-on, the B4 situation will cause the parameter loading process to enter the branch process where PosH is an odd number. Since the L block is erased at this time and the content is all 0xFF, and no 0 is written to the first byte, it will enter the branch process where the L block is all 0xFF and continue the PosL=0 and WL1 operations. This has no effect on the next correct execution of the parameter loading process.
8. The method for recording the accumulated working time of a device using NorFlash according to claim 7, characterized in that: When power is lost after the WL1 operation begins, the Flash bytes at the corresponding addresses in the L block may appear in two situations: A5, 0xFF, and B5, non-0xFF. After the next power-on, the parameter loading process enters the branch where PosH is an odd number, and then enters the conditional judgment where the L block is all 0xFF. At this time, the A5 situation will cause the parameter loading process to enter the branch where the L block is all 0xFF, and continue the PosL = 0 and WL1 operation. This has no effect on the next correct execution of this process. At this time, the B5 situation will cause the parameter loading process to enter the branch where the L block is all 0xFF is not satisfied, which has no effect on the next correct execution of this process.