Digital circuit, quantum computing device, voltage drop method, and controller
Through the alternating digital circuit of high and low voltage swing logic gate, the ultra-low temperature characteristics of the logic gate are used to alternately adjust the power line and ground line voltage, solving the problems of high cost and poor flexibility in the prior art, and achieving the effect of efficiently reducing the power consumption of digital circuits in ultra-low temperature environments.
Patent Information
- Application Number
- CN202411138754.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-19
- Publication Date
- 2025-08-29
AI Technical Summary
The prior art methods to reduce the power consumption of digital circuits in ultra-low temperature environments are costly and have poor flexibility, and the new process devices are unstable under the increase in temperature, and the physical layout design area is expensive.
The alternating digital circuit of high and low voltage swing logic gate is adopted, and the voltages of the power line and ground line are adjusted respectively by alternately connecting the first logic gate and the second logic gate, so as to construct an alternating digital circuit structure of the high and low voltage swing logic gate by utilizing the ultra-low temperature characteristics of the logic gate.
Effectively reduce the overall power consumption of the circuit in ultra-low temperature environment, achieve higher dynamic voltage frequency adjustment efficiency than traditional methods, without damaging circuit performance, and at the same time reduce production costs and area overhead.
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Figure CN120562346A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of digital circuit technology, and in particular to a high-low voltage swing logic gate alternating digital circuit, a quantum computing device, a voltage drop method, and a controller. Background Art
[0002] In order to reduce the power consumption of digital circuits in ultra-low temperature areas in related technologies, iterative optimization is often performed on the process of digital circuits or special design methods of the physical layout of digital circuits are used to reduce power consumption. However, in order to reduce the power consumption of digital circuits in ultra-low temperature environments (4K), the methods in related technologies require process iterations, which have high production costs. In addition, the performance of transistor devices using new processes for ultra-low temperature applications is difficult to predict when the temperature rises, and the application flexibility is poor. The special design area overhead of the physical layout is large. Summary of the Invention
[0003] In view of this, the present invention aims to solve at least one of the problems in the related art to a certain extent. To this end, the purpose of this application is to provide a high-low voltage swing logic gate alternating digital circuit, quantum computing device, voltage drop method and controller.
[0004] The present application provides a high-low voltage swing logic gate alternating digital circuit. The high-low voltage swing logic gate alternating digital circuit includes a first logic gate, a second logic gate, a first power line, a first ground line, a second power line, and a second ground line. The first logic gate is electrically connected to the second logic gate. The first logic gate includes a first power terminal and a first ground terminal. The first power terminal is electrically connected to the first power line, and the first ground terminal is electrically connected to the first ground line. The second logic gate includes a second power terminal and a second ground terminal. The second power terminal is electrically connected to the second power line, and the second ground terminal is electrically connected to the second ground line. The supply voltage of the first power line is greater than the supply voltage of the second power line. The ground voltage of the second ground line is greater than the ground voltage of the first ground line.
[0005] In some embodiments, when there are plural first logic gates and plural second logic gates, the first logic gates and the second logic gates are electrically connected alternately.
[0006] In some embodiments, a voltage swing of the first logic gate is greater than a voltage swing of the second logic gate.
[0007] In some embodiments, the high-low voltage swing logic gate alternating digital circuit includes a first node and a second node. The first node is respectively provided at an input of the first logic gate and an output of the second logic gate. The second node is respectively provided at the output of the first logic gate and an input of the second logic gate. The voltage swing of the first node is smaller than the voltage swing of the second node.
[0008] In some embodiments, the first logic gate includes a first transistor and a second transistor, the second logic gate includes a third transistor and a fourth transistor, the source of the first transistor is electrically connected to the first power line, the source of the second transistor is electrically connected to the first ground line, the gate of the first transistor is electrically connected to the gate of the second transistor, the drain of the first transistor is electrically connected to the drain of the second transistor and then electrically connected to the gate of the third transistor and the gate of the fourth transistor respectively, the source of the third transistor is electrically connected to the second power line, the drain of the third transistor is electrically connected to the drain of the fourth transistor, and the source of the fourth transistor is electrically connected to the second ground line.
[0009] In some embodiments, the load capacitance at the first node is greater than the load capacitance at the second node.
[0010] In some embodiments, the number of logic gates in the high-low voltage swing logic gate alternating digital circuit is an even number.
[0011] The present application also provides a quantum computing device, which includes the high-low voltage swing logic gate alternating digital circuit described in any of the above embodiments.
[0012] The present application further provides a voltage reduction method for use in a high-low voltage swing logic gate alternating digital circuit as described in any of the above embodiments, the voltage reduction method comprising:
[0013] The supply voltage of the second power line is lowered, and the ground voltage of the second ground line is increased.
[0014] The present application also provides a controller for use in the high-low voltage swing logic gate alternating digital circuit described in any of the above embodiments, wherein the controller includes a voltage drop module, which is used to lower the supply voltage of the second power line and increase the ground voltage of the second ground line.
[0015] The high-low voltage swing logic gate alternating digital circuit, quantum computing device, voltage drop method and controller of the embodiments of the present application construct a high-low voltage swing logic gate alternating digital circuit structure by electrically connecting the first power supply terminal of the first logic gate to the first power line and the first ground terminal of the first logic gate to the first ground line, and electrically connecting the second power supply terminal of the second logic gate to the second power line with a supply voltage lower than the supply voltage of the first power line, and electrically connecting the second ground terminal of the second logic gate to the second ground line with a ground voltage higher than the ground voltage of the first ground line. This fully utilizes the ultra-low temperature characteristics of the logic gate transistors themselves, and thus has no special requirements for process manufacturing, has a small area overhead for the physical layout, and has low production costs. At the same time, when the digital circuit is in an ultra-low temperature environment, the overall power consumption of the circuit can be effectively reduced without almost damaging the circuit performance, thereby achieving a higher dynamic voltage and frequency adjustment efficiency than the dynamic voltage and frequency adjustment method in the related art.
[0016] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:
[0018] Figure 1 2. It is a schematic diagram of the structure of a high-low voltage swing logic gate alternating digital circuit according to certain embodiments of the present application;
[0019] Figure 2 It is a structural diagram of a digital circuit in the related art;
[0020] Figure 3 Schematic diagram of current-voltage curves of transistors of logic gates of a high-low voltage swing logic gate alternating digital circuit at room temperature and ultra-low temperature according to certain embodiments of the present application;
[0021] Figure 4 This is a schematic structural diagram of a first logic gate and a second logic gate in a buffer in certain embodiments of the present application;
[0022] Figure 5 This is a schematic diagram of the structure of the first logic gate and the second logic gate in certain embodiments of the present application applied to other standard cells;
[0023] Figure 6 is a schematic flow diagram of a pressure drop method in certain embodiments of the present application;
[0024] Figure 7 It is a schematic diagram of the structure of the controller of certain embodiments of the present application.
[0025] Main components reference numbers:
[0026] High and low voltage swing logic gate alternating digital circuit 100;
[0027] A first logic gate 10; a first power supply terminal 11; a first ground terminal 13; a first transistor P1, a source P11 of the first transistor, a drain P12 of the first transistor, and a gate P13 of the first transistor; a second transistor N1, a drain N11 of the second transistor, a source N12 of the second transistor, and a gate N13 of the second transistor; a second logic gate 20; a second power supply terminal 21; a second ground terminal 23; a third transistor P2, a gate P21 of the third transistor, a source P22 of the third transistor, and a drain P23 of the third transistor; a fourth transistor N2, a gate N21 of the fourth transistor, a drain N22 of the fourth transistor, and a source N23 of the fourth transistor; a first power line 30; a first ground line 40; a second power line 50; a second ground line 60; a first node L; and a second node N.
[0028] Controller 200 and voltage drop module 210 . DETAILED DESCRIPTION
[0029] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be understood as limiting the present application.
[0030] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance, or implicitly specifying the number of the technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the described features. In the description of this application, "plurality" means two or more, unless otherwise expressly and specifically defined.
[0031] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed" and "connected" should be understood broadly, and may refer to fixed connection, detachable connection, or integral connection; mechanical connection, electrical connection, or mutual communication; direct connection, indirect connection through an intermediate medium, internal communication between two components, or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.
[0032] The disclosure below provides many different embodiments or examples for implementing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, these are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed.
[0033] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be understood as limiting the present application.
[0034] See also Figure 1 The present application provides a high-low voltage swing logic gate alternating digital circuit 100. The high-low voltage swing logic gate alternating digital circuit 100 includes a first logic gate 10, a second logic gate 20, a first power line 30, a first ground line 40, a second power line 50, and a second ground line 60. The first logic gate 10 is electrically connected to the second logic gate 20. The first logic gate 10 includes a first power terminal 11 and a first ground terminal 13. The first power terminal 11 is electrically connected to the first power line 30, and the first ground terminal 13 is electrically connected to the first ground line 40. The second logic gate 20 includes a second power terminal 21 and a second ground terminal 23. The second power terminal 21 is electrically connected to the second power line 50, and the second ground terminal 23 is electrically connected to the second ground line 60. The supply voltage of the first power line 30 is greater than the supply voltage of the second power line 50. The ground voltage of the second ground line 60 is greater than the ground voltage of the first ground line 40.
[0035] Specifically, the first logic gates 10 and the second logic gates 20 can be alternately connected in series. The first power supply terminal 11 of the first logic gate 10 can be electrically connected to the first power line 30, and the first ground terminal 13 of the first logic gate 10 can be electrically connected to the first ground line 40. The second power supply terminal 21 of the second logic gate 20 can be electrically connected to the second power line 50, and the second ground terminal 23 of the second logic gate 20 can be electrically connected to the second ground line 60. The supply voltage of the first power line 30 can be greater than the supply voltage of the second power line 50. The voltage of the second ground line 60 can be greater than the voltage of the first ground line 40.
[0036] In one embodiment, when the high-low voltage swing logic gate alternating digital circuit 100 is in an ultra-low temperature environment (4K), Figure 1 As shown, the supply voltage of the first power line 30 can be V DD，NOM , the ground voltage of the first ground line 40 can be V SS, ΔV can represent the reduction or increase of the power supply voltage and the ground voltage. The power supply voltage of the second power line 50 can be V DDL (V DDL = DD，NOM -ΔV), the ground voltage of the second ground line 60 can be V SSL (V SSL = SS +ΔV), the voltage swing range from the first power supply terminal 11 to the first ground terminal 13 of the first logic gate 10 can be V DD，NOM -V SS The voltage swing range from the second power supply terminal 21 to the second ground terminal 23 of the second logic gate 20 can be V DDL -V SSL , at this time with Figure 2 In the related art, the digital circuit only changes the power supply voltage of the power line from V DD，NOM Reduce to V DDL (V DDL = DD，NOM -ΔV), the embodiment of the present application adopts a circuit structure in which a first logic gate 10 with normal power supply and a second logic gate 20 with bilateral voltage drop (reducing the power supply voltage of the second power supply terminal 21 and increasing the ground voltage of the second ground terminal 23) are alternately electrically connected. This can ensure a normal low-power working state when the high-low voltage swing logic gate alternating digital circuit 100 is in an ultra-low temperature environment. Therefore, when the digital circuit is in an ultra-low temperature environment, the overall power consumption of the circuit can be effectively reduced without almost damaging the circuit performance, achieving a higher dynamic voltage and frequency adjustment efficiency than the dynamic voltage and frequency adjustment method in the related art. Moreover, the invention can be manufactured by a mature transistor manufacturing process in the related art, has no special requirements for the process, and has a low area overhead cost.
[0037] Thus, the high-low voltage swing logic gate alternating digital circuit 100 of the embodiment of the present application is constructed by electrically connecting the first power supply terminal 11 of the first logic gate 10 to the first power line 30, the first ground terminal 13 of the first logic gate 10 to the first ground line 40, the second power supply terminal 21 of the second logic gate 20 to the second power line 50 having a supply voltage lower than the supply voltage of the first power line 30, and the second ground terminal 23 of the second logic gate 20 to the second ground line 60 having a ground voltage higher than the ground voltage of the first ground line 40. This structure fully utilizes the ultra-low temperature characteristics of the logic gate transistors, thus eliminating special manufacturing process requirements, reducing physical layout area overhead, and lowering production costs. Furthermore, when the digital circuit is in an ultra-low temperature environment, the overall power consumption of the circuit can be effectively reduced without compromising circuit performance, thereby achieving higher dynamic voltage and frequency adjustment efficiency than the dynamic voltage and frequency adjustment methods in the related art.
[0038] It can be understood that the embodiment of the present application can define the power consumption reduction per frequency reduction of the high-low voltage swing logic gate alternating digital circuit 100 in an ultra-low temperature environment as the dynamic voltage frequency scaling efficiency (DVFS efficiency), that is, DVFS efficiency = Δpower / Δfrequency, where Δpowe can represent the power consumption reduction amplitude, and Δfrequency can represent the frequency reduction amplitude.
[0039] like Figure 3 As shown in Figure 1, the transistor devices of the logic gate in the ultra-low temperature environment (4K) have higher turn-on voltage and lower turn-off current than those at room temperature (300K). Therefore, for digital circuits, the high and low levels of the logic gate output are determined by the on and off of the transistor device, and the on and off of the transistor device is determined by the voltage difference between the gate and drain of the transistor device (i.e., V GS ) determines that, at the same time, different V GS Also corresponds to different drain currents (I D ), generally speaking, the transistor device turn-on current (i.e. the transistor device I D ) is larger, the faster the logic gate flips, and the higher the performance of the entire digital circuit. The high and low input levels of the next stage signal (and the V applied to the transistor of the next stage logic gate circuit) G ) is the power supply voltage of the previous logic gate circuit (the previous V DD or V SS ), and from the dynamic and static power consumption formula of digital circuits: P dynamic =CV 2 f,P static = OFF V, P dynamic is the dynamic power consumption, α is the gate flip rate (the probability of logic gate flipping), C is the load capacitance of the logic gate, V is the voltage swing of the driving load capacitance (output high level minus output low level), f is the clock frequency of the digital circuit, P static is the static power consumption, I OFF is the off current (i.e., the I D ), it can be seen that if the voltage swing can be reduced, the dynamic power consumption can be reduced in a quadratic order. However, the voltage drop method of the digital circuit in the related art is to reduce the supply voltage of the power line and keep the ground voltage of the ground line at 0 to reduce the voltage swing and thus reduce the power consumption. The embodiment of the present application can achieve a double reduction in the voltage swing by adopting a bilateral voltage drop method of reducing the supply voltage of the power supply end of the logic gate and increasing the ground voltage of the ground end of the logic gate, without any additional increase in static power consumption (benefiting from the higher turn-on voltage and lower turn-off current I of the transistor device of the logic gate in the ultra-low temperature environment). OFF) at the same time, it can ensure that its flip speed is not reduced (because it has the same turn-on current I as the related technology voltage drop) ON ).
[0040] In some implementations, when there are multiple first logic gates 10 and second logic gates 20, the first logic gates 10 and the second logic gates 20 are electrically connected alternately. That is, when there are multiple first logic gates 10 and second logic gates 20 in the embodiment of the present application, the first logic gates 10 and the second logic gates 20 are electrically connected alternately. Figure 1 The structure of the alternating high and low voltage swing logic gate alternating digital circuit 100 constructed by alternately electrically connecting the gates can fully utilize the ultra-low temperature characteristics of the logic gate transistors themselves, thereby effectively reducing the overall power consumption of the circuit when the digital circuit is in an ultra-low temperature environment without compromising the circuit performance. This achieves a higher dynamic voltage and frequency adjustment efficiency than the dynamic voltage and frequency adjustment method in the related art, while facilitating the user to use a standard digital IC design process for design.
[0041] In some embodiments, the voltage swing of the first logic gate 10 is greater than the voltage swing of the second logic gate 20. Specifically, in the embodiments of the present application, by electrically connecting the first power terminal 11 of the first logic gate 10 to the first power line 30, the first ground terminal 13 of the first logic gate 10 to the first ground line 40, the second power terminal 21 of the second logic gate 20 to the second power line 50 having a supply voltage lower than the supply voltage of the first power line 30, and the second ground terminal 23 of the second logic gate 20 to the second ground line 60 having a ground voltage higher than the ground voltage of the first ground line 40, the voltage swing of the first logic gate 10 is greater than the voltage swing of the second logic gate 20, thereby constructing a high-low voltage swing logic gate alternating digital circuit 100. This circuit can effectively reduce the overall power consumption of the circuit by utilizing the ultra-low temperature characteristics of the logic gate transistors when the digital circuit is in an ultra-low temperature environment, achieving higher dynamic voltage and frequency adjustment efficiency than the dynamic voltage and frequency adjustment methods used in related arts.
[0042] See also Figure 1 In some embodiments, the high-low voltage swing logic gate alternating digital circuit 100 includes a first node L and a second node N. The first node L is respectively provided at the input end of the first logic gate 10 and the output end of the second logic gate 20. The second node N is respectively provided at the output end of the first logic gate 10 and the input end of the second logic gate 20. The voltage swing of the first node L is smaller than the voltage swing of the second node N.
[0043] That is, in the digital back-end process of designing the high-low voltage swing logic gate alternating digital circuit 100, the input end of the first logic gate 10 and the output end of the second logic gate 20 can be used as the first node L, and the output end of the first logic gate 10 and the input end of the second logic gate 20 can be used as the second node N to form the high-low voltage swing logic gate alternating digital circuit 100, thereby reducing the power consumption of the digital circuit as much as possible, effectively reducing the overall power consumption of the digital circuit in an ultra-low temperature environment, and achieving a higher dynamic voltage frequency adjustment efficiency than the dynamic voltage frequency adjustment method in the related art.
[0044] It should be noted that in the digital back-end process of designing the high-low voltage swing logic gate alternating digital circuit 100, the nodes with long wires and large fan-outs (long metal wires and large fan-outs mean that the load capacitance connected to the logic gate is large, such as the output nodes of the buffer and inverter in the clock network) of the high-low voltage swing logic gate alternating digital circuit 100 can be set as the first node L (i.e., driven by the logic gate powered by a lower voltage swing), and the nodes with short wires and small fan-outs (e.g., the output nodes of the series logic gates located close to the first node L) can be set as the second node N (i.e., driven by the logic gate powered by a normal voltage swing) to minimize the power consumption of the circuit.
[0045] See also Figure 4 In some embodiments, the first logic gate 10 includes a first transistor P1 and a second transistor N1. The second logic gate 20 includes a third transistor P2 and a fourth transistor N2. The source P11 of the first transistor is electrically connected to the first power line 30, the source N12 of the second transistor is electrically connected to the first ground line 40, the gate P13 of the first transistor is electrically connected to the gate N13 of the second transistor, the drain P12 of the first transistor is electrically connected to the drain N11 of the second transistor, and then electrically connected to the gate P21 of the third transistor and the gate N21 of the fourth transistor, respectively. The source P22 of the third transistor is electrically connected to the second power line 50, the drain P23 of the third transistor is electrically connected to the drain N22 of the fourth transistor, and the source N23 of the fourth transistor is electrically connected to the second ground line 60.
[0046] Specifically, in one embodiment, a high-low swing logic gate alternating digital circuit 100 includes a buffer as an example. The buffer may include a first logic gate 10 and a second logic gate 20. The first logic gate 10 may include a first transistor P1 and a second transistor N1. The second logic gate 20 may include a third transistor P2 and a fourth transistor N2. The source P11 of the first transistor may be electrically connected to the first power line 30, the source N12 of the second transistor may be electrically connected to the first ground line 40, the gate P13 of the first transistor may be electrically connected to the gate N13 of the second transistor, the drain P12 of the first transistor may be electrically connected to the drain N11 of the second transistor, and then to the gate P21 of the third transistor and the gate N21 of the fourth transistor, respectively. The source P22 of the third transistor may be electrically connected to the second power line 50, the drain P23 of the third transistor may be electrically connected to the drain N22 of the fourth transistor, and the source N23 of the fourth transistor may be electrically connected to the second ground line 60.
[0047] It should be noted that the connection point after the gate P13 of the first transistor and the gate N13 of the second transistor are electrically connected can be set to the first node L (that is, the first node L can serve as a buffer or the input node of the first logic gate 10). The drain P12 of the first transistor can be electrically connected to the drain N11 of the second transistor, and the connection point after they are electrically connected to the gate P21 of the third transistor and the gate N21 of the fourth transistor can be set to the second node N (that is, the second node N can serve as the output node of the first logic gate 10 and the input node of the second logic gate 20). The drain P23 of the third transistor and the drain N22 of the fourth transistor can be electrically connected to the first node L (that is, the first node L can serve as the output node of the buffer or the second logic gate 20).
[0048] Furthermore, if Figure 4 As shown, at this time, the first logic gate 10 is powered by a normal voltage swing range (V DD，NOM -V SS ), the output level is V DD，NOM or V SS The second logic gate 20 is powered by a double-side voltage drop voltage swing range (V DDL -V SSL ), the output level is V DDL or V SSL At ultra-low temperatures, for the first transistor P1 and the second transistor N1 constituting the first logic gate 10, the turn-off voltage may be ΔV, and the turn-on voltage may be V DD，NOM -ΔV, at this time according to Figure 3From the voltage-current curve of the transistor device shown in FIG. 1 , it can be seen that when ΔV is not large, the turn-off voltage and turn-on voltage can effectively turn off and turn on the first transistor P1 and the second transistor N1. For the third transistor P2 and the fourth transistor N2 constituting the second logic gate 20, the turn-off voltage can be -ΔV, and the turn-on voltage can be V DD，NOM -ΔV, at this time according to Figure 3 As shown in the voltage-current curve of the transistor device, when ΔV is not large, the turn-off voltage and the turn-on voltage can effectively turn off and turn on the third transistor P2 and the fourth transistor N2.
[0049] In addition, in addition to Figure 4 In addition to the buffers exemplified in the embodiment of the present application, Figure 5 The diagram also illustrates several standard cell implementations (including but not limited to Figure 5 It should be noted that the black logic gate may represent the first logic gate 10 in the voltage swing range without voltage reduction, and the gray logic gate may represent the second logic gate 20 in the voltage swing range after adopting the double-side voltage reduction method.
[0050] In some embodiments, the load capacitance at the first node L is greater than the load capacitance at the second node N. That is, because circuit power consumption is related to the voltage swing and the load capacitance, the embodiments of the present application set the load capacitance at the first node L to be greater than the load capacitance at the second node N, so that the constructed high-low voltage swing logic gate alternating digital circuit 100 can achieve better power consumption reduction. That is, when the load capacitance at the first node L is greater than the load capacitance at the second node N, the power consumption reduction effect achieved by the voltage drop method is better.
[0051] In some embodiments, the number of logic gates in the high-low voltage swing alternating logic gate digital circuit 100 is an even number. That is, in the embodiments of the present application, the number of logic gates is designed to be an even number when constructing a standard cell of the high-low voltage swing alternating logic gate digital circuit 100. This maximizes the low power consumption advantage of the double-side voltage drop approach while facilitating user design using standard digital IC design processes.
[0052] It should be noted that the number of logic gates of the high-low voltage swing logic gate alternating digital circuit 100 can also be an odd number. That is, when the number of logic gates of the high-low voltage swing logic gate alternating digital circuit 100 is an odd number, when the first logic gate 10 and the second logic gate 20 are alternately arranged, a small number (the fewer the better) of first logic gates 10 connected to the first logic gate 10 can be interspersed in the middle of the high-low voltage swing logic gate alternating digital circuit 100 to form a high-low voltage swing logic gate alternating digital circuit 100 with an odd number of logic gates.
[0053] This application also provides a quantum computing device. The quantum computing device includes the aforementioned digital circuit 100 with alternating high- and low-voltage swing logic gates. The specific structure of the digital circuit 100 with alternating high- and low-voltage swing logic gates is as described above and will not be further described here for the sake of brevity. It should be noted that the quantum computing device can be, for example, a quantum computer, without limitation.
[0054] In this way, the quantum computing device of the embodiment of the present application constructs a high-low voltage swing logic gate alternating digital circuit 100 structure by electrically connecting the first power supply terminal 11 of the first logic gate 10 to the first power line 30 and the first ground terminal 13 of the first logic gate 10 to the first ground line 40, and electrically connecting the second power supply terminal 21 of the second logic gate 20 to the second power line 50 having a supply voltage lower than the supply voltage of the first power line 30, and electrically connecting the second ground terminal 23 of the second logic gate 20 to the second ground line 60 having a ground voltage higher than the ground voltage of the first ground line 40. This structure fully utilizes the ultra-low temperature characteristics of the logic gate transistors themselves, and thus has no special requirements for process manufacturing, has a small area overhead for the physical layout, and has low production costs. At the same time, when the digital circuit is in an ultra-low temperature environment, the overall power consumption of the circuit can be effectively reduced without compromising the circuit performance, thereby achieving a higher dynamic voltage and frequency adjustment efficiency than the dynamic voltage and frequency adjustment method in the related art.
[0055] See also Figure 6 The present application also provides a voltage reduction method for the aforementioned high-low voltage swing logic gate alternating digital circuit 100, the voltage reduction method comprising:
[0056] 01: Lower the power supply voltage of the second power line and increase the ground voltage of the second ground line.
[0057] See also Figure 7 The present application further provides a controller 200. The controller 200 includes a voltage drop module 210. The voltage drop module 210 is configured to execute step 01. That is, the voltage drop module 210 is configured to lower the supply voltage of the second power line 50 and to increase the ground voltage of the second ground line 60.
[0058] Specifically, when the high-low voltage swing logic gate alternating digital circuit 100 is in an ultra-low temperature environment, the supply voltage of the second power line 50 can be lowered and the ground voltage of the second ground line 60 can be increased, so that the voltage swing of the second logic gate 20 is smaller than the voltage swing of the first logic gate 10. The high-low voltage swing logic gate alternating digital circuit 100 structure is constructed, and the ultra-low temperature characteristics of the logic gate transistor itself are fully utilized. Therefore, there are no special requirements for process manufacturing, the area overhead of the physical layout is small, and the production cost is low. At the same time, when the digital circuit is in an ultra-low temperature environment, the overall power consumption of the circuit can be effectively reduced without almost damaging the circuit performance, thereby achieving a higher dynamic voltage and frequency adjustment efficiency than the dynamic voltage and frequency adjustment method in the related art.
[0059] In this way, the voltage drop method of the embodiment of the present application constructs a high-low voltage swing logic gate alternating digital circuit 100 by electrically connecting the first power supply terminal 11 of the first logic gate 10 to the first power line 30, the first ground terminal 13 of the first logic gate 10 to the first ground line 40, the second power supply terminal 21 of the second logic gate 20 to the second power line 50 having a supply voltage lower than the supply voltage of the first power line 30, and the second ground terminal 23 of the second logic gate 20 to the second ground line 60 having a ground voltage higher than the ground voltage of the first ground line 40. This method fully utilizes the ultra-low temperature characteristics of the logic gate transistors themselves, thus eliminating special manufacturing process requirements, reducing physical layout area overhead, and lowering production costs. Furthermore, when the digital circuit is in an ultra-low temperature environment, the overall power consumption of the circuit can be effectively reduced without compromising circuit performance, thereby achieving higher dynamic voltage and frequency adjustment efficiency than the dynamic voltage and frequency adjustment method in the related art.
[0060] See also Figure 7 The present application further provides a controller 200 for use in the aforementioned high-low voltage swing logic gate alternating digital circuit 100. The specific controller 200 is as described above, and for the sake of brevity, it will not be described here in detail.
[0061] In this way, the controller 200 of the embodiment of the present application constructs a high-low voltage swing logic gate alternating digital circuit 100 structure by electrically connecting the first power supply terminal 11 of the first logic gate 10 to the first power line 30, the first ground terminal 13 of the first logic gate 10 to the first ground line 40, the second power supply terminal 21 of the second logic gate 20 to the second power line 50 having a supply voltage lower than the supply voltage of the first power line 30, and the second ground terminal 23 of the second logic gate 20 to the second ground line 60 having a ground voltage higher than the ground voltage of the first ground line 40. This structure fully utilizes the ultra-low temperature characteristics of the logic gate transistors themselves, and thus has no special requirements for process manufacturing, with a small physical layout area overhead and low production cost. At the same time, when the digital circuit is in an ultra-low temperature environment, the overall power consumption of the circuit can be effectively reduced without compromising the circuit performance, thereby achieving a higher dynamic voltage and frequency adjustment efficiency than the dynamic voltage and frequency adjustment method in the related art.
[0062] The above embodiments merely illustrate several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.
Claims
1. A high-low voltage swing logic gate alternating digital circuit, characterized in that: The high-low voltage swing logic gate alternating digital circuit comprises: First logic gate; a second logic gate, the first logic gate being electrically connected to the second logic gate; a first power line and a first ground line, the first logic gate including a first power terminal and a first ground terminal, the first power terminal being electrically connected to the first power line, and the first ground terminal being electrically connected to the first ground line; and A second power line and a second ground line, the second logic gate includes a second power terminal and a second ground terminal, the second power terminal is electrically connected to the second power line, the second ground terminal is electrically connected to the second ground line, the supply voltage of the first power line is greater than the supply voltage of the second power line, and the ground voltage of the second ground line is greater than the ground voltage of the first ground line.
2. The high-low voltage swing logic gate alternating digital circuit according to claim 1, characterized in that: When there are plural first logic gates and plural second logic gates, the first logic gates and the second logic gates are electrically connected alternately.
3. The high-low voltage swing logic gate alternating digital circuit according to claim 1, wherein: A voltage swing of the first logic gate is greater than a voltage swing of the second logic gate.
4. The high-low voltage swing logic gate alternating digital circuit according to claim 1, wherein: The high-low voltage swing logic gate alternating digital circuit includes a first node and a second node, the first node is respectively set at the input end of the first logic gate and the output end of the second logic gate, the second node is respectively set at the output end of the first logic gate and the input end of the second logic gate, and the voltage swing of the first node is smaller than the voltage swing of the second node.
5. The high-low voltage swing logic gate alternating digital circuit according to claim 4, characterized in that: The first logic gate includes a first transistor and a second transistor, and the second logic gate includes a third transistor and a fourth transistor. The source of the first transistor is electrically connected to the first power line, the source of the second transistor is electrically connected to the first ground line, the gate of the first transistor is electrically connected to the gate of the second transistor, the drain of the first transistor is electrically connected to the drain of the second transistor and then electrically connected to the gate of the third transistor and the gate of the fourth transistor respectively, the source of the third transistor is electrically connected to the second power line, the drain of the third transistor is electrically connected to the drain of the fourth transistor, and the source of the fourth transistor is electrically connected to the second ground line.
6. The high-low voltage swing logic gate alternating digital circuit according to claim 4, characterized in that: The load capacitance at the first node is greater than the load capacitance at the second node.
7. The high-low voltage swing logic gate alternating digital circuit according to claim 1, wherein: The number of logic gates in the high-low voltage swing logic gate alternating digital circuit is an even number.
8. A quantum computing device, characterized in that The quantum computing device comprises the high-low voltage swing logic gate alternating digital circuit according to any one of claims 1 to 7.
9. A voltage drop method for use in the high-low voltage swing logic gate alternating digital circuit according to any one of claims 1 to 7, characterized in that: The pressure drop method includes: The supply voltage of the second power line is lowered, and the ground voltage of the second ground line is increased.
10. A controller for use in the high-low voltage swing logic gate alternating digital circuit according to any one of claims 1 to 7, characterized in that: The controller includes a voltage drop module, which is used to lower the supply voltage of the second power line and increase the ground voltage of the second ground line.