Control method and device of power factor correction circuit, equipment and medium

Abstract

The embodiment of the invention provides a control method of a power factor correction circuit. The method comprises the following steps: determining a plurality of sampling points of a conduction time period and a plurality of sampling points of a turn-off time period of a pulse width modulation signal of a current period; a plurality of sampling points of the turn-on time period and the turn-off time period do not coincide with the rising edge moment and the falling edge moment of the pulse width modulation signal; and acquiring the inductive current of the power factor correction circuit at the plurality of sampling points, and determining the pulse width modulation signal of the next period according to the acquired inductive current of the power factor correction circuit. According to the embodiment of the invention, a plurality of sampling points are arranged in the turn-on period and the turn-off period of the pulse width modulation signal, and the sampling points do not coincide with the rising edge moment and the falling edge moment of the pulse width modulation signal, so that the sampled current value is closer to the real inductive current, and the control effect of the PFC circuit can be improved.

Description

Technical Field

[0001] The present invention relates to the field of circuit control technology, and in particular to a current sampling method, device, electronic device and computer-readable storage medium for a power factor correction circuit. Background Art

[0002] When AC power is connected to electrical devices from the grid, it must first be rectified to convert it into DC power that the devices can directly use. This process is usually performed by a switching power supply. During this conversion process, harmonic currents are generated, causing harmonic pollution to the grid and reducing the system's power factor. To reduce harmonic pollution and maximize energy utilization, power factor correction (PFC) circuits are often used to implement power factor correction. By synchronizing the input current waveform with the voltage waveform, this reduces reactive power and harmonic interference, thereby improving energy utilization efficiency.

[0003] A PFC circuit typically consists of a rectifier bridge, a boost inductor, and power switching devices. Average current control is currently the most popular control method in PFC circuits. This method achieves high power factor and low harmonic distortion by real-time monitoring and adjustment of the inductor current, ensuring that its instantaneous value closely follows the input voltage waveform. Because the current contains a considerable amount of switching ripple and high-frequency switching noise, accurate current sampling is crucial for PFC control stability. Currently, the average current is typically sampled at the midpoint of the on-time or off-time of the power device under pulse-width modulation (PWM) control.

[0004] When the inductor current of the PFC circuit is intermittent or the duty cycle is small, the current value at the middle moment of the power device's on period or off period deviates greatly from the average current value, resulting in poor control effect of the PFC circuit. Summary of the Invention

[0005] In view of the above problems, embodiments of the present invention are proposed to provide a control method, device, electronic device and computer-readable storage medium for a power factor correction circuit that overcome the above problems or at least partially solve the above problems.

[0006] In one aspect, an embodiment of the present invention provides a control method for a power factor correction circuit, wherein the power factor correction circuit includes a switch module, wherein the switch module is configured to respond to a pulse width modulation signal, and the method includes:

[0007] Determining a plurality of sampling points of an on-period of a pulse width modulation signal of a current cycle, and determining a plurality of sampling points of an off-period of the pulse width modulation signal of the current cycle; wherein the plurality of sampling points of the on-period and the plurality of sampling points of the off-period do not coincide with a rising edge time or a falling edge time of the pulse width modulation signal;

[0008] collecting the inductor current of the power factor correction circuit at a plurality of sampling points in the on-time period and a plurality of sampling points in the off-time period;

[0009] The inductor current of the power factor correction circuit is collected according to multiple sampling points in the on period and multiple sampling points in the off period, and a pulse width modulation signal of the next cycle is determined and input into the switch module.

[0010] Optionally, determining a plurality of sampling points of an on-period of the pulse width modulation signal of the current cycle, and determining a plurality of sampling points of an off-period of the pulse width modulation signal of the current cycle, comprises:

[0011] Get the duty cycle of the pulse width modulation signal of the current cycle;

[0012] determining an on-period of the pulse width modulation signal of the current cycle and an off-period of the pulse width modulation signal of the current cycle according to a duty cycle of the pulse width modulation signal of the current cycle;

[0013] determining a plurality of sampling points during the conduction period;

[0014] A plurality of sampling points of the off period are determined.

[0015] Optionally, determining the on-time period of the pulse width modulation signal of the current cycle according to the duty cycle of the pulse width modulation signal of the current cycle includes:

[0016] Align the centers of the pulse width modulation signal of the first half cycle with the pulse width modulation signal of the second half cycle, count in an increasing manner in the first half cycle, and count in a decreasing manner in the second half cycle;

[0017] determining a first count value according to a duty cycle of the pulse width modulation signal of the current cycle;

[0018] determining a first time point when the first count value is reached by counting in an incremental manner in the first half cycle;

[0019] determining a second time point when counting in a decremental manner in the second half cycle reaches the first count value;

[0020] Determining a time period between the second time point and the first time point as a conduction period;

[0021] Optionally, determining the off period of the pulse width modulation signal of the current cycle includes:

[0022] determining a third time point at which counting starts in the first half cycle, and determining a fourth time point at which counting ends in the second half cycle;

[0023] A time period between the first time point and the third time point, and a time period between the fourth time point and the second time point are determined as an off period.

[0024] Optionally, determining a plurality of sampling points of the conduction period includes:

[0025] A first sampling point, a second sampling point, and a third sampling point of the conduction period are determined, wherein the first sampling point, the second sampling point, and the third sampling point equally divide the conduction period.

[0026] Optionally, determining a plurality of sampling points of the shutdown period includes:

[0027] Determine the starting point of the first off period as the fourth sampling point, and determine the midpoint of the first off period as the fifth sampling point; the first off period is the time period between the first time point and the third time point;

[0028] The midpoint of the second off period is determined to be the sixth sampling point; the second off period is a time period between the fourth time point and the second time point.

[0029] Optionally, the determining of the pulse width modulation signal of the next cycle by collecting the inductor current of the power factor correction circuit according to multiple sampling points in the on-time period and multiple sampling points in the off-time period includes:

[0030] The sampling point whose time interval with the rising edge of the pulse width modulation signal is greater than or equal to a preset threshold, and the sampling point whose time interval with the falling edge of the pulse width modulation signal is greater than or equal to a preset threshold are used as valid sampling points;

[0031] A pulse width modulation signal of the next cycle is determined according to the inductor current of the power factor correction circuit collected at the effective sampling point.

[0032] Optionally, the power factor correction circuit includes an acquisition module;

[0033] The collecting of the inductor current of the power factor correction circuit at multiple sampling points in the on-time period and multiple sampling points in the off-time period includes:

[0034] A sampling trigger signal is determined based on the multiple sampling points of the on-time period and the multiple sampling points of the off-time period and is input into the acquisition module; the acquisition module is used to respond to the sampling trigger signal to acquire the inductor current of the power factor correction circuit.

[0035] Optionally, the determining of the pulse width modulation signal of the next cycle by collecting the inductor current of the power factor correction circuit according to multiple sampling points in the on-time period and multiple sampling points in the off-time period includes:

[0036] Determining an average inductor current by sampling the inductor current of the power factor correction circuit at multiple sampling points during the on-time period and multiple sampling points during the off-time period;

[0037] A pulse width modulation signal of a next cycle is determined according to the average inductor current.

[0038] On the other hand, an embodiment of the present invention provides a control device for a power factor correction circuit, the device comprising:

[0039] a sampling point determination module, configured to determine a plurality of sampling points in an on-period of a pulse width modulation signal of a current cycle, and to determine a plurality of sampling points in an off-period of the pulse width modulation signal of the current cycle; wherein the plurality of sampling points in the on-period and the plurality of sampling points in the off-period do not coincide with a rising edge moment and a falling edge moment of the pulse width modulation signal;

[0040] a current acquisition module, configured to acquire the inductor current of the power factor correction circuit at a plurality of sampling points during the on-time period and a plurality of sampling points during the off-time period;

[0041] A signal determination module is used to determine the pulse width modulation signal of the next cycle and input it into the switch module based on the inductor current of the power factor correction circuit collected at multiple sampling points during the conduction period and multiple sampling points during the off period; the switch module is used to respond to the pulse width modulation signal.

[0042] On the other hand, an embodiment of the present invention provides an electronic device comprising: a processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein the computer program, when executed by the processor, implements the steps of the control method of the power factor correction circuit as described above.

[0043] On the other hand, an embodiment of the present invention provides a computer-readable storage medium storing a computer program, which implements the steps of the control method of the power factor correction circuit as described above when executed by a processor.

[0044] The embodiments of the present invention include the following advantages:

[0045] The present embodiment first determines multiple sampling points during the on-time period and the off-time period of the pulse-width modulation signal in the current cycle. These sampling points do not coincide with the rising or falling edges of the pulse-width modulation signal. The inductor current is then sampled at these sampling points during the on-time period and the off-time period, and the pulse-width modulation signal for the next cycle is determined based on these inductor currents, thereby achieving continuous regulation of the inductor current. Because current oscillations occur at both the rising and falling edges of the pulse-width modulation signal, avoiding these edges for sampling improves the accuracy of the sampled current. Furthermore, by performing multiple samplings during both the on-time period and the off-time period of the pulse-width modulation signal, the current value determined from the sampled current is closer to the actual inductor current, thereby improving the control effect of the PFC circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. Those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0047] Figure 1 This is a flowchart of a method for controlling a power factor correction circuit provided by an embodiment of the present invention;

[0048] Figure 2 This is a power factor correction circuit diagram provided by an embodiment of the present invention;

[0049] Figure 3 This is a timing diagram of a control method for a power factor correction circuit provided by an embodiment of the present invention;

[0050] Figure 4 is a timing diagram of another control method for a power factor correction circuit provided by an embodiment of the present invention;

[0051] Figure 5 This is a structural block diagram of a control device for a power factor correction circuit provided by an embodiment of the present invention.

[0052] The accompanying drawings are as follows:

[0053] 21: AC power supply; 22: diode rectifier bridge; 23: PFC inductor; 24: fast recovery diode; 25: capacitor; 26: switch module; 27: sampling resistor. DETAILED DESCRIPTION

[0054] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0055] PFC circuits are commonly used in electrical equipment to implement power factor correction (PFC). By synchronizing the input current waveform with the voltage waveform, they reduce reactive power and harmonic interference, thereby improving energy efficiency. PFC circuits typically achieve high power factor and low harmonic distortion by real-time monitoring and adjusting the inductor current so that its instantaneous value closely matches the input voltage waveform. Currently, the inductor current is typically sampled midway between the on-time and off-time periods of the PWM-controlled power device, taking the average current as the sampled value. If the inductor current in a PFC circuit exhibits intermittent behavior, the current value midway between the on-time and off-time periods of the power device can deviate significantly from the average current value. Sampling the current value at this time can result in poor PFC circuit control.

[0056] The present invention sets multiple sampling points in both the on-period and the off-period of the pulse width modulation signal, and none of the sampling points are located at the rising edge moment (turn-on moment) and the falling edge moment (turn-off moment) of the pulse width modulation signal. This allows for multiple sampling in both the on-period and the off-period, and reduces the interference of current oscillations generated by the power device switches on the sampled current, so that the current value determined based on the sampled current is closer to the actual inductor current, thereby improving the control effect of the PFC circuit.

[0057] Figure 1 This is a flowchart of a control method for a power factor correction circuit provided by an embodiment of the present invention.

[0058] like Figure 1 As shown, the method may specifically include the following steps:

[0059] Step 101: determining a plurality of sampling points of an on-period of a pulse width modulation signal of a current cycle, and determining a plurality of sampling points of an off-period of the pulse width modulation signal of the current cycle; wherein the plurality of sampling points of the on-period and the plurality of sampling points of the off-period do not coincide with a rising edge moment and a falling edge moment of the pulse width modulation signal;

[0060] Figure 2 This is a power factor correction circuit diagram provided by an embodiment of the present invention.

[0061] like Figure 2As shown, AC power 21 is converted to DC by a diode rectifier bridge 22, and then charges capacitor 25 through a PFC inductor 23 and a fast recovery diode 24. A control unit (such as an MCU, not shown) samples the inductor current, capacitor voltage, and input voltage of the PFC circuit through a sampling resistor 27. A control algorithm generates a PWM signal to drive a switch module 26 (such as an IGBT) on and off, thereby regulating the inductor current so that its instantaneous value strictly follows the sinusoidal absolute value waveform of the input voltage, achieving a high power factor and low harmonic distortion.

[0062] Since the on and off of the switch module is driven and controlled by the PWM signal generated by the control unit, the rising and falling edge moments of the PWM signal correspond to the on and off moments of the switch module. There are voltage spikes and ringing noise at the on and off moments, and the current is in an unstable state during the switching transient. Therefore, setting the sampling point at the rising and falling edge moments can ensure that the sampled value reflects the actual inductor current.

[0063] At the same time, multiple sampling is performed during the on-time and off-time periods, which can capture the rise and decay changes of the current to a greater extent, avoid the current estimation deviation caused by a single sampling point, and make the current value determined based on the sampled current closer to the actual inductor current, thereby improving the control effect of the PFC circuit.

[0064] It's worth noting that the PWM signal and sampling points for each cycle are calculated and determined in the previous cycle. In the current cycle, the inductor current is regulated based on the PWM signal determined in the previous cycle. The inductor current is sampled based on the sampling points determined in the previous cycle. The PWM signal and sampling points for the next cycle are then calculated based on the sampled inductor current, enabling continuous detection and regulation of the inductor current.

[0065] In some embodiments, step 101 specifically includes the following sub-steps:

[0066] Sub-step S11, obtaining the duty cycle of the pulse width modulation signal of the current cycle;

[0067] Duty cycle refers to the ratio of the time a signal is at a high level to the total cycle time within a cycle, usually expressed as a percentage. As an example, if a PWM signal has a period of 10 milliseconds and a duty cycle of 50%, the PWM signal is at a high level for 5 milliseconds.

[0068] In some embodiments, the duty cycle of the pulse width modulation signal in the current cycle is obtained by calculating the inductor current collected in the previous cycle through the PFC control parameters.

[0069] The duty cycle of the PWM signal in each cycle is calculated based on the previous cycle, thus determining the PWM signal for the current cycle. The duty cycle of the PWM signal for the next cycle is then determined based on the inductor current in the current cycle, further determining the PWM signal for the next cycle. This cycle continuously detects the inductor current and generates a PWM signal based on the detected inductor current to regulate the inductor current.

[0070] Sub-step S12, determining an on-period of the pulse width modulation signal of the current cycle and an off-period of the pulse width modulation signal of the current cycle according to the duty cycle of the pulse width modulation signal of the current cycle;

[0071] The on-period is the time period during each PWM cycle when the signal remains high, and the switch module is in the on state. This period can be directly determined based on the duty cycle and cycle time. The off-period is the time period during each PWM cycle when the signal remains low, and the switch module is in the off state. This period can also be directly determined based on the duty cycle and cycle time.

[0072] In some embodiments, sub-step S12 specifically includes the following sub-steps:

[0073] Align the centers of the pulse width modulation signal of the first half cycle with the pulse width modulation signal of the second half cycle, count in an increasing manner in the first half cycle, and count in a decreasing manner in the second half cycle;

[0074] Determining a first count value based on a duty cycle of the pulse width modulation signal of the current cycle; determining a first time point when the first count value is reached by counting in an incremental manner in the first half cycle; and determining a second time point when the first count value is reached by counting in a decremental manner in the second half cycle;

[0075] The time period between the second time point and the first time point is determined as the on-time period.

[0076] In one practical application scenario, an MCU is configured to sample the PFC circuit inductor current and other parameters through a sampling resistor, generating a PWM signal to turn the IGBT on and off. The MCU timer is configured in center-aligned mode.

[0077] Figure 3 A timing diagram of a control method for a power factor correction circuit provided by an embodiment of the present invention.

[0078] like Figure 3 As shown in the figure, from top to bottom are the PWM signal timing diagram and the MCU timer timing diagram.

[0079] By configuring the MCU timer in center-aligned mode, the switching behavior of the PWM waveform becomes symmetrical about the center of the timer's counting cycle. That is, the PWM signal's upper and lower half cycles are center-aligned, with the count increasing in the upper half cycle until the timer reaches its maximum count value, and then decreasing in the lower half cycle until it reaches 0.

[0080] The rising and falling edges of the PWM waveform are triggered at the same count value in the increasing and decreasing phases, respectively, forming a centrally symmetrical waveform. Figure 3 In the example, the timer count value is equal to the PWM waveform flip at the moment of CCR1, that is, at t on The PWM signal is turned on at t off The PWM signal is turned off at this moment.

[0081] Therefore, the first count value CCR1 is determined according to the duty cycle of the pulse width modulation signal in the current cycle. Thus, the first time point t when the first count value CCR1 is reached by counting in an incremental manner in the first half cycle is determined. on , determine the second time point t when the count reaches the first count value CCR1 in a decrement manner in the second half cycle off , finally determine t on to t off The time period between is the on-time period.

[0082] The first count value CCR1 is determined by the PFC voltage loop and the current loop according to the duty cycle and the timer period value.

[0083] In some embodiments, sub-step S12 specifically includes the following sub-steps:

[0084] Determine a third time point at which counting starts in the upper half cycle, and determine a fourth time point at which counting ends in the lower half cycle; determine the time period between the first time point and the third time point, and the time period between the fourth time point and the second time point as the off period.

[0085] As mentioned above, Figure 3 The PWM waveform flips when the timer count value is equal to CCR1, that is, at t on The PWM signal is turned on at t off The PWM signal is turned off at the moment. Thus, the third time point t0 at which counting starts in the first half cycle is determined, and the fourth time point t1 at which counting ends in the second half cycle is determined. T , thus determining t on The time period between t and t0, and t T With t off The time period between is the off period.

[0086] Sub-step S13, determining a plurality of sampling points during the conduction period;

[0087] Determining multiple sampling points during the conduction period can play an important role in accurately controlling the output signal. Through multiple sampling points, the waveform characteristics of the inductor current can be captured more carefully, a more accurate current value can be determined, and the inductor current can be adjusted more precisely.

[0088] In some embodiments, sub-step S13 specifically includes the following sub-steps:

[0089] A first sampling point, a second sampling point, and a third sampling point of the conduction period are determined, wherein the first sampling point, the second sampling point, and the third sampling point equally divide the conduction period.

[0090] Figure 4 A timing diagram of another power factor correction circuit control method provided by an embodiment of the present invention. From top to bottom, the inductor current timing diagram for discontinuous current, the inductor current timing diagram for continuous current, the PWM signal timing diagram, and the MCU timer timing diagram.

[0091] like Figure 4 As shown, the first sampling point t2, the second sampling point t3 and the third sampling point t4 of the conduction period are determined. The first sampling point t2, the second sampling point t3 and the third sampling point t4 evenly divide the conduction period t on to t off , that is, the first sampling point t2, the second sampling point t3 and the third sampling point t4 are all quarter-divided points of the conduction period.

[0092] As an example, in order to determine the quarter-division points of the conduction period, the MCU timer is configured to be in center alignment mode, and the maximum value of the timer count is Tp.

[0093] Since in center-aligned mode, the switching action of the PWM waveform will be symmetrical with the center of the counting cycle. Therefore, the timer counts to the maximum value T p The midpoint of the PWM on-time period is the quarter-division point in the middle of the on-time period (the second sampling point t3 ).

[0094] The count value CCR2 is determined according to the following formula:

[0095]

[0096] Among them, CCR1 corresponds to the PWM waveform flip time t on and t off , Tp is the maximum value of the timer count, corresponding to the midpoint t3 of the conduction period, CCR2 corresponds to time t2 and time t4. According to the formula, the time t2 corresponding to CCR2 is ton The midpoint of t3 and time t4 is t3~t off That is, time t2 and time t4 are both quarter-division points of the conduction period.

[0097] The count value CCR2 is determined by the above formula, thereby determining the other two quarter-division points of the conduction period, and finally determining the first sampling point t2 and the third sampling point t4.

[0098] In the center alignment mode, by determining the count value CCR1 and the count value CCR2, the sampling points of the evenly divided conduction period can be determined simply and quickly, so that the sampling can be uniformly performed during the conduction period, and Figure 4 As shown in the figure, in both the discontinuous current case and the continuous current case, the corresponding inductor current can be collected by determining the sampling points determined by the count values ​​CCR1 and CCR2, thereby capturing the changing characteristics of the inductor current corresponding to the PWM conduction period, further improving the sampling accuracy of the inductor current.

[0099] Sub-step S14: determining a plurality of sampling points in the shutdown period.

[0100] Determining multiple sampling points during the conduction period can play an important role in accurately controlling the output signal. Through multiple sampling points, the waveform characteristics of the inductor current can be captured more carefully, a more accurate current value can be determined, and the inductor current can be adjusted more precisely.

[0101] In some embodiments, sub-step S14 specifically includes the following sub-steps:

[0102] Determine the starting point of the first off period as the fourth sampling point, and determine the midpoint of the first off period as the fifth sampling point; the first off period is the time period between the first time point and the third time point;

[0103] The midpoint of the second off period is determined to be the sixth sampling point; the second off period is a time period between the fourth time point and the second time point.

[0104] like Figure 4 As shown, the first off period is t on The time period between t0 and t1, the second off period is t2 T With t off The starting point of the first off period is determined as the fourth sampling point t0, the midpoint of the first off period is determined as the fifth sampling point t1, and the midpoint of the second off period is determined as the sixth sampling point t5.

[0105] As an example, in order to determine the above sampling points, configure the MCU timer to center alignment mode, the maximum timer count is Tp, and the PWM waveform flip time t on and t off Corresponding count value CCR1.

[0106] The count value CCR3 is determined according to the following formula:

[0107]

[0108] Among them, CCR1 corresponds to the PWM waveform flip time t on and t off According to the formula, the time t1 corresponding to CCR3 is the first off period t on The midpoint of t0 and time t5 is the second off period t T ~t off midpoint.

[0109] The count value CCR3 is determined by the above formula, thereby determining the midpoint of the first off period and the midpoint of the second off period, and finally determining the fifth sampling point t1 and the sixth sampling point t5.

[0110] In the center alignment mode, by determining the count value CCR1 and the count value CCR3, the uniform sampling points on the off period can be determined simply and quickly, so that uniform sampling can be achieved during the off period, and Figure 4 As shown in the figure, in both the discontinuous current case and the continuous current case, the corresponding inductor current can be collected by determining the sampling points determined by the count values ​​CCR1 and CCR3, thereby capturing the changing characteristics of the inductor current corresponding to the PWM off period, further improving the sampling accuracy of the inductor current.

[0111] Step 102: collecting the inductor current of the power factor correction circuit at a plurality of sampling points during the on-time period and a plurality of sampling points during the off-time period;

[0112] As an example, the inductor current of the power factor correction circuit is collected at the first sampling point t2 of the conduction period to obtain current i2; the inductor current of the power factor correction circuit is collected at the second sampling point t3 to obtain current i3; and the inductor current of the power factor correction circuit is collected at the third sampling point t4 to obtain current i4.

[0113] At a fourth sampling point t0 during the off period, the inductor current of the power factor correction circuit is collected to obtain a current i0; at a fifth sampling point t1, the inductor current of the power factor correction circuit is collected to obtain a current i1; and at a sixth sampling point t5, the inductor current of the power factor correction circuit is collected to obtain a current i5.

[0114] In some embodiments, the power factor correction circuit includes a collection module, and the collection module is used to respond to a sampling trigger signal to collect the inductor current of the power factor correction circuit.

[0115] In some embodiments, step 102 includes the following sub-steps:

[0116] Sub-step S21 : determining a sampling trigger signal according to the multiple sampling points in the on-period and the multiple sampling points in the off-period, and inputting the signal into the acquisition module.

[0117] After the sampling point is determined according to the pulse width modulation signal in step 101, a sampling trigger signal is generated according to the determined sampling point, and the sampling trigger signal is input into the acquisition module at the sampling point, so that the acquisition module responds to the sampling trigger signal to complete the inductor current acquisition operation of the power factor correction circuit.

[0118] As an example, the MCU's timer module includes channels 1, 2, and 3. Timer channel 1 outputs a PWM signal to drive the IGBT (switch module), while timer channels 2 and 3 trigger ADC sampling (sampling trigger signal). After determining the sampling point, timer channels 2 and 3 are configured to trigger the ADC sampling at the sampling point, and the inductor current of the power factor correction circuit is collected through the sampling resistor (acquisition module).

[0119] Step 103: determining a pulse width modulation signal for the next cycle based on the inductor current of the power factor correction circuit collected at multiple sampling points during the on-time period and multiple sampling points during the off-time period, and inputting the pulse width modulation signal into the switch module;

[0120] In some embodiments, based on the inductor current of the power factor correction circuit collected at multiple sampling points in the conduction period and multiple sampling points in the off period, the duty cycle of the pulse width modulation signal of the next cycle is first determined, and then the pulse width modulation signal of the next cycle is determined based on the duty cycle of the pulse width modulation signal of the next cycle.

[0121] The duty cycle of the pulse width modulation signal in each cycle is calculated based on the previous cycle, thereby determining the pulse width modulation signal for the current cycle. This pulse width modulation signal is then input into the switching module of the PFC circuit, causing the switching module to respond to the pulse width modulation signal to regulate the inductor current in the current cycle. The inductor current of the current cycle is then collected and the duty cycle of the pulse width modulation signal for the next cycle is determined based on the inductor current of the current cycle, thereby determining the pulse width modulation for the next cycle. This cycle is repeated continuously, thereby continuously detecting the inductor current and generating a pulse width modulation signal based on the detected inductor current to continuously regulate the inductor current.

[0122] In some embodiments, step 103 specifically includes the following sub-steps:

[0123] Sub-step S31, taking the sampling points whose time intervals with the rising edge of the pulse width modulation signal are greater than or equal to a preset threshold, and the sampling points whose time intervals with the falling edge of the pulse width modulation signal are greater than or equal to the preset threshold, as valid sampling points;

[0124] Since current oscillation occurs at the rising and falling edges of the PWM signal, if the time interval between the sampling point and the rising or falling edge of the PWM signal is too small, a large sampling error will result.

[0125] Therefore, a preset threshold is determined. For sampling points whose time interval with the rising or falling edge of the PWM signal is less than the preset threshold, the inductor current collected at these sampling points is not included in subsequent calculations. In other words, sampling points whose time interval with the rising or falling edge of the PWM signal is greater than or equal to the preset threshold are considered valid sampling points. Subsequent calculations are performed on the inductor current collected at these valid sampling points to determine the PWM signal for the next cycle.

[0126] As an example, the setting threshold T is determined D When TD>(T p -CCR1) / 2, indicating that the time distances between the first sampling point t2 and the third sampling point t4 and CCR1 are too close. In other words, the first sampling point t2 and the third sampling point t4 are too close to the on / off timing of the switch module. Therefore, sampling at times t2 and t4 is affected by the current oscillations generated by the switch, resulting in large sampling errors. Therefore, CCR2 is set to CCR1, and the flag bit Flagon is set to 1. This means that during the on-time period, only the second sampling point t3 is used as the valid sampling point.

[0127] When TD > CCR1 / 2, the fifth and sixth sampling points t1 and t5 are close to CCR1 in time. This means that the fifth and sixth sampling points t1 and t5 are close to the on / off timing of the switch module. Therefore, sampling at times t1 and t2 is affected by the current oscillations generated by the switch, resulting in large sampling errors. Therefore, CCR3 is set to CCR1, and Flagoff is set to 1. This means that during the off period, only the fourth sampling point t0 is considered the valid sampling point.

[0128] Sub-step S32 , determining a pulse width modulation signal of a next cycle according to the inductor current of the power factor correction circuit collected at the effective sampling point.

[0129] In some embodiments, step 103 specifically includes the following sub-steps:

[0130] Sub-step S41, determining an average inductor current based on the inductor current of the power factor correction circuit collected at multiple sampling points during the on-time period and the inductor current of the power factor correction circuit collected at multiple sampling points during the off-time period;

[0131] As an example, an average value of the current i2 collected at the first sampling point t2 of the on-period, the current i3 collected at the second sampling point t3, the current i4 collected at the third sampling point t4, the current i0 collected at the fourth sampling point t0 of the off-period, the current i1 collected at the fifth sampling point t1, and the current i5 collected at the sixth sampling point t5 is calculated and determined as the average inductor current.

[0132] Sub-step S42 : determining a pulse width modulation signal for the next cycle according to the average inductor current.

[0133] As an example, the average inductor current is compared with a reference current given by the output voltage loop or an external command to determine the current error. This error is then fed into a proportional-integral controller, which adjusts the proportional and integral gains to output a duty cycle adjustment. This adjustment is then added to the current cycle's duty cycle to determine the next cycle's duty cycle, ultimately determining the pulse-width modulation signal for the next cycle.

[0134] The present embodiment first determines multiple sampling points during the on-time period and the off-time period of the pulse-width modulation signal in the current cycle. These sampling points do not coincide with the rising or falling edges of the pulse-width modulation signal. The inductor current is then sampled at these sampling points during the on-time period and the off-time period, and the pulse-width modulation signal for the next cycle is determined based on these inductor currents, thereby achieving continuous regulation of the inductor current. Because current oscillations occur at both the rising and falling edges of the pulse-width modulation signal, avoiding these edges for sampling improves the accuracy of the sampled current. Furthermore, by performing multiple samplings during both the on-time period and the off-time period of the pulse-width modulation signal, the current value determined from the sampled current is closer to the actual inductor current, thereby improving the control effect of the PFC circuit.

[0135] It should be noted that for the sake of simplicity, the method embodiments are described as a series of actions. However, those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0136] Figure 5 This is a structural block diagram of a control device for a power factor correction circuit provided by an embodiment of the present invention.

[0137] like Figure 5 As shown, a control device for a power factor correction circuit provided by an embodiment of the present invention may specifically include the following modules:

[0138] a sampling point determination module 51, configured to determine a plurality of sampling points in an on-period of a pulse width modulation signal of a current cycle, and to determine a plurality of sampling points in an off-period of the pulse width modulation signal of the current cycle; wherein the plurality of sampling points in the on-period and the plurality of sampling points in the off-period do not coincide with a rising edge moment and a falling edge moment of the pulse width modulation signal;

[0139] a current acquisition module 52, configured to acquire the inductor current of the power factor correction circuit at a plurality of sampling points during the on-time period and a plurality of sampling points during the off-time period;

[0140] The signal determination module 53 is used to determine the pulse width modulation signal of the next cycle based on the inductor current of the power factor correction circuit collected at multiple sampling points during the conduction period and multiple sampling points during the off period, and input the pulse width modulation signal to the switch module; the switch module is used to respond to the pulse width modulation signal.

[0141] In some embodiments, the sampling point determination module 51 includes:

[0142] The duty cycle acquisition submodule is used to obtain the duty cycle of the pulse width modulation signal of the current cycle;

[0143] a signal period determination submodule, configured to determine an on-period of the pulse width modulation signal of the current period and an off-period of the pulse width modulation signal of the current period according to a duty cycle of the pulse width modulation signal of the current period;

[0144] A conduction sampling point determination submodule, configured to determine a plurality of sampling points in the conduction period;

[0145] The shutdown sampling point determination submodule is used to determine multiple sampling points in the shutdown period.

[0146] In some embodiments, the signal period determination submodule includes:

[0147] A center alignment counting unit, for aligning the centers of the pulse width modulation signal of the upper half cycle with the pulse width modulation signal of the lower half cycle, counting in an increasing manner in the upper half cycle and counting in a decreasing manner in the lower half cycle;

[0148] a count value determining unit, configured to determine a first count value according to a duty cycle of the pulse width modulation signal of the current cycle;

[0149] a first time point determining unit, configured to determine a first time point when the first count value is reached by counting in an incremental manner in the first half cycle;

[0150] a second time point determining unit, configured to determine a second time point when the second half cycle reaches the first count value by counting in a decreasing manner;

[0151] The conduction period determination unit is configured to determine a time period between the second time point and the first time point as a conduction period.

[0152] In some embodiments, the signal period determination submodule includes:

[0153] a third time point determining unit, configured to determine a third time point at which counting starts in the first half cycle, and determine a fourth time point at which counting ends in the second half cycle;

[0154] The shutdown period determining unit is configured to determine a time period between the first time point and the third time point, and a time period between the fourth time point and the second time point, as a shutdown period.

[0155] In some embodiments, the conducting sampling point determination submodule includes:

[0156] The first sampling point determining unit is configured to determine a first sampling point, a second sampling point, and a third sampling point of the conduction period, wherein the first sampling point, the second sampling point, and the third sampling point equally divide the conduction period.

[0157] In some embodiments, the shut-down sampling point determination submodule includes:

[0158] a second sampling point determining unit, configured to determine a starting point of a first off period as a fourth sampling point, and a midpoint of the first off period as a fifth sampling point; the first off period being a time period between the first time point and the third time point;

[0159] The midpoint of the second off period is determined to be the sixth sampling point; the second off period is a time period between the fourth time point and the second time point.

[0160] In some embodiments, the signal determination module 53 includes:

[0161] a valid sampling point determination submodule, configured to select, as valid sampling points, the sampling points whose time interval with the rising edge of the pulse width modulation signal is greater than or equal to a preset threshold, and the sampling points whose time interval with the falling edge of the pulse width modulation signal is greater than or equal to the preset threshold;

[0162] The first duty cycle determination submodule is configured to determine a pulse width modulation signal of a next cycle according to the inductor current of the power factor correction circuit collected at the effective sampling point.

[0163] In some embodiments, the current acquisition module 52 includes:

[0164] The sampling signal determination submodule is configured to determine a sampling trigger signal based on the plurality of sampling points during the on-period and the plurality of sampling points during the off-period, and input the signal into the acquisition module. The acquisition module is configured to acquire the inductor current of the power factor correction circuit in response to the sampling trigger signal.

[0165] In some embodiments, the signal determination module 53 includes:

[0166] an average current determination submodule, configured to determine an average inductor current based on the inductor current of the power factor correction circuit collected at multiple sampling points during the on-time period and multiple sampling points during the off-time period;

[0167] The second duty cycle determination submodule is configured to determine a pulse width modulation signal of a next cycle according to the average inductor current.

[0168] The present embodiment first determines multiple sampling points during the on-time period and the off-time period of the pulse-width modulation signal in the current cycle, ensuring that none of these sampling points coincide with the rising or falling edges of the pulse-width modulation signal. The inductor current is then sampled at these sampling points during the on-time period and the off-time period, and the pulse-width modulation signal for the next cycle is determined based on these inductor currents, thereby achieving continuous regulation of the inductor current. Because current oscillations occur at both the rising and falling edges of the pulse-width modulation signal, avoiding these edges for sampling improves the accuracy of the sampled current. Furthermore, by performing multiple samplings during both the on-time period and the off-time period of the pulse-width modulation signal, the current value determined from the sampled current is closer to the actual inductor current, thereby improving the control effectiveness of the PFC circuit.

[0169] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0170] An embodiment of the present invention also provides an electronic device, comprising: a processor, a memory, and a computer program stored in the memory and capable of running on the processor. When the computer program is executed by the processor, the various processes of the above-mentioned power factor correction circuit control method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0171] An embodiment of the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the various processes of the above-mentioned power factor correction circuit control method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0172] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0173] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, apparatus, or computer program products. Thus, embodiments of the present invention may take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0174] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems) and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0175] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0176] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0177] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they become aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0178] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0179] The above is a detailed introduction to the control method, device, electronic device and computer-readable storage medium of a power factor correction circuit provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for general technical personnel in this field, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A control method for a power factor correction circuit, characterized in that: The power factor correction circuit includes a switch module, the switch module is used to respond to a pulse width modulation signal, and the method includes: Determining a plurality of sampling points of an on-period of a pulse width modulation signal of a current cycle, and determining a plurality of sampling points of an off-period of the pulse width modulation signal of the current cycle; wherein the plurality of sampling points of the on-period and the plurality of sampling points of the off-period do not coincide with a rising edge time or a falling edge time of the pulse width modulation signal; collecting the inductor current of the power factor correction circuit at a plurality of sampling points in the on-time period and a plurality of sampling points in the off-time period; According to the inductor current of the power factor correction circuit collected at multiple sampling points in the on period and multiple sampling points in the off period, a pulse width modulation signal of the next cycle is determined and input into the switch module.

2. The control method of the power factor correction circuit according to claim 1, characterized in that: The step of determining a plurality of sampling points of an on-period of a pulse width modulation signal of a current cycle, and determining a plurality of sampling points of an off-period of a pulse width modulation signal of a current cycle, comprises: Get the duty cycle of the pulse width modulation signal of the current cycle; determining an on-period of the pulse width modulation signal of the current cycle and an off-period of the pulse width modulation signal of the current cycle according to a duty cycle of the pulse width modulation signal of the current cycle; determining a plurality of sampling points during the conduction period; A plurality of sampling points of the off period are determined.

3. The control method of the power factor correction circuit according to claim 2, characterized in that: The step of determining the on-time period of the pulse width modulation signal of the current cycle according to the duty cycle of the pulse width modulation signal of the current cycle includes: Align the centers of the pulse width modulation signal of the first half cycle with the pulse width modulation signal of the second half cycle, count in an increasing manner in the first half cycle, and count in a decreasing manner in the second half cycle; determining a first count value according to a duty cycle of the pulse width modulation signal of the current cycle; determining a first time point when the first count value is reached by counting in an incremental manner in the first half cycle; determining a second time point when counting in a decremental manner in the second half cycle reaches the first count value; The time period between the second time point and the first time point is determined as the on-time period.

4. The control method of the power factor correction circuit according to claim 3, characterized in that: The step of determining the off period of the pulse width modulation signal of the current cycle includes: determining a third time point at which counting starts in the first half cycle, and determining a fourth time point at which counting ends in the second half cycle; A time period between the first time point and the third time point, and a time period between the fourth time point and the second time point are determined as an off period.

5. The control method of the power factor correction circuit according to claim 2, characterized in that: The determining of the plurality of sampling points of the conduction period comprises: A first sampling point, a second sampling point, and a third sampling point of the conduction period are determined, wherein the first sampling point, the second sampling point, and the third sampling point equally divide the conduction period.

6. The control method of the power factor correction circuit according to claim 4, characterized in that: The determining of the plurality of sampling points of the shutdown period comprises: Determine the starting point of the first off period as the fourth sampling point, and determine the midpoint of the first off period as the fifth sampling point; the first off period is the time period between the first time point and the third time point; The midpoint of the second off period is determined to be the sixth sampling point; the second off period is a time period between the fourth time point and the second time point.

7. The control method of the power factor correction circuit according to claim 1, characterized in that: Determining the pulse width modulation signal of the next cycle according to the inductor current of the power factor correction circuit collected at multiple sampling points in the conduction period and multiple sampling points in the off period includes: The sampling point whose time interval with the rising edge of the pulse width modulation signal is greater than or equal to a preset threshold, and the sampling point whose time interval with the falling edge of the pulse width modulation signal is greater than or equal to a preset threshold are used as valid sampling points; A pulse width modulation signal of a next cycle is determined according to the inductor current of the power factor correction circuit collected at the effective sampling point.

8. The control method of the power factor correction circuit according to claim 1, characterized in that: The power factor correction circuit includes an acquisition module; The collecting of the inductor current of the power factor correction circuit at multiple sampling points in the on-time period and multiple sampling points in the off-time period includes: Determine a sampling trigger signal according to the plurality of sampling points in the on-time period and the plurality of sampling points in the off-time period and input the signal into the acquisition module; The acquisition module is used to respond to the sampling trigger signal to acquire the inductor current of the power factor correction circuit.

9. The control method of the power factor correction circuit according to claim 1, characterized in that: Determining the pulse width modulation signal of the next cycle according to the inductor current of the power factor correction circuit collected at multiple sampling points in the conduction period and multiple sampling points in the off period includes: determining an average inductor current according to the inductor current of the power factor correction circuit collected at a plurality of sampling points during the on-time period and a plurality of sampling points during the off-time period; A pulse width modulation signal of a next cycle is determined according to the average inductor current.

10. A control device for a power factor correction circuit, characterized in that: The device comprises: a sampling point determination module, configured to determine a plurality of sampling points in an on-period of a pulse width modulation signal of a current cycle, and to determine a plurality of sampling points in an off-period of the pulse width modulation signal of the current cycle; wherein the plurality of sampling points in the on-period and the plurality of sampling points in the off-period do not coincide with a rising edge moment and a falling edge moment of the pulse width modulation signal; a current acquisition module, configured to acquire the inductor current of the power factor correction circuit at a plurality of sampling points during the on-time period and a plurality of sampling points during the off-time period; A signal determination module is used to determine the pulse width modulation signal of the next cycle and input it into the switch module based on the inductor current of the power factor correction circuit collected at multiple sampling points during the conduction period and multiple sampling points during the off period; the switch module is used to respond to the pulse width modulation signal.

11. An electronic device, characterized in that: include: A processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein when the computer program is executed by the processor, the steps of the control method of the power factor correction circuit as described in any one of claims 1 to 9 are implemented.

12. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the control method of the power factor correction circuit according to any one of claims 1 to 9 are implemented.

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