Gate drive circuit and power circuit

Abstract

A gate drive circuit and a power circuit, belonging to the technical field of gate drive circuits, the gate drive circuit comprising: a drive module (100) provided with a drive output end for connecting with a gate of a power field effect transistor (400); and the feed-forward module (200) is provided with a feed-forward detection end and a feed-forward compensation end, and the feed-forward detection end and the feed-forward compensation end are both connected with the driving output end. The feed-forward module (200) is arranged to generate feed-forward current, the feed-forward current is increased when the voltage of the feed-forward detection end is increased, and the feed-forward current is removed when the voltage of the feed-forward detection end reaches the maximum value, the drain-source voltage of the power field-effect tube (400) does not need to be detected, the circuit structure is simplified, and before the voltage of the driving output end reaches the steady state, the voltage of the power field-effect tube (400) is not required to be detected. Therefore, the current flowing to the grid electrode of the power field effect transistor (400) is prevented from being obviously reduced, the time consumed for the drain-source voltage and the grid-source voltage of the power field effect transistor (400) to reach the steady state is shortened as much as possible when the power field effect transistor (400) is driven, the conduction speed is improved, and the conduction loss is reduced.

Description

A gate drive circuit and a power circuit Technical Field

[0001] The present application relates to the technical field of gate drive circuits, and in particular to a gate drive circuit. Background Art

[0002] The gate drive circuit is used to drive power field-effect transistors such as high electron mobility transistors (HEMTs) and insulated gate bipolar transistors (IGBTs) to provide sufficient current and voltage to control the gate of the power field-effect transistor, ensuring that the power field-effect transistor is turned on and off quickly and reliably.

[0003] Referring to Figure 1, the commonly used gate drive circuit adopts push-pull circuit direct drive. However, in this driving mode, referring to Figure 2, during the conduction process, the drain-source voltage V DS The slope of the change increases with the drain-source voltage V DS decreases with the decrease of the drain-source voltage V DS It takes a long time to reach steady state, resulting in additional conduction loss. Referring to Figure 1, the main reason for this situation is the existence of Miller capacitance Cgd between the gate and drain of the power FET, also known as reverse transfer capacitance Crss. Referring to Figure 3, it shows the input capacitance Ciss, output capacitance Coss and reverse transfer capacitance Crss of the power FET with the drain-source voltage V DS The reverse transfer capacitance Crss changes with the drain-source voltage V DS The gate-source voltage V DS The slope of change decreases. At the same time, referring to Figure 2, the gate-source voltage V GS When the gate current continues to increase after passing the Miller platform, the gate current I G But it gradually becomes smaller, making the gate-source voltage V GS It takes a long time to reach steady state, that is, the power field effect tube reaches the fully conductive state, which affects the conduction speed.

[0004] In the prior art, for the above situation, referring to FIG4 and FIG5, by detecting the drain-source voltage V DS Apply the second-stage delayed driving current IG2 to shorten the charging time of the reverse transfer capacitor Crss, so that the drain-source voltage V DS The time taken to reach steady state is shortened, which can also shorten the gate-source voltage V GS However, this method requires detecting the drain-source voltage V DS , the structure is more complicated, and according to the drain-source voltage V DSThe delay value of the driving current IG2 is determined. It is easy to have an inappropriate delay value, that is, the driving current IG2 is applied too early or too late, which leads to problems in the circuit and is difficult to implement. In addition, this circuit structure also has the gate-source voltage V GS In the process of increasing to steady state, the gate current IG1+IG2 decreases significantly, which is not conducive to the gate-source voltage V GS Reaching steady state as quickly as possible affects the conduction speed.

[0005] Summary of the Invention

[0006] The present application provides a gate drive circuit and a power circuit to solve the defects of the prior art in that the circuit is complex and difficult to implement in order to shorten the drain-source voltage and the gate-source voltage, and the problem that the gate current decreases when the gate-source voltage increases and reaches a steady state.

[0007] The present application provides a gate drive circuit, comprising: a drive module, provided with a drive output terminal, the drive output terminal being used to be connected to the gate of a power field effect transistor; a feedforward module, provided with a feedforward detection terminal and a feedforward compensation terminal, the feedforward detection terminal and the feedforward compensation terminal both being connected to the drive output terminal, the feedforward module being used to control the magnitude of a feedforward current output by the feedforward compensation terminal according to the voltage of the feedforward detection terminal, so that the feedforward current increases when the voltage of the feedforward detection terminal increases, and the feedforward current is removed when the voltage of the feedforward detection terminal reaches a maximum value.

[0008] According to a gate drive circuit provided by the present application, the feedforward module includes a voltage conversion unit and a first transistor, the input end of the voltage conversion unit forms the feedforward detection end and is connected to the drive output end, the output end of the voltage conversion unit is connected to the controlled end of the first transistor, the input end of the first transistor is connected to the drive voltage, and the output end of the first transistor forms the feedforward compensation end and is connected to the drive output end.

[0009] According to a gate drive circuit provided by the present application, the voltage conversion unit includes a second transistor, a resistor R1 and a resistor R2, the controlled end of the second transistor forms the feedforward detection end and is connected to the drive output end, the input end of the second transistor is respectively connected to one end of the resistor R2 and the controlled end of the second transistor, the output end of the first transistor is grounded through the resistor R1, and the other end of the resistor R2 is connected to the drive voltage.

[0010] According to a gate drive circuit provided by the present application, the first transistor is a first P-type field effect transistor, and the second transistor is a first N-type field effect transistor.

[0011] According to a gate drive circuit provided in this application, the magnitude of the feedforward current is calculated by the following formula:

[0012] Among them, I G2 is the feedforward current value; K is the conduction coefficient of the first transistor; V GS is the voltage value of the drive output terminal; V TNO is the conduction threshold voltage of the second transistor; R1 is the resistance of resistor R1; R2 is the resistance of resistor R2; V TPO is the turn-on threshold voltage of the first transistor.

[0013] According to a gate drive circuit provided by the present application, the drive module includes a second P-type field effect transistor, a second N-type field effect transistor and a resistor Ron, the source of the second P-type field effect transistor is connected to the drive voltage through the resistor Ron, the drain of the second P-type field effect transistor is connected to the drain of the second N-type field effect transistor to form the drive output end, and the source of the second N-type field effect transistor is grounded.

[0014] A gate drive circuit provided according to the present application also includes a protection module, which is respectively connected to the gate of the second P-type field effect transistor and the gate of the second N-type field effect transistor. The protection module is used to drive the second P-type field effect transistor and the second N-type field effect transistor to be turned on or off according to the input control signal and prevent the second P-type field effect transistor and the second N-type field effect transistor from being turned on at the same time.

[0015] According to a gate drive circuit provided by the present application, the protection module includes a NAND gate, a NOR gate, a first delay unit, a second delay unit, a first NAND gate and a second NAND gate. The first input end of the NAND gate and the first input end of the NOR gate are both connected to the external control signal, the output end of the NAND gate is respectively connected to the gate of the second P-type field effect transistor and the input end of the first delay unit, the output end of the first delay unit is connected to the second input end of the NOR gate through the first NOR gate, the output end of the NOR gate is respectively connected to the gate of the second N-type field effect transistor and the input end of the second delay unit, and the output end of the second delay unit is connected to the second input end of the NAND gate through the second NOR gate.

[0016] According to a gate drive circuit provided in the present application, the protection module also includes a first shaping unit and a second shaping unit, the output end of the NAND gate is connected to the input end of the first shaping unit, the output end of the first shaping unit is respectively connected to the gate of the second P-type field effect transistor and the input end of the first delay unit, the output end of the NOR gate is connected to the input end of the second shaping unit, and the output end of the second shaping unit is respectively connected to the gate of the second N-type field effect transistor and the input end of the second delay unit.

[0017] According to a gate drive circuit provided by the present application, the first shaping unit includes a third NOT gate and a fourth NOT gate connected in series, the input end of the third NOT gate forms the input end of the first shaping unit, and the output end of the fourth NOT gate forms the output end of the first shaping unit; and / or, the second shaping unit includes a fifth NOT gate and a sixth NOT gate connected in series, the input end of the fifth NOT gate forms the input end of the second shaping unit, and the output end of the sixth NOT gate forms the output end of the second shaping unit.

[0018] The present application also provides a power circuit, including the above-mentioned gate drive circuit and a power field effect transistor, wherein the drive output end is connected to the gate of the power field effect transistor.

[0019] According to the power circuit provided in the present application, the power field effect tube is a gallium nitride HEMT tube.

[0020] A gate drive circuit provided in the present application has at least the following beneficial effects: a drive module is connected to the gate of a power field-effect transistor. When the drive module drives the power field-effect transistor to turn on, the feedforward module is connected to the drive output terminal through the feedforward detection terminal to obtain the voltage of the drive output terminal. According to the voltage change of the drive output terminal, that is, the voltage of the feedforward detection terminal, the magnitude of the feedforward current output by the feedforward compensation terminal is controlled, so that when the voltage of the drive output terminal increases, that is, the current of the drive output terminal decreases, the increase in feedforward current can compensate for the decrease in the current of the drive output terminal, thereby preventing the current flowing to the gate of the power field-effect transistor from decreasing significantly. When the voltage of the drive output terminal reaches a steady state, the feedforward current is removed, thereby meeting the requirement of controlling the stable operation of the power field-effect transistor. In this way, by providing a feedforward module, a feedforward current is output before the voltage at the driving output terminal reaches a steady state, and there is no need to detect the drain-source voltage of the power field-effect transistor, which is conducive to simplifying the circuit structure and reducing the difficulty of implementation. It can also prevent the current flowing to the gate of the power field-effect transistor from being significantly reduced before the voltage at the driving output terminal reaches a steady state, which is conducive to shortening the time taken for the drain-source voltage and gate-source voltage of the power field-effect transistor to reach a steady state when driving the power field-effect transistor, thereby improving the conduction speed and reducing the conduction loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the present application or the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0022] FIG1 is a circuit diagram of a driving circuit in the prior art;

[0023] FIG2 is a diagram showing changes in electrical parameters during the conduction process of a driving circuit in the prior art;

[0024] FIG3 is a graph showing the variation of the parasitic capacitance values ​​of a power field effect transistor with the drain-source voltage;

[0025] FIG4 is a circuit diagram of another driving circuit in the prior art;

[0026] FIG5 is a diagram showing changes in electrical parameters during the conduction process of another driving circuit in the prior art;

[0027] FIG6 is a circuit diagram of one embodiment of the present application;

[0028] FIG7 is a diagram showing changes in electrical parameters during a conduction process according to one embodiment of the present application;

[0029] FIG8 is a circuit diagram of a protection module in one embodiment of the present application.

[0030] Figure numerals: Driving module 100; second P-type field effect transistor 110; second N-type field effect transistor 120; feedforward module 200; voltage conversion unit 210; first transistor 220; second transistor 211; protection module 300; NAND gate 310; NOR gate 320; first delay unit 330; second delay unit 340; first NOT gate 350; second NOT gate 360; first shaping unit 370; third NOT gate 371; fourth NOT gate 372; second shaping unit 380; fifth NOT gate 381; sixth NOT gate 382; power field effect transistor 400. DETAILED DESCRIPTION

[0031] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure and not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present disclosure.

[0032] The following describes a gate drive circuit of the present application in conjunction with Figures 6 to 8, including: a drive module 100, provided with a drive output terminal, the drive output terminal is used to connect to the gate of the power field effect transistor 400; a feedforward module 200, provided with a feedforward detection terminal and a feedforward compensation terminal, the feedforward detection terminal and the feedforward compensation terminal are both connected to the drive output terminal, and the feedforward module 200 is used to control the feedforward current output by the feedforward compensation terminal according to the voltage of the feedforward detection terminal, so that the feedforward current increases when the voltage of the feedforward detection terminal increases and the feedforward current is removed when the voltage of the feedforward detection terminal reaches a maximum value.

[0033] The driving module 100 is connected to the gate of the power field effect transistor 400. When the driving module 100 drives the power field effect transistor 400 to turn on, the feedforward module 200 is connected to the driving output end through the feedforward detection end to obtain the voltage of the driving output end. According to the voltage change of the driving output end, that is, the voltage of the feedforward detection end, the feedforward current output by the feedforward compensation end is controlled. When the voltage of the driving output end increases, that is, the current of the driving output end decreases, the increase in the feedforward current can compensate for the decrease in the current of the driving output end, thereby preventing the current flowing to the gate of the power field effect transistor 400 from decreasing significantly. When the voltage of the driving output end reaches the maximum value, that is, in the steady state, the feedforward current is removed to meet the requirement of controlling the stable operation of the power field effect transistor 400. In this way, by providing the feedforward module 200, the feedforward current is output before the voltage at the driving output end reaches a steady state, and there is no need to detect the drain-source voltage of the power field effect tube 400, which is conducive to simplifying the circuit structure and reducing the difficulty of implementation. It can also prevent the current flowing to the gate of the power field effect tube 400 from being significantly reduced before the voltage at the driving output end reaches a steady state. This is conducive to shortening the time taken for the drain-source voltage and gate-source voltage of the power field effect tube 400 to reach a steady state when driving the power field effect tube 400, thereby improving the conduction speed and reducing the conduction loss.

[0034] It should be noted that the power field effect transistor 400 may be alternately turned on and off during operation. The above-mentioned voltage at the driving output terminal reaches a steady state, which means that when the power field effect transistor 400 is controlled to be turned on, the voltage at the driving output terminal, that is, the gate voltage of the power field effect transistor 400 reaches the maximum value. The steady state here refers to a single conduction process, not the entire working process.

[0035] Referring to Figure 7, when the voltage at the driving output end increases, that is, the current at the driving output end decreases, the method of increasing the feedforward current for compensation can maintain the current at the driving output end from decreasing significantly while not causing the total current at the driving output end to be too large. Compared with the method of directly increasing the total current at the driving end to shorten the conduction time, the method of using the feedforward current can avoid damage to the gate of the power field effect transistor 400, which is conducive to reliably and safely driving the power field effect transistor 400.

[0036] Referring to Figure 6, in some embodiments of a gate drive circuit of the present application, the feedforward module 200 includes a voltage conversion unit 210 and a first transistor 220, the input end of the voltage conversion unit 210 forms the feedforward detection end and is connected to the drive output end, the output end of the voltage conversion unit 210 is connected to the controlled end of the first transistor 220, the input end of the first transistor 220 is connected to the drive voltage, and the output end of the first transistor 220 forms the feedforward compensation end and is connected to the drive output end.

[0037] The input terminal of the voltage conversion unit 210 detects the voltage at the driver output terminal and converts the voltage at the driver output terminal into a voltage that drives the first transistor 220, causing the first transistor 220 to conduct and generate a feedforward current. Because the voltage output by the voltage conversion unit 210 varies with the voltage at the driver output terminal, when the voltage at the driver output terminal increases, the voltage output by the voltage conversion unit 210 changes, increasing the degree of conduction of the first transistor 220 and thus increasing the feedforward current generated by the first transistor 220. When the voltage at the driver output terminal reaches a steady state, the voltage at the driver output terminal is equivalent to the driving voltage connected to the input terminal of the first transistor 220. At this point, the input and output voltages of the first transistor 220 can be considered equal, and the first transistor 220 no longer generates a feedforward current, i.e., the feedforward current is removed. In this way, the voltage conversion unit 210 is used to drive the first transistor 220, so that the feedforward current increases when the voltage at the feedforward detection end, that is, the voltage at the driving output end, increases, and the working characteristics of the first transistor 220 are used to remove the feedforward current when the voltage at the driving output end reaches the maximum value. The structure is simple and easy to implement.

[0038] Referring to Figure 6, in some embodiments of a gate drive circuit of the present application, the voltage conversion unit 210 includes a second transistor 211, a resistor R1 and a resistor R2, the controlled end of the second transistor 211 forms the feedforward detection end and is connected to the drive output end, the input end of the second transistor 211 is respectively connected to one end of the resistor R2 and the controlled end of the second transistor 211, the output end of the first transistor 220 is grounded through the resistor R1, and the other end of the resistor R2 is connected to the drive voltage.

[0039] The controlled end of the second transistor 211 is connected to the driving output end. The second transistor 211 changes its conduction level according to the voltage of the driving output end, causing its own voltage drop to change, thereby changing the voltage of the controlled end of the first transistor 220, controlling the conduction level of the first transistor 220 to generate a feedforward current, thereby achieving a voltage conversion effect. The structure is simple, and by setting the resistance value of the resistor R1 and the resistance value of the resistor R2, the change process of the size of the feedforward current can be controlled, which facilitates circuit design.

[0040] 6 , in some embodiments of a gate driving circuit of the present application, the first transistor 220 is a first P-type field effect transistor, and the second transistor 211 is a first N-type field effect transistor.

[0041] The first transistor 220 is a first P-type field-effect transistor (FET), whose threshold voltage for conduction is related to the gate-source voltage. The input terminal of the first transistor 220 is connected to the driving voltage, that is, the source terminal serving as the input terminal is connected to the driving voltage. The source voltage is determined, and the operating state of the first P-type FET can be stably controlled by controlling the gate voltage, which helps simplify the control design. The second transistor 211 is a first N-type FET. The first N-type FET requires a high voltage to be applied to the gate to turn on, which is consistent with the voltage change at the drive output terminal when driving the power FET 400 to turn on. The gate of the first N-type FET is connected to the drive output terminal, and its conduction state can be changed according to the change of the drive output terminal, which helps simplify the circuit structure.

[0042] The first transistor 220 is a first P-type field-effect transistor, the gate of the first P-type field-effect transistor corresponds to the controlled terminal of the first transistor 220, the source of the first P-type field-effect transistor corresponds to the input terminal of the first transistor 220, and the drain of the first P-type field-effect transistor corresponds to the output terminal of the first transistor 220. The second transistor 211 is a first N-type field-effect transistor, the gate of the first N-type field-effect transistor corresponds to the controlled terminal of the second transistor 211, the drain of the first N-type field-effect transistor corresponds to the input terminal of the second transistor 211, and the source of the first N-type field-effect transistor corresponds to the output terminal of the second transistor 211.

[0043] 6 , in some embodiments of a gate drive circuit of the present application, the magnitude of the feedforward current is calculated using the following formula:

[0044] Among them, I G2 is the feedforward current value; K is the conduction coefficient of the first transistor 220; V GS is the voltage value of the driving output terminal, that is, the gate voltage value of the power field effect tube 400; V TNO is the conduction threshold voltage value of the second transistor 211; R1 is the resistance value of the resistor R1; R2 is the resistance value of the resistor R2; V TPOis the turn-on threshold voltage of the first transistor 220 .

[0045] The conduction coefficient and the on-threshold voltage of the first transistor 220 and the on-threshold voltage of the second transistor 211 are determined by the type and model parameters of the specific transistors, which can generally be obtained from the user manual of the transistor. These parameters can be considered as fixed values. According to the above formula, by setting the resistance value of the resistor R1 and the resistance value of the resistor R2, the feedforward current can be quantitatively controlled, which is conducive to making the increasing slope of the feedforward current close to the decreasing slope of the current at the driving output end, and maintaining the total current flowing to the gate of the power field effect transistor 400 without significantly decreasing.

[0046] Referring to Figure 6, in some embodiments of a gate drive circuit of the present application, the driving module 100 includes a second P-type field effect transistor 110, a second N-type field effect transistor 120 and a resistor Ron, the source of the second P-type field effect transistor 110 is connected to the driving voltage through the resistor Ron, the drain of the second P-type field effect transistor 110 is connected to the drain of the second N-type field effect transistor 120 to form the driving output end, and the source of the second N-type field effect transistor 120 is grounded.

[0047] Second P-type FET 110 and second N-type FET 120 are connected to form a push-pull circuit. This push-pull circuit structure drives power FET 400. During operation, one of second P-type FET 110 and second N-type FET 120 is turned on while the other is turned off, reducing conduction losses and improving driving efficiency. Furthermore, the resistor Ron acts as a current-limiting resistor, preventing excessive current from flowing when power FET 400 is turned on. This helps protect power FET 400 and improves safety.

[0048] In addition to the implementation of the push-pull circuit, in some embodiments of the present application, the driving module 100 may also include other commonly used driving circuits or driving chips, such as an isolation driving circuit.

[0049] In the case where the driving module 100 includes a push-pull circuit formed by a second P-type field-effect transistor 110 and a second N-type field-effect transistor 120, since the second P-type field-effect transistor 110 and the second N-type field-effect transistor 120 have an on-time and an off-time, if a control signal, such as a PWM signal, is directly transmitted to the gates of the second P-type field-effect transistor 110 and the second N-type field-effect transistor 120, it is possible that the second P-type field-effect transistor 110 is turned on while the second N-type field-effect transistor 120 is in the off-time process, that is, the second N-type field-effect transistor 120 is still in the on state. This is equivalent to the second P-type field-effect transistor 110 and the second N-type field-effect transistor 120 being turned on at the same time, resulting in a large current that may damage the second P-type field-effect transistor 110 and the second N-type field-effect transistor 120.

[0050] Regarding the above problem, referring to Figures 6 and 8, in some embodiments of a gate drive circuit of the present application, a protection module 300 is further included, and the protection module 300 is respectively connected to the gate of the second P-type field effect transistor 110 and the gate of the second N-type field effect transistor 120. The protection module 300 is used to drive the second P-type field effect transistor 110 and the second N-type field effect transistor 120 to be turned on or off according to the input control signal and prevent the second P-type field effect transistor 110 and the second N-type field effect transistor 120 from being turned on at the same time.

[0051] By providing the protection module 300, the second P-type field effect transistor 110 and the second N-type field effect transistor 120 are controlled to be turned on and off respectively according to the control signal. During the control process, the second P-type field effect transistor 110 and the second N-type field effect transistor 120 are prevented from being turned on at the same time, which is conducive to making the second P-type field effect transistor 110 and the second N-type field effect transistor 120 operate more reliably and safely.

[0052] Referring to Figure 8, in some embodiments of a gate drive circuit of the present application, the protection module 300 includes a NAND gate 310, a NOR gate 320, a first delay unit 330, a second delay unit 340, a first NOT gate 350 and a second NOT gate 360. The first input end of the NAND gate 310 and the first input end of the NOR gate 320 are both connected to the external control signal, the output end of the NAND gate 310 is respectively connected to the gate of the second P-type field effect transistor 110 and the input end of the first delay unit 330, the output end of the first delay unit 330 is connected to the second input end of the NOR gate 320 through the first NOT gate 350, the output end of the NOR gate 320 is respectively connected to the gate of the second N-type field effect transistor 120 and the input end of the second delay unit 340, and the output end of the second delay unit 340 is connected to the second input end of the NAND gate 310 through the second NOT gate 360.

[0053] According to the external control signal, when controlling the second P-type field effect transistor 110 to turn on and the second N-type field effect transistor 120 to turn off, the control signal changes from a low level to a high level. At this time, the NOR gate 320 outputs a low level, turning off the second N-type field effect transistor 120. The low level output by the NOR gate 320 is transmitted to the second delay unit 340. At this time, the level output by the second delay unit 340 remains high. The high level output by the second delay unit 340 is converted to a low level by the second NOT gate 360 ​​and then transmitted to the second input terminal of the NAND gate 310, causing the NAND gate 310 to maintain a high level output, thus keeping the second P-type field effect transistor 110 turned off. After the delay time of the second delay unit 340, the second delay unit outputs a low level at the output terminal based on the low level at the input terminal. After being converted to a high level by the second NOT gate 360, it is input to the second input terminal of the NAND gate 310, causing the NAND gate 310 to output a low level, thereby turning on the second P-type field effect transistor 110. In this way, the second delay unit 340 is utilized so that when the second N-type field effect transistor 120 is driven to turn off, the second P-type field effect transistor 110 remains turned off. After the delay time has elapsed, the second N-type field effect transistor 120 is ensured to be turned off, and the second P-type field effect transistor 110 begins to turn on. This achieves the goal of preventing the second P-type field effect transistor 110 and the second N-type field effect transistor 120 from being turned on at the same time during the process of controlling the second P-type field effect transistor 110 to turn on and the second N-type field effect transistor 120 to turn off.

[0054] In the process of controlling the second P-type field effect transistor 110 to be turned on and the second N-type field effect transistor 120 to be turned off, the output level changes can be referred to the following table, where 1 represents a high level, 0 represents a low level, GP represents the level output to the gate of the second P-type field effect transistor 110, and GN represents the level output to the gate of the second N-type field effect transistor 120:

[0055] Accordingly, according to the external control signal, during the process of controlling the second P-type field-effect transistor 110 to be turned off and the second N-type field-effect transistor 120 to be turned on, the control signal changes from a high level to a low level. At this time, the NAND gate 310 outputs a high level, turning off the second P-type field-effect transistor 110. The high level output by the NAND gate 310 is transmitted to the first delay unit 330. At this time, the level output by the first delay unit 330 remains at a low level. The low level output by the first delay unit 330 is converted to a high level by the first NOT gate 350 and then transmitted to the second input terminal of the NOR gate 320, causing the NOR gate 320 to maintain a low level output, thus keeping the second N-type field-effect transistor 120 turned off. After the delay time of the first delay unit 330, the first delay unit outputs a high level at its output terminal based on the high level at its input terminal. After being converted to a low level by the first NOT gate 350, it is input to the second input terminal of the NOR gate 320, causing the NOR gate 320 to output a high level, thereby turning on the second N-type field-effect transistor 120. In this way, by utilizing the first delay unit 330, when the second P-type field effect transistor 110 is driven to turn off, the second N-type field effect transistor 120 remains turned off. After the delay time, the second P-type field effect transistor 110 is ensured to be turned off, and the second N-type field effect transistor 120 begins to be turned on. In this way, when the second P-type field effect transistor 110 is controlled to be turned off and the second N-type field effect transistor 120 is controlled to be turned on, the second P-type field effect transistor 110 and the second N-type field effect transistor 120 are prevented from being turned on at the same time.

[0056] In the process of controlling the second P-type field effect transistor 110 to be turned off and the second N-type field effect transistor 120 to be turned on, the output level change can be referred to the following table, where 1 represents a high level, 0 represents a low level, GP represents the level output to the gate of the second P-type field effect transistor 110, and GN represents the level output to the gate of the second N-type field effect transistor 120:

[0057] In summary, by utilizing the delay function of the first delay unit 330 and the second delay unit 340, it is ensured that during the operation of the push-pull circuit, there will be no moment when the gate input of the second P-type field effect transistor 110 is low and the gate input of the second N-type field effect transistor 120 is high, that is, there will be no situation where GP is 0 and GN is 1, which can avoid the situation where the second P-type field effect transistor 110 and the second N-type field effect transistor 120 are turned on at the same time, which is beneficial to improving the reliability and safety of the push-pull circuit.

[0058] The first delay unit 330 and the second delay unit 340 may be implemented by common delay circuits, delay chips, and the like.

[0059] Referring to Figure 8, in some embodiments of a gate drive circuit of the present application, the protection module 300 also includes a first shaping unit 370 and a second shaping unit 380, the output end of the NAND gate 310 is connected to the input end of the first shaping unit 370, the output end of the first shaping unit 370 is respectively connected to the gate of the second P-type field effect transistor 110 and the input end of the first delay unit 330, the output end of the NOR gate 320 is connected to the input end of the second shaping unit 380, and the output end of the second shaping unit 380 is respectively connected to the gate of the second N-type field effect transistor 120 and the input end of the second delay unit 340.

[0060] The first shaping unit 370 shapes the output voltage waveform of the NAND gate 310, which helps to make the gate voltage input to the second P-type field effect transistor 110 more stable and reliable. The second shaping unit 380 shapes the output voltage waveform of the NOR gate 320, which helps to make the gate voltage input to the second N-type field effect transistor 120 more stable and reliable, thereby more accurately controlling the conduction and shutdown of the second P-type field effect transistor and the second N-type field effect transistor 120.

[0061] 8 , in some embodiments of a gate driving circuit of the present application, the first shaping unit 370 includes a third NOT gate 371 and a fourth NOT gate 372 connected in series, wherein the input end of the third NOT gate 371 forms the input end of the first shaping unit 370 , and the output end of the fourth NOT gate 372 forms the output end of the first shaping unit 370 ;

[0062] The second shaping unit 380 includes a fifth NOT gate 381 and a sixth NOT gate 382 connected in series. The input end of the fifth NOT gate 381 forms the input end of the second shaping unit 380 , and the output end of the sixth NOT gate 382 forms the output end of the second shaping unit 380 .

[0063] The third NOT gate 371 and the fourth NOT gate 372 are connected in series to form the first shaping unit 370, and the fifth NOT gate 381 and the sixth NOT gate 382 are connected in series to form the second shaping unit 380, thereby achieving the shaping function. The structure is simple and easy to implement. At the same time, the third NOT gate 371 and the fourth NOT gate 372 are connected in series, and the fifth NOT gate 381 and the sixth NOT gate 382 are connected in series to improve the driving capability, which is conducive to driving the second P-type field effect transistor 110 and the second N-type field effect transistor 120 to be turned on and off more quickly and reliably.

[0064] In some embodiments of the present application, the third NOT gate 371 , the fourth NOT gate 372 , the fifth NOT gate 381 , and the sixth NOT gate 382 may be implemented as Schmitt triggers.

[0065] 6 , the present application also provides a power circuit, which includes a gate drive circuit according to any of the above embodiments, and also includes a power field effect transistor 400 , wherein the drive output terminal is connected to the gate of the power field effect transistor 400 .

[0066] The driving module 100 is connected to the gate of the power field effect transistor 400. When the driving module 100 drives the power field effect transistor 400 to turn on, the feedforward module 200 is connected to the driving output end through the feedforward detection end to obtain the voltage of the driving output end. According to the voltage change of the driving output end, that is, the voltage of the feedforward detection end, the feedforward current output by the feedforward compensation end is controlled. When the voltage of the driving output end increases, that is, the current of the driving output end decreases, the increase in the feedforward current can compensate for the decrease in the current of the driving output end, thereby preventing the current flowing to the gate of the power field effect transistor 400 from decreasing significantly. When the voltage of the driving output end reaches a steady state, the feedforward current is removed, thereby meeting the requirement of controlling the stable operation of the power field effect transistor 400. In this way, by providing the feedforward module 200, the feedforward current is output before the voltage at the driving output end reaches a steady state, and there is no need to detect the drain-source voltage of the power field effect tube 400, which is conducive to simplifying the circuit structure and reducing the difficulty of implementation. It can also prevent the current flowing to the gate of the power field effect tube 400 from being significantly reduced before the voltage at the driving output end reaches a steady state. This is conducive to shortening the time taken for the drain-source voltage and gate-source voltage of the power field effect tube 400 to reach a steady state when driving the power field effect tube 400, thereby improving the conduction speed and reducing the conduction loss.

[0067] In some embodiments of the power circuit of the present application, the power field effect transistor 400 is a gallium nitride HEMT tube.

[0068] By driving the GaN HEMT high electron mobility transistor to conduct through the cooperation of the driver module 100 and the feedforward module 200, the time taken to reach a steady state can be shortened as much as possible. In other words, the conduction speed of the GaN HEMT can be maximized, and conduction losses can be reduced. At the same time, the high electron mobility, high saturation electron velocity, and high breakdown electric field of the GaN HEMT can make the GaN HEMT more suitable for high-frequency and high-power environments.

[0069] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A gate drive circuit, characterized in that: include: A driving module (100) is provided with a driving output end, wherein the driving output end is used to be connected to a gate of a power field effect transistor (400); A feedforward module (200) is provided with a feedforward detection terminal and a feedforward compensation terminal, both of which are connected to the drive output terminal. The feedforward module (200) is used to control the magnitude of a feedforward current output by the feedforward compensation terminal according to the voltage of the feedforward detection terminal, so that the feedforward current increases when the voltage of the feedforward detection terminal increases, and the feedforward current is removed when the voltage of the feedforward detection terminal reaches a maximum value.

2. A gate drive circuit according to claim 1, characterized in that: The feedforward module (200) comprises a voltage conversion unit (210) and a first transistor (220), wherein the input end of the voltage conversion unit (210) forms the feedforward detection end and is connected to the drive output end, the output end of the voltage conversion unit (210) is connected to the controlled end of the first transistor (220), the input end of the first transistor (220) is connected to the drive voltage, and the output end of the first transistor (220) forms the feedforward compensation end and is connected to the drive output end.

3. A gate drive circuit according to claim 2, characterized in that: The voltage conversion unit (210) comprises a second transistor (211), a resistor R1 and a resistor R2; the controlled end of the second transistor (211) forms the feedforward detection end and is connected to the drive output end; the input end of the second transistor (211) is respectively connected to one end of the resistor R2 and the controlled end of the second transistor (211); the output end of the first transistor (220) is grounded through the resistor R1; and the other end of the resistor R2 is connected to the drive voltage.

4. A gate drive circuit according to claim 3, characterized in that: The first transistor (220) is a first P-type field effect transistor, and the second transistor (211) is a first N-type field effect transistor.

5. A gate drive circuit according to claim 4, characterized in that: The magnitude of the feedforward current is calculated by the following formula: Among them, I G2 is the feedforward current value; K is the conduction coefficient of the first transistor (220); V GS is the voltage value of the drive output terminal; V TNO is the conduction threshold voltage value of the second transistor (211); R1 is the resistance value of the resistor R1; R2 is the resistance value of the resistor R2; V TPO is the on-threshold voltage value of the first transistor (220).

6. The gate driving circuit according to claim 1, characterized in that: The driving module (100) comprises a second P-type field effect transistor (110), a second N-type field effect transistor (120) and a resistor Ron; the source of the second P-type field effect transistor (110) is connected to a driving voltage via the resistor Ron; the drain of the second P-type field effect transistor (110) is connected to the drain of the second N-type field effect transistor (120) to form the driving output end; and the source of the second N-type field effect transistor (120) is grounded.

7. A gate driving circuit according to claim 6, characterized in that: The invention also comprises a protection module (300), wherein the protection module (300) is respectively connected to the gate of the second P-type field effect transistor (110) and the gate of the second N-type field effect transistor (120), and the protection module (300) is used to drive the second P-type field effect transistor (110) and the second N-type field effect transistor (120) to be turned on or off according to an input control signal, and to prevent the second P-type field effect transistor (110) and the second N-type field effect transistor (120) from being turned on at the same time.

8. The gate driving circuit according to claim 7, characterized in that: The protection module (300) comprises a NAND gate (310), a NOR gate (320), a first delay unit (330), a second delay unit (340), a first NOT gate (350) and a second NOT gate (360); the first input end of the NAND gate (310) and the first input end of the NOR gate (320) are both connected to an external control signal; the output end of the NAND gate (310) is respectively connected to the gate of the second P-type field effect transistor (110) and the input end of the first delay unit (330); the output end of the first delay unit (330) is connected to the second input end of the NOR gate (320) through the first NOT gate (350); the output end of the NOR gate (320) is respectively connected to the gate of the second N-type field effect transistor (120) and the input end of the second delay unit (340); the output end of the second delay unit (340) is connected to the second input end of the NAND gate (310) through the second NOT gate (360).

9. The gate driving circuit according to claim 8, characterized in that: The protection module (300) further comprises a first shaping unit (370) and a second shaping unit (380); the output end of the NAND gate (310) is connected to the input end of the first shaping unit (370); the output end of the first shaping unit (370) is respectively connected to the gate of the second P-type field effect transistor (110) and the input end of the first delay unit (330); the output end of the NOR gate (320) is connected to the input end of the second shaping unit (380); the output end of the second shaping unit (380) is respectively connected to the gate of the second N-type field effect transistor (120) and the input end of the second delay unit (340).

10. The gate driving circuit according to claim 9, characterized in that: The first shaping unit (370) comprises a third NOT gate (371) and a fourth NOT gate (372) connected in series, the input end of the third NOT gate (371) forms the input end of the first shaping unit (370), and the output end of the fourth NOT gate (372) forms the output end of the first shaping unit (370); And / or, the second shaping unit (380) includes a fifth NOT gate (381) and a sixth NOT gate (382) connected in series, the input end of the fifth NOT gate (381) forms the input end of the second shaping unit (380), and the output end of the sixth NOT gate (382) forms the output end of the second shaping unit (380).

11. A power circuit, characterized in that: It comprises a gate drive circuit as claimed in any one of claims 1 to 10, and further comprises a power field effect transistor (400), wherein the drive output terminal is connected to the gate of the power field effect transistor (400).

12. The power circuit according to claim 11, characterized in that: The power field effect tube (400) is a gallium nitride HEMT tube.

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