A method and system for initial high-speed serdes power pdn channel design

Abstract

The application relates to a kind of initial high-speed SERDES power supply PDN passage design method and system, the method comprises: obtaining the key information of SERDES power supply;The chip power supply model of SERDES power supply is obtained, and the chip internal power supply network information is obtained;Based on the historical data of past design project, the power distribution network fitting of each component parameter of power distribution network is adjusted, and the power distribution network is established;Determine the passage design parameter variable scanning table;Obtain the noise size corresponding to each group of design parameter variables in the scanning table, and determine whether each group of design parameters meets the requirements;Based on the chip internal power supply network information, power noise analysis is carried out, and whether each group of design parameters meets the requirements is determined;According to the scanning table and the determination result, the key design parameters of power distribution network passage are determined.The designed PDN passage model can quickly identify power noise risk and reasonably allocate design resources, provide accurate power noise optimization guidance, and significantly reduce design cost and cycle.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of integrated circuits, and particularly relates to a method and system for designing a primary high-speed SERDES power supply PDN channel. BACKGROUND

[0002] In modern integrated circuit (IC) design, high-speed serial interface (SERDES) technology has become a core component of data transmission, especially in data centers, high-performance computing, and communication equipment. With the continuous improvement of data transmission rate, high-speed SERDES design at 25 Gbps and above faces many challenges, among which power supply noise problem is particularly prominent.

[0003] High-speed SERDES circuits are extremely sensitive to power supply noise, especially at transmission rates of 25 Gbps and above. Power supply noise directly affects signal integrity and timing, leading to an increase in bit error rate (BER) and even causing the system to malfunction. High-speed SERDES IP power supply noise requirements are very sensitive at 25 Gbps and above. Typically, high-speed SERDES design requires the peak-to-peak noise of the power supply to be less than 2% to ensure signal stability and reliability. The sources of power supply noise include the impedance characteristics of the power distribution network (PDN), the design of the power management circuit, and the parasitic effects in the package and PCB layout.

[0004] The tape-out cycle in IC design is a critical time node. Once the chip is taped out and design problems are found, especially SERDES functional failure caused by power supply noise, it will cause serious delay in project progress and bring high design cost. Since the modification and re-spin after tape-out require a lot of time and resources, the design team must identify and solve potential power supply noise problems in the early design stage to avoid uncontrollable risks in the later stage.

[0005] The existing power supply noise analysis method has the following technical defects:

[0006] 1. Existing technologies usually rely on late PCB and package layout data, which cannot provide accurate enough noise prediction in the early design stage. Even if simulation is performed after layout is completed, it cannot guarantee that the power supply noise simulation result can meet the design requirements (such as peak-to-peak noise less than 2%). This uncertainty increases the design risk, leading to the discovery of power supply noise problems after tape-out, and thus triggering the expensive re-design and re-spin process.

[0007] 2. The prior art cannot provide clear resource allocation guidance at the initial design stage, such as the number of package layers, power plane allocation, type and number of package capacitors, and other key design parameters. This uncertainty makes it difficult for the design team to make optimal design decisions at an early stage, resulting in resource waste or design deficiencies. SUMMARY

[0008] The purpose of the present application is to provide an initial high-speed SERDES power PDN channel design method and system, which is aimed at the design of high-speed SERDES power PDN channels above 25Gbps. In the early design stage without any package and PCB LAYOUT input, it realizes fast identification of power noise risk and clear and reasonable design resource allocation, such as package layer arrangement, package capacitor type and number arrangement.

[0009] The present application provides an initial high-speed SERDES power PDN channel design method, comprising the following steps:

[0010] Step 1: Obtain the key information of the SERDES power supply, including the type and supply voltage of the power supply, the power supply noise specification requirement, and the power supply power consumption;

[0011] Step 2: Obtain the chip power supply model of the SERDES power supply, and analyze the chip power supply model to obtain the chip internal power supply network information;

[0012] Step 3: Based on the historical data of past design projects, adjust the parameters of each component of the power distribution network to fit the power distribution network, and establish the power distribution network;

[0013] Step 4: Determine the channel design parameter variable scanning table for the parameter fluctuation of the power distribution network in step 3;

[0014] Step 5: Obtain the noise size corresponding to each group of design parameter variables in the channel design parameter variable scanning table through time domain noise simulation, and determine whether each group of design parameters meets the requirements according to the power supply noise specification requirement in step 1, to obtain a determination result;

[0015] Step 6: Perform power noise analysis based on the chip internal power supply network information obtained in step 2, and compare the noise analysis result with the power supply noise specification requirement in step 1 to determine whether each group of design parameters in the channel design parameter variable scanning table meets the requirements, to obtain a determination result;

[0016] Step 7: Determine the key design parameters of the power distribution network channel according to the channel design parameter variable scanning table determined in step 4, and the determination results of steps 5 and 6.

[0017] Further, the SERDES power supply in step 1 includes an IO power supply, a PLL power supply, an analog power supply, and a digital DSP module power supply.

[0018] Further, the chip internal power supply network information in step 2 includes dynamic current distribution, parasitic parameters, and power supply and ground network characteristics; the parasitic parameters include resistance, inductance, and capacitance.

[0019] Further, the components in step 3 include a voltage regulation module, a power supply plane, a decoupling capacitor, a package power supply network, and a chip internal power grid.

[0020] Further, the step 3 includes:

[0021] Using past design projects, adjusting the parameters of each component of the power distribution network to be completely consistent with the actual design parameters, including fitting of the frequency domain Z impedance curve, determination of the high-frequency equivalent inductance, consistency of the resonance frequency and amplitude, and consistency of the time domain noise; and determining the fitting topology and the key parameters of each component.

[0022] Further, the power supply noise analysis in step 6 includes:

[0023] Integrating the chip power supply model in step 2 into the power distribution network in step 3 to construct a system-level simulation framework, checking the change of the power distribution network impedance with frequency through frequency domain analysis, identifying noise amplification points caused by resonance or parasitic effects; and evaluating the transient voltage fluctuation caused by rapid current change through time domain simulation, quantifying the peak-to-peak ripple and voltage drop indicators.

[0024] The application further provides a preliminary high-speed SERDES power supply PDN channel design system, which comprises a PDN channel design module.

[0025] The application further provides a non-transitory computer readable storage medium, which stores computer instructions, and the computer instructions are executed by a processor to implement the preliminary high-speed SERDES power supply PDN channel design method.

[0026] The application further provides an electronic device, which comprises:

[0027] A memory and a processor, which are connected in communication with each other, and the memory stores computer instructions; and the processor executes the computer instructions to implement the preliminary high-speed SERDES power supply PDN channel design method.

[0028] With the above solution, through the initial high-speed SERDES power PDN channel design method and system, the designed PDN channel model can quickly identify power noise risks and reasonably allocate design resources, provide accurate power noise optimization guidance, and significantly reduce design costs and cycles.

[0029] The above description is only an overview of the technical solution of the present invention. In order to be able to understand the technical means of the present invention more clearly and to be implemented in accordance with the content of the specification, the following takes the preferred embodiments of the present invention and describes them in detail in conjunction with the drawings as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is the initial high-speed SERDES power PDN channel design method of the present invention;

[0031] Figure 2 is the SERDES IP power noise requirement from the IP manufacturer in an embodiment of the present invention;

[0032] Figure 3 is the spectral analysis diagram of the SERDES IP CPM current model in an embodiment of the present invention;

[0033] Figure 4 is the PDN channel fitting in an embodiment of the present invention Figure 1 :

[0034] Figure 5 is the PDN channel fitting in an embodiment of the present invention Figure 2 :

[0035] Figure 6 is the variable parameter scan table and its corresponding result analysis in an embodiment of the present invention;

[0036] Figure 7 is the structural schematic diagram of an electronic device of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0037] The following further describes in detail the specific embodiments of the present invention in conjunction with the drawings and embodiments. The following embodiments are used to illustrate the present invention but are not used to limit the scope of the present invention.

[0038] Refer Figure 1 As shown, this embodiment provides an initial high-speed SERDES power PDN channel design method, including the following steps:

[0039] Step S1, obtain the key information of the SERDES power supply, including the power supply type and supply voltage, the power noise specification requirements, and the power consumption.

[0040] By reading the data sheet provided by the IP manufacturer, obtain the following key information:

[0041] Power supply type and supply voltage; power supply noise specification requirement (see Figure 2 Power supply consumption; typical SERDES power supply includes IO power supply, PLL power supply, analog power supply or digital DSP module power supply. For example, 1.2V SERDES IO power supply, AC noise peak to peak requirement 2%; power supply noise specification data mainly provides pass / fail judgment basis for subsequent step analysis of power supply noise simulation results. At the same time, it also preliminarily confirms which power supply types need higher priority and more resource analysis in design, such as power supply types with larger power consumption and more stringent AC noise requirements, which need to consider placing more package capacitors.

[0042] In step S2, a chip power supply model of the SERDES power supply is obtained, and the chip power supply model is analyzed to obtain chip internal power supply network information.

[0043] In the field of power integrity (Power Integrity), the chip power supply model (CPM: CHIP POWER MODEL) is an equivalent circuit model describing the behavior of the chip power supply network. It contains the dynamic current distribution, parasitic parameters (resistance, inductance, capacitance) and power / ground network characteristics of the chip. CPM describes the internal power supply network of the chip, including dynamic current distribution and parasitic parameters such as resistance, inductance and capacitance. PDN covers the power supply path of the chip, package and printed circuit board, including voltage regulation module, power plane and decoupling capacitor. Figure 3 As shown in the figure, Figure 3 a shows a current model curve, by which the current size of each power supply can be analyzed; Figure 3 b is a frequency spectrum curve, which can analyze the key components of the current in the frequency domain.

[0044] In step S3, based on the historical data of past design projects, the parameters of each component of the power distribution network are adjusted to fit the power distribution network, and the power distribution network is established.

[0045] Power distribution network (PDN, Power Distribution Network) refers to the entire power supply path from the power supply to the chip in an electronic system, covering voltage regulation module (VRM), power plane of printed circuit board (PCB), power network in package and internal power distribution structure of chip. It includes parasitic parameters such as resistance, inductance and capacitance, and elements such as decoupling capacitor. The main function of PDN is to provide stable and reliable power supply for the chip, while suppressing noise and voltage fluctuation, and ensuring power integrity (Power Integrity).

[0046] Power distribution network (PDN) mainly contains the following components:

[0047] Voltage regulator module (VRM): converts input power to stable voltage required by the chip.

[0048] Power plane: low impedance conductive layer copper skin of printed circuit board (PCB) for power transmission.

[0049] Decoupling capacitor: distributed on the chip, package and PCB, to suppress voltage fluctuations caused by transient current changes.

[0050] Package power network: power distribution structure connecting the chip and PCB, including solder balls and internal power copper skin plane.

[0051] Chip internal power grid: metal layer and power distribution network within the chip, distributing power to various functional units.

[0052] At the initial stage of chip design, the power network connection of PCB, package, chip, etc. has not been completed, and the above-mentioned power distribution network components cannot be obtained through design, so it is crucial to determine the specifications and parameters of PCB, package and chip in subsequent design through fast fitting method at this stage.

[0053] Power distribution network (PDN) fitting:

[0054] Using past design projects, adjust the parameters of each component of the power distribution network to match the actual design parameters exactly, including frequency domain Z impedance curve fitting, determining high frequency equivalent inductance, resonant frequency and amplitude consistency, as well as time domain noise consistency; determine the fitting topology and key parameters of each component, such as power plane parasitic parameters, number of capacitors, etc.

[0055] PDN component fitting topology:

[0056] Voltage regulator module (VRM): use resistance inductance (RL) series model equivalent, which is a first-order model; the size of the inductance parameter can be obtained by testing the VRM using a network analyzer or by obtaining the SPICE MODEL provided by the manufacturer.

[0057] Printed circuit board (PCB) and chip package power plane network: use resistance inductance capacitance (RLC) model equivalent, resistance inductance represents the parasitic parameters of the plane network, and capacitance represents the coupling capacitance between the power planes.

[0058] Capacitor: mainly uses multilayer ceramic capacitor (MLCC), polymer capacitor (BULK), and the capacitor model can obtain the SPICE model from the capacitor official website.

[0059] Chip: the chip model uses the chip power model (CPM) in step S2, which is provided by the chip IP manufacturer.

[0060] As shown in Figure 4 、 Figure 5 the figure, by fitting the Z impedance curves of the PCB and the package, it can be seen that the curves of the parameters extracted from the actual design and the fitting channels are basically fitted. Among them:

[0061] As shown in Figure 4 a is the fitting impedance curve of the SERDES PHY0 VDD package (excluding package capacitance);

[0062] As shown in Figure 4 b is the fitting impedance curve of the SERDES PHY1 VDD package (excluding package capacitance);

[0063] As shown in Figure 4 c is the fitting impedance curve of the SERDES PHY2 VDD package (excluding package capacitance);

[0064] As shown in Figure 4 d is the fitting impedance curve of the SERDES PHY3 VDD package (excluding package capacitance);

[0065] As shown in Figure 5 a is the fitting impedance curve of the SERDES PHY0 VDD package (including package capacitance);

[0066] As shown in Figure 5 b is the fitting impedance curve of the SERDES PHY1 VDD package (including package capacitance);

[0067] As shown in Figure 5 c is the fitting impedance curve of the SERDES PHY2 VDD package (including package capacitance);

[0068] As shown in Figure 5 d is the fitting impedance curve of the SERDES PHY3 VDD package (including package capacitance).

[0069] Step S4. For the parameter fluctuations of the power distribution network in step S3, determine the channel design parameter variable scan table.

[0070] Due to differences in the number of power plane layers, copper clad width, capacitance quantity, via punching method, etc. in different designs, the final impact will be reflected through parameter changes of the fitting channel. Due to the changes in the PDN caused by design differences, it is necessary to clarify the allowable range of design differences, that is, the variables brought by design differences, and the corresponding scan ranges.

[0071] Due to design differences, fluctuations exist in various parameters within the power distribution network (PDN) structure. It is necessary to clarify the following key parameters to determine the channel design parameter variable scan table:

[0072] Equivalent parasitic parameters of the chip (equivalent resistance ESR, equivalent capacitance C_die);

[0073] Number and type of package capacitors (capacitance, size specifications, etc.);

[0074] Loop inductance of package capacitors (parasitic parameters of the trace from package capacitors to the chip);

[0075] Parasitic resistance and inductance of the package & PCB power supply network.

[0076] Step S5: Through time-domain noise simulation, obtain the noise magnitude corresponding to each group of design parameter variables in the channel design parameter variable scan table. According to the power supply noise specification requirements in Step S1, determine whether each group of design parameters meets the requirements, and obtain the determination result.

[0077] Step S6: Based on the chip internal power supply network information obtained in Step S2, perform power supply noise analysis, and compare the noise analysis result with the power supply noise specification requirements in Step S1 to determine whether each group of design parameters in the channel design parameter variable scan table meets the requirements, and obtain the determination result.

[0078] Parameter Figure 6 As shown, OPD represents on package decap, 4*100n represents 4 100nF capacitors; L_OPD represents the parasitic inductance of package capacitors, with the unit of pH; L_sys represents the system parasitic inductance, including all planes, traces, and vias of the PCB and package. Under the combined parameters of different numbers and capacitances of package capacitors, different parasitic inductances of package capacitors, and different system parasitic inductances, obtain the corresponding noise magnitude.

[0079] Power supply noise analysis includes:

[0080] Integrate the chip power supply model in Step S2 into the power distribution network in Step 3 to construct a system-level simulation framework. Check the change of the power distribution network impedance with frequency through frequency-domain analysis to identify the noise amplification points caused by resonance or parasitic effects; evaluate the transient voltage fluctuations caused by rapid current changes, quantify indicators such as peak-to-peak ripple and voltage drop through time-domain simulation. The CPM is provided by the IP manufacturer. Through the CPM current waveform curve and in combination with the power supply channel PDN impedance, the power supply noise can be quickly analyzed and compared with the power supply noise specification requirements obtained in Step S1 to determine whether the design passes.

[0081] Step S7: According to the channel design parameter variable scan table determined in Step S4 and the determination results of Step S5 and Step S6, determine the key design parameters of the power distribution network channel.

[0082] In this embodiment, the following packaging and printed circuit board (PCB) power distribution network (PDN) channel key design parameters are formulated:

[0083] Chip capacitance size;

[0084] Packaging capacitance number & type;

[0085] Packaging power plane layer distribution;

[0086] Packaging BGA power ground tin ball number and arrangement.

[0087] Therefore, even in the absence of design files in the early design stage, the key parameters of each component of the entire power network design network are determined, ensuring project progress and efficiency.

[0088] The application can provide accurate power noise optimization guidance in the early design stage, significantly reduce design cost and cycle, and can be widely applied to high-speed SERDES interface design, power integrity analysis and related fields.

[0089] The embodiment also provides a preliminary high-speed SERDES power PDN channel design system, which comprises a PDN channel design module.

[0090] The embodiment also provides a non-transitory computer readable storage medium storing computer instructions, which, when executed by a processor, implement the preliminary high-speed SERDES power PDN channel design method.

[0091] Referring to Figure 7 The embodiment also provides an electronic device, which comprises:

[0092] The memory 201 and the processor 202 are in communication connection with each other, the memory 201 stores computer instructions, and the processor 202 executes the computer instructions to implement the preliminary high-speed SERDES power PDN channel design method.

[0093] The above only describes the preferred embodiments of the application and is not intended to limit the application. It should be noted that for those skilled in the art, without departing from the technical principles of the application, a number of improvements and modifications can be made, and these improvements and modifications should also be considered as the protection scope of the application.

Claims

1. A method for designing an initial high-speed SERDES power supply PDN channel, characterized in that, Includes the following steps: Step 1: Obtain key information about the SERDES power supply, including power supply type and supply voltage, power supply noise specifications, and power consumption. Step 2: Obtain the chip power model of the SERDES power supply and analyze the chip power model to obtain the internal power network information of the chip. Step 3: Based on historical data from previous design projects, adjust the parameters of each component of the power distribution network to fit the power distribution network and establish the power distribution network. Step 4: Determine the channel design parameter variable scan table for the parameter fluctuations of the power distribution network in Step 3; Step 5: Through time-domain noise simulation, obtain the noise level corresponding to each group of design parameter variables in the channel design parameter variable scanning table. Based on the power supply noise specification requirements described in Step 1, determine whether each group of design parameters meets the requirements and obtain the determination result. Step 6: Perform power noise analysis based on the internal power network information of the chip obtained in Step 2, and compare the noise analysis results with the power noise specification requirements described in Step 1 to determine whether each set of design parameters in the channel design parameter variable scanning table meets the requirements, and obtain the determination result. Step 7: Based on the channel design parameter variable scan table determined in Step 4 and the judgment results of Steps 5 and 6, determine the key design parameters of the power distribution network channel.

2. The initial high-speed SERDES power PDN channel design method according to claim 1, characterized in that, The SERDES power supply mentioned in step 1 includes IO power supply, PLL power supply, analog power supply, and digital DSP module power supply.

3. The initial high-speed SERDES power PDN channel design method according to claim 2, characterized in that, The chip internal power network information mentioned in step 2 includes dynamic current distribution, parasitic parameters, and power and ground network characteristics; the parasitic parameters include resistance, inductance, and capacitance.

4. The initial high-speed SERDES power PDN channel design method according to claim 3, characterized in that, The components mentioned in step 3 include a voltage regulation module, a power plane, a decoupling capacitor, a packaged power network, and an internal power grid.

5. The initial high-speed SERDES power PDN channel design method according to claim 4, characterized in that, Step 3 includes: Using previous design projects, the parameters of each component of the power distribution network were adjusted to achieve complete consistency with the actual design parameters, including frequency domain Z-impedance curve fitting, determination of high-frequency equivalent inductance, consistency of resonant frequency and amplitude, and consistency of time domain noise. Define the fitting topology and the key parameters of each component.

6. The initial high-speed SERDES power PDN channel design method according to claim 5, characterized in that, The power supply noise analysis described in step 6 includes: The chip power supply model from step 2 is integrated into the power distribution network from step 3 to build a system-level simulation framework. Frequency domain analysis is used to examine the impedance change of the power distribution network with frequency and to identify noise amplification points caused by resonance or parasitic effects. Time domain simulation is used to evaluate transient voltage fluctuations caused by rapid current changes, quantify peak-to-peak ripple, and voltage drop indicators.

7. A design system for an initial high-speed SERDES power PDN channel, characterized in that, It includes a PDN channel design module, which performs the initial high-speed SERDES power PDN channel design method as described in any one of claims 1-6.

8. A non-transitory computer-readable storage medium, characterized in that, The non-transitory computer-readable storage medium stores computer instructions that, when executed by a processor, implement the initial high-speed SERDES power PDN channel design method as described in any one of claims 1-6.

9. An electronic device, characterized in that, include: A memory and a processor are communicatively connected, the memory stores computer instructions, and the processor executes the computer instructions to perform the initial high-speed SERDES power PDN channel design method as described in any one of claims 1-6.

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