Reworking method of thin film defect and manufacturing method of SGT structure

Abstract

The invention provides a reworking method of thin film defects and a manufacturing method of an SGT structure, the reworking method of the thin film defects comprises the step of carrying out chemical mechanical grinding treatment on a thin film deposited with the thin film defects, and the thin film defects comprise film forming particle defects. Furthermore, according to the manufacturing method of the SGT structure provided by the invention, in the process of depositing polycrystalline silicon to fill the first groove and / or the first groove to form source polycrystalline silicon and / or gate polycrystalline silicon, a CeO2 grinding liquid with a high selection ratio is adopted to carry out chemical mechanical grinding treatment on a deposited polycrystalline silicon thin film, so that the defect of film forming particles is reduced, the polycrystalline silicon residue is avoided, and the yield of the SGT structure is improved. Therefore, the bridging between the gate polysilicon and the source electrode is avoided, and the performance of the SGT device is ensured.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for reworking thin film defects and a method for manufacturing an SGT structure. Background Art

[0002] Thin film defects are common in semiconductor integrated circuit manufacturing processes. These defects are primarily categorized into two types: fall-on particle defects and in-film particle defects. While fall-on particle defects can be easily removed through wet cleaning, in-film particle defects are difficult to remove, particularly for critical layers, where they can become fatal defects. For example, in SGT (Shield Gate Trench) products, in-film particle defects in the polysilicon layer can become polysilicon residues after etchback, potentially leading to bridging between the gate polysilicon and the source. Summary of the Invention

[0003] The object of the present invention is to provide a method for reworking thin film defects and a method for manufacturing an SGT structure, comprising chemical mechanical polishing treatment of a thin film deposited with thin film defects, wherein the thin film defects include film-forming particle defects, and reducing the film-forming particle defects through chemical mechanical polishing rework treatment.

[0004] To achieve the above object, the present invention provides a method for reworking thin film defects, comprising: performing chemical mechanical polishing on a thin film deposited with thin film defects, wherein the thin film defects include film-forming particle defects.

[0005] Alternatively, for a thin film that can be repaired, a defective layer of the thin film near the surface is removed by chemical mechanical polishing, and then the thin film is repaired.

[0006] Optionally, for non-replenishable films, determine the size of the process window.

[0007] If the process window is larger than the set value, the film defect layer close to the surface is directly removed by chemical mechanical polishing;

[0008] If the process window is smaller than the set value, based on the type of deposited film and the differences in the polishing rates of different films in the chemical mechanical polishing process, a high selectivity polishing fluid is used to control the polishing rate of the chemical mechanical polishing process to remove the defective layer of the film close to the surface while ensuring that the deposited thickness of the film is within the specification range.

[0009] Furthermore, the present invention also provides a method for manufacturing an SGT structure, which uses the thin film defect reworking method as described in any of the above items to remove thin film defects, comprising:

[0010] Providing a substrate, forming a plurality of spaced first trenches in the substrate, wherein the first trenches are hollow and have field oxide layers formed on inner walls;

[0011] depositing polysilicon to fill the first trench to form source polysilicon;

[0012] Etching a portion of the field oxide layer and the substrate on both sides of the source polysilicon to expose a portion of the surface of the source polysilicon to form a second trench;

[0013] depositing polysilicon to fill the second trench to form gate polysilicon;

[0014] Wherein, depositing polysilicon to fill the first trench and / or the first trench comprises:

[0015] The deposited polysilicon film is subjected to chemical mechanical polishing using a high selectivity CeO2 polishing liquid.

[0016] Optionally, the field oxide layer includes silicon dioxide and silicon nitride.

[0017] Optionally, the chemical mechanical polishing process has a polishing removal rate of polysilicon:silicon dioxide:silicon nitride=7:27:1.

[0018] Optionally, the chemical mechanical polishing treatment time is 40 seconds to 50 seconds.

[0019] Optionally, after forming the second trench and before depositing polysilicon to fill the second trench, the method further includes:

[0020] forming a gate oxide layer, wherein the gate oxide layer at least covers the exposed source polysilicon and an inner wall of the second trench;

[0021] Optionally, the method for manufacturing the SGT structure further includes:

[0022] A P-well region and an N-type heavily doped region are formed between adjacent SGT structures. The N-type heavily doped region is close to the surface of the substrate and is located above the P-well region.

[0023] Optionally, the method for manufacturing the SGT structure further includes:

[0024] forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer covers the SGT structure;

[0025] The interlayer dielectric layer, the N-type heavily doped region and the P-well region are etched to form contact holes.

[0026] In summary, the present invention provides a method for reworking thin film defects and a method for fabricating an SGT structure, comprising chemically mechanically polishing a thin film deposited with thin film defects, wherein the thin film defects include film-forming particle defects. Furthermore, the method for fabricating an SGT structure provided by the present invention includes chemically mechanically polishing the deposited polysilicon film using a high-selectivity CeO2 polishing liquid during the process of depositing polysilicon to fill the first trench and / or the first trench to form source polysilicon and / or gate polysilicon, thereby reducing film-forming particle defects, avoiding polysilicon residue, and thereby preventing bridging between the gate polysilicon and the source, thereby ensuring the performance of the SGT device. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1A It is a structural diagram of an SGT structure;

[0028] Figure 1B A schematic flow chart of a method for manufacturing an SGT structure provided in an embodiment of the present invention;

[0029] Figure 2 Electron microscope images of corresponding steps in the method for manufacturing an SGT structure provided in one embodiment of the present invention;

[0030] Figure 3A is the corresponding wafer defect map after source polysilicon deposition;

[0031] Figure 3B This is a defect map of the wafer detected after source polysilicon etching;

[0032] Figure 4A This is an electron microscope image of the wafer after gate polysilicon etching;

[0033] Figure 4B This is the FIB image of the gate polysilicon after etching;

[0034] Figure 5 Electron microscope images of corresponding steps in a method for manufacturing an SGT structure provided by another embodiment of the present invention;

[0035] Figure 6A This is the corresponding wafer defect map after gate polysilicon deposition;

[0036] Figure 6B This is a wafer defect map detected after gate polysilicon etching.

[0037] The description of the accompanying drawings is as follows:

[0038] 100 - substrate; 101 - field oxide layer; 102 - source polysilicon; 103 - gate oxide layer; 104 - gate polysilicon; 105 - P-well region; 106 - N-type heavily doped region; 107 - contact through hole. DETAILED DESCRIPTION

[0039] To make the content of the present invention more clear and understandable, the content of the present invention is further described below in conjunction with the accompanying drawings. Of course, the present invention is not limited to this specific embodiment, and general replacements known to those skilled in the art are also covered within the scope of protection of the present invention.

[0040] Secondly, the present invention is described in detail using schematic diagrams. When describing the examples of the present invention in detail, for the sake of ease of explanation, the schematic diagrams are not partially enlarged according to general proportions, and this should not be regarded as a limitation of the present invention.

[0041] For ease of description, some embodiments of the present invention may use spatially relative terms such as "above", "below", "top", "below", etc. to describe the relationship between one element or component and another (or other) elements or components as shown in the various figures of the embodiments. It should be understood that in addition to the orientations described in the figures, the spatially relative terms are also intended to include different orientations of the device in use or operation. For example, if the device in the figures is turned over, the elements or components described as being "below" or "beneath" other elements or components will subsequently be positioned as being "above" or "above" the other elements or components. The terms "first", "second", etc., hereinafter, are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence.

[0042] Figure 1 is a schematic diagram of an SGT structure. As shown in Figure 1, after a first trench is formed in a substrate 100, the interior of the first trench is hollow and a field oxide layer 101 is formed on the inner wall. Polysilicon is deposited to fill the first trench, forming source polysilicon (P0) 102. Then, a portion of the field oxide layer 101 and substrate 100 on both sides of the source polysilicon 102 are etched back to form a second trench, where polysilicon is deposited to form gate polysilicon (P1) 104. Because film-forming particle defects in the deposited source polysilicon 102 become polysilicon residues after etching back, the subsequent deposition of gate polysilicon 104 forms a poly bump (shown in A in Figure 1), which can lead to a bridge between the gate polysilicon and the source (shown in B in Figure 1), affecting the performance of the SGT device.

[0043] In view of this, the present invention provides a method for reworking thin film defects and a method for fabricating an SGT structure. The method for reworking thin film defects includes chemical mechanical polishing of a thin film deposited with thin film defects, wherein the thin film defects include film-forming particle defects. Furthermore, the method for fabricating an SGT structure provided by the present invention includes chemical mechanical polishing of the deposited polysilicon thin film using a high-selectivity CeO2 polishing liquid during the process of depositing polysilicon to fill the first trench and / or the first trench to form source polysilicon and / or gate polysilicon, thereby reducing film-forming particle defects, avoiding polysilicon residue, and thereby preventing bridging between the gate polysilicon and the source, thereby ensuring the performance of the SGT device.

[0044] The present invention provides a method for reworking film defects, comprising: performing chemical mechanical polishing (CMP) on a film with film defects, wherein the film defects include film-forming particle defects. Chemical mechanical polishing (CMP) can be used as a reworking method for the film defects.

[0045] For thin films that can be lengthened (mainly flat surfaces), chemical mechanical polishing is used to remove the defective layer of the thin film near the surface, and then the thin film is lengthened for rework.

[0046] For non-replenishable films (mainly those with uneven surfaces), determine the size of the process window:

[0047] If the process window is larger than the set value, the film defect layer close to the surface can be directly removed by chemical mechanical polishing;

[0048] If the process window is smaller than the set value, based on the type of deposited film and the differences in the CMP process's polishing rates for different films, a highly selective slurry can be used to control the CMP polishing rate (for example, a CMP process with an extremely low polishing rate) to remove film defects near the surface while ensuring that the film's deposition thickness is within the specified range. For example, PLY_CMP (Poly slurry) can be used to polish oxide or SiN film defects, while DSTI_CMP (CeO2 slurry) can be used to rework Poly or SiN films.

[0049] The present invention also provides a method for manufacturing an SGT structure, comprising removing film defects by using the above-mentioned film defect reworking method.

[0050] Figure 1B A flow chart of a method for manufacturing an SGT structure provided by an embodiment of the present invention is shown as follows: Figure 1B As shown, the method for manufacturing the SGT structure provided in this embodiment includes the following steps:

[0051] Step S01: providing a substrate, forming a plurality of spaced first trenches in the substrate, wherein the first trenches are hollow and have field oxide layers formed on their inner walls;

[0052] Step S02: depositing polysilicon to fill the first trench to form source polysilicon;

[0053] Step S03: etching a portion of the field oxide layer and the substrate on both sides of the source polysilicon to expose a portion of the surface of the source polysilicon to form a second trench, and

[0054] Step S04: depositing polysilicon to fill the second trench to form gate polysilicon; wherein,

[0055] Depositing polysilicon to fill the first trench and / or the first trench includes:

[0056] The deposited polysilicon film is subjected to chemical mechanical polishing using a high selectivity CeO2 polishing liquid.

[0057] refer to Figure 1A As shown, specifically, first, a substrate 100 is provided, and a plurality of spaced first trenches are formed in the substrate 100 . The interior of the first trench is hollow and a field oxide layer 101 is formed on the inner wall. Polysilicon is deposited to fill the first trench to form source polysilicon 102 .

[0058] The formation of the source polysilicon 102 includes: performing chemical mechanical polishing on the deposited polysilicon film using a high selectivity CeO2 polishing liquid to remove film particle defects to avoid affecting the subsequent filling of gate polysilicon.

[0059] The field oxide layer 10 includes silicon dioxide and silicon nitride, and the chemical mechanical polishing process has a polishing removal rate of polysilicon: silicon dioxide: silicon nitride = 7:27:1. The chemical mechanical polishing process lasts for 40 seconds to 50 seconds, for example, 45 seconds.

[0060] Next, a portion of the field oxide layer 101 and the substrate 100 on both sides of the source polysilicon 102 is etched to expose a portion of the surface of the source polysilicon 102, thereby forming a second trench. Polysilicon is deposited to fill the second trench, thereby forming a gate polysilicon 104. After forming the second trench and before depositing polysilicon to fill the second trench, the process further includes: forming a gate oxide layer 103, wherein the gate oxide layer 103 at least covers the exposed source polysilicon 102 and the inner wall of the second trench;

[0061] Next, polysilicon is deposited to fill the second trench to form gate polysilicon 104. In one embodiment of the present invention, the process of depositing polysilicon to fill the second trench to form gate polysilicon includes chemical mechanical polishing of the filled polysilicon film. For example, a highly selective CeO2 polishing solution can be used to chemical mechanical polish the deposited polysilicon film.

[0062] In one embodiment of the present invention, the method for manufacturing the SGT structure further includes: forming a P-well region 105 and an N-type heavily doped region 106 between adjacent SGT structures, wherein the N-type heavily doped region 106 is close to the surface of the substrate and located above the P-well region 105 .

[0063] In another embodiment of the present invention, the method for manufacturing the SGT structure further includes:

[0064] forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer covers the SGT structure;

[0065] The interlayer dielectric layer, the N-type heavily doped region, and the P-well region are etched to form a contact through hole (CT) 107 .

[0066] Figure 2 Electron microscope images of corresponding steps in the method for manufacturing the SGT structure provided in one embodiment of the present invention; and Figure 2 Correspondingly, Figure 3A is the wafer defect map corresponding to the source polysilicon deposition (P0_DEP), Figure 3B is the wafer defect map of source polysilicon after etching inspection (P0_AEI); Figure 2 、 Figure 3A and Figure 3B Correspondingly, Figure 4A This is the wafer electron microscope image after gate polysilicon etching (P1_AEI). Figure 4B This is the FIB image of the gate polysilicon post-etch inspection (P1_AEI).

[0067] refer to Figures 1A to 4B As shown, after the source polysilicon (P0) is deposited and chemical mechanical polishing (Post CMP RWK) is performed, the film particle defects are basically removed, and no polysilicon remains at the mesa after the poly recess step. The defect of P0_AEI is based on the first trench. From the FIB image of P1_AEI, it can be seen that the defect of P0_DEP after CMP RWK treatment does not affect the filling and recessing steps of P1.

[0068] Figure 5 This is an electron microscope image of the corresponding steps in a method for manufacturing an SGT structure provided by another embodiment of the present invention; accordingly, Figure 6A This is the wafer defect map corresponding to gate polysilicon deposition (P1_DEP), Figure 6B This is the wafer defect map of gate polysilicon post-etch inspection (P1_AEI). Figure 1A 、 Figure 1B 、 Figure 5 、 Figure 6A and Figure 6B As shown, after the gate polysilicon (P1) is deposited, it is subjected to chemical mechanical polishing (Post CMP RWK) treatment, and the film particle defects are basically removed. No polysilicon residue is found after the poly recess step, and the defects of P1_AEI meet the basic requirements.

[0069] In summary, the present invention provides a method for reworking thin film defects and a method for fabricating an SGT structure. The method for reworking thin film defects includes chemical mechanical polishing of a thin film deposited with thin film defects, wherein the thin film defects include film-forming particle defects. Furthermore, the method for fabricating an SGT structure provided by the present invention includes chemical mechanical polishing of the deposited polysilicon thin film using a high-selectivity CeO2 polishing liquid during the process of depositing polysilicon to fill the first trench and / or the first trench to form source polysilicon and / or gate polysilicon, thereby reducing film-forming particle defects, avoiding polysilicon residue, and thereby preventing bridging between the gate polysilicon and the source, thereby ensuring the performance of the SGT device.

[0070] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for reworking film defects, characterized in that: include: A chemical mechanical polishing process is performed on a thin film deposited with film defects, wherein the film defects include film-forming particle defects.

2. The method for reworking thin film defects according to claim 1, characterized in that: For the growable film, the defective layer of the film near the surface is removed by chemical mechanical polishing, and then the film is grown.

3. The method for reworking thin film defects according to claim 1, characterized in that: For non-replenishable films, determine the size of the process window. If the process window is larger than the set value, the film defect layer close to the surface is directly removed by chemical mechanical polishing; If the process window is smaller than the set value, based on the type of deposited film and the differences in the polishing rates of different films in the chemical mechanical polishing process, a high selectivity polishing fluid is used to control the polishing rate of the chemical mechanical polishing process to remove the defective layer of the film close to the surface while ensuring that the deposited thickness of the film is within the specification range.

4. A method for manufacturing an SGT structure, characterized in that: The thin film defect rework method according to any one of claims 1 to 3 is used to remove the thin film defect, comprising: Providing a substrate, forming a plurality of spaced first trenches in the substrate, wherein the first trenches are hollow and have field oxide layers formed on inner walls; depositing polysilicon to fill the first trench to form source polysilicon; Etching a portion of the field oxide layer and the substrate on both sides of the source polysilicon to expose a portion of the surface of the source polysilicon to form a second trench; depositing polysilicon to fill the second trench to form gate polysilicon; Wherein, depositing polysilicon to fill the first trench and / or the first trench comprises: The deposited polysilicon film is subjected to chemical mechanical polishing using a high selectivity CeO2 polishing liquid.

5. The method for manufacturing the SGT structure according to claim 4, characterized in that: The field oxide layer includes silicon dioxide and silicon nitride.

6. The method for manufacturing the SGT structure according to claim 5, characterized in that: The chemical mechanical polishing process has a polishing removal rate of polysilicon:silicon dioxide:silicon nitride=7:27:

1.

7. The method for manufacturing the SGT structure according to claim 6, characterized in that: The chemical mechanical polishing treatment lasts for 40 to 50 seconds.

8. The method for manufacturing the SGT structure according to claim 1, wherein: After forming the second trench and before depositing polysilicon to fill the second trench, the method further includes: A gate oxide layer is formed, wherein the gate oxide layer at least covers the exposed source polysilicon and the inner wall of the second trench.

9. The method for manufacturing the SGT structure according to claim 1, wherein: Also includes: A P-well region and an N-type heavily doped region are formed between adjacent SGT structures. The N-type heavily doped region is close to the surface of the substrate and is located above the P-well region.

10. The method for manufacturing the SGT structure according to claim 9, characterized in that: Also includes: forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer covers the SGT structure; The interlayer dielectric layer, the N-type heavily doped region and the P-well region are etched to form contact holes.

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