Semiconductor film layer etching method and semiconductor process equipment

Abstract

The invention relates to the technical field of semiconductor etching, in particular to an etching method of a semiconductor film layer and semiconductor process equipment. The method comprises the following steps: a main etching step: introducing a process gas into a process chamber, exciting to generate plasma, and etching a target film layer attached to the surface layer of a deep groove structure and the upper part of the inner wall of the deep groove structure; a deposition step: depositing a self-mask layer on the surface of the surface oxide layer of the deep groove structure; and an over-etching step: introducing process gas into the process chamber, exciting to generate plasma, and etching the target film layer attached to the lower part of the inner wall of the deep groove structure. According to the etching method of the semiconductor film layer and the semiconductor process equipment provided by the invention, the target film layers attached to the surface layer of the deep groove structure and the upper part and the lower part of the inner wall can be etched step by step, and the oxide layer of the surface layer is not easy to etch; in addition, the residual amount of the target film layer in the side wall groove of the deep groove structure can be ensured to meet the requirement.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor etching technology, and in particular to a semiconductor film layer etching method and semiconductor process equipment. Background Art

[0002] As the gate width of transistors decreases, the electrostatic problem of Fin field-effect transistors restricts the further development of transistors. Gate all around (GAA) transistors are considered to be a new technology that can replace traditional methods.

[0003] In a fully surrounded gate structure, the periphery is covered with a TiN film layer, which needs to be selectively removed. The relevant etching method mainly adopts wet etching. However, wet etching has isotropic etching characteristics. It is difficult to complete the etching of the TiN film layer inside the fully surrounded gate structure while ensuring that SiO2 is not etched, and it is difficult to control the remaining amount of TiN in the sidewall groove. Summary of the Invention

[0004] The purpose of the present invention is to provide a semiconductor film etching method and semiconductor process equipment to solve the technical problems existing in the related art of etching TiN film layers, namely, it is difficult to complete the etching of the TiN film layer inside the full-ring gate structure while ensuring that SiO2 is not etched, and it is difficult to control the residual amount of TiN in the sidewall groove.

[0005] The semiconductor film etching method provided by the present invention is used to etch a target film layer attached to the surface layer and inner wall of a deep trench structure, and the method comprises:

[0006] A main etching step, introducing a process gas into the process chamber and exciting to generate plasma, etching the target film layer attached to the surface layer and the upper portion of the inner wall of the deep trench structure;

[0007] In a deposition step, a self-mask layer is deposited on the surface of the surface oxide layer of the deep trench structure;

[0008] In the over-etching step, process gas is introduced into the process chamber and excited to generate plasma, so as to etch the target film layer attached to the lower portion of the inner wall of the deep trench structure.

[0009] Preferably, as an implementation method, the upper RF power in the main etching step is greater than the upper RF power in the over-etching step, and the lower RF power in the main etching step is zero;

[0010] And / or, in the over-etching step, the upper RF power is greater than the lower RF power, and the lower RF power is greater than zero.

[0011] Preferably, as an implementation method, in the main etching step, the upper RF power adopts a high-selectivity film removal mode, and the upper RF power ranges from 1200 to 1600 W;

[0012] And / or, in the over-etching step, the upper RF power is 600-1000W, the lower RF power adopts a pulse mode, and the lower RF power is 40-100W.

[0013] Preferably, as an implementation method, in the over-etching step, the pulse frequency of the lower RF power supply is 200-500 Hz, and the duty cycle is 20%-50%.

[0014] Preferably, as an implementation method, the gas pressure in the main etching step is greater than the gas pressure in the over-etching step.

[0015] Preferably, as an implementation method, the gas pressure in the main etching step is 300-500 mT, and / or the gas pressure in the over-etching step is 50-80 mT.

[0016] Preferably, as an implementation method, in the process gas of the main etching step, the flow rate of the etching gas is 300-500 sccm, the flow rate of the dilution gas is 100-200 sccm, and the flow rate of the protective gas is 300-500 sccm;

[0017] And / or, in the process gas of the over-etching step, the flow rate of the etching gas is 50-200 sccm, the flow rate of the dilution gas is 100-200 sccm, and the flow rate of the protective gas is 200-300 sccm;

[0018] Wherein, the etching gas includes Cl2 or BCl3, the dilution gas includes He or Ar, and the protective gas includes N2.

[0019] Preferably, as an implementation method, in the process gas of the main etching step, the etching gas accounts for 30% to 50%, the dilution gas accounts for 10% to 20%, and the protective gas accounts for 30% to 50%.

[0020] Preferably, as an implementable embodiment, in the main etching step and the over-etching step, the temperature of the electrostatic chuck is 50-80°C.

[0021] Preferably, as an implementation method, the composition of the target film layer includes any one of TiN, TaO, TaN, HfO2 and TiAl.

[0022] Preferably, as an implementation method, before the main etching step, the method further includes:

[0023] In the transfer step, process gas is introduced into the process chamber to assist the main etching step in stabilizing the ignition.

[0024] Preferably, as an implementable embodiment, the transfer step includes a first transfer step and a second transfer step.

[0025] The gas pressure in the first transfer step is smaller than the gas pressure in the second transfer step, which is smaller than the gas pressure in the main etching step, and / or the upper RF power in the first transfer step and the upper RF power in the second transfer step are both consistent with the values ​​of the upper RF power in the main etching step.

[0026] Preferably, as an implementation method, the gas pressure in the first transfer step is 50-70 mT, and the gas pressure in the second transfer step is 150-250 mT;

[0027] And / or, in the first transfer step and the second transfer step, the upper RF power is 1200-1600 W, and the process time is 2-4 s.

[0028] Preferably, as an embodiment, the deposition step includes:

[0029] A C-containing gas is introduced into the process chamber to deposit a self-masking layer with C as a main component on the surface of the surface oxide layer.

[0030] Preferably, as an implementation method, in the deposition step, the flow rate of the C-containing gas is 100-300 sccm, and / or the gas pressure is 10-30 mT, and / or the temperature of the electrostatic chuck is 40-60° C., and / or the upper RF power is 800-1200 W, and / or the process time is 30-60 s;

[0031] And / or, the C-containing gas includes CH4.

[0032] Preferably, as an embodiment, after the over-etching step, the method further comprises:

[0033] The deep trench structure is cleaned to remove the remaining self-mask layer and the attachments on the surface of the deep trench structure.

[0034] Preferably, as an implementable method, the cleaning step includes:

[0035] A cleaning gas is introduced into the process chamber, with a gas pressure of 20 to 50 mT, an upper RF power of 800 to 1200 W, and a lower RF power of zero; wherein the cleaning gas includes O2 and / or N2.

[0036] The semiconductor process equipment provided by the present invention includes a process chamber, an air inlet assembly, an upper electrode assembly, a lower electrode assembly and a controller. The controller includes at least one processor and at least one memory. The memory stores a computer program. When the computer program is executed by the processor, the above-mentioned semiconductor film layer etching method is implemented.

[0037] Compared with the related art, the present invention has the following beneficial effects:

[0038] The semiconductor film etching method and semiconductor process equipment provided by the present invention can achieve step-by-step etching of the target film layer attached to the surface layer and the upper and lower parts of the inner wall of the deep trench structure, and by arranging a deposition step between two etching steps (the main etching step and the over-etching step), the surface oxide layer of the deep trench structure can be protected. Thus, while ensuring that the surface oxide layer is not etched, the etching of the target film layer (such as a TiN film layer) inside the deep trench structure can be completed; in addition, the process duration of the main etching step can be set as needed to ensure that the remaining amount of the target film layer in the sidewall groove of the deep trench structure meets the requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0040] Figure 1 A schematic diagram of a three-dimensional semiconductor structure in related technology;

[0041] Figure 2 A first schematic flow chart of a method for etching a semiconductor film layer provided in an embodiment of the present invention;

[0042] Figure 3a-Figure 3e A schematic diagram of a process flow of a semiconductor film etching method provided by an embodiment of the present invention;

[0043] Figure 4 A second schematic flow chart of a method for etching a semiconductor film layer provided in an embodiment of the present invention;

[0044] Figure 5 A schematic structural diagram of a semiconductor process equipment provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0045] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0046] See also Figure 1 In the related technology for lateral etching of a three-dimensional semiconductor structure, a stacked layer 120 is first formed, in which multiple first layers 121 to be etched and multiple second layers 122 overlap. At least two spaced-apart filling layers 1231 are formed in the stacked layer 120, and a channel bridge 1211 for the passage of an etching solution is formed between two adjacent filling layers 1231. Along a lateral etching path parallel to the surface of the stacked layer 120, the volume of the first layer 121 is narrowed at the channel bridge 1211. Wet etching is used to laterally etch the first layer 121. In the wet etching environment, the etching rate of the first layer 121 is greater than the etching rate of the filling layer 1231. In this related technology, although the diffusion flux of the etching components in the etching solution is limited when the etching solution passes through the channel bridge 1211 between two adjacent filling layers 1231, the difference in the etching amount between different first layers 121 is reduced to a certain extent, and the uniformity of the etching amount of each first layer 121 is improved to a certain extent, based on the etching characteristics of wet etching, it is still impossible to accurately control the etching rate in each direction, so the remaining amount of the TiN film layer in the sidewall groove cannot be well controlled.

[0047] Another related technique uses dry etching, with CF4 and C4F6 as the etching process gases, a C4F6 / CF4 ratio of 1:7 to 1:10, and a total gas flow rate range of 100 to 150 sccm, to selectively etch the SiGe sacrificial layer of the GAA ring gate structure. The specific steps include: Main Etch 1 (Me1), an oxygen deposition protection step (O2 deposition, O2 dep), and Main Etch 2 (Me2). Although this related technique can ultimately remove the SiGe sacrificial layer and protect the Si layer during the etching process, the etching gas used has a low etching rate for TiN and is less selective for the oxide layer (OX). Therefore, it cannot ensure that the top oxide layer (OX) will not be etched during the effective removal of the sidewall TiN film.

[0048] Based on this, an embodiment of the present invention provides a semiconductor film etching method and semiconductor process equipment. By optimizing the etching process, gas, temperature, pressure and radio frequency power, high selective etching of TiN to SiO2 (the selectivity of TiN to SiO2 is greater than 40) can be achieved. On the basis of ensuring that SiO2 is not etched, the etching of the TiN film layer in various peripheral parts (including the surface layer and the inner wall of the deep trench) of the deep trench structure (such as: full-ring gate structure) is completed. At the same time, the etching rate in each direction can be precisely controlled, and the remaining amount of the TiN film layer in the sidewall groove of the full-ring gate structure can be controlled. In this case, the transistor size can be made smaller.

[0049] The present invention will be further described in detail below through specific implementation examples in conjunction with the accompanying drawings.

[0050] Figure 2 The following is a schematic flow chart of a method for etching a semiconductor film layer in one embodiment of the present invention. The method can be used to etch a target film layer attached to the surface and inner wall of a deep trench structure (e.g., a gate-all-around structure). The method includes:

[0051] S102, a main etching step, introduces process gas into the process chamber and excites plasma to etch the target film layer attached to the surface layer and the upper portion of the inner wall of the deep trench structure.

[0052] Specifically, the deep trench structure 100 before etching is as follows: Figure 3a As shown; a radio frequency power supply can be used to excite the process gas to generate plasma, and the target film layer 11 of the shallower portion such as the surface layer and the upper portion of the inner wall of the deep trench structure 100 is etched. By controlling the process time of the main etching step, the remaining amount of the target film layer 11 in the sidewall groove of the deep trench structure 100 can reach the target amount, as shown in FIG. Figure 3b shown.

[0053] S104, a deposition step, deposits a self-mask layer on the surface of the surface oxide layer of the deep trench structure.

[0054] It should be noted that a self-mask layer 13 is deposited on the surface of the surface oxide layer 12, such as Figure 3c can be used to deposit the self-mask layer 13 as a protective layer to protect the surface oxide layer 12 to prevent subsequent etching steps from damaging the surface oxide layer 12.

[0055] S106, an over-etching step, introducing a process gas into the process chamber and exciting to generate plasma, thereby etching the target film layer attached to the lower portion of the inner wall of the deep trench structure.

[0056] Specifically, a radio frequency power supply can be used to excite the process gas to generate plasma to etch the target film layer 11 at the lower portion of the inner wall of the deep trench structure 100. Since the surface oxide layer 12 is covered with a self-mask layer 13, the plasma will not damage the surface oxide layer 12 when bombarding the surface of the deep trench structure 100. The deep trench structure 100 after etching is as shown in FIG. Figure 3d shown.

[0057] In summary, the etching method of the semiconductor film layer provided in this embodiment can realize the etching of the target film layer 11 attached to the surface layer and the upper and lower parts of the inner wall of the deep trench structure 100 in steps, and by setting the deposition step S104 between the two etching steps (the main etching step S102 and the over-etching step S106), the surface oxide layer 12 of the deep trench structure 100 can be protected. Therefore, on the basis of ensuring that the surface oxide layer 12 is not etched, the etching of the target film layer 11 (such as TiN film layer) inside the deep trench structure 100 can be completed; in addition, the process duration of the main etching step can be set as needed to ensure that the remaining amount of the target film layer 11 in the sidewall groove of the deep trench structure 100 meets the requirements.

[0058] It should be noted that, during the etching process, the main etching step ME, the deposition step dep and the over-etching step OE may be sequentially executed once, or may be sequentially executed several times in a cycle.

[0059] In the related art, the upper RF power and the lower RF power are usually set to be greater than 0, that is, the upper RF power and the lower RF power are combined to etch the TiN film layer. Under this condition, although the surface TiN film layer can be etched, the TiN film layer on the inner wall of the deep groove structure cannot be etched, and the TiN film layer has a relatively low etching selectivity for the oxide layer. In the present application, the upper RF power in the main etching step is set to be greater than the upper RF power in the over-etching step, and the lower RF power in the main etching step is set to zero, that is, in the main etching step, a high lateral selectivity etching process with only high upper RF power is adopted, which can make the process gas dissociated more fully, and the obtained plasma can bombard the surface layer and the upper part of the inner wall of the deep groove structure 100, so that the target film layer 11 attached to the surface layer and the upper part of the inner wall of the deep groove structure 100 can be well etched and removed, and the target film layer 11 has a relatively high etching selectivity for the oxide layer, and the oxide layer is not easily lost.

[0060] Specifically, during the main etching step, the upper RF power supply can be set to a high-selectivity film removal mode (high SFR mode), and the upper RF power can be set to 1200-1600W. This ensures sufficient dissociation of the process gas while preventing excessive current from burning the coil of the upper RF power supply due to excessive power. Preferably, the upper RF power is set to 1300-1500W, and more preferably, 1350-1450W.

[0061] Preferably, in the over-etching step, the upper RF power is set to be greater than the lower RF power, and the lower RF power is set to be greater than zero. Under the action of the lower RF power, it can be ensured that the excited plasma can move downward to the bottom of the deep trench structure 100 to bombard the lower part of the inner wall of the deep trench structure 100, so that the remaining target film layer 11 attached to the lower part of the inner wall of the deep trench structure 100 can be completely removed.

[0062] Specifically, in the over-etching step, the upper RF power can be set to 600-1000W to ensure that the process gas can be fully dissociated. The lower RF power supply is set to pulse mode. When the lower RF power is turned on, the plasma can be accelerated to enter the bottom of the deep groove and etch and remove the target film layer 11 at the lower part of the inner wall of the deep groove structure 100; when the lower RF power is turned off, the plasma will no longer continue to move downward. At the same time, the attachments in the deep groove will be extracted to ensure that the bottom will not be stopped due to excessive attachments. The lower RF power is set to 40-100W. Setting it to a lower power value can ensure that the self-mask layer 13 of the surface layer will not be lost too much, and further ensure the protective effect of the self-mask layer 13 on the surface oxide layer 12, so that the surface oxide layer 12 will not be lost. It is preferred to set the upper RF power to 700-900W, and more preferably to 750-850W. It is preferred to set the lower RF power to 50-90W, and more preferably to 60-80W.

[0063] During the overetching step, the pulse frequency of the lower RF power supply can be set to 200-500 Hz, and the duty cycle can be set to 20%-50%. This allows for efficient etching and removal of the target film layer 11 at the bottom of the deep trench. Preferably, the pulse frequency of the lower RF power supply is set to 250-450 Hz, more preferably 300-400 Hz. Preferably, the duty cycle is set to 25%-45%, more preferably 30%-40%.

[0064] In the related art, the TiN film layer is usually etched under a low-pressure environment, and the isotropic etching is weak, making it difficult to etch the TiN film layer in the sidewall groove. The present application sets the gas pressure in the main etching step to be greater than the gas pressure in the over-etching step, and adopts a high-pressure environment in the main etching step, which can strengthen the collision of dissociated ions, shorten the free path, and make the isotropic etching stronger. As a result, it is possible to etch both the surface target film layer 11 and the target film layer 11 in the sidewall groove; at the same time, under high pressure, combined with RF power, a higher plasma density can be obtained to achieve etching of the target film layer 11. Using a low-pressure environment in the over-etching step can reduce ion collisions when the process gas dissociates, increase the ion free path, and ensure that the ions can reach the bottom of the deep groove.

[0065] Specifically, the gas pressure in the main etching step can be set to 300-500 mT, within which the isotropy of etching can be ensured, and the gas pressure in the over-etching step can be set to 50-80 mT, within which the ions can reach the bottom of the deep trench.

[0066] In one embodiment, the flow rate of the etching gas in the process gas of the main etching step is set to 300-500 sccm, the flow rate of the dilution gas is set to 100-200 sccm, and the flow rate of the protective gas is set to 300-500 sccm, wherein the etching gas can be Cl2, BCl3 or other gases; the dilution gas can be He, Ar or other gases; the protective gas can be N2 or other gases. The target film layer 11 is etched using the process gas under this combination and flow rate, which not only ensures the etching rate of the target film layer 11, but also improves the etching selectivity of the target film layer 11 to the oxide layer 12, and can ensure that the surface oxide layer 12 is not etched while the side wall target film layer 11 is cleared.

[0067] Similarly, the flow rate of the etching gas in the process gas of the over-etching step can be set to 50-200 sccm, the flow rate of the dilution gas can be set to 100-200 sccm, and the flow rate of the protective gas can be set to 200-300 sccm, wherein the etching gas can be Cl2, BCl3 or other gases; the dilution gas can be He, Ar or other gases, which can assist in ignition; the protective gas can be N2 or other gases. The target film layer 11 is etched by using the process gas under this combination and flow rate, which not only ensures the etching rate of the target film layer 11, but also improves the etching selectivity of the target film layer 11 to the oxide layer, and can complete the etching of the target film layer 11 (such as TiN film layer) on the basis of ensuring that the oxide layer is not etched.

[0068] Furthermore, the proportion of etching gas in the process gas of the main etching step can be set to 30% to 50%, the proportion of dilution gas can be set to 10% to 20%, and the proportion of protective gas can be set to 30% to 50%. Under this ratio, a good etching effect can be obtained.

[0069] Optionally, in the main etching step and the over-etching step, the temperature of the electrostatic chuck (ESC temperature) is set to 50-80°C. On the one hand, the selectivity of the target film layer 11 to the oxide layer will not be too low due to the ESC temperature being too high, so that after the surface target film layer 11 is etched, it is not easy to cause the loss of the surface oxide layer 12; on the other hand, the etching rate of the target film layer 11 will not be too slow due to the ESC temperature being too low, so that a higher etching rate can be obtained.

[0070] The target film layer 11 may be made of any one of TiN, TaO, TaN, HfO 2 and TiAl.

[0071] Taking the target film layer 11 as TiN, the oxide layer as SiO2, and the etching gas as Cl2 as an example, Cl2 has a better etching effect on TiN. Since the bond energy of Si-O is greater than the bond energy of Si-Cl, the etching rate of Cl2 on SiO2 is low, thereby obtaining a high etching selectivity ratio of the target film layer 11 to the oxide layer.

[0072] Before the main etching step, the method provided in this embodiment may further include a transfer step, in which a process gas is introduced into the process chamber to assist in stable ignition during the main etching step and prevent unstable ignition under high voltage and high RF power conditions. The composition and proportions of the process gas in the transfer step are consistent with those in the main etching step.

[0073] The above-mentioned transfer step transfer can be carried out in two steps, namely the first transfer step transfer1 and the second transfer step transfer2. Optionally, the gas pressure in the first transfer step is set to be lower than the gas pressure in the second transfer step, and the gas pressure in the second transfer step is set to be lower than the gas pressure in the main etching step. In this way, the gas pressure can be gradually increased to the gas pressure required for the main etching step; optionally, the upper RF power in the first transfer step and the upper RF power in the second transfer step are both set to be consistent with the value of the upper RF power in the main etching step, so that the environmental parameters in the process chamber can be smoothly adjusted from the standby state to the stable conditions required for etching, thereby ensuring the smooth start of the main etching step.

[0074] Specifically, the gas pressure in the first transfer step can be set to 50-70 mT, preferably 55-65 mT, more preferably 58-62 mT. The gas pressure in the second transfer step can be set to 150-250 mT, preferably 170-230 mT, more preferably 190-210 mT, and even more preferably 200 mT.

[0075] The upper RF power in the first and second transfer steps can be set to 1200-1600W, and the process duration can be set to 2-4s to ensure smooth ignition of the main etching step. The process duration is preferably 2.5-3.5s, more preferably 2.8-3.2s, and even more preferably 3s.

[0076] As an embodiment, the above-mentioned deposition step includes: introducing a C-containing gas into the process chamber to deposit a self-masking layer 13 with C as the main component on the surface of the surface oxide layer 12, which can achieve a protective effect on the surface oxide layer 12.

[0077] In the deposition step, the flow rate of the C-containing gas can be set to 100-300 sccm, preferably 150-250 sccm, and more preferably 180-220 sccm; the gas pressure is set to 10-30 mT, preferably 15-25 mT, and more preferably 18-22 mT; the temperature of the electrostatic chuck is set to 40-60°C, preferably 45-55°C, and more preferably 48-52°C; the upper RF power is set to 800-1200 W, preferably 900-1100 W, and more preferably 950-1050 W; the process time is set to 30-60 s, preferably 35-55 s, and more preferably 40-50 s, so that a self-masking layer 13 of suitable thickness can be obtained, which can well protect the surface oxide layer 12.

[0078] Specifically, CH 4 can be used as the C-containing gas.

[0079] After the over-etching step, the method provided in this embodiment further includes a flushing step for cleaning the deep trench structure 100 to remove the remaining self-mask layer 13 and the attachments on the surface of the deep trench structure 100, thereby obtaining a clean deep trench structure 100 of the desired structure. Figure 3e shown.

[0080] The cleaning step may specifically include introducing a cleaning gas into the process chamber at a pressure of 20-50 mT, an upper RF power of 800-1200 W, and a lower RF power of zero. The cleaning gas may include one or both of O₂ and N₂, thereby achieving excellent cleaning results.

[0081] After etching the TiN film layer using the above method, the morphology of the full-ring gate structure is as follows: Figure 3e As shown, it can be seen that the method provided by the present invention is used to etch the TiN film layer of the full-ring gate structure, which can not only etch the surface TiN film layer cleanly, but also etch away a portion of the TiN in the groove, and also ensure that the surface SiO2 is not damaged. The etching selectivity of TiN to SiO2 is greater than 100, which is greater than the etching selectivity of 40 that keeps SiO2 from being damaged, and a very good morphology can be obtained.

[0082] Figure 4 FIG. 1 is a schematic flow chart of a method for etching a semiconductor film layer in one embodiment of the present invention, the method comprising:

[0083] S201, first transfer step transfer1;

[0084] S202, second transfer step transfer2;

[0085] S203, main etching step ME;

[0086] S204, deposition step dep;

[0087] S205, over etching step OE;

[0088] S206, flush step.

[0089] Figure 5 A semiconductor process equipment provided by one embodiment of the present invention includes a process chamber 20, an inlet assembly 20A, an upper electrode assembly 20B and a lower electrode assembly 20C and a controller ( Figure 5 The controller includes at least one processor and at least one memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the method of any one of the above embodiments is implemented.

[0090] For example, the controller can be either a host computer or a slave computer. Specifically, the controller can control the opening of the valve of the gas inlet assembly 20A to introduce the corresponding process gas into the process chamber 20. The controller can also control the opening and closing of the valve of the gas inlet assembly 20A to control the flow rate of the process gas. The controller can also control the exhaust assembly 20D to exhaust the interior of the process chamber 20, thereby controlling the gas pressure within the process chamber 20 and removing reaction byproducts.

[0091] The upper electrode assembly 20B includes an RF coil 21, an upper RF power supply 23, and an upper matcher 25. The controller is further configured to control the upper RF power supply 23 to provide upper electrode power to the RF coil 21 via the upper matcher 25, so that the RF coil 21 excites the process gas inside the process chamber 20 to generate plasma.

[0092] The lower electrode assembly 20C includes a wafer carrier 22, a lower RF power supply 24, and a lower matcher 26. The controller is further configured to control the lower RF power supply 24 to provide lower electrode power to the lower electrode of the wafer carrier 22 via the lower matcher 26, thereby providing an RF bias to the lower electrode of the wafer carrier 22 to attract plasma above the target film layer 11 and bombard the target film layer 11. The wafer carrier 22 includes an electrostatic chuck.

[0093] The semiconductor process equipment 200 of the embodiment of the present application can be an inductively coupled plasma (ICP) etching equipment or a capacitively coupled plasma (CCP) etching equipment. The embodiment of the present application does not limit the type of the semiconductor process equipment 200.

[0094] The semiconductor process equipment provided in the embodiment of the present invention has the same technical features as the semiconductor film etching method provided in the above embodiment, and therefore can also solve the same technical problems and achieve the same technical effects.

[0095] This embodiment also provides a machine-readable storage medium, which stores machine-executable instructions. When the machine-executable instructions are called and executed by a processor, the machine-executable instructions prompt the processor to implement the above-mentioned semiconductor film layer etching method.

[0096] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described equipment and devices can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0097] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0098] In the description of the present invention, it should be noted that the terms "upper," "lower," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0099] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for etching a semiconductor film layer, for etching a target film layer attached to the surface layer and inner wall of a deep trench structure, characterized in that: The method comprises: A main etching step, introducing a process gas into the process chamber and exciting to generate plasma, etching the target film layer attached to the surface layer and the upper portion of the inner wall of the deep trench structure; In a deposition step, a self-mask layer is deposited on the surface of the surface oxide layer of the deep trench structure; In the over-etching step, process gas is introduced into the process chamber and excited to generate plasma, so as to etch the target film layer attached to the lower portion of the inner wall of the deep trench structure.

2. The method for etching a semiconductor film layer according to claim 1, wherein: The upper radio frequency power in the main etching step is greater than the upper radio frequency power in the over etching step, and the lower radio frequency power in the main etching step is zero; And / or, in the over-etching step, the upper RF power is greater than the lower RF power, and the lower RF power is greater than zero.

3. The method for etching a semiconductor film layer according to claim 1, wherein: In the main etching step, the upper RF power adopts a high-selectivity film removal mode, and the upper RF power ranges from 1200 to 1600W; And / or, in the over-etching step, the upper RF power is 600-1000W, the lower RF power adopts a pulse mode, and the lower RF power is 40-100W.

4. The method for etching a semiconductor film layer according to claim 3, wherein: In the over-etching step, the pulse frequency of the lower radio frequency power supply is 200-500 Hz, and the duty cycle is 20%-50%.

5. The method for etching a semiconductor film layer according to claim 1, wherein: The gas pressure in the main etching step is greater than the gas pressure in the over-etching step.

6. The method for etching a semiconductor film layer according to claim 5, wherein: The gas pressure in the main etching step is 300-500 mT, and / or the gas pressure in the over-etching step is 50-80 mT.

7. The method for etching a semiconductor film layer according to claim 1, wherein: In the process gas of the main etching step, the flow rate of the etching gas is 300-500 sccm, the flow rate of the dilution gas is 100-200 sccm, and the flow rate of the protective gas is 300-500 sccm; And / or, in the process gas of the over-etching step, the flow rate of the etching gas is 50-200 sccm, the flow rate of the dilution gas is 100-200 sccm, and the flow rate of the protective gas is 200-300 sccm; Wherein, the etching gas includes Cl2 or BCl3, the dilution gas includes He or Ar, and the protective gas includes N2.

8. The method for etching a semiconductor film layer according to claim 7, wherein: In the process gas of the main etching step, the etching gas accounts for 30% to 50%, the dilution gas accounts for 10% to 20%, and the protective gas accounts for 30% to 50%.

9. The method for etching a semiconductor film layer according to claim 1, wherein: In the main etching step and the over-etching step, the temperature of the electrostatic chuck is 50-80°C.

10. The method for etching a semiconductor film layer according to claim 1, wherein: The composition of the target film layer includes any one of TiN, TaO, TaN, HfO2 and TiAl.

11. The method for etching a semiconductor film layer according to claim 1, wherein: Before the main etching step, the method further includes: In the transfer step, process gas is introduced into the process chamber to assist the main etching step in stabilizing the ignition.

12. The method for etching a semiconductor film layer according to claim 11, wherein: The transfer step includes a first transfer step and a second transfer step; The gas pressure in the first transfer step is smaller than the gas pressure in the second transfer step, which is smaller than the gas pressure in the main etching step, and / or the upper RF power in the first transfer step and the upper RF power in the second transfer step are both consistent with the values ​​of the upper RF power in the main etching step.

13. The method for etching a semiconductor film layer according to claim 12, wherein: The gas pressure in the first transfer step is 50-70 mT, and the gas pressure in the second transfer step is 150-250 mT; And / or, in the first transfer step and the second transfer step, the upper RF power is 1200-1600W, and the process time is 2-4s 。 14. The method for etching a semiconductor film layer according to claim 1, wherein: The deposition step comprises: A C-containing gas is introduced into the process chamber to deposit a self-masking layer with C as a main component on the surface of the surface oxide layer.

15. The method for etching a semiconductor film layer according to claim 13, wherein: In the deposition step, the flow rate of the C-containing gas is 100-300 sccm, and / or the gas pressure is 10-30 mT, and / or the temperature of the electrostatic chuck is 40-60° C., and / or the upper RF power is 800-1200 W, and / or the process duration is 30-60 s; And / or, the C-containing gas includes CH4.

16. The method for etching a semiconductor film layer according to any one of claims 1 to 15, characterized in that: After the over-etching step, the method further comprises: The deep trench structure is cleaned to remove the remaining self-mask layer and the attachments on the surface of the deep trench structure.

17. The method for etching a semiconductor film layer according to claim 16, wherein: The cleaning step comprises: A cleaning gas is introduced into the process chamber, with a gas pressure of 20 to 50 mT, an upper RF power of 800 to 1200 W, and a lower RF power of zero; wherein the cleaning gas includes O2 and / or N2.

18. A semiconductor process equipment comprising a process chamber, an air inlet assembly, an upper electrode assembly, a lower electrode assembly and a controller, characterized in that: The controller includes at least one processor and at least one memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the semiconductor film layer etching method according to any one of claims 1 to 17 is implemented.

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