Transistor, preparation method and quantum computing device
By adjusting the three-dimensional arrangement of quantum dots and dual-gate mode regulation, the problem of suboptimal quantum bit coupling efficiency in existing semiconductor quantum computing devices has been solved, and more efficient quantum bit coupling has been achieved.
Patent Information
- Application Number
- CN202510572661.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-30
- Publication Date
- 2025-09-12
AI Technical Summary
The array arrangement of existing semiconductor quantum computing devices results in unsatisfactory quantum bit coupling efficiency.
By adjusting the arrangement of quantum dots, a three-dimensional arrangement in the vertical direction is adopted, and the coupling of quantum bits is achieved by regulating the gate voltage, and the coupling of quantum dots is further regulated by combining the dual-gate mode.
The coupling efficiency of quantum bits is improved, and more effective quantum bit coupling is achieved.
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Figure CN120640731A_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the field of semiconductor quantum computing technology, and specifically relates to a transistor, a preparation method, and a quantum computing device. Background Art
[0002] Quantum computing technology, as a new computing technology under development, has received increasing attention in recent years. By utilizing the superposition and entangled states of quantum mechanics to perform computer calculations, quantum computers will greatly increase the operating efficiency of computers and solve some computing problems that current classical computers cannot solve.
[0003] A quantum computing device is a device that realizes quantum computing by operating quantum bits. The quantum computing devices currently under research mainly include semiconductor quantum computing devices. Semiconductor quantum computing devices have the potential for scalability due to their advantage of being able to be integrated into small chips to form multi-bit arrays.
[0004] However, the linear arrangement of existing semiconductor quantum computing devices easily leads to the problem of unsatisfactory quantum bit coupling efficiency. Summary of the Invention
[0005] The technical purpose of this application is to at least solve the technical problem that the array arrangement of existing semiconductor quantum computing devices leads to unsatisfactory quantum bit coupling efficiency. The transistor provided in this application improves the quantum bit coupling efficiency by adjusting the quantum dot arrangement.
[0006] A first aspect of the present application is to provide a transistor, comprising: a semiconductor substrate and a plurality of semiconductor layers stacked along a first direction;
[0007] Each semiconductor layer includes a plurality of source / drain regions and a channel region located between the source / drain regions;
[0008] The source / drain regions are stacked along a first direction and spaced apart in a second direction; the second direction intersects the first direction;
[0009] Along the first direction, the orthographic projections of the source / drain regions of the adjacent semiconductor layers on the semiconductor substrate at least partially overlap;
[0010] The transistor further comprises a passivation layer, which is located on a surface of the semiconductor layer away from the semiconductor substrate. A first metal gate is provided in the passivation layer, which penetrates the passivation layer and abuts against the channel region.
[0011] In some embodiments, there are multiple first metal gates, and the orthographic projection of each first metal gate on the semiconductor layer is located between the source / drain regions arranged at intervals along the second direction, and the first metal gates are arranged at intervals and relatively to each other in the third direction; the third direction is arranged to intersect with the second direction.
[0012] In some embodiments, the transistor includes a second metal gate connected to the semiconductor substrate.
[0013] In some embodiments, an insulating dielectric layer is provided between adjacent semiconductor layers along the first direction.
[0014] In some embodiments, the source / drain regions of each semiconductor layer are distributed along the periphery of the insulating dielectric layer, and each source / drain region abuts against the insulating dielectric layer respectively;
[0015] The insulating dielectric layer includes an insulating dielectric main region and an insulating dielectric edge region. The insulating dielectric main region is arranged between the passivation layer and the semiconductor substrate. The insulating dielectric edge region is arranged between the source / drain regions stacked along the first direction.
[0016] In some embodiments, a quantum dot is formed in a region where an orthographic projection of the metal gate on the semiconductor substrate overlaps with an orthographic projection of the channel layer on the semiconductor substrate.
[0017] In some embodiments, a plurality of source / drain contacts are provided in the passivation layer, and each source / drain contact penetrates the passivation layer and is respectively connected to each source / drain region.
[0018] In some embodiments, the semiconductor substrate includes a silicon semiconductor substrate or a silicon-germanium semiconductor substrate;
[0019] In some embodiments, the silicon semiconductor substrate includes any one or more of single crystal silicon, polycrystalline silicon, amorphous silicon, silicon on a void layer, and silicon on an insulator.
[0020] A second aspect of the present application is to provide a method for manufacturing a transistor, comprising the following steps:
[0021] providing a semiconductor substrate;
[0022] A plurality of semiconductor layers are grown on a surface of one side of a semiconductor substrate, and a plurality of source / drain regions of the transistor and a channel region located between the source / drain regions are formed on each semiconductor layer, wherein the source / drain regions are stacked along a first direction and spaced apart in a second direction; the second direction intersects the first direction; and along the first direction, orthographic projections of the source / drain regions of adjacent semiconductor layers on the semiconductor substrate at least partially overlap;
[0023] A sacrificial layer is provided between adjacent semiconductor layers;
[0024] removing the sacrificial layer and forming an insulating dielectric layer;
[0025] A metal gate and a passivation layer are formed on a surface of the insulating dielectric layer away from the semiconductor substrate; the metal gate penetrates the passivation layer and abuts against the channel region.
[0026] In some embodiments, the step of forming a plurality of source / drain regions of transistors on each semiconductor layer includes:
[0027] forming a hard mask on one surface of the semiconductor layer and exposing portions of the semiconductor layer located at both ends of the hard mask;
[0028] forming source / drain regions on a portion of the semiconductor layer;
[0029] Remove the hard mask.
[0030] The third aspect of the present application is to provide a quantum computing device, comprising the transistor described in the first aspect.
[0031] Beneficial effects of this application:
[0032] 1. The transistor provided in this application improves the coupling efficiency of qubits by adjusting the quantum dot arrangement. Specifically, the quantum dot arrangement includes a three-dimensional arrangement in the vertical direction, which facilitates vertical qubit coupling by regulating the gate voltage.
[0033] 2. The transistor provided in the present application also includes a control electrode extending from the semiconductor substrate. The control electrode and the gate together form a dual-gate mode, which facilitates further regulation of the coupling of quantum dots. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present application. The same reference numerals are used throughout the drawings to denote the same components. In the drawings:
[0035] Figure 1A Schematically shows a three-dimensional structure diagram of the transistor of the present application;
[0036] Figure 1B Schematically shows Figure 1A A top view of
[0037] Figure 1C Schematically shows the Figure 1B A cross-sectional view taken along the A-A' direction;
[0038] Figure 1D Schematically shows the Figure 1B A cross-sectional view taken along the BB' direction;
[0039] Figure 2 Schematically shows Figure 1D Enlarged view of the middle P part;
[0040] Figure 3 The flowchart of the transistor manufacturing method of the present application is schematically shown;
[0041] Figure 4A 、 Figure 4B 、 Figure 5A 、 Figure 5B 、 Figure 6A 、 Figure 6B 、 Figure 7A 、 Figure 7B 、 Figure 7C 、 Figure 8A 、 Figure 8B 、 Figure 8C 、 Figure 9A 、 Figure 9B 、 Figure 9C 、 Figure 10A 、 Figure 10B 、 Figure 10C 、 Figure 11A 、 Figure 11B 、 Figure 11C 、 Figure 12A 、 Figure 12B 、 Figure 12C 、 Figure 13A 、 Figure 13B 、 Figure 13C 、 Figure 14A 、 Figure 14B 、 Figure 14C The figure schematically shows the process of manufacturing the transistor of the present application;
[0042] Figure A is a top view of the transistor, Figure B is a cross-sectional view taken along the line AA' of Figure A, and Figure C is a cross-sectional view taken along the line BB' of Figure A.
[0043] The reference numerals in the accompanying drawings represent the following:
[0044] 1000, transistor;
[0045] 110. Semiconductor substrate;
[0046] 120, insulation layer;
[0047] 130, semiconductor layer; 131, first semiconductor layer; 132, second semiconductor layer;
[0048] 131a, a first source / drain region of the first semiconductor layer; 131b, a second source / drain region of the first semiconductor layer; 131c, a channel region of the first semiconductor layer;
[0049] 132a, a first source / drain region of the second semiconductor layer; 132b, a second source / drain region of the second semiconductor layer; 132c, a channel region of the second semiconductor layer;
[0050] 140, insulating dielectric layer; 1401, insulating dielectric main region; 1402, insulating dielectric edge region;
[0051] 140 ′, sacrificial layer; 140A, first sacrificial layer; 140B, second sacrificial layer;
[0052] 150a, first metal gate; 160, passivation layer;
[0053] 170a, first source / drain contact;
[0054] 170b, second source / drain contact;
[0055] 200, hard mask;
[0056] 300a, first gap; 300b, second gap; 300c, third gap;
[0057] First direction: Z direction of the transistor coordinate axis shown in FIG1 ;
[0058] Second direction: X direction of the transistor coordinate axis shown in FIG1 ;
[0059] Third direction: the Y direction of the transistor coordinate axis shown in FIG1 . DETAILED DESCRIPTION
[0060] In order to make the purpose, technical solutions and advantages of this application more clearly understood, this application is further described below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.
[0061] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments of the present disclosure. These figures are not drawn to scale, and for the purpose of clarity, certain details are exaggerated and certain details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.
[0062] In the context of this application, when a layer / element is referred to as being "on" another layer / element, it can be directly on the other layer / element or an intervening layer / element may be present therebetween. In addition, if a layer / element is "on" another layer / element in one orientation, it may be "below" the other layer / element when the orientation is reversed.
[0063] This application may use the term "coupled with," along with its derivatives. "Coupled" may mean one or more of the following. "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements are in indirect contact with each other, yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements said to be coupled to each other. The term "directly coupled" may mean that two or more elements are in direct contact.
[0064] Quantum computing devices perform quantum computations by manipulating qubits (qubits). These devices use qubits and place them in a superposition of 0 and 1 simultaneously to implement quantum gate operations and quantum information transmission. Quantum dot coupling refers to the exchange of energy or information between two or more quantum dots through physical interactions (such as electric and magnetic fields, or quantum tunneling). Quantum dot coupling enables coupling between qubits, allowing them to influence each other and transmit quantum information. Therefore, the layout of qubits is crucial; an optimized quantum layout maximizes qubit coupling.
[0065] Fin field effect transistors (FinFETs) are three-dimensional metal oxide semiconductor field effect transistors (MOSFETs). Compared to traditional planar FETs, FinFETs offer significant advantages in terms of size reduction, power consumption reduction, high-speed performance, and resistance to leakage current, making them widely used in various integrated circuits and microelectronic devices. FinFETs consist of a fin-shaped channel (the fin layer), a set of source / drain regions, and multiple metal gates. Unlike traditional planar FETs, FinFETs have only a one-dimensional fin channel as the conductive path, and the area below each gate and above the one-dimensional fin channel can form a quantum dot. Quantum bits (qubits) can be encoded based on the hole spin direction of the quantum dots in the FinFET.
[0066] However, the linear arrangement of multiple quantum dots in FinFETs (Fin Field Effect Transistors) can easily lead to suboptimal qubit coupling efficiency. For example, in existing FinFETs, due to the single qubit layout, quantum dots can only be controlled by adjusting the voltage between the source and drain on both sides, which can easily lead to suboptimal qubit coupling efficiency.
[0067] In order to solve the above technical problems, the first aspect of the present application is to provide a transistor, such as Figure 1A 、 Figure 1B 、 Figure 1C and Figure 1D As shown in FIG. 1 , the transistor 1000 includes: a semiconductor substrate 110 and a plurality of semiconductor layers 130 stacked along a first direction. Figures 1A to 1D As shown in the figure, there are two semiconductor layers 130, namely the first semiconductor layer 131 and the second semiconductor layer 132; in fact, there can be more than three semiconductor layers 130. The drawings and descriptions of this application are only for illustration and are not limiting. The first semiconductor layer 131 includes a first source / drain region 131a of the first semiconductor layer, a second source / drain region 131b of the first semiconductor layer, and a channel region 131c of the first semiconductor layer between the first source / drain region 131a of the first semiconductor layer and the second source / drain region 131b of the first semiconductor layer; the second semiconductor layer 132 includes a first source / drain region 132a of the second semiconductor layer and the second source / drain region 132b of the second semiconductor layer, and a channel region 132c of the second semiconductor layer between the first source / drain region 132a of the second semiconductor layer and the second source / drain region 132b of the second semiconductor layer; wherein the first source / drain region 131a of the first semiconductor layer and the second source / drain region 131b of the first semiconductor layer are spaced apart in the second direction, and the first source / drain region 132a of the second semiconductor layer and the second source / drain region 132b of the second semiconductor layer are spaced apart in the second direction. The second source / drain regions 132b of the conductive layer are arranged at intervals in the second direction, the first source / drain regions 131a of the first semiconductor layer and the first source / drain regions 132a of the second semiconductor layer are stacked along the first direction, the second source / drain regions 131b of the first semiconductor layer and the second source / drain regions 132b of the second semiconductor layer are stacked along the first direction, and along the first direction, the orthographic projection of the first source / drain region 131a of the first semiconductor layer on the above-mentioned semiconductor substrate 110 and the orthographic projection of the first source / drain region 132a of the second semiconductor layer on the above-mentioned semiconductor substrate 110 have at least partial overlap, and the orthographic projection of the second source / drain region 131b of the first semiconductor layer on the above-mentioned semiconductor substrate 110 and the orthographic projection of the second source / drain region 132b of the second semiconductor layer on the above-mentioned semiconductor substrate 110 have at least partial overlap, and the present application is in Figure 1C and Figure 1D The complete overlap is shown, which is only a partial illustration of each source / drain region and does not constitute any limitation.
[0068] Combine Figures 1A to 1D It can be seen that a passivation layer 160 is further provided on the surface of the semiconductor layer 130 away from the semiconductor substrate 110 . A first metal gate 150 a is provided in the passivation layer 160 . The first metal gate 150 a penetrates the passivation layer 160 and abuts against the channel region.
[0069] In summary, the transistor provided in this application improves the coupling efficiency of qubits by adjusting the quantum dot arrangement. Specifically, the quantum dot arrangement includes a three-dimensional arrangement in the vertical direction, which facilitates vertical qubit coupling by regulating the gate voltage.
[0070] Combine Figures 1A to 1D It can be seen that there are multiple first metal gates 150a. Figures 1A to 1D Two are illustrated in the figure. The orthographic projection of each first metal gate 150a on the semiconductor layer 130 is located between the source / drain regions spaced apart along the second direction. The first metal gates 150a are spaced apart and arranged opposite each other in a third direction; the third direction intersects the second direction. For example, the orthographic projection of the first metal gate 150a on the first semiconductor layer 131 is located between the first source / drain region 131a of the first semiconductor layer and the second source / drain region 131b of the first semiconductor layer. The orthographic projection of the first metal gate 150a on the second semiconductor layer 132 is located between the first source / drain region 132a of the second semiconductor layer and the second source / drain region 132b of the second semiconductor layer. The first metal gates 150a are spaced apart and arranged opposite each other in the third direction. Therefore, these first metal gates 150a can be easily controlled by voltage to achieve coupling of horizontal quantum dots.
[0071] This application also discloses, in some embodiments, that transistor 1000 includes a second metal gate connected to the semiconductor substrate 110. This second metal gate is not directly illustrated in the drawings, but it is actually present. This second metal gate, together with the first metal gate 150a, facilitates further control of quantum dot coupling.
[0072] Combine Figure 1D It can be seen that along the first direction, an insulating dielectric layer 140 is provided between adjacent semiconductor layers 130. Figure 2As can be seen, the source / drain regions of each semiconductor layer 130 are distributed along the periphery of the insulating dielectric layer 140, and each source / drain region abuts the insulating dielectric layer 140. The insulating dielectric layer 140 includes an insulating dielectric main region 1401 and an insulating dielectric edge region 1402. The insulating dielectric main region 1401 is disposed between the passivation layer 160 and the semiconductor substrate 110, and the insulating dielectric edge region 1402 is disposed between the source / drain regions stacked along the first direction. Specifically, the insulating dielectric edge region 1402 is disposed between the second source / drain region 131b of the first semiconductor layer and the second source / drain region 132b of the second semiconductor layer. Quantum dots are formed in the region where the orthographic projections of each metal gate on the semiconductor substrate 110 overlap with the orthographic projections of each channel region 0 on the semiconductor substrate 110. Therefore, this design facilitates the three-dimensional arrangement of quantum dots in the vertical direction and facilitates the control of the quantum dots by the metal gates.
[0073] Combine Figures 1A to 1D It can be seen that the passivation layer 160 is provided with a plurality of source / drain contacts, each source / drain contact passes through the passivation layer 160 and is respectively connected to each source / drain region. Specifically, it includes a first source / drain contact 170a and a second source / drain contact 170b. The first source / drain contact 170a passes through the passivation layer 160 to be respectively connected to the first source / drain region 132a of the second semiconductor layer and the first source / drain region 131a of the first semiconductor layer. The second source / drain contact 170b passes through the passivation layer 160 to be respectively connected to the second source / drain region 132b of the second semiconductor layer and the second source / drain region 131b of the first semiconductor layer.
[0074] In some embodiments, an insulating layer 120 is further provided on one side surface of the semiconductor substrate 110 . The insulating layer 120 includes a buried oxide layer. The buried oxide layer can provide physical support for the active region and also serve as an etching stop layer.
[0075] The present application also discloses a method for preparing a transistor, which comprises: Figure 3 Schematic preparation process:
[0076] S100, providing a semiconductor substrate;
[0077] S200, growing a plurality of semiconductor layers on a surface of one side of the semiconductor substrate, forming a plurality of source / drain regions of a transistor and a channel region located between the source / drain regions on each semiconductor layer, wherein the source / drain regions are stacked along a first direction and spaced apart in a second direction; the second direction intersects the first direction; and along the first direction, orthographic projections of the source / drain regions of adjacent semiconductor layers on the semiconductor substrate at least partially overlap;
[0078] S300, providing a sacrificial layer between adjacent semiconductor layers;
[0079] S400, removing the sacrificial layer and using it to form an insulating dielectric layer;
[0080] S500 , forming a metal gate and a passivation layer on a surface of the insulating dielectric layer away from the semiconductor substrate; the metal gate penetrates the passivation layer and abuts against the channel region.
[0081] In some embodiments, the step of forming a plurality of source / drain regions of transistors on each semiconductor layer includes:
[0082] forming a hard mask on one surface of the semiconductor layer and exposing portions of the semiconductor layer located at both ends of the hard mask;
[0083] forming source / drain regions on a portion of the semiconductor layer;
[0084] Remove the hard mask.
[0085] This application is combined with the following Figures 4A to 14C For this application Figure 1A The fabrication method of the schematic transistor is described in detail.
[0086] The transistor includes providing a semiconductor substrate 110, which includes a silicon semiconductor substrate or a silicon germanium semiconductor substrate; specifically, the silicon semiconductor substrate includes any one or more of single crystal silicon, polycrystalline silicon, amorphous silicon, silicon on a void layer, and silicon on an insulator. An insulating layer 120 is grown on the surface of one side of the semiconductor substrate 110, and the insulating layer includes a buried oxide layer. The material of the buried oxide layer includes any material conventional in the art, such as silicon dioxide. A first semiconductor layer 131 is grown on the surface of the insulating layer 120 away from the semiconductor substrate 110. The material and thickness of the first semiconductor layer and the subsequent second semiconductor layer include any material conventional in the art, and are not described in detail in this application. In these embodiments, the present application discloses that the material of the semiconductor layer is silicon material, and any crystal orientation of the silicon material is within the scope of protection of this application, and the growth method of the semiconductor layer 130 includes but is not limited to epitaxial growth.
[0087] like Figure 4A and Figure 4B As shown, a hard mask 200 is placed on a surface of the first semiconductor layer 131 away from the semiconductor substrate 110 . The hard mask 200 covers most of the surface of the first semiconductor layer 131 and exposes portions of the first semiconductor layer at both ends distributed along a first direction.
[0088] like Figure 5A and Figure 5BAs shown, the exposed portion of the first semiconductor layer 131 is processed to form a first source / drain region 131a and a second source / drain region 131b of the first semiconductor layer, respectively. The processing method includes any conventional method in the art, such as ion doping, silicidation, etc. The ion doping herein includes, but is not limited to, a cold implantation process of ion implantation. After the source / drain regions of the first semiconductor layer 131 are formed, the hard mask 200 is removed.
[0089] like Figure 6A and Figure 6B As shown, two hard masks 200 are placed on the first semiconductor layer 131, the first source / drain region 131a of the first semiconductor layer, and the second source / drain region 131b of the first semiconductor layer, away from the side surface of the semiconductor substrate 110, and the two hard masks 200 extend along the second direction and are spaced apart in the third direction.
[0090] like Figure 7A 、 Figure 7B and Figure 7C Indicate, etch and remove Figure 6A The semiconductor layer schematically located between the two hard masks 200 forms a first gap 300 a . The etching here and the etching described below include but are not limited to dry etching, wet etching, electron beam lithography, etc.
[0091] like Figure 8A 、 Figure 8B and Figure 8C As shown, the hard mask 200 is removed, and a first sacrificial layer 140A is grown in the first gap 300a. The first sacrificial layer 140A fills the first gap 300a and covers the first source / drain region 131a and the second source / drain region 131b of the first semiconductor layer.
[0092] like Figure 9A 、 Figure 9B and Figure 9C As shown, the second semiconductor layer 132 is grown on a surface of the first sacrificial layer 140A away from the semiconductor substrate 110 , and the second semiconductor layer 132 covers the first sacrificial layer 140A.
[0093] A first source / drain region 132a and a second source / drain region 132b of the second semiconductor layer are formed on the second semiconductor layer 132. The formation method here can be the same as the formation method of the first semiconductor layer 131, and will not be repeated here in this application.
[0094] And combined Figures 10A to 10CIt can be seen that the first source / drain region 131a of the first semiconductor layer and the second source / drain region 131b of the first semiconductor layer are arranged at intervals in the second direction, the first source / drain region 132a of the second semiconductor layer and the second source / drain region 132b of the second semiconductor layer are arranged at intervals in the second direction, the first source / drain region 131a of the first semiconductor layer and the first source / drain region 132a of the second semiconductor layer are stacked along the first direction, the second source / drain region 131b of the first semiconductor layer and the second source / drain region 132b of the second semiconductor layer are stacked along the first direction, and along the first direction, the orthographic projection of the first source / drain region 131a of the first semiconductor layer on the above-mentioned semiconductor substrate 110 and the orthographic projection of the first source / drain region 132a of the second semiconductor layer on the above-mentioned semiconductor substrate 110 have at least partial overlap, and the orthographic projection of the second source / drain region 131b of the first semiconductor layer on the above-mentioned semiconductor substrate 110 and the orthographic projection of the second source / drain region 132b of the second semiconductor layer on the above-mentioned semiconductor substrate 110 have at least partial overlap.
[0095] like Figure 10A 、 Figure 10B and Figure 10C As shown in FIG. 2 , two hard masks 200 are placed on the second semiconductor layer 132 , the first source / drain region 132 a of the second semiconductor layer, and the second source / drain region 132 b of the second semiconductor layer, on a surface away from the semiconductor substrate 110 . The two hard masks 200 extend along the second direction and are spaced apart in the third direction.
[0096] like Figure 11A 、 Figure 11B and Figure 11C Indicate, etch and remove Figure 10A A second gap 300 b is formed in the semiconductor layer schematically located between the two hard masks 200 , and then the hard masks 200 are removed.
[0097] like Figure 12A 、 Figure 12B and Figure 12C As shown, a second sacrificial layer 140B is grown in the second gap 300b. The second sacrificial layer 140B fills the second gap 300b and is connected to the first sacrificial layer 140A to form a sacrificial layer 140'. The material of the sacrificial layer 140' includes any conventional material in the art, such as silicon germanium.
[0098] like Figure 13A 、 Figure 13B and Figure 13C As shown, the sacrificial layer 140 ′ is removed by etching to form a third gap 300 c . Therefore, the present application uses stacked silicon germanium and releases the channel to facilitate the realization of a vertical quantum dot coupling structure.
[0099] like Figure 14A 、 Figure 14B and Figure 14C As shown in FIG. 1 , an isolation material, such as silicon dioxide, is deposited and grown in the third gap 300c to form an isolation dielectric layer 140. Figure 14C The isolation dielectric layer 140 includes an isolation dielectric main region 1401 and an isolation dielectric edge region 1402 , wherein the isolation dielectric edge region 1402 is disposed between the source / drain regions stacked along the first direction.
[0100] A plurality of first metal gates 150a are grown on the surface of the active region 132c away from the semiconductor substrate 110. The orthographic projection of each first metal gate 150a on the semiconductor layer 130 is located between the source / drain regions spaced apart along the second direction. Figure 1A Two first metal gates 150a are illustrated in the figure. The positive projection of each first metal gate 150a on the above-mentioned semiconductor layer 130 is located between the source / drain regions arranged at intervals along the second direction. At the same time, the two first metal gates 150a are arranged at intervals in the third direction and are relatively set. The first metal gates 150a facilitate voltage control and realize the coupling of horizontal quantum dots.
[0101] At the same time, a passivation layer 160 is also grown on the surface of the semiconductor layer away from the semiconductor substrate 110, and the passivation layer 160 covers the first metal gate 150a, the first source / drain region 132a of the second semiconductor layer, the second source / drain region 132b of the second semiconductor layer and each channel region.
[0102] In some embodiments, the present application discloses forming a through hole in the passivation layer 160, sinking multiple source / drain contacts in the through hole, each source / drain contact penetrates the passivation layer 160 and is connected to each source / drain region. Figures 1A to 1D Schematic diagram of a transistor.
[0103] The present application discloses forming a second metal gate in some embodiments, wherein the second metal gate is connected to the semiconductor substrate 110. The second metal gate here, together with the first metal gate 150a, facilitates further regulation of the coupling of quantum dots.
[0104] In some embodiments, the material of the first metal gate and the second metal gate includes but is not limited to metal tungsten. Similarly, in these embodiments, the material of the source / drain contacts includes metal, such as metal tungsten.
[0105] Therefore, the transistor provided in this application improves the coupling efficiency of qubits by adjusting the quantum dot arrangement. Specifically, the quantum dot arrangement includes a three-dimensional arrangement in the vertical direction, which facilitates the vertical qubit coupling by regulating the gate voltage.
[0106] It should be understood that the terms used herein are for the purpose of describing specific example embodiments only and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "a," "an," and "said" as used herein may also be intended to include the plural forms. The terms "comprise," "include," "contain," and "have" are inclusive and therefore specify the presence of the stated features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not to be construed as requiring them to be performed in the specific order described or illustrated, unless an order of execution is explicitly indicated. It should also be understood that additional or alternative steps may be used. The above description is merely a preferred embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included within the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.
Claims
1. A transistor, characterized in that: include: A semiconductor substrate and a plurality of semiconductor layers stacked along a first direction; Each of the semiconductor layers includes a plurality of source / drain regions and a channel region located between the source / drain regions; The source / drain regions are stacked along a first direction and spaced apart in a second direction; the second direction intersects the first direction; Along the first direction, orthographic projections of the source / drain regions of adjacent semiconductor layers on the semiconductor substrate at least partially overlap; The transistor further includes a passivation layer, which is located on a surface of the semiconductor layer away from the semiconductor substrate. A first metal gate is provided in the passivation layer, which penetrates the passivation layer and abuts against the channel region.
2. The transistor according to claim 1, wherein: There are a plurality of first metal gates, and the orthographic projection of each first metal gate on the semiconductor layer is located between source / drain regions spaced apart along the second direction, and the first metal gates are spaced apart and arranged opposite to each other in the third direction; The third direction is arranged to intersect with the second direction.
3. The transistor according to claim 1, wherein: The transistor includes a second metal gate connected to the semiconductor substrate.
4. The transistor according to any one of claims 1 to 3, characterized in that: An insulating dielectric layer is provided between adjacent semiconductor layers along the first direction.
5. The transistor according to claim 4, wherein: The source / drain regions of each semiconductor layer are distributed along the periphery of the insulating dielectric layer, and each source / drain region abuts against the insulating dielectric layer respectively; The insulating dielectric layer includes an insulating dielectric main region and an insulating dielectric edge region. The insulating dielectric main region is arranged between the passivation layer and the semiconductor substrate, and the insulating dielectric edge region is arranged between the source / drain regions stacked along the first direction.
6. The transistor according to any one of claims 1 to 3, characterized in that: A plurality of source / drain contact portions are provided in the passivation layer, and each of the source / drain contact portions penetrates the passivation layer and is respectively connected to each source / drain region.
7. The transistor according to any one of claims 1 to 3, characterized in that: The semiconductor substrate includes a silicon semiconductor substrate or a silicon-germanium semiconductor substrate; Preferably, the silicon semiconductor substrate includes any one or more of single crystal silicon, polycrystalline silicon, amorphous silicon, silicon on a void layer, and silicon on an insulator.
8. A method for preparing a transistor, characterized in that: The process includes the following: providing a semiconductor substrate; Growing a plurality of semiconductor layers on a surface of one side of the semiconductor substrate, forming a plurality of source / drain regions of the transistor and a channel region located between the source / drain regions on each of the semiconductor layers, wherein the source / drain regions are stacked along a first direction and spaced apart in a second direction; The second direction intersects the first direction; and along the first direction, orthographic projections of source / drain regions of adjacent semiconductor layers on the semiconductor substrate at least partially overlap; A sacrificial layer is provided between adjacent semiconductor layers; removing the sacrificial layer and using it to form an insulating dielectric layer; A metal gate and a passivation layer are formed on a surface of the insulating dielectric layer away from the semiconductor substrate; the metal gate penetrates the passivation layer and abuts against the channel region.
9. The preparation method according to claim 8, characterized in that: The step of forming a plurality of source / drain regions of the transistor on each of the semiconductor layers comprises: forming a hard mask on one surface of the semiconductor layer and exposing portions of the semiconductor layer located at both ends of the hard mask; forming a source / drain region on the portion of the semiconductor layer; Remove the hard mask.
10. A quantum computing device, characterized in that: A transistor comprising the transistor according to any one of claims 1 to 7.