Circuit board

Abstract

This circuit board has a first laminated ceramic electronic component and a second laminated ceramic electronic component. Each of the laminated ceramic electronic components has a height dimension of 1.3 times or more with respect to the width dimension or the length dimension, and is disposed adjacent to each other in a state in which the respective width directions are the same direction. Furthermore, in the length direction, one of a first external electrode and a second external electrode of the first laminated ceramic electronic component is positioned between a first external electrode and a second external electrode of the second laminated ceramic electronic component. One of the first external electrode and the second external electrode of the second laminated ceramic electronic component is arranged in a staggered state so as to be positioned between the first external electrode and the second external electrode of the first laminated ceramic electronic component.

Description

Technical Field

[0001] The present invention relates to circuit boards. Background Art

[0002] In recent years, the miniaturization and high functionality of various electronic devices have been continuously developed, and the mounting area of ​​electronic components including laminated ceramic electronic components in circuit boards has tended to decrease. On the other hand, there is a demand for further multilayer stacking of laminated ceramic electronic components. In order to meet such demands, a component structure oriented to achieve further high-density mounting and multilayer stacking has been proposed (for example, refer to Patent Document 1). In laminated ceramic electronic components, the mounting area of ​​the circuit board can be determined by the length and width dimensions of the laminated ceramic electronic components. In Patent Document 1, a technology is proposed to increase the height dimension, that is, the dimension in the direction perpendicular to the mounting surface of the circuit board, compared with the length or width dimension of the laminated ceramic electronic component to make it high-back. High-back laminated ceramic electronic components are suitable for multilayer stacking.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2020-031152 Summary of the Invention

[0006] Technical problem to be solved by the invention

[0007] However, if a multilayer ceramic electronic component that is large in height and mounted at a high density tilts, it may come into contact with other electronic components mounted around it and cause a short circuit.

[0008] Therefore, an object of the present invention is to suppress short circuits that occur when high-profile multilayer ceramic electronic components are tilted in a circuit board on which the multilayer ceramic electronic components are densely mounted.

[0009] Technical solutions to technical problems

[0010] In order to solve the above technical problems, the circuit board disclosed in this specification includes: a substrate; and a plurality of laminated ceramic electronic components mounted on a mounting surface of the substrate, when the direction along a first axis is set as a height direction, the direction along a second axis orthogonal to the direction along the first axis is set as a width direction, and the direction along a third axis orthogonal to the directions along the first axis and the second axis is set as a length direction, at least the first laminated ceramic electronic component and the second laminated ceramic electronic component of the plurality of laminated ceramic electronic components each have a first external electrode having a prescribed length along the length direction at one end in the length direction, and a second external electrode having a prescribed length along the length direction at the other end in the length direction, the height dimension of the first laminated ceramic electronic component is not less than 1.3 times the width dimension or the length dimension of the first laminated ceramic electronic component, and The height dimension of the above-mentioned second multilayer ceramic electronic component is more than 1.3 times the width dimension or length dimension of the above-mentioned second multilayer ceramic electronic component. The above-mentioned first multilayer ceramic electronic component and the above-mentioned second multilayer ceramic electronic component are adjacent to each other in a state of being arranged in a manner such that their respective height directions are perpendicular to the above-mentioned mounting surface and their respective width directions are in the same direction. In the length direction, they are arranged on the above-mentioned mounting surface in a state of being staggered with each other in a manner such that one of the above-mentioned first external electrode and the above-mentioned second external electrode of the above-mentioned first multilayer ceramic electronic component is located between the above-mentioned first external electrode and the above-mentioned second external electrode of the above-mentioned second multilayer ceramic electronic component, and one of the above-mentioned first external electrode and the above-mentioned second external electrode of the above-mentioned second multilayer ceramic electronic component is located between the above-mentioned first external electrode and the above-mentioned second external electrode of the above-mentioned first multilayer ceramic electronic component.

[0011] In the circuit board having the above structure, another electronic component may be mounted adjacent to at least one of the first and second multilayer ceramic electronic components on a side in the width direction and covered with an insulating cover.

[0012] In the circuit board having the above structure, at least one of the height of the first multilayer ceramic electronic component and the height of the second multilayer ceramic electronic component may be 1.5 times or more the width or length of the respective components.

[0013] In addition, in the circuit board of the above-mentioned structure, the following method can be adopted: at least one of the internal electrodes provided in the ceramic body of the above-mentioned first laminated ceramic electronic component and the internal electrodes provided in the ceramic body of the above-mentioned second laminated ceramic electronic component are stacked in the direction along the above-mentioned first axis in a manner relative to each other.

[0014] In addition, in the circuit board of the above structure, the following method can be adopted: the above-mentioned internal electrodes stacked in the direction along the above-mentioned first axis include: a first internal electrode connected to the above-mentioned first external electrode; and a second internal electrode connected to the above-mentioned second external electrode, the above-mentioned first internal electrode has a connecting end connected to the above-mentioned first external electrode and an open end located on the opposite side of the connecting end, the above-mentioned connecting end has a narrow width portion whose width dimension is narrower than the width dimension of the portion away from the above-mentioned connecting end toward the above-mentioned open end, the above-mentioned second internal electrode has a connecting end connected to the above-mentioned second external electrode and an open end located on the opposite side of the connecting end, the above-mentioned connecting end has a narrow width portion whose width dimension is narrower than the width dimension of the portion away from the above-mentioned connecting end toward the above-mentioned open end.

[0015] In addition, in the circuit board of the above-mentioned structure, the following method can be adopted: at least one of the internal electrodes provided in the ceramic body of the above-mentioned first laminated ceramic electronic component and the internal electrodes provided in the ceramic body of the above-mentioned second laminated ceramic electronic component are stacked in the direction along the above-mentioned second axis in a manner relative to each other.

[0016] In addition, in the circuit board of the above structure, the following method can be adopted: the above-mentioned internal electrodes stacked in the direction along the above-mentioned second axis include: a first internal electrode connected to the above-mentioned first external electrode; and a second external electrode connected to the above-mentioned second external electrode, the above-mentioned first internal electrode has a connecting end connected to the above-mentioned first external electrode and an open end located on the opposite side of the connecting end, the above-mentioned connecting end has a narrow width portion whose width dimension is narrower than the width dimension of the portion away from the above-mentioned connecting end toward the above-mentioned open end, the above-mentioned second internal electrode has a connecting end connected to the above-mentioned second external electrode and an open end located on the opposite side of the connecting end, the above-mentioned connecting end has a narrow width portion whose width dimension is narrower than the width dimension of the portion away from the above-mentioned connecting end toward the above-mentioned open end.

[0017] In the circuit board having the above structure, a low melting point metal may be contained in the internal electrodes or in a dielectric layer formed between the internal electrodes.

[0018] Furthermore, in the circuit board of the above structure, the following method can be adopted: the above-mentioned multiple laminated ceramic electronic components also include a third laminated ceramic electronic component, the above-mentioned third laminated ceramic electronic component has a first external electrode with a specified length along the above-mentioned length direction at one end portion in the above-mentioned length direction, and has a second external electrode with a specified length along the above-mentioned length direction at the other end portion in the above-mentioned length direction, and the third laminated ceramic electronic component is configured so that one of the above-mentioned first external electrode and the above-mentioned second external electrode of the third laminated ceramic electronic component is located between the above-mentioned first external electrode and the above-mentioned second external electrode of one of the above-mentioned first laminated ceramic electronic component and the above-mentioned second laminated ceramic electronic component, and is configured adjacent to the other of the above-mentioned first laminated ceramic electronic component and the above-mentioned second laminated ceramic electronic component along the above-mentioned length direction.

[0019] Effects of the Invention

[0020] According to the invention disclosed in this specification, in a circuit board on which high-profile multilayer ceramic electronic components are mounted at a high density, it is possible to suppress the occurrence of short circuits when the multilayer ceramic electronic components are tilted. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Fig. 1(A) is a front view of a circuit board according to the first embodiment, and Fig. 1(B) is a top view thereof. Fig. 1(C) is an equivalent circuit diagram of the circuit boards shown in Figs. 1(A) and 1(B).

[0022] Figure 2 This is a perspective view of first and second multilayer ceramic capacitors used in the circuit board of the first embodiment.

[0023] Figures 3(A) to 3(D) are four views of the first and second multilayer ceramic capacitors used in the circuit board of the first embodiment. Figure 3(A) is a top view, Figure 3(B) is a bottom view, Figure 3(C) is a front view, and Figure 3(D) is a rear view.

[0024] Figure 4 The first multilayer ceramic capacitor used in the circuit board of the first embodiment Figure 2 A cross-sectional view taken along line A1-A1.

[0025] FIG. 5(A) shows a first multilayer ceramic capacitor used in the circuit board of the first embodiment. Figure 2 FIG5(B) is a cross-sectional view of the first multilayer ceramic capacitor used in the circuit board of the first embodiment. Figure 2 A3-A3 section view in.

[0026] Figure 6 The first multilayer ceramic capacitor is placed in Figure 2A perspective view of the circuit board according to the first embodiment, partially cut along line A1-A1 in FIG. 1 and showing the second multilayer ceramic capacitor partially cut away in the same manner.

[0027] Figure 7 It is a top view of the circuit board according to the second embodiment.

[0028] Figure 8 The first multilayer ceramic capacitor used in the circuit board of the third embodiment is along the Figure 2 The cross-sectional view is taken along the line A1-A1.

[0029] FIG. 9(A) shows a first multilayer ceramic capacitor used in a circuit board according to a third embodiment along the Figure 2 FIG9(B) is a cross-sectional view taken along the line corresponding to line A2-A2 in FIG9 , and FIG9(B) is a cross-sectional view taken along the line corresponding to line A2-A2 in FIG9 . Figure 2 The cross-sectional view is taken along the line A3-A3.

[0030] Figure 10 This is a perspective view of a circuit board according to a third embodiment, showing a first multilayer ceramic capacitor and a second multilayer ceramic capacitor in partial cross-section.

[0031] Figure 11 It is a plan view of a circuit board according to a fourth embodiment.

[0032] Figure 12 This is a partially exploded view showing a ceramic body of a first multilayer ceramic capacitor according to a fifth embodiment.

[0033] Figure 13 This is a diagram showing an exploded portion of a ceramic main body included in a first multilayer ceramic capacitor according to a modification of the fifth embodiment.

[0034] Figure 14 This is a perspective view of a circuit board showing a first multilayer ceramic capacitor and a second multilayer ceramic capacitor according to a modification of the fifth embodiment in partial cross-section.

[0035] FIG. 15(A) is a side view of a circuit board of a comparative example, and FIG. 15(B) is a top view thereof.

[0036] 16(A) and 16(B) are diagrams schematically showing a tilted state of a first multilayer ceramic capacitor according to a comparative example, with FIG16(A) being a side view and FIG16(B) being a top view. DETAILED DESCRIPTION

[0037] Hereinafter, the circuit board of the embodiment of the present application will be described with reference to the drawings. In the drawings, the size, ratio, and the like of each portion are not always illustrated to be completely identical with the actual size, ratio, and the like. In addition, in order to facilitate the description, a detailed portion or a constituent element itself is sometimes omitted according to the drawing. In addition, in the drawings, an X axis, a Y axis, and a Z axis that are orthogonal to each other are appropriately shown. The X axis, the Y axis, and the Z axis define a fixed coordinate system that is fixed with respect to the circuit board 110. In the following description, the Z axis direction corresponds to the direction along the first axis, and the Y axis direction corresponds to the direction along the second axis. In addition, the X axis direction corresponds to the direction along the third axis.

[0038] (First Embodiment)

[0039] [Circuit Board]

[0040] First, with reference to FIGS. 1(A) to 1(C), the outline structure of the circuit board 110 of the first embodiment will be described. FIG. 1(A) is a front view of the circuit board 110 of the first embodiment. FIG. 1(B) is a plan view of the circuit board 110. FIG. 1(C) is an equivalent circuit diagram of the circuit board 110 according to the first embodiment. The circuit board 110 has a printed wiring substrate 1 as a substrate, a first multilayer ceramic capacitor (MLCC: Multi Layered Ceramic Capacitor) 10, and a second multilayer ceramic capacitor 30. In the present embodiment, the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 are the same article, but different reference numerals are attached for the sake of convenience of the description. The first multilayer ceramic capacitor 10 has a first external electrode 14 and a second external electrode 15. As will be described later, the second multilayer ceramic capacitor 30 also has a first external electrode 34 and a second external electrode 35.

[0041] In the circuit board 110, short-circuiting of the first external electrode 14 and the second external electrode 15 of the first multilayer ceramic capacitor 10 with the first external electrode 34 and the second external electrode 35 of the second multilayer ceramic capacitor 30 is required to be avoided. Specifically, for example, short-circuiting of the first external electrode 14 of the first multilayer ceramic capacitor 10 with the first external electrode 34 or the second external electrode 35 of the second multilayer ceramic capacitor 30 is required to be avoided. In addition, for example, short-circuiting of the second external electrode 15 of the first multilayer ceramic capacitor 10 with the first external electrode 34 or the second external electrode 35 of the second multilayer ceramic capacitor 30 is required to be avoided.

[0042] In the circuit configuration of this embodiment, as shown in the equivalent circuit of Figure 1(C), one external electrode of the first multilayer ceramic capacitor 10 is grounded, and an input is provided to the other external electrode via the first terminal 4a. Furthermore, one external electrode of the second multilayer ceramic capacitor 30 is grounded, and an input is provided to the other external electrode via the second terminal 4b. Therefore, in this embodiment, it is necessary to avoid contact between the grounded external electrode of the first multilayer ceramic capacitor 10 and the external electrode connected to the second terminal 4b of the second multilayer ceramic capacitor 30. Furthermore, it is necessary to avoid contact between the external electrode connected to the first terminal 4a of the first multilayer ceramic capacitor 10 and the external electrode connected to the ground of the second multilayer ceramic capacitor 30. Furthermore, it is necessary to avoid contact between the external electrode connected to the first terminal 4a of the first multilayer ceramic capacitor 10 and the external electrode connected to the second terminal 4b of the second multilayer ceramic capacitor 30. However, this circuit configuration is merely an example, and the combination of external electrodes to be avoided will vary depending on the circuit configuration.

[0043] A first pad 2a, a second pad 2b, a third pad 2c, and a fourth pad 2d are provided on the printed wiring board 1. The first pad 2a and the third pad 2c are grounded. The second pad 2b is provided with a first terminal 4a. The fourth pad 2d is provided with a second terminal 4b.

[0044] The first external electrode 14 of the first multilayer ceramic capacitor 10 is disposed on the grounded first pad 2a. The second external electrode 15 of the first multilayer ceramic capacitor 10 is disposed on the second pad 2b on which the first terminal 4a is provided. Furthermore, the second external electrode 35 of the second multilayer ceramic capacitor 30 is disposed on the grounded third pad 2c. Furthermore, the first external electrode 34 of the second multilayer ceramic capacitor 30 is disposed on the fourth pad 2d on which the second terminal 4b is provided.

[0045] Therefore, in this embodiment, it is necessary to avoid contact between the first external electrode 14 of the first multilayer ceramic capacitor 10 and the first external electrode 34 of the second multilayer ceramic capacitor 30. Furthermore, it is necessary to avoid contact between the second external electrode 15 of the first multilayer ceramic capacitor 10 and the second external electrode 35 of the second multilayer ceramic capacitor 30. Furthermore, it is necessary to avoid contact between the second external electrode 15 of the first multilayer ceramic capacitor 10 and the first external electrode 34 of the second multilayer ceramic capacitor 30.

[0046] Furthermore, each external electrode is fixed to each of the arranged pads by a solder fillet 3. Thus, the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 are mounted on the mounting surface 1a of the printed wiring board 1.

[0047] The first and second multilayer ceramic capacitors 10, 30 are mounted side by side on the mounting surface 1a along the Y-axis. The first and second multilayer ceramic capacitors 10, 30 are mounted adjacent to each other. In this specification, the term "adjacent" means that no other components are mounted between the first and second multilayer ceramic capacitors 10, 30.

[0048] Furthermore, the first and second multilayer ceramic capacitors 10 and 30 are arranged so as to be offset in their longitudinal direction, i.e., in the X-axis direction. Consequently, the first external electrode 14 of the first multilayer ceramic capacitor 10 is positioned between the first and second external electrodes 34 and 35 of the second multilayer ceramic capacitor 30. Furthermore, the second external electrode 35 of the second multilayer ceramic capacitor 30 is positioned between the first and second external electrodes 14 and 15 of the first multilayer ceramic capacitor 10. The positional relationship between the first and second multilayer ceramic capacitors 10 and 30 will be described in further detail later.

[0049] <Dimensions of the First and Second Multilayer Ceramic Capacitors>

[0050] Here, referring to the perspective view of the first multilayer ceramic capacitor 10, Figure 2 , the dimension markings of each part of the first multilayer ceramic capacitor 10 are explained. The X-axis dimension, i.e., the length, of the first multilayer ceramic capacitor 10 is marked as L

[10] , and the Y-axis dimension, i.e., the width, is marked as W

[10] . The Z-axis dimension, i.e., the height, is marked as T

[10] . In addition, the X-axis dimension, i.e., the length, of the first external electrode 14 is marked as L

[14] . Similarly, the X-axis dimension, i.e., the length, of the second external electrode 15 is marked as L

[15] . Furthermore, the interval between the first external electrode 14 and the second external electrode 15 along the X-axis direction is marked as G

[10] . In addition, the ceramic body 11 described later is exposed between the first external electrode 14 and the second external electrode 15.

[0051] The second multilayer ceramic capacitor 30 is labeled similarly. The length of the second multilayer ceramic capacitor 30 in the X-axis direction is labeled L

[30] , and the width in the Y-axis direction is labeled W

[30] . The height in the Z-axis direction is labeled T

[30] . In addition, the length of the first external electrode 34 in the X-axis direction is labeled L

[34] . Similarly, the length of the second external electrode 35 in the X-axis direction is labeled L

[35] . Furthermore, the distance between the first external electrode 34 and the second external electrode 35 along the X-axis direction is labeled G

[30] . In addition, the ceramic body 31 described later is exposed between the first external electrode 34 and the second external electrode 35.

[0052] <First Multilayer Ceramic Capacitor>

[0053] Next, refer to Figure 2 3 (A) to 3 (D), the first multilayer ceramic capacitor 10 will be described in detail. FIG3 (A) to FIG3 (D) are four views of the first multilayer ceramic capacitor 10. In addition, the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 are the same article and have substantially the same external shape. Therefore, Figure 2 3(A) to 3(D) , reference numerals representing both components are shown.

[0054] <<Appearance and shape>>

[0055] First, the external appearance of the first multilayer ceramic capacitor 10 will be described.

[0056] The first multilayer ceramic capacitor 10 includes a ceramic body 11, a first external electrode 14, and a second external electrode 15. The ceramic body 11 is configured as a hexahedron having first and second principal surfaces M11, M12 perpendicular to the Z axis, first and second end surfaces E11, E12 perpendicular to the X axis, and first and second side surfaces S11, S12 perpendicular to the Y axis. The "hexahedron" only needs to be substantially hexahedral; for example, the edges connecting the faces of the ceramic body 11 may be rounded.

[0057] The main surfaces M11, M12, end surfaces E11, E12, and side surfaces S11, S12 of the ceramic body 11 are all configured as flat surfaces. A flat surface in this embodiment is any surface that is recognizable as flat when viewed as a whole, and may not be a strictly flat surface. For example, it may include a surface having slight surface irregularities, a gently curved surface within a specified range, or the like.

[0058] The first multilayer ceramic capacitor 10 is a high-back type in which the height T

[10] is greater than or equal to 1.3 times the width W

[10] . In the first multilayer ceramic capacitor 10, the capacity is increased by increasing the height [T10]. Thus, the first multilayer ceramic capacitor 10 can be installed in an installation space that is limited in the Y-axis direction. In addition, it is preferred that the height T

[10] is greater than or equal to 1.5 times the width W

[10] . The height T

[10] can be, for example, 1.6 times, 1.7 times, or a higher ratio of the width W

[10] . Thus, the capacitance of the first multilayer ceramic capacitor 10 can be further increased.

[0059] In this embodiment, the conditions for height T

[10] are determined based on the ratio to width W

[10] . However, the conditions for height T

[10] may be determined based on the relationship to length L

[10] instead of width W

[10] . In other words, the first multilayer ceramic capacitor 10 may be a high-back type in which height T

[10] is 1.3 times or more of length W

[10] . Alternatively, height T

[10] may be 1.5 times or more of length L

[10] .

[0060] In the first multilayer ceramic capacitor 10, the dimension of the ceramic body 11 in the X-axis direction may be larger than the dimension in the Y-axis direction, or smaller than the dimension in the Z-axis direction. In the first multilayer ceramic capacitor 10, the dimensions of the ceramic body 11 in the three axes can be arbitrarily determined within the range that satisfies the above conditions.

[0061] In the first multilayer ceramic capacitor 10 of this embodiment, for example, the length L

[10] can be set to 0.2 mm or more and 1.2 mm or less, and the width W

[10] can be set to 0.1 mm or more and 0.7 mm or less. Furthermore, the height T

[10] can be set to 0.15 mm or more and 1.0 mm or less. The height T

[10] , width W

[10] , and length L

[10] are all the maximum dimensions of the first multilayer ceramic capacitor 10 in each direction.

[0062] The first external electrode 14 includes a first surface portion 14a that covers the end surface E11 of the ceramic body 11. The first external electrode 14 includes a second surface portion 14b that extends from the first surface portion 14a toward the side surface S11, and a third surface portion 14c that extends toward the side surface S12. The first external electrode 14 also includes a fourth surface portion 14d that extends from the first surface portion 14a toward the main surface M11, and a fifth surface portion 14e that extends toward the main surface M12.

[0063] The second external electrode 15 includes a first surface portion 15a that covers the end surface E12 of the ceramic body 11. The second external electrode 15 includes a second surface portion 15b that extends from the first surface portion 15a toward the side surface S11, and a third surface portion 15c that extends toward the side surface S12. The second external electrode 15 also includes a fourth surface portion 15d that extends from the first surface portion 15a toward the main surface M11, and a fifth surface portion 15e that extends toward the main surface M12.

[0064] Here, the second surface portions 14b, 15b, the third surface portions 14c, 15c, the fourth surface portions 14d, 15d, and the fifth surface portions 14e, 15e correspond to the extended portions.

[0065] The cross sections parallel to the XZ plane and the cross sections parallel to the XY plane of the external electrodes 14 and 15 are both U-shaped. The shapes of the external electrodes 14 and 15 are not limited to the examples shown in the drawings.

[0066] Furthermore, the external electrodes 14 and 15 contain a metal material as a main component. Examples of the metal material constituting the external electrodes 14 and 15 include copper (Cu), nickel (Ni), tin (Sn), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), and alloys thereof. In this embodiment, the main component refers to the component with the highest content ratio.

[0067] <<Internal Structure>>

[0068] Next, refer to Figure 4 5(B) , the internal structure of the first multilayer ceramic capacitor 10 will be described. Figure 4 The first multilayer ceramic capacitor 10 is Figure 2 FIG5(A) is a cross-sectional view of the first multilayer ceramic capacitor 10. Figure 2 FIG5(B) is a cross-sectional view of the first multilayer ceramic capacitor 10. Figure 2 5(B), the second external electrode 15 is omitted.

[0069] The ceramic body 11 has a laminated portion 20 and a pair of margin portions 18. The laminated portion 20 has a capacitor-forming portion 16 and a pair of covering portions 17. The capacitor-forming portion 16 includes a plurality of first and second internal electrodes 12 and 13 alternately laminated with a plurality of ceramic layers 19 along the Z-axis direction. In this embodiment, the first and second internal electrodes 12 and 13 and the ceramic layers 19 are each formed into a sheet extending along the XY plane. The number of first and second internal electrodes 12 and 13 stacked in each figure does not represent the actual number of layers stacked.

[0070] The first and second inner electrodes 12 and 13 are arranged alternately along the Z-axis, facing each other in the Z-axis direction. The first and second inner electrodes 12 and 13 face each other in the Z-axis direction in a central facing region in the X-axis and Y-axis directions. The first inner electrodes 12, which constitute the first group, extend from the facing region to one end face E11 and are connected to the first external electrode 14. The second inner electrodes 13, which constitute the second group, extend from the facing region to the other end face E12 and are connected to the second external electrode 15.

[0071] The first and second internal electrodes 12 and 13 contain a metal material as their main component. Typical examples of this metal material include nickel (Ni), but other examples include copper (Cu), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), and alloys thereof. Furthermore, the metal material forming the internal electrodes 12 and 13 may also contain a low-melting-point metal with a lower melting point than the main component, nickel (Ni), as an additive element. Examples of such low-melting-point metals include tin (Sn), zinc (Zn), aluminum (Al), gallium (Ga), and germanium (Ge). The internal electrodes 12 and 13 may contain at least one of these low-melting-point metals. The addition of such a low-melting-point metal improves the sinterability of the ceramic body 11 and the insulation between the first and second internal electrodes 12 and 13.

[0072] With this structure, in the first multilayer ceramic capacitor 10, when a voltage is applied between the external electrodes 14 and 15, a voltage is applied to the plurality of ceramic layers 19 between the internal electrodes 12 and 13 in the opposing region. Consequently, charge corresponding to the voltage between the external electrodes 14 and 15 is accumulated in the first multilayer ceramic capacitor 10.

[0073] In the laminated portion 20, a high-dielectric-constant dielectric ceramic is used to increase the capacitance of each ceramic layer 19 between the first and second internal electrodes 12 and 13. Examples of high-dielectric-constant dielectric ceramics include perovskite-structured materials containing barium (Ba) and titanium (Ti), such as barium titanate (BaTiO3).

[0074] Alternatively, the dielectric ceramic may be composed of strontium titanate (SrTiO3), calcium titanate (CaTiO3), magnesium titanate (MgTiO3), calcium zirconate (CaZrO3), calcium zirconate titanate (Ca(Zr,Ti)O3), barium calcium zirconate titanate ((Ba,Ca)(Zr,Ti)O3), barium zirconate (BaZrO3), titanium oxide (TiO2), or the like. Instead of adding a low-melting-point metal to the first and second inner electrodes 12, 13, a low-melting-point metal may be added to the dielectric ceramic, or alternatively, a low-melting-point metal may be added to the first and second inner electrodes 12, 13 and the dielectric ceramic. The nature of the low-melting-point metal and the effects of adding the low-melting-point metal have been described above, so detailed description is omitted here.

[0075] A pair of covers 17 cover capacitor-forming portion 16 from both sides in the stacking direction, i.e., the Z-axis direction. Covers 17 are sometimes referred to as height-direction protective layers. Covers 17 are, for example, composed of a stack of ceramic sheets extending along the XY plane. To suppress internal stress, the dielectric ceramic comprising covers 17 preferably has the same composition as ceramic layer 19.

[0076] A pair of edge portions 18 are formed along the Z-axis direction and cover the laminate portion 20 from the Y-axis direction. The edge portion 18 is sometimes also called a protective layer in the width direction. The edge portion 18 is later installed on the surface of the laminate portion 20 that is perpendicular to the Y-axis. For example, the edge portion 18 is formed by a ceramic sheet and is configured as a sheet extending along the XZ plane. From the viewpoint of suppressing internal stress, etc., the dielectric ceramic constituting the edge portion 18 is preferably the same composition as the ceramic layer 19. The method of forming the edge portion 18 is not limited to this. For example, the edge portion 18 can also be formed by stacking a plurality of ceramic sheets provided with an internal electrode forming layer in a manner that retains a portion corresponding to the edge portion.

[0077] <Second Multilayer Ceramic Capacitor>

[0078] The second multilayer ceramic capacitor 30 is identical to the first multilayer ceramic capacitor 10. Specifically, the second multilayer ceramic capacitor 30 includes a ceramic body 31, a first external electrode 34, and a second external electrode 35. The ceramic body 31 is configured as a hexahedron having first and second principal surfaces M31, M32 perpendicular to the Z axis, first and second end surfaces E31, E32 perpendicular to the X axis, and first and second side surfaces S31, S32 perpendicular to the Y axis.

[0079] In addition, the ceramic body 31 is not labeled with any reference numerals, but has a laminated portion and a pair of edge portions, similar to the ceramic body 11. The laminated portion has a capacitor-forming portion and a pair of covering portions 17. The capacitor-forming portion includes a plurality of first and second internal electrodes alternately laminated with a plurality of ceramic layers along the Z-axis direction. The components of the second laminated ceramic capacitor 30 are the same as the components of the first laminated ceramic capacitor 10 with the same names, and therefore their detailed description is omitted here.

[0080] <Dimensional and Positional Relationship Between the First and Second Multilayer Ceramic Capacitors>

[0081] Here, refer to Figure 6 1 (A) and (B) again, the dimensional relationship and arrangement of the respective parts of the first and second multilayer ceramic capacitors 10 and 30 will be described. Figure 6 , which schematically shows the arrangement of the first and second multilayer ceramic capacitors 10 and 30 , does not accurately represent the dimensional ratios of the respective components.

[0082] The first and second multilayer ceramic capacitors 10 and 30 are each arranged so that their lengths coincide with the X-axis and their widths coincide with the Y-axis. The first and second multilayer ceramic capacitors 10 and 30 are arranged offset from each other in the X-axis direction. The offset in the X-axis direction is the amount by which the first external electrode 14 of the first multilayer ceramic capacitor 10 is positioned between the first external electrode 34 and the second external electrode 35 of the second multilayer ceramic capacitor 30. Consequently, the second external electrode 35 of the second multilayer ceramic capacitor 30 is also positioned between the first external electrode 14 and the second external electrode 15 of the first multilayer ceramic capacitor 10.

[0083] Here, the interval G

[10] between the first external electrode 14 and the second external electrode 15 of the first multilayer ceramic capacitor 10 is longer than the length L

[35] of the second external electrode 35 of the second multilayer ceramic capacitor 30 .

[0084] Similarly, the interval G[ 30 ] between the first external electrode 34 and the second external electrode 35 of the second multilayer ceramic capacitor 30 is also longer than the length L[ 14 ] of the first external electrode 14 of the first multilayer ceramic capacitor 10 .

[0085] Thus, the external electrodes included in the first multilayer ceramic capacitor 10 and the external electrodes included in the second multilayer ceramic capacitor 30 are alternately arranged along the X-axis direction.

[0086] At this time, as shown in Figure 1B , a gap G[14-35] is formed between the first external electrode 14 of the first multilayer ceramic capacitor 10 and the second external electrode 35 of the second multilayer ceramic capacitor 30. This gap G[14-35] is the shortest distance between the opposing corners of the first and second external electrodes 14, 35. This gap G[14-35] prevents contact between the first and second external electrodes 14, 35, even when one or both of the first and second multilayer ceramic capacitors 10, 30 are tilted toward each other.

[0087] More specifically, regarding the gap G[14-35], the lower limit of the gap G[14-35] is 10% or more of the gap G

[30] , and more preferably 20% or more. Thus, even if the first and second multilayer ceramic capacitors 10 and 30 tilt in the X-axis direction due to chip warping, such as the Manhattan effect or tombstoning phenomenon, contact between the first external electrode 14 of the first multilayer ceramic capacitor 10 and the second external electrode 35 of the second multilayer ceramic capacitor 30 can be avoided.

[0088] The upper limit of the gap G[14-35] is equal to or less than the length L

[14] of the first external electrode 14, and more preferably equal to or less than 80% of the length L

[14] . This prevents contact between the first external electrode 14 and the second external electrode 35.

[0089] Furthermore, the first external electrode 14 of the first multilayer ceramic capacitor 10 and the second external electrode 35 of the second multilayer ceramic capacitor 30 are arranged with a spacing S therebetween along the Y-axis direction. Here, spacing S is the shortest distance along the Y-axis direction between the first external electrode 14 of the first multilayer ceramic capacitor 10 and the second external electrode 35 of the second multilayer ceramic capacitor 30. No other components are mounted between the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30. Therefore, from the perspective of high-density packaging, spacing S is preferably 0.3 mm or less, and more preferably 0.2 mm or less.

[0090] [Effect]

[0091] This prevents contact between the external electrodes when the first multilayer ceramic capacitor 10 is tilted toward the second multilayer ceramic capacitor 30, or when the second multilayer ceramic capacitor 30 is tilted toward the first multilayer ceramic capacitor 10. Specifically, contact between the first external electrode 14 of the first multilayer ceramic capacitor 10 and the second external electrode 35 of the second multilayer ceramic capacitor 30 can be prevented. This prevents short circuits between the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30.

[0092] Furthermore, it is also conceivable that the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 are in contact with each other. However, in this case, the first external electrode 14 of the first multilayer ceramic capacitor 10 contacts the ceramic body 31 of the second multilayer ceramic capacitor 30. Furthermore, the second external electrode 35 of the second multilayer ceramic capacitor 30 contacts the ceramic body 11 of the first multilayer ceramic capacitor 10. Therefore, a short circuit between the two is suppressed.

[0093] Thus, according to this embodiment, even if at least one of the first and second multilayer ceramic capacitors 10 and 30 is tilted so that the two are close to each other, a short circuit between the first and second multilayer ceramic capacitors 10 and 30 can be avoided. Therefore, the distance between the first and second multilayer ceramic capacitors 10 and 30 can be narrowed. In addition, the height T

[10] of the first and second multilayer ceramic capacitors 10 and 30 can be set to be large.

[0094] In this embodiment, in FIG1B , the first multilayer ceramic capacitor 10 is located on the right side and the second multilayer ceramic capacitor 30 is located on the left side. However, the positional relationship between the two is not limited to this. Specifically, the first multilayer ceramic capacitor 10 may be located on the left side and the second multilayer ceramic capacitor 30 may be located on the right side. In this case, the second external electrode 15 of the first multilayer ceramic capacitor 10 is located between the first external electrode 34 and the second external electrode 35 of the second multilayer ceramic capacitor 30. Furthermore, the first external electrode 34 of the second multilayer ceramic capacitor 30 is located between the first external electrode 14 and the second external electrode 15 of the first multilayer ceramic capacitor 10. Even with this arrangement, the same effect can be achieved. Furthermore, the first and second multilayer ceramic capacitors 10 and 30 may be arranged in a 180° rotated state, with the positions of their respective first and second external electrodes swapped on the X-axis.

[0095] In this embodiment, the first and second multilayer ceramic capacitors 10 and 30 are identical, but they do not necessarily need to be identical. The two multilayer ceramic capacitors may be arranged such that one external electrode of one multilayer ceramic capacitor is located between a pair of external electrodes of the other multilayer ceramic capacitor.

[0096] (Second embodiment)

[0097] Next, refer to Figure 7 The second embodiment is described. The circuit board 120 of the second embodiment has a third multilayer ceramic capacitor 40 in addition to the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30. The third multilayer ceramic capacitor 40 is the same as the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30. The third multilayer ceramic capacitor 40 has a ceramic body 41, a first external electrode 44, and a second external electrode 45. The X-axis dimension, i.e., the length, of the first external electrode 44 is marked as L

[44] . The X-axis dimension, i.e., the length, of the second external electrode 45 is marked as L

[45] . Furthermore, the interval between the first external electrode 44 and the second external electrode 45 along the X-axis direction is marked as G

[40] . The ceramic body 41 is exposed between the first external electrode 44 and the second external electrode 45. In addition, since the third multilayer ceramic capacitor 40 is the same as the first multilayer ceramic capacitor 10, a detailed description of its internal structure, etc. is omitted.

[0098] The third multilayer ceramic capacitor 40 is arranged such that the first external electrode 44 is located between the first external electrode 14 and the second external electrode 15 of the first multilayer ceramic capacitor 10 , and is arranged adjacent to the second multilayer ceramic capacitor 30 in the longitudinal direction.

[0099] That is, the second external electrode 35 of the second multilayer ceramic capacitor 30 and the first external electrode 44 of the third multilayer ceramic capacitor 40 are arranged between the first external electrode 14 and the second external electrode 15 of the first multilayer ceramic capacitor 10 .

[0100] At this time, the first external electrode 14 of the first multilayer ceramic capacitor 10 and the second external electrode 35 of the second multilayer ceramic capacitor 30 are arranged along the Y-axis direction with a gap S therebetween. Here, the gap S is the shortest distance along the Y-axis direction between the first external electrode 14 of the first multilayer ceramic capacitor 10 and the second external electrode 35 of the second multilayer ceramic capacitor 30.

[0101] Similarly, the second external electrode 15 of the first multilayer ceramic capacitor 10 and the first external electrode 44 of the third multilayer ceramic capacitor 40 are also arranged along the Y-axis direction with a spacing S therebetween. Here, the spacing S is the shortest distance along the Y-axis direction between the second external electrode 15 of the first multilayer ceramic capacitor 10 and the first external electrode 44 of the third multilayer ceramic capacitor 40.

[0102] No other components are mounted between the first and second multilayer ceramic capacitors 10 and 30, and between the first and third multilayer ceramic capacitors 10 and 40. Therefore, from the perspective of high-density packaging, the interval S is preferably 0.3 mm or less, and more preferably 0.2 mm or less.

[0103] The gap G

[10] between the first external electrode 14 and the second external electrode 15 of the first multilayer ceramic capacitor 10 is at least longer than the sum of the length L

[35] of the second external electrode 35 of the second multilayer ceramic capacitor 30 and the length L

[44] of the first external electrode 44 of the third multilayer ceramic capacitor 40. Thus, the second external electrode 35 of the second multilayer ceramic capacitor 30 and the first external electrode 44 of the third multilayer ceramic capacitor 40 can be arranged between the external electrodes of the first multilayer ceramic capacitor 10 while a gap is provided between them. Furthermore, when such a dimensional relationship is satisfied, the gap G

[30] of the second multilayer ceramic capacitor 30 is greater than the length L

[14] of the first external electrode 14 of the first multilayer ceramic capacitor 10. Furthermore, the gap G

[40] of the third multilayer ceramic capacitor 40 is greater than the length L

[15] of the second external electrode 15 of the first multilayer ceramic capacitor 10.

[0104] In such a circuit board 120, even if the first multilayer ceramic capacitor 10 is tilted toward the second multilayer ceramic capacitor 30 and the third multilayer ceramic capacitor 40, contact between the external electrodes can be avoided. Furthermore, even if the second multilayer ceramic capacitor 30 and the third multilayer ceramic capacitor 40 are tilted toward the first multilayer ceramic capacitor 10, contact between the external electrodes can be avoided.

[0105] Therefore, the distance between the first and second multilayer ceramic capacitors 10 and 30, and the distance between the first and third multilayer ceramic capacitors 10 and 40 can be reduced. Furthermore, the height T

[10] of the first and second multilayer ceramic capacitors 10 and 30 can be set larger. Furthermore, the height (not shown) of the third multilayer ceramic capacitor 40 can also be set larger.

[0106] (Third embodiment)

[0107] Next, refer to Figures 8 to 10 , the third embodiment is described. Figure 10 As shown, a first multilayer ceramic capacitor 50 and a second multilayer ceramic capacitor 61 are provided instead of the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor of the first embodiment.

[0108] The first multilayer ceramic capacitor 50 and the second multilayer ceramic capacitor 61 are identical. Therefore, in the following description, the first multilayer ceramic capacitor 50 will be mainly described.

[0109] Figure 8 The first multilayer ceramic capacitor 50 is connected to Figure 2 9 (A) is a diagram obtained by cutting the first multilayer ceramic capacitor 50 along the line corresponding to the line A1-A1 in FIG. That is, it is a diagram equivalent to the cross-sectional view of the first multilayer ceramic capacitor 10 along the line A1-A1 in the first embodiment. Figure 2 9B is a cross-sectional view of the first multilayer ceramic capacitor 50 taken along the line corresponding to the A2-A2 line in FIG. Figure 2 That is, it is a cross-sectional view corresponding to the A3-A3 cross-sectional view of the first multilayer ceramic capacitor 10 according to the first embodiment. Figure 10 9(B) is a perspective view of the circuit board 130 showing the first multilayer ceramic capacitor 50 and the second multilayer ceramic capacitor 30 in partial cross-section. In addition, the second external electrode 55 is omitted in FIG. Figure 10, which schematically shows the arrangement of the first multilayer ceramic capacitor 50 and the second multilayer ceramic capacitor 61, does not accurately represent the dimensional ratio of each component.

[0110] <<Appearance and shape>>

[0111] The first multilayer ceramic capacitor 50 has a substantially similar appearance to the first multilayer ceramic capacitor 10 of the first embodiment. Specifically, the first multilayer ceramic capacitor 50 includes a ceramic body 51, a first external electrode 54, and a second external electrode 55. The first external electrode 54 includes a first surface 54a, a second surface (not shown), a third surface (not shown), a fourth surface 54d, and a fifth surface 54e. The second external electrode 55 includes a first surface (not shown), a second surface 55b, a third surface 55c, a fourth surface (not shown), and a fifth surface (not shown). Furthermore, the first multilayer ceramic capacitor 50 includes a first main surface M51, a first side surface S51, and other components. These components are identical to the corresponding components of the first multilayer ceramic capacitor 10 of the first embodiment, and therefore detailed descriptions thereof are omitted here.

[0112] The length, width, and height of the first multilayer ceramic capacitor 50 are not shown in the figure, but are indicated as length L

[50] , width W

[50] , and height T

[50] , respectively, similar to the first multilayer ceramic capacitor 10 of the first embodiment. Furthermore, the first multilayer ceramic capacitor 50 is a high-back type, with the height T

[50] being at least 1.3 times the width W

[50] . This point is also the same as the first multilayer ceramic capacitor 10 of the first embodiment.

[0113] <<Internal Structure>>

[0114] Next, refer to Figure 8 9(B) , the internal structure of the first multilayer ceramic capacitor 50 in the second embodiment will be described.

[0115] The ceramic body 51 has a stacking portion 56 and a pair of covering portions 57. The stacking portion 56 has a capacitor forming portion 60 and a pair of edge portions 58. The capacitor forming portion 60 includes a plurality of first and second internal electrodes 52, 53 alternately stacked with a plurality of ceramic layers 59 along the Y-axis direction. In the present embodiment, the internal electrodes 52, 53 and the ceramic layers 59 are respectively configured as sheets extending along the XZ plane. The internal electrodes 52, 53 are stacked along the Y-axis direction and are opposite to each other in a direction parallel to the mounting surface 1a, so that the bonding area between each first internal electrode 52 and the first external electrode 54 and the bonding area between each second internal electrode 53 and the second external electrode 55 can be expanded. As a result, the reduction in capacitance caused by poor contact, the so-called capacitance loss, is suppressed. In addition, the number of stacking of the first internal electrodes 52 and the second internal electrodes 53 in each figure does not represent the actual number of stacking.

[0116] The first and second internal electrodes 52 and 53 are arranged alternately along the Y-axis, facing each other in the Y-axis direction. The internal electrodes 52 and 53 face each other in the Y-axis direction in a central facing region in the X-axis and Z-axis directions. The first internal electrodes 52, which constitute the first group, extend from the facing region to one end face E51 and are connected to the first external electrode 54. The second internal electrodes 53, which constitute the second group, extend from the facing region to the other end face E52 and are connected to the second external electrode 55.

[0117] The internal electrodes 52 and 53 contain a metal material as a main component. Typical examples of this metal material include nickel (Ni), but also copper (Cu), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), and alloys thereof. Similar to the first and second internal electrodes 12 and 13 in the first embodiment, the internal electrodes 52 and 53 can contain a low-melting-point metal.

[0118] With this structure, when a voltage is applied between the external electrodes 54 and 55 in the first multilayer ceramic capacitor 50, a voltage is applied to the plurality of ceramic layers 59 between the internal electrodes 52 and 53 in the facing region. Consequently, charge corresponding to the voltage between the external electrodes 54 and 55 is accumulated in the second multilayer ceramic capacitor 30.

[0119] In the laminated portion 56, a high-dielectric-constant dielectric ceramic is used to increase the capacitance of each ceramic layer 59 between the first and second inner electrodes 52 and 53. Examples of high-dielectric-constant dielectric ceramics include perovskite-structured materials containing barium (Ba) and titanium (Ti), such as barium titanate (BaTiO3).

[0120] Alternatively, the dielectric ceramic may be composed of strontium titanate (SrTiO3), calcium titanate (CaTiO3), magnesium titanate (MgTiO3), calcium zirconate (CaZrO3), calcium zirconate titanate (Ca(Zr,Ti)O3), barium calcium zirconate titanate ((Ba,Ca)(Zr,Ti)O3), barium zirconate (BaZrO3), titanium oxide (TiO2), or the like. As in the first embodiment, a low-melting-point metal may be added to the dielectric ceramic.

[0121] A pair of covering portions 57 covers the laminated portion 56 from both sides in the Z-axis direction. The covering portions 57 are sometimes also referred to as protective layers in the height direction. The covering portions 57 are subsequently mounted on the surface of the laminated portion 56 that is perpendicular to the Z-axis. The covering portion 57 is composed, for example, of a stack of ceramic sheets extending along the XY plane. From the viewpoint of suppressing internal stress, etc., the dielectric ceramic constituting the covering portion 57 is preferably of the same composition as that of the ceramic layer 59. In addition, the method for forming the covering portion 57 is not limited thereto. For example, the covering portion 57 can also be formed by stacking a plurality of ceramic sheets having internal electrode forming layers while retaining portions corresponding to the covering portions.

[0122] A pair of edge portions 58 are formed along the Z-axis direction and cover the capacitor-forming portion 60 from the Y-axis direction. Edge portions 58 are sometimes referred to as widthwise protective layers. Edge portions 58 are formed, for example, from a ceramic sheet in a sheet-like shape extending along the XZ plane. To suppress internal stress, the dielectric ceramic forming edge portions 58 preferably has the same composition as ceramic layer 59.

[0123] In addition, regarding the second multilayer ceramic capacitor 61, components required for the following description are denoted by reference numerals different from those of the first multilayer ceramic capacitor 50. Specifically, Figure 10 Reference numeral 64 in FIG. 8 denotes a first external electrode, and reference numeral 65 denotes a second external electrode 65 .

[0124] like Figure 11 As shown, the first and second multilayer ceramic capacitors 50 and 61 are similar to those shown in FIG. 1(A), FIG. 1(B), and FIG. Figure 6 The first and second multilayer ceramic capacitors 10 and 30 of the first embodiment shown are mounted on a printed wiring board 1 in the same manner. Specifically, the first external electrode 54 of the first multilayer ceramic capacitor 50 is positioned in the X-axis direction between the first and second external electrodes 64 and 65 of the second multilayer ceramic capacitor 61. Furthermore, the second external electrode 65 of the second multilayer ceramic capacitor 61 is positioned in the X-axis direction between the first and second external electrodes 54 and 55 of the first multilayer ceramic capacitor 50.

[0125] Thus, even if the high-profile first multilayer ceramic capacitor 50 and the second multilayer ceramic capacitor 61 are tilted, contact between the external electrodes can be avoided.

[0126] In addition, an electrostriction phenomenon sometimes occurs in the first multilayer ceramic capacitor 50 and the second multilayer ceramic capacitor 61. The electrostriction phenomenon becomes a cause of so-called ringing. However, the stacking direction of the first and second internal electrodes 52 and 53 in the first multilayer ceramic capacitor 50 and the second multilayer ceramic capacitor 61 is along the direction of the Y axis, which is a direction orthogonal to the mounting direction, that is, the direction of the Z axis. Thus, ringing sound is suppressed in the first multilayer ceramic capacitor 50 and the second multilayer ceramic capacitor 61.

[0127] In the present embodiment, the first multilayer ceramic capacitor 50 and the second multilayer ceramic capacitor 61 are used as the same components, but one of them can be replaced with, for example, the first multilayer ceramic capacitor 10 of the first embodiment.

[0128] (Fourth Embodiment)

[0129] Next, the fourth embodiment will be described. The fourth embodiment is different from the first embodiment in that, as shown in FIG. 7, electronic components 70 are arranged on both sides of the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 in the direction of the Y axis. Figure 11

[0130] The electronic components 70 are covered with a cover member that is insulating. Thus, even if the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 are tilted toward the electronic components 70 on the respective side, a short circuit does not occur between the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 and the electronic components.

[0131] Thus, it is possible to reduce the interval of the first multilayer ceramic capacitor 10 and the electronic components 70 and the interval of the second multilayer ceramic capacitor 30 and the electronic components 70. In addition, it is possible to set the height of the first multilayer ceramic capacitor 10 and the height of the second multilayer ceramic capacitor 30 to be larger.

[0132] In addition, in the present embodiment, the electronic components 70 are arranged on the side of the first multilayer ceramic capacitor 10 and on the side of the second multilayer ceramic capacitor 30, but either one of them can be arranged with the electronic components 70.

[0133] (Fifth Embodiment)

[0134] Next, the fifth embodiment will be described. The fifth embodiment is different from the first embodiment in the following respects. Referring to FIG. 8, the fifth embodiment is different from the first embodiment in that, as shown in FIG. 8, electronic components 70 are arranged on both sides of the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 in the direction of the Y axis. Figure 12 ​, showing the ceramic body of the first multilayer ceramic capacitor 10 in an exploded state. The fifth embodiment, like the first embodiment, includes first and second internal electrodes 12 and 13, but their shapes differ. Other aspects are the same as those of the first embodiment, so the following description of the fifth embodiment will refer to the figures used to illustrate the first embodiment as appropriate. Components common to the first embodiment are denoted by the same reference numerals.

[0135] As shown in FIG5(A) , the first internal electrodes 12 included in the first group are connected to the first external electrode 14 , and the second internal electrodes 13 included in the second group are connected to the second external electrode 15 .

[0136] Return Figure 12 In this embodiment, the first internal electrode 12 has a connection end 12a connected to the first external electrode 14 and an open end 12b located opposite the connection end 12a. A notch 12a2 is provided in the connection end 12a, forming a narrow portion 12a1. The width of the narrow portion 12a1 is narrower than the width of the portion away from the connection end 12a toward the open end 12b.

[0137] Similarly, the second internal electrode 13 of this embodiment has a connection end 13a connected to the second external electrode 15 and an open end 13b located opposite the connection end 13a. A notch 13a2 is provided in the connection end 13a, thereby forming a narrow portion 13a1. The width of the narrow portion 13a1 is narrower than the width of the portion away from the connection end 13a toward the open end 13b.

[0138] By adopting this structure, for example, when the internal electrodes 12 and 13 are made of Ni and the external electrodes 14 and 15 are made of Cu, it is possible to suppress expansion of the internal electrodes 12 and 13 due to diffusion of Cu from the external electrodes 14 and 15, thereby preventing cracks from forming at the corners of the first multilayer ceramic capacitor. In particular, even when a low-melting-point metal is added to the internal electrodes 12 and 13 and the dielectric ceramic, as described in the first embodiment, expansion of the internal electrodes 12 and 13 can be avoided, thereby suppressing the formation of cracks.

[0139] In the fifth embodiment, the appearance, dimensional relationship, and positional relationship between the first and second multilayer ceramic capacitors 10, 30 are maintained as in the first embodiment. Therefore, in the fifth embodiment, short circuits between the first and second multilayer ceramic capacitors 10, 30 can be suppressed, similarly to the first embodiment.

[0140] (Variation)

[0141] Next, a modified example of the fifth embodiment will be described. The circuit board 150 of the fifth embodiment maintains the basic configuration of the first embodiment, but modifies the shapes of the internal electrodes 12 and 13. In contrast, this modified example maintains the basic configuration of the third embodiment, but modifies the shapes of the internal electrodes 52 and 53.

[0142] Reference Figure 13 , showing the first laminated ceramic capacitor 80 and the second laminated ceramic capacitor 90 (refer to Figure 14 The first and second multilayer ceramic capacitors 80 and 90 correspond to the first and second multilayer ceramic capacitors 50 and 61 in the third embodiment, respectively.

[0143] This modification has the same first and second internal electrodes 52 and 53 as the third embodiment, but their shapes differ. Other parts do not differ from the third embodiment. Therefore, in the following description, the modification of the fifth embodiment will be described with appropriate reference to the drawings used to illustrate the third embodiment. Components common to the third embodiment will be denoted by the same reference numerals.

[0144] Although not shown, the first internal electrodes 52 included in the first group are connected to the first external electrode 54. Furthermore, as shown in FIG9(A) , the second internal electrodes 53 included in the second group are connected to the second external electrode 55.

[0145] Return Figure 13 The first internal electrode 52 of this modified example has a connection end 52a connected to the first external electrode 54 and an open end 52b located opposite the connection end 52a. A notch 52a2 is provided in the connection end 52a, forming a narrow portion 52a1. The width of the narrow portion 52a1 is narrower than the width of the portion away from the connection end 52a toward the open end 52b. The width of the first internal electrode 52 is the dimension along the Z-axis direction.

[0146] Similarly, the second inner electrode 53 of this modified example has a connection end 53a connected to the second outer electrode 55 and an open end 53b located opposite the connection end 53a. A notch 53a2 is provided in the connection end 53a, thereby forming a narrow portion 53a1. The width of the narrow portion 53a1 is narrower than the width of the portion away from the connection end 53a toward the open end 53b. The width of the second inner electrode 53 also extends along the Z-axis direction.

[0147] By adopting such a structure, for example, when the internal electrodes 52 and 53 are formed of Ni and the external electrodes 54 and 55 are formed of Cu, it is possible to suppress expansion of the internal electrodes 52 and 53 due to diffusion of Cu from the external electrodes 54 and 55, thereby preventing cracks from occurring at the corners of the first multilayer ceramic capacitor 90. In particular, even when a low-melting-point metal is added to the internal electrodes 52 and 53 or the dielectric ceramic as described in the third embodiment, expansion of the internal electrodes 12 and 13 can be avoided, thereby suppressing the occurrence of cracks.

[0148] Even in this modified example, the external shapes, dimensional relationship, and positional relationship between the first and second multilayer ceramic capacitors 80, 90 of the third embodiment are maintained. Therefore, in this modified example, as in the third embodiment, short circuits between the first and second multilayer ceramic capacitors 80, 90 are suppressed.

[0149] Example

[0150] (Example)

[0151] Next, examples will be described along with comparative examples. In the circuit board 110 of the first embodiment, the dimensions of the various components of the first and second multilayer ceramic capacitors 10 and 30 were set to the values ​​shown below. Three combinations of the first and second multilayer ceramic capacitors 10 and 30 were prepared: Patterns 1 to 3.

[0152] As shown in Figures 15(A) and 15(B), the comparative example arranges two first multilayer ceramic capacitors 10 along the Y-axis. In this case, the two first multilayer ceramic capacitors 10 are aligned along the X-axis. Specifically, the first external electrodes 14 are adjacent to each other along the Y-axis, and the second external electrodes 15 are adjacent to each other along the Y-axis.

[0153] <Mode 1>

[0154] First multilayer ceramic capacitor 10:

[0155] Length L

[10] : 0.6mm, Width W

[10] : 0.3mm, Height T

[10] : 0.4mm

[0156] Second multilayer ceramic capacitor 30:

[0157] It is the same product as the first multilayer ceramic and has the same dimensions.

[0158] Interval S:

[0159] 0.1mm

[0160] T

[10] / W

[10] in mode 1 is approximately 1.33, satisfying the condition of the first multilayer ceramic capacitor 10 of the first embodiment, that is, T

[10] is 1.3 times or greater than W

[10] .

[0161] <Mode 2>

[0162] First multilayer ceramic capacitor 10:

[0163] Same as Mode 1.

[0164] Second multilayer ceramic capacitor 30:

[0165] Length L

[30] : 0.4mm, Width W

[30] : 0.2mm, Height T

[30] : 0.3mm

[0166] Interval S:

[0167] Same as Mode 1.

[0168] In Mode 2, T

[30] / W

[30] is 1.5, satisfying the condition of the second multilayer ceramic capacitor 30 of the first embodiment, namely, T

[30] is 1.3 times or more, and further, 1.5 times or more, of W

[30] . The first multilayer ceramic capacitor 10, like Mode 1, satisfies the condition of the first multilayer ceramic capacitor 10 of the first embodiment, namely, T

[10] is 1.3 times or more, of W

[10] .

[0169] <Mode 3>

[0170] First multilayer ceramic capacitor 10:

[0171] Same as Mode 1.

[0172] Second multilayer ceramic capacitor 30:

[0173] Length L

[30] : 1.0mm, Width W

[30] : 0.5mm, Height T

[30] : 0.7mm

[0174] Interval S:

[0175] Same as Mode 1.

[0176] In Mode 3, T

[30] / W

[30] is 1.4, satisfying the condition of the second multilayer ceramic capacitor 30 in the first embodiment, namely, T

[30] is 1.3 times or greater than W

[30] . The first multilayer ceramic capacitor 10, like Mode 1, satisfies the condition of the first multilayer ceramic capacitor 10 in the first embodiment, namely, T

[10] is 1.3 times or greater than W

[10] .

[0177] <Comparative Example>

[0178] First multilayer ceramic capacitor 10:

[0179] Length L

[10] : 0.6mm, Width W

[10] : 0.3mm, Height T

[10] : 0.4mm

[0180] Interval S:

[0181] 0.1mm

[0182] T

[10] / W

[10] in the comparative example is approximately 1.33, which satisfies the condition of the first multilayer ceramic capacitor 10 of the first embodiment that T

[10] is 1.3 times or greater than W

[10] .

[0183] [Test method]

[0184] A predetermined number of samples were prepared for each of Patterns 1 to 3 of the Examples and the Comparative Example. Samples were then selected in which at least one of the adjacent multilayer ceramic capacitors, aligned with their widths in the same direction, was tilted toward each other. A voltage was applied between test terminals 4a and 4b to confirm the presence of a short circuit.

[0185] [Test results]

[0186] In Patterns 1 to 3 of the Examples, the occurrence of short circuit was not confirmed in any of the samples.

[0187] Among the comparative examples, some samples experienced short circuits. In these samples, tilting of the first multilayer ceramic capacitor 10 was observed. In the comparative examples, as shown in Figures 16(A) and 16(B), when one or both of the first multilayer ceramic capacitors 10 tilted, the first external electrodes 14 and the second external electrodes 15 came into contact with each other, causing a short circuit.

[0188] Thus, according to this embodiment, even when T

[10] is 1.3 times or more of W

[10] , and further even when T

[10] is 1.5 times or more of W

[10] , the occurrence of a short circuit can be suppressed.

[0189] The second to fourth embodiments and their modifications all maintain the appearance of the first multilayer ceramic capacitor 10 and the dimensional and positional relationship with the second multilayer ceramic capacitor 30 of the first embodiment. Therefore, it is believed that the occurrence of short circuits can be similarly suppressed in any of the embodiments.

[0190] Furthermore, the above embodiments describe a multilayer ceramic capacitor as an example of a multilayer ceramic electronic component, but the present invention is not limited thereto. For example, the structures of the above embodiments can also be applied to other multilayer ceramic electronic components such as varistors and thermistors.

[0191] The above embodiments are merely examples for implementing the present invention, and the present invention is not limited thereto. Various modifications to these embodiments are within the scope of the present invention. It is obvious from the above description that various other embodiments can be implemented within the scope of the present invention.

[0192] Description of Reference Numerals

[0193] 1: Printed wiring board, 2a: First pad, 2b: Second pad, 2c: Third pad, 2d: Fourth pad, 3: Solder joint, 10, 50, 80: First multilayer ceramic capacitor, 11, 31, 51: Ceramic body, M11, M51: First main surface, M12…second main surface, E11…first end surface, E12…second end surface, S11, S51…first side surface, S12…second side surface, 12, 13, 52, 53, 92, 93…internal electrodes, 14, 34, 54…first external electrodes, 15, 35, 55…second external electrodes, 16, 60…capacitor forming portion, 17, 57…covering portion, 18, 58…edge portion, 19, 59…ceramic layer, 20, 56…laminated portion, 30, 61, 90…second laminated ceramic capacitor, 110, 120, 130, 140, 150…circuit board.

Claims

1. A circuit board, characterized in that: include: substrate; and A plurality of multilayer ceramic electronic components mounted on the mounting surface of the substrate, When a direction along a first axis is defined as a height direction, a direction along a second axis perpendicular to the direction along the first axis is defined as a width direction, and a direction along a third axis perpendicular to the directions along the first axis and along the second axis is defined as a length direction, at least a first and a second multilayer ceramic electronic component among the plurality of multilayer ceramic electronic components each have a first external electrode having a predetermined length along the length direction at one end portion in the length direction, and a second external electrode having a predetermined length along the length direction at the other end portion in the length direction. The height of the first multilayer ceramic electronic component is 1.3 times or more of the width or length of the first multilayer ceramic electronic component, and the height of the second multilayer ceramic electronic component is 1.3 times or more of the width or length of the second multilayer ceramic electronic component. The first and second multilayer ceramic electronic components are adjacent to each other in a state where their respective height directions are perpendicular to the mounting surface and their respective width directions are in the same direction, and are arranged on the mounting surface in a state where they are staggered from each other in a length direction such that one of the first external electrode and the second external electrode of the first multilayer ceramic electronic component is located between the first external electrode and the second external electrode of the second multilayer ceramic electronic component, and one of the first external electrode and the second external electrode of the second multilayer ceramic electronic component is located between the first external electrode and the second external electrode of the first multilayer ceramic electronic component.

2. The circuit board according to claim 1, wherein: Another electronic component is mounted so as to be adjacent to a side of at least one of the first and second multilayer ceramic electronic components in the width direction and covered with an insulating cover.

3. The circuit board according to claim 1 or 2, characterized in that: At least one of the height of the first multilayer ceramic electronic component and the height of the second multilayer ceramic electronic component is 1.5 times or more the respective width or length.

4. The circuit board according to claim 1, wherein: At least one of the internal electrodes provided in the ceramic body of the first multilayer ceramic electronic component and the internal electrodes provided in the ceramic body of the second multilayer ceramic electronic component are stacked in the direction along the first axis so as to oppose each other.

5. The circuit board according to claim 4, wherein: The internal electrodes stacked in the direction along the first axis include: a first internal electrode connected to the first external electrode; and a second internal electrode connected to the second external electrode, The first internal electrode has a connection end connected to the first external electrode and an open end located on the opposite side of the connection end, the connection end having a narrow portion having a width smaller than a width of a portion away from the connection end toward the open end. The second internal electrode has a connection end connected to the second external electrode and an open end located opposite to the connection end. The connection end has a narrow portion having a width smaller than a width of a portion away from the connection end toward the open end.

6. The circuit board according to claim 1, wherein: At least one of the internal electrodes provided in the ceramic body of the first multilayer ceramic electronic component and the internal electrodes provided in the ceramic body of the second multilayer ceramic electronic component are stacked in the direction along the second axis so as to oppose each other.

7. The circuit board according to claim 6, wherein: The internal electrodes stacked in the direction along the second axis include: a first internal electrode connected to the first external electrode; and a second internal electrode connected to the second external electrode, The first internal electrode has a connection end connected to the first external electrode and an open end located on the opposite side of the connection end, the connection end having a narrow portion having a width smaller than a width of a portion away from the connection end toward the open end. The second internal electrode has a connection end connected to the second external electrode and an open end located opposite to the connection end. The connection end has a narrow portion having a width smaller than a width of a portion away from the connection end toward the open end.

8. The circuit board according to claim 5 or 7, characterized in that: The internal electrodes or the dielectric layer formed between the internal electrodes contain a low melting point metal.

9. The circuit board according to claim 1, wherein: The plurality of multilayer ceramic electronic components further include a third multilayer ceramic electronic component having a first external electrode having a predetermined length along the longitudinal direction at one end portion thereof and a second external electrode having a predetermined length along the longitudinal direction at the other end portion thereof. The third multilayer ceramic electronic component is configured so that one of the first external electrode and the second external electrode of the third multilayer ceramic electronic component is located between the first external electrode and the second external electrode of one of the first multilayer ceramic electronic component and the second multilayer ceramic electronic component, and is configured adjacent to the other of the first multilayer ceramic electronic component and the second multilayer ceramic electronic component along the length direction.

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