Ceramic circuit board production parameter optimization method and device

Abstract

The invention discloses a ceramic circuit board production parameter optimization method and device, and relates to the technical field of image data processing. The ceramic circuit board production parameter optimization method comprises the following steps: defect feature identification and first production parameter optimization; feature point extraction and second production parameter optimization; and quantifying the overlap ratio and optimizing the third production parameters. According to the method, the interference degree is identified through the defect features under the heat conduction condition so as to judge whether the first production parameter optimization is carried out, then the feature points are quantified to extract the interference degree so as to judge whether the second production parameter optimization is carried out, and finally the overlap ratio between the thermal anomaly defects is quantified so as to judge whether the third production parameter optimization is carried out. The effect of improving the accuracy of production parameter optimization of the ceramic insulation substrate under the heat conduction condition is achieved, and the problem that in the prior art, due to the fact that the recognition accuracy of the temperature feature points of the ceramic insulation substrate embedded in the ceramic heat conduction circuit board under the heat conduction condition is not high, the reliability of production parameter optimization is not high is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of image data processing, and particularly relates to a ceramic circuit board production parameter optimization method and device. BACKGROUND

[0002] The inlaid ceramic heat-conducting circuit board is widely used in the electronic device field due to its unique structure and performance advantages. The production step process thereof is generally as follows: firstly, a first and a second insulating substrate are respectively prepared, and the thickness, flatness and other parameters of the substrate are controlled through a specific process; then, a vertical channel is processed on the substrate, and the dimensional accuracy of the channel is crucial to the installation adaptability of the subsequent ceramic body; then, the ceramic body is embedded into the vertical channel, so as to ensure that the upper and lower ends of the ceramic body form flush planes; subsequently, a first metal layer and a second metal layer are respectively laid on the upper and lower flush planes of the ceramic body, and the laying process and thickness of the metal layer affect the electrical connection and heat dissipation performance of the circuit board; finally, the first and the second insulating substrates distributed above and below are bonded through an insulating adhesive layer, and the overall assembly of the circuit board is completed.

[0003] In the entire production process, the ceramic insulating substrate as a key component of the circuit board has many problems in the production parameter optimization. On the one hand, the firing temperature of the ceramic insulating substrate significantly affects its physical and chemical properties, and too high or too low temperature will cause cracks, insufficient strength and other problems of the substrate, thereby affecting the overall performance of the circuit board; on the other hand, the raw material ratio of the substrate changes its insulation performance and mechanical strength, and an inappropriate ratio may cause the voltage resistance of the circuit board to decrease, which is difficult to meet the safe use requirements of the electronic device. In addition, the forming process parameters of the substrate, such as pressure and time, also affect the density and uniformity of the substrate, thereby adversely affecting the heat dissipation and stability of the circuit board.

[0004] In order to effectively solve the above problems and determine the optimal production parameters, a trial production stage is set before formal mass production. In the trial production stage, the technicians set multiple different temperature gradients for the firing temperature of the ceramic insulating substrate, and the temperature gradient is increased in turn, and a certain number of substrate samples are fired under each temperature gradient. The prior art usually adopts single parameter adjustment or empirical parameter combination optimization method, specifically: collecting and analyzing all initial production parameters of the ceramic circuit board, such as ceramic body firing temperature, metal layer laying thickness, etc., determining the appropriate firing temperature range by observing the quality of the finished ceramic insulating substrate at different firing temperatures; then constructing an accurate circuit board thermal-electric coupling model with the help of advanced computer simulation technology, which can accurately simulate the heat dissipation effect and voltage resistance performance of the circuit board under different production parameter combinations, and through a large number of simulation experiments, small-scale adjustment of raw material proportion and test of substrate performance, the parameter range considering heat dissipation and voltage resistance is selected; on this basis, small-batch trial production is carried out, the optimal parameters obtained by simulation are applied to test the actual circuit board performance and compared with the simulation results, and the optimal production parameters are determined after fine-tuning the parameters. However, these methods often fail to achieve the coordinated optimization of multiple performance indicators due to insufficient consideration of the mutual relationship and coupling effect between parameters, resulting in the optimized ceramic insulating substrate still failing to achieve the ideal state in terms of heat dissipation, voltage resistance and other key performances.

[0005] For example, the announcement number: CN114022439B Chinese invention patent discloses a flexible circuit board defect detection method based on morphological image processing, which comprises: acquiring the real image of the circuit board to be detected, and denoising the real image; adaptive binaryzation processing is performed on the denoised real image, and the area of the printed circuit is determined based on the binaryzation real image; the corresponding CAD data is obtained according to the area of the printed circuit, and the reference image is generated; then, according to the first rule, the reference sub-region set containing multiple reference sub-regions is determined based on the reference image; one of the reference sub-regions is selected, and the position of the reference sub-region in the binaryzation real image is determined to obtain the target sub-region; multi-printing detection and missing printing detection are performed to generate a new image; and the new image is processed according to the region marking method to determine whether there is a multi-printing defect.

[0006] For example, the announcement number: CN114298996B Chinese invention patent discloses a circuit board scratch detection method and system based on image processing, which comprises: acquiring the surface image of the circuit board; performing grayscale and filtering processing on the image to obtain a grayscale image; performing Gaussian filter denoising and then Gaussian smoothing processing on the grayscale image; using the circuit component manufacturing background template to match the template with the image to locate the position of the circuit component in the image; removing the circuit component in the image and obtaining the image shielding the circuit component through region filling; and performing scratch extraction on the image without circuit components.

[0007] In the prior art, under the condition of heat conduction, micro defects such as cracks and pores inevitably occur in the ceramic insulating substrate due to thermal stress concentration caused by heat generated by the continuous operation of electronic components. At the same time, the significant difference in the thermal expansion coefficient between the metal layer (used for connecting components) and the ceramic body (used as a heat conduction medium and structural support) will cause uneven deformation at the interface when the temperature changes. This deformation not only enlarges the size of the original defects, but also causes the internal microstructure of the ceramic insulating substrate to appear local loosening or stress concentration areas, thereby destroying the uniform distribution of the temperature field and forming a complex heat flow path. In addition, although the prior art simulates and optimizes production parameters through a thermal-electric coupling model and introduces a PID controller to dynamically adjust key process variables (such as molding pressure) to suppress thermal stress fluctuations, the model is mostly based on the assumption of static thermal load and fails to fully capture the real-time influence of dynamic heat flow on temperature gradient during heat conduction. This results in a low coincidence rate of the three-dimensional thermal structure model in locating the thermal abnormal area with the actual thermal resistance position (such as the defect area of cracks, pores, etc.), making it difficult to accurately match the temperature defects, thereby limiting the reliability of production parameter optimization and the stability of long-term operation of the circuit board. There is a problem of low reliability of production parameter optimization caused by low accuracy of temperature feature point recognition of the ceramic insulating substrate in the inlaid ceramic heat conduction circuit board under the condition of heat conduction. SUMMARY

[0008] To solve the technical problems in the prior art, the embodiments of the present application provide a ceramic circuit board production parameter optimization method and device. The technical solution is as follows: In one aspect, a ceramic circuit board production parameter optimization method is provided, which comprises the following steps: in step one, during a ceramic circuit board trial production stage, an internal structure image of a specified batch of ceramic insulating substrate samples is obtained, and the interference degree of quantized defect feature recognition of the specified batch of ceramic insulating substrate samples under a heat conduction condition is determined to determine whether to perform first production parameter optimization, the defect feature recognition includes crack recognition and pore recognition, and the first production parameter optimization is used to improve the recognition rate of cracks and pores of the specified batch of ceramic insulating substrate samples under the heat conduction condition; in step two, a temperature distribution image of the specified batch of ceramic insulating substrate samples corresponding to the qualified defect recognition is obtained, and the interference degree of temperature positioning difference data on feature point extraction of the temperature distribution image is quantized to determine whether to perform second production parameter optimization, the feature point extraction includes explicit feature point extraction and implicit feature point extraction, and the second production parameter optimization is used to reduce the interference degree of heat of the conductive circuit on the feature point extraction efficiency; in step three, the feature point temperature corresponding to the qualified feature point extraction is obtained and input to a temperature field in a built three-dimensional thermal structure model of the ceramic circuit board for temperature defect matching to obtain a thermal abnormal area, and the coincidence degree between the thermal abnormal area and a thermal resistance defect of a heating electronic component is quantized to determine whether to perform third production parameter optimization, and the third production parameter optimization is used to improve the temperature position positioning accuracy of the three-dimensional thermal structure model of the ceramic circuit board.

[0009] In another aspect, a ceramic circuit board production parameter optimization device is provided, which is applied to a ceramic circuit board production parameter optimization method, and comprises an industrial CT scanner, a material metering sensor, an infrared thermal imager, an infrared temperature sensor, a laser positioner and a PID controller; the industrial CT scanner is used to obtain an internal structure image and a thermal abnormal area; the material metering sensor is used to obtain a sintering aid amount; the infrared thermal imager is used to obtain a temperature distribution image, a thermal abnormal area area and a temperature field; the infrared temperature sensor is used to obtain a feature point temperature, a temperature extreme point and an actual temperature value; the laser positioner is used to obtain a horizontal coordinate deviation and a vertical coordinate deviation; and the PID controller is used to dynamically control a sintering aid proportion, a circuit copper foil thickness, a forming pressure and a sintering cooling speed.

[0010] The technical scheme provided by the embodiment of the present application has at least the following beneficial effects: 1. During the trial production of ceramic circuit boards, the degree of interference in defect feature identification under thermal conductivity conditions is used to determine whether to carry out the first production parameter optimization. This can accurately identify the interference caused by improper sintering aid ratios and uneven thermal stress of materials, resulting in crack and pore identification, greatly improving the recognition rate. The degree of interference in feature point extraction is then quantified to determine whether to carry out the second production parameter optimization. This can clearly identify the interference of conductive circuit heat on the positioning of explicit and implicit feature points and reduce the impact. Finally, the degree of overlap of thermal anomaly defects is quantified to determine whether to carry out the third production parameter optimization. This can accurately locate the overlap of thermal anomaly areas and heat-generating electronic components, improve the temperature positioning accuracy of the three-dimensional thermal model, accurately capture thermal anomaly areas, greatly improve the reliability of production parameter optimization, and ensure the stable operation of ceramic circuit boards in complex thermal conductivity environments.

[0011] 2. Based on the temperature distribution image, the coordinate deviation of the conductive circuit inflection point and the temperature deviation of the temperature extreme point are obtained. The harmonic mean is used as the feature point to extract the interference degree value. If it is greater than the set value, the second production parameter optimization is carried out. First, the circuit copper foil thickness is adjusted, and then the feature point coordinates are verified. If qualified, the optimization is completed. This method can accurately quantify the interference degree of feature point extraction, providing a scientific basis for whether to optimize. By adjusting the circuit copper foil thickness, the interference of the conductive circuit heat on the temperature distribution can be reduced, the temperature mutation point can be reduced, and the error of implicit feature point extraction can be reduced. The feature point coordinate verification step ensures the optimization effect and the accuracy of the extraction of explicit and implicit feature points. It effectively solves the problem of unreliable production parameter optimization due to inaccurate feature point extraction, improves the production quality of ceramic circuit boards, and ensures their stability and performance under complex working conditions.

[0012] 3. The actual temperature value is obtained by mapping the pixel values ​​of the temperature distribution image to the temperature of the feature point. This is input into the three-dimensional thermal model to obtain the thermal anomaly area. The degree of overlap between the thermal anomaly area and the set area is then quantified, namely the temperature positioning overlap rate. If the overlap rate is low, the third production parameter optimization is carried out, including temperature parameter adjustment and material thermal resistance parameter update. This method can accurately locate the thermal anomaly area and determine the positioning accuracy by quantifying the overlap rate, providing a reliable basis for the third production parameter optimization. The temperature parameter adjustment can reduce air holes and crack propagation, and the material thermal resistance parameter update can verify the effectiveness of the adjustment. This forms a closed-loop optimization, effectively solving the problem of unreliable production parameter optimization caused by inaccurate thermal anomaly positioning, and enhancing its stability and reliability in complex thermal environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 A flow chart of a ceramic circuit board production parameter optimization method provided in an embodiment of the present application is shown in FIG. 1. Figure 2 A flow chart of defect feature recognition and first production parameter optimization and determination provided in an embodiment of the present application is shown in FIG. 2. Figure 3 A flow chart of feature point extraction and second production parameter optimization and determination provided in an embodiment of the present application is shown in FIG. 3. Figure 4 A flow chart of coincidence quantification and third production parameter optimization and determination provided in an embodiment of the present application is shown in FIG. 4. Figure 5 A homepage interface diagram of a ceramic circuit board production optimization system provided in an embodiment of the present application is shown in FIG. 5. Figure 6 A defect recognition optimization block interface diagram in a ceramic circuit board production optimization system provided in an embodiment of the present application is shown in FIG. 6. Figure 7 A temperature field distribution optimization block interface diagram in a ceramic circuit board production optimization system provided in an embodiment of the present application is shown in FIG. 7. DETAILED DESCRIPTION

[0015] The technical solutions in the present application will be described below with reference to the accompanying drawings.

[0016] In the embodiments of the present application, the words such as "example", "for example" are used to represent as an example, illustration or description. Any embodiment or design scheme described as "example" in the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. In fact, the word "example" is intended to present the concept in a specific way. In addition, in the embodiments of the present application, the meaning expressed by "and / or" can be both, or can be one of the two.

[0017] In the embodiments of the present application, "image" and "picture" can be used interchangeably at times. It should be pointed out that when the distinction is not emphasized, the meanings expressed are consistent. "Of", "corresponding" and "corresponding" can be used interchangeably at times. It should be pointed out that when the distinction is not emphasized, the meanings expressed are consistent.

[0018] In the embodiments of the present application, sometimes the subscript such as W1 can be written in the form of non-subscript such as W1. When the distinction is not emphasized, the meanings expressed are consistent.

[0019] In order to make the technical problems, technical solutions and advantages to be solved by the present application clearer, specific embodiments will be described in detail below with reference to the accompanying drawings.

[0020] The embodiment of the present application provides a ceramic circuit board production parameter optimization method, such as Figure 1 As shown in a flow chart of a ceramic circuit board production parameter optimization method, the processing flow of the method can include the following steps: Step one, in the ceramic circuit board trial production stage, the internal structure image of the specified batch of ceramic insulating substrate samples is obtained, and the interference degree of the specified batch of ceramic insulating substrate samples in the heat conduction condition (that is, the heat generated by the heating electronic components on the specified ceramic insulating substrate sample when working) is quantified for defect feature recognition (that is, the reduction amplitude of the correct recognition rate of cracks and pores under the heat conduction condition relative to the non-heat conduction condition), to determine whether to perform the first production parameter optimization, the internal structure image is used for visualizing the internal structure of the specified batch of ceramic insulating substrate samples, including layer structure, crack, pore and other defect information, the defect feature recognition includes crack recognition and pore recognition, and the first production parameter optimization is used to improve the recognition rate of cracks and pores of the specified batch of ceramic insulating substrate samples under the heat conduction condition.

[0021] Step two, the temperature distribution image of the specified batch of ceramic insulating substrate samples corresponding to the qualified defect recognition is obtained, and the interference degree of the temperature positioning difference data for feature point extraction of the temperature distribution image is quantified, to determine whether to perform the second production parameter optimization, the temperature distribution image is used for visualizing the temperature distribution state of the contact interface between the specified batch of ceramic insulating substrate samples and the corresponding conductive circuit in the embedded ceramic heat-conducting circuit board, the feature point extraction includes explicit feature point extraction and implicit feature point extraction, the explicit feature point refers to the contour boundary point of the heating electronic component, the circuit corner point, the substrate edge vertex and the like, and the coordinates of the explicit feature point and the implicit feature point on the temperature distribution image are obtained through an image edge detection algorithm (such as Canny operator); the implicit feature point refers to the temperature extreme point (such as the highest temperature point of the heating center of the heating electronic component, the temperature mutation point of the substrate defect area), and the temperature value is marked, and the second production parameter optimization is used to reduce the interference degree of the heat of the conductive circuit (such as the heat generated by the circuit power consumption) on the feature point extraction efficiency.

[0022] Step three, the feature point temperature corresponding to the qualified feature point extraction is obtained, and is input to the temperature field in the constructed three-dimensional thermal structure model of the ceramic circuit board for temperature defect matching, to obtain a thermal abnormal area, and the coincidence degree between the thermal abnormal area (the abnormal temperature area positioned by the three-dimensional thermal structure model of the ceramic circuit board) and the thermal resistance defect (such as the gap between the ceramic insulating substrate and the heating electronic component, the local cracking of the solder joint) of the heating electronic component is quantified, to determine whether to perform the third production parameter optimization, and the third production parameter optimization is used to improve the temperature position positioning accuracy of the three-dimensional thermal structure model of the ceramic circuit board.

[0023] In this embodiment, when the ceramic circuit board is trial-produced, the temperature of the sample of the ceramic insulating substrate of the specified batch is scanned by a high-precision temperature sensor array (such as an infrared thermal imager) during the operation of the heat-generating electronic components on the sample of the ceramic insulating substrate of the specified batch, the temperature information of each position on the surface of the substrate is captured in real time and converted into a digital temperature value, and then the temperature data (such as the temperature at the center of the substrate and the temperature at the edge of the air hole) are matched with the spatial coordinates according to the size of the sample and the layout of the sensor, so that each temperature value corresponds to a specific position on the surface of the substrate. Using a special thermal map generation software or algorithm, the processed temperature data is visually converted according to the preset color mapping rule. Generally, high-temperature areas are mapped to warm colors such as red and orange, low-temperature areas are mapped to cold colors such as blue and green, and intermediate temperature areas are mapped to transition colors according to the temperature gradient. In this way, the temperature data is presented in the form of intuitive color distribution, forming a thermal map.

[0024] The generated thermal map is superimposed and displayed with the internal structure image, so that the production personnel can intuitively see the heat dissipation of the sample of the ceramic insulating substrate under the heat conduction condition, including the problem of heat accumulation area. By presenting the heat dissipation of the sample of the ceramic insulating substrate of the specified batch in the internal structure image under the heat conduction condition, the production personnel can intuitively understand the quality of the ceramic insulating substrate, which provides an important basis for defect feature recognition and production parameter optimization. At the same time, the internal structure image can also be used for quality traceability and fault analysis, helping enterprises to improve product quality and production management level.

[0025] Further, the interference degree of the specified batch of ceramic insulating substrate samples in the heat conduction condition is quantified for defect feature recognition, specifically including: based on the internal structure image, obtaining the crack recognition interference degree and the pore recognition interference degree of the specified batch of ceramic insulating substrate samples at the end of the defect feature recognition period, synchronously obtaining the set crack recognition interference degree and the pore recognition interference degree from the database, respectively performing interference degree proportion operation, obtaining the crack recognition interference score and the pore recognition interference score, the crack recognition interference score representing the complement of the crack recognition interference degree, the pore recognition interference score representing the complement of the pore recognition interference degree, the crack recognition interference degree representing the ratio of the crack recognition rate of the specified batch of ceramic insulating substrate samples at the end of the defect feature recognition period to the set crack recognition rate in the database, the crack recognition rate representing the ratio of the total number of crack pixels recognized in the defect feature recognition period to the total number of set crack pixels in the database, the total number of set crack pixels being represented by the result of summing and averaging the total number of historical crack pixels recognized in the historical defect feature recognition period in the database, the crack recognition interference degree representing the ratio of the pore recognition rate of the specified batch of ceramic insulating substrate samples at the end of the defect feature recognition period to the set pore recognition rate in the database, the pore recognition rate representing the ratio of the total number of pores recognized in the defect feature recognition period to the total number of set pores in the database, the total number of set pores being represented by the result of summing and averaging the total number of historical pores recognized in the historical defect feature recognition period in the database, the set crack recognition interference degree and the set pore recognition interference degree being respectively represented by the result of summing and averaging the historical crack recognition interference degree and the historical pore recognition interference degree at the end of the historical defect feature recognition period in the database, the set crack recognition rate and the set pore recognition rate being respectively represented by the result of summing and averaging the historical crack recognition rate and the historical pore recognition rate at the end of the historical defect feature recognition period in the database; the harmonic mean of the obtained crack recognition interference score and the pore recognition interference score is recorded as the defect recognition interference degree value, which is used to quantify the interference degree of the crack recognition interference degree and the pore recognition interference degree on the defect recognition accuracy.

[0026] In this embodiment, cracks and pores often appear simultaneously in ceramic insulating substrates, and the recognition interference degrees of the two are related to each other. On the one hand, when the crack recognition interference degree is high, it means that the crack features in the image have low distinguishability from the background or other defects, which may cause the corresponding defect feature recognition algorithm to misjudge some pores as cracks in the recognition process, or ignore the pores due to excessive attention to crack features, resulting in an increase in the pore recognition interference degree. On the other hand, when the pore recognition interference degree is high, the existence of a large number of pores and their irregular shapes will interfere with the overall texture and structure of the image, making the boundaries of the cracks blurred, increasing the difficulty of crack recognition, and further increasing the crack recognition interference degree. In addition, if the pores are distributed near the cracks, the two will block or fuse each other, simultaneously increasing the recognition interference degrees of the two defects.

[0027] This method accurately quantifies the degree of interference in defect feature recognition under thermal conductivity conditions. By calculating the identification interference scores for cracks and pores separately and taking the harmonic mean, it comprehensively considers the identification of both major defects, avoiding the one-sidedness of single-defect identification interference assessment. By clarifying the mutual influence of crack and pore identification interference, it facilitates in-depth analysis of the causes of interference, helping to improve the accuracy of defect recognition in ceramic insulating substrates under thermal conductivity conditions, ensuring product quality, reducing defective rates, and enhancing companies' market competitiveness.

[0028] like Figure 2 The figure below shows a flowchart for defect feature identification and first production parameter optimization and determination, according to an embodiment of the present invention. The specific design logic is as follows: first, an internal structure image is acquired to quantify the degree of interference with defect feature identification (cracks and pores) under thermal conductivity conditions. By comparing this with the set value, a determination is made as to whether to optimize the first production parameter. If interference is significant, optimization is performed, including adjusting the sintering aid dosage and testing thermal cycle stability. If interference is minimal, the process proceeds to feature point extraction. The "1" at the beginning of the flowchart indicates that this is the first step in the entire ceramic circuit board production parameter optimization process, namely, acquiring an internal structure image. The "2" at the end indicates that after this step, the process proceeds to the second step, acquiring a temperature distribution image.

[0029] What needs to be further understood is that the determination of whether to perform the first production parameter optimization is specifically as follows: if the obtained defect recognition interference level value meets the first judgment condition, it is recorded as defect recognition failure and the first production parameter optimization is performed. The first judgment condition indicates that the obtained defect recognition interference level value is greater than the defect recognition interference level value set in the database. The set defect recognition interference level value is represented by the sum and average of the historical defect recognition interference level values ​​at the end of the historical defect feature recognition period in the database; if the obtained defect recognition interference level value meets the second judgment condition, it is recorded as defect recognition qualification and feature point extraction is performed. The second judgment condition indicates that the obtained defect recognition interference level value is not greater than the defect recognition interference level value set in the database; the first production parameter optimization includes sintering aid dosage adjustment direction determination, sintering aid dosage adjustment and thermal cycle stability test.

[0030] The sintering aid amount adjustment direction is determined as follows: the sintering aid amount of the ceramic insulating substrate sample of the specified batch at the end of the defect feature identification period is obtained, if the obtained sintering aid amount is greater than the sintering aid amount set in the database, it is determined that the sintering aid amount is reduced, and the sintering aid amount set in the database is represented by the sum average of the historical sintering aid amount at the end of the historical defect feature identification period in the database; if the obtained sintering aid amount is less than the sintering aid amount set in the database, it is determined that the sintering aid amount is increased; if the obtained sintering aid amount is equal to the sintering aid amount set in the database, the current sintering aid amount is maintained.

[0031] The sintering aid amount adjustment is as follows: based on the deviation of the obtained defect identification interference degree value, the sintering aid proportion adjustment value is obtained by mapping in the database, and the PID controller is prompted to dynamically adjust the sintering aid proportion based on the obtained sintering aid proportion adjustment value to reduce thermal stress concentration. When the PID (Proportional-Integral-Derivative) controller dynamically adjusts the sintering aid proportion, the sintering aid proportion adjustment value is first determined according to the defect identification interference degree value deviation, which represents the difference between the obtained defect identification interference degree value and the set defect identification interference degree value. The defect identification interference degree value deviation represents the difference between the obtained defect identification interference degree value and the set defect identification interference degree value. The proportional element quickly changes the sintering aid addition amount according to the adjustment value proportion. The integral element accumulates past deviations to eliminate steady-state errors and make adjustments more accurate. The derivative element predicts the trend of the deviation to make adjustments in advance and avoid overshooting. The three work together to enable the PID controller to dynamically adjust the sintering aid proportion in real time and accurately.

[0032] Thermal cycle stability test: after adjusting the sintering aid proportion, monitor whether the corresponding thermal expansion coefficient deviation is not greater than the thermal expansion coefficient deviation set in the database (usually, the set thermal expansion coefficient deviation is ), the thermal expansion coefficient deviation represents the absolute value of the difference between the thermal expansion coefficient of the specified ceramic substrate sample in the ceramic circuit board and the thermal expansion coefficient of the corresponding heat-generating electronic component. If the obtained thermal expansion coefficient deviation is not greater than the thermal expansion coefficient deviation set in the database, the ceramic insulating substrate sample after sintering aid proportion adjustment is obtained, and a preset number of thermal cycle tests are performed at different thermal cycle test temperature points (-20℃ to 80℃), the thermal cycle test time at different thermal cycle test temperature points is the same, to simulate the thermal stress impact of the specified ceramic substrate sample under different heat conduction conditions. After the thermal cycle test is completed, if the re-obtained defect identification interference degree value is greater than the defect identification interference degree value set in the database, a first production parameter warning is performed, otherwise the first production parameter optimization is completed and the feature point extraction is performed.

[0033] In the embodiment, if the obtained thermal expansion coefficient deviation is greater than the thermal expansion coefficient deviation set in the database, a thermal expansion warning is performed, indicating that the corresponding specified ceramic substrate sample has a risk of cracking or delamination under thermal stress, at which time the preset personnel need to be prompted to suspend production and check the sintering aid formula and the sintering process flow; the example accurately determines whether to perform first production parameter optimization, effectively improving the production quality of the ceramic insulating substrate, and according to the comparison between the defect recognition interference degree value and the set value, it is clear whether to optimize the production parameters, avoiding blind adjustment. In the sintering aid dosage adjustment direction determination, according to the comparison between the actual dosage and the set value, the adjustment direction is accurately determined, laying a foundation for subsequent accurate adjustment. The PID controller dynamically adjusts the sintering aid proportion, combining the advantages of proportional, integral and differential links, which can accurately control the sintering aid dosage in real time, reducing thermal stress concentration. The thermal cycle stability test simulates the thermal stress impact under actual heat conduction conditions to ensure that the adjusted parameters can meet the requirements of different working conditions, fully guaranteeing the quality stability and production reliability of the ceramic insulating substrate.

[0034] Further, the interference degree of the temperature positioning difference data to the feature point extraction of the temperature distribution image is quantified, specifically including: obtaining the temperature positioning difference data of the specified batch of ceramic insulating substrate samples at the end of the feature point extraction period based on the temperature distribution image, the temperature positioning difference data including the conductive line inflection point coordinate deviation and the temperature extreme point temperature deviation, the conductive line inflection point coordinate deviation being the Euclidean distance between the horizontal coordinate deviation and the vertical coordinate deviation of the conductive line inflection point in the temperature distribution image, and the temperature extreme point temperature deviation being the absolute value of the difference between the temperature extreme point of the corresponding conductive line in the temperature distribution image and the reference temperature set in the database (set by the manufacturer of the ceramic circuit board based on the historical conductive line temperature summed and averaged at the end of the historical feature point extraction period in the database), the conductive line inflection point being the point where the temperature gradient changes, such as the position on the conductive line corresponding to the turning point from heating to cooling; the harmonic mean of the conductive line inflection point coordinate deviation and the temperature extreme point temperature deviation is recorded as the feature point extraction interference degree value, which represents the interference degree of the temperature positioning difference data to the feature point recognition accuracy.

[0035] In the embodiment, the greater the conductive line inflection point coordinate deviation, the more obvious the difference between the position of the conductive line in the temperature distribution image and the standard position, which may cause the position of the temperature extreme point to shift, thereby affecting the accuracy of the temperature extreme point temperature deviation. Conversely, when the temperature extreme point temperature deviation increases, it may reflect that the temperature distribution is abnormal, which will also interfere with the accurate judgment of the conductive line inflection point coordinate, because the temperature anomaly may change the physical properties of the conductive line, leading to inaccurate measurement of the inflection point position. The two are interrelated and jointly affect the accuracy of feature point extraction.

[0036] The example comprehensively considers the inflection point coordinate deviation of the conductive circuit and the temperature extreme point temperature deviation, takes the mean value as a feature point extraction interference degree value, comprehensively and accurately quantifies the interference degree of feature point extraction, which helps to accurately evaluate the quality of feature point extraction of the temperature distribution image, provides a reliable basis for subsequent production parameter optimization, based on the interference degree value, problems existing in the feature point extraction process can be found in time, production parameters are adjusted in a targeted manner, the production quality of the ceramic insulating substrate is improved, and product defects caused by inaccurate feature point extraction are reduced.

[0037] As Figure 3 shown, the flowchart of feature point extraction and second production parameter optimization and determination provided by the embodiment of the application, the specific design logic is: after the defect recognition is qualified, the temperature distribution image is obtained and the interference degree of feature point extraction (explicit and implicit) is quantified, whether to perform second production parameter optimization is determined according to the interference degree, if the interference is large, the circuit copper foil thickness is adjusted and the feature point coordinates are verified to ensure the accuracy of feature point extraction; if the interference is small, temperature defect matching is performed. "2" in the flowchart represents the end of step 1, and "3" at the end represents that after the completion of this step, the process enters the third step, that is, the feature point temperature is obtained.

[0038] It is further understood that whether to perform second production parameter optimization is determined by: if the obtained feature point extraction interference degree value is greater than the set feature point extraction interference degree value in the database, it is recorded as unqualified feature point extraction and second production parameter optimization is performed, otherwise it is recorded as qualified feature point extraction and temperature defect matching is performed, the set feature point extraction interference degree value is represented by the result of summing and averaging the historical feature point extraction interference degree values at the end of the historical feature point extraction period in the database, and the second production parameter optimization includes circuit copper foil thickness adjustment and feature point coordinate verification.

[0039] Among them, the circuit copper foil thickness adjustment: based on the deviation of the obtained feature point extraction interference degree value, the circuit copper foil thickness adjustment value is obtained by mapping in the database, the PID controller is prompted to dynamically adjust the circuit copper foil thickness based on the obtained circuit copper foil thickness adjustment value, so as to reduce the interference of the heat of the conductive circuit on the temperature distribution state, and then reduce the temperature sudden change point caused by heat flow concentration, and reduce the extraction error of the hidden feature point.

[0040] Feature point coordinate verification: obtain the temperature field in the corresponding temperature distribution image after adjusting the thickness of the circuit copper foil, and obtain the coordinate deviation of the explicit feature point and the temperature deviation of the implicit feature point. If the obtained explicit feature point coordinate deviation is not greater than the set explicit feature point coordinate deviation in the database (usually set to 0.05mm), and the obtained implicit feature point temperature deviation is not greater than the set implicit feature point temperature deviation in the database (usually set to 3℃), the second production parameter optimization is completed and temperature defect matching is performed. Otherwise, the second production parameter warning is performed. The explicit feature point coordinate deviation is the Euclidean distance between the horizontal coordinate deviation and the vertical coordinate deviation corresponding to the explicit feature point in the temperature distribution image. The implicit feature point coordinate deviation is the Euclidean distance between the horizontal coordinate deviation and the vertical coordinate deviation corresponding to the implicit feature point in the temperature distribution image.

[0041] In this embodiment, the proportional element of the PID controller outputs the corresponding circuit copper foil thickness adjustment amount according to the current feature point extraction disturbance degree value deviation at a fast rate, which can quickly reduce the deviation, but is prone to overshoot. The integral element accumulates historical deviation to eliminate static error, and the differential element predicts the deviation trend to adjust the output in advance to suppress overshoot. The PID controller synthesizes the outputs of the three elements to obtain an accurate control amount, which is fed back to the actuator in real time to dynamically change the circuit copper foil thickness, reduce the heat disturbance of the conductive circuit, and reduce the temperature sudden change point.

[0042] This example can reduce the interference of the heat of the conductive circuit on the temperature distribution and improve the accuracy of feature point extraction through dynamic adjustment of the PID controller. The feature point coordinate verification uses Euclidean distance to accurately calculate the explicit and implicit feature point deviation, and strictly controls the accuracy of the feature point position and temperature in a quantitative manner. Only when the explicit feature point coordinate deviation and the implicit feature point temperature deviation both meet the set threshold value, the optimization is determined to be successful. The combination of the two effectively improves the quality and stability of feature point extraction in the production process, providing reliable protection for subsequent processes.

[0043] Further, the specific acquisition process of the thermal abnormal area is as follows: obtaining the temperature extreme point positioned in the temperature distribution image, inputting the image pixel value in the temperature distribution image and the obtained feature point temperature into the database (which stores the mapping data set between the historical image pixel value in the temperature distribution image and the corresponding historical feature point temperature), obtaining the corresponding actual temperature value based on the mapping relationship between the image pixel value and the feature point temperature; inputting the obtained actual temperature value as the temperature boundary condition into the constructed three-dimensional thermal structure model of the ceramic circuit board, and combining the built-in temperature field to generate a spatial temperature gradient field, so as to screen out the area exceeding the actual temperature value and record it as the thermal abnormal area.

[0044] In the embodiment, the actual temperature value is obtained by locating the temperature extreme point and using the database mapping relationship, which provides accurate data basis for subsequent analysis and avoids errors that may be caused by simply relying on image pixel values. The actual temperature value is input into the three-dimensional thermal structure model to generate a spatial temperature gradient field to screen the thermal anomaly area, which can comprehensively consider the heat conduction characteristics of the ceramic circuit board, accurately locate the thermal anomaly position from the three-dimensional space, and is more comprehensive and accurate than the traditional method. This not only helps to discover potential thermal faults of the ceramic circuit board in time, but also improves product quality and production safety, and reduces failure rate and loss caused by thermal anomalies.

[0045] Further, the degree of coincidence between the thermal anomaly area and the thermal resistance defect of the heat-generating electronic component is quantified, specifically including: based on the intersection between the obtained thermal anomaly area and the set thermal anomaly area in the database, a first thermal anomaly area is obtained, and based on the union between the obtained thermal anomaly area and the set thermal anomaly area in the database, a second thermal anomaly area is obtained; the ratio operation result of the obtained first thermal anomaly area and the second thermal anomaly area is recorded as a temperature positioning coincidence rate, that is, the ratio of the obtained first thermal anomaly area and the second thermal anomaly area, and the temperature positioning coincidence rate is used to quantify the spatial overlap degree between the actual thermal anomaly in the temperature distribution image and the position of the heat-generating electronic component.

[0046] In the embodiment, the first thermal anomaly area (intersection area) and the second thermal anomaly area (union area) are related to each other. When the coincidence degree between the actual thermal anomaly area and the set thermal anomaly area of the heat-generating electronic component is higher, the intersection area is closer to the union area, that is, the ratio (temperature positioning coincidence rate) of the two tends to 1; on the contrary, if the coincidence degree is low, the intersection area is small, and the union area is greatly affected by the non-coincidence part, and the ratio will be significantly reduced. Both of them reflect the spatial coincidence of the actual and expected thermal anomaly areas.

[0047] This quantitative method can accurately measure the degree of coincidence between the thermal anomaly area and the thermal resistance defect of the heat-generating electronic component, and provide a quantitative basis for fault positioning. If the coincidence rate is low, it indicates that the local heat flow is blocked, that is, there is a thermal resistance defect, and the position corresponds to the thermal field anomaly area, thereby realizing rapid positioning of the defect, and improving the accuracy and efficiency of fault diagnosis, which helps to take measures to repair in time and ensure stable operation of the equipment.

[0048] As Figure 4As shown, the flow chart of the coincidence quantification and third production parameter optimization and determination provided by the embodiment of the application, the specific design logic is: after the feature point extraction is qualified, the feature point temperature is obtained and input into the model to obtain the thermal anomaly area through temperature defect matching, the coincidence degree of the thermal anomaly area and the heating electronic component thermal resistance defect is quantified, and it is judged whether to perform the third production parameter optimization according to the coincidence degree. If the coincidence degree is low, the temperature parameters (molding pressure and sintering cooling speed) are adjusted and the material thermal resistance parameters are updated until the requirements are met and the next production stage is entered. The "3" in the flow chart represents the end of step 2, and after completing this step, it means that the production parameter optimization process of the entire trial production stage is completed.

[0049] It is further understood that the judgment of whether to perform the third production parameter optimization is specifically: judging whether the obtained temperature positioning coincidence rate is greater than the temperature positioning coincidence rate set in the database (usually set to 60%), if yes, it is recorded as temperature positioning unqualified and the third production parameter optimization is performed, otherwise it is recorded as temperature positioning qualified and the production parameter optimization of the next ceramic circuit board trial production stage is performed; the third production parameter optimization includes temperature parameter adjustment and material thermal resistance parameter update, and the material thermal resistance parameter update means that the effectiveness of the temperature parameter adjustment is verified through the automatic updating process of the three-dimensional thermal structure model of the ceramic circuit board.

[0050] Among them, the temperature parameter adjustment is specifically: based on the temperature positioning coincidence rate deviation obtained in the database, the molding pressure adjustment value and the sintering cooling speed adjustment value are obtained, and the PID controller is prompted to dynamically adjust the molding pressure and the sintering cooling speed based on the obtained molding pressure adjustment value and the sintering cooling speed adjustment value, so as to reduce the volume fraction of pores while reducing the crack propagation caused by thermal stress concentration.

[0051] The material thermal resistance parameter update is specifically: the molding pressure and the sintering cooling speed after the temperature parameter adjustment are jointly input into the three-dimensional thermal structure model of the ceramic circuit board, and it is judged whether the obtained thermal anomaly area temperature drop amplitude is greater than the thermal anomaly area temperature drop amplitude set in the database (usually set to 10℃), if yes, the material thermal resistance parameter update is continued for a preset number of times (usually set to 3 times), until the obtained temperature positioning coincidence rate is not greater than the temperature positioning coincidence rate set in the database, the third production parameter optimization is completed, and the production parameter optimization of the next ceramic circuit board trial production stage is performed, otherwise the third production parameter warning is performed.

[0052] It needs to be understood that a three-dimensional geometric model of the ceramic circuit board is constructed using computer-aided design (CAD) software: accurately depicting the layer structure (ceramic insulating substrate, conductive circuit layer, solder mask layer, etc.), wherein the size error of the ceramic insulating substrate is controlled within ±0.01 mm; the width, thickness and distribution path of the conductive circuit (copper layer or silver paste circuit) are labeled, and the position coordinates and size (length x width x height) of the heat-generating electronic components (such as chips, resistors) are labeled; the spatial coordinate system parameters of the model are retained to provide a reference for subsequent feature matching.

[0053] Thermal conduction model parameter input: import the geometric model in the computer-aided engineering (CAE) software, input key parameters: ceramic insulating substrate (based on the defect sample detected in step one, correct the thermal conductivity coefficient, such as the effective thermal conductivity coefficient of the air hole substrate according to the air hole volume ratio), conductive circuit (the thermal conductivity coefficient of copper is about 401 W / (m·K)), specific heat capacity of heat-generating electronic components; set the heat dissipation environment (such as the heat transfer coefficient of natural convection or forced air cooling), initial temperature (room temperature 25℃); input the heat power distribution of components (such as the power density of chips, uniform or non-uniform heating area), simulate the thermal behavior under different workloads (such as 20%, 50%, 100% load).

[0054] Temperature field simulation and three-dimensional thermal structure model output: run the thermal conduction simulation block of the CAE software to get the three-dimensional temperature field distribution under different loads, generate a three-dimensional thermal structure model containing temperature gradient and heat flux density vector, i.e. a three-dimensional thermal structure model of the ceramic circuit board, and export the coordinates and temperature data of the feature points in the model (such as the temperature values of the component center, the circuit intersection point, and the substrate corner).

[0055] In this embodiment, the PID controller adjusts the forming pressure and sintering cooling rate according to the obtained forming pressure adjustment value and sintering cooling rate adjustment value, and quickly and accurately increases or decreases the forming pressure according to the proportional, differential and integral algorithm, optimizes the material density, and dynamically adjusts the cooling rate to avoid excessive cooling and thermal stress concentration. This example uses temperature positioning coincidence rate as the key indicator to determine whether to perform the third production parameter optimization, which can accurately position the matching problem of temperature distribution and heat-generating components, avoid unnecessary optimization process, improve production efficiency; material thermal resistance parameter updating combined with three-dimensional thermal structure model, with heat abnormal area temperature drop amplitude as verification standard, through multiple updates to ensure parameter optimization effective, guarantee production stability, reduce product defects.

[0056] The embodiment of the present application provides a ceramic circuit board production parameter optimization device, which comprises an industrial computed tomography (CT, Computed Tomography) instrument, a material metering sensor, an infrared thermal imager, an infrared temperature sensor, a laser positioning instrument and a PID controller; the industrial CT scanner is used for acquiring internal structure images, thermal anomaly areas, crack recognition rates and porosity recognition rates; the material metering sensor is used for acquiring sintering aid amounts; the infrared thermal imager is used for acquiring temperature distribution images, thermal anomaly area areas and temperature fields; the infrared temperature sensor is used for acquiring feature point temperatures, temperature extreme points and actual temperature values; the laser positioning instrument is used for acquiring horizontal coordinate deviations and vertical coordinate deviations; and the PID controller is used for dynamically regulating and controlling sintering aid proportions, circuit copper foil thicknesses, forming pressures and sintering cooling speeds. The devices and the memory are connected through hardware interfaces (such as Ethernet, USB, RS-485), the industrial CT scanner and the like are converted into data formats through special adapters, are encapsulated after a data protocol layer, are stored in corresponding memories (volatile real-time data and nonvolatile historical data) according to priorities, and indexes are established to facilitate calling.

[0057] It should be noted that, as shown in Figure 5 The interface diagram homepage of the ceramic circuit board production optimization system provided by the embodiment of the present application is shown in the drawings. In the core data board area, the key production indexes of the current batch "A005" are displayed, such as that the defect recognition rate is as high as 95%, the temperature positioning coincidence rate is 82%, and the production state is displayed as trial production, so that the user can quickly master the production overview; the defect recognition analysis board can be clicked to view the latest batch of ceramic substrate defect data, helping to analyze product quality problems; the temperature field real-time monitoring can view the thermal diagram and the feature point, so as to facilitate the control of temperature changes in the production process; the three-dimensional model preview can view the thermal anomaly area matching state, assisting in optimizing the production process, and at the same time, facilitating the user to understand the production process. Through the intuitive data display and convenient function entrance of the system interface, the efficiency and accuracy of production management are effectively improved, and the optimization of ceramic circuit board production is facilitated.

[0058] As shown in Figure 6The figure shows the interface of the defect identification optimization section in the ceramic circuit board production optimization system provided by an embodiment of the present invention. The feature point analysis section displays temperature positioning difference data, clearly defining target values ​​and deviations, such as X deviation of 0.12mm and Y deviation of 0.09mm. It also displays temperature extreme point differences and feature extraction interference values, providing data support for precise adjustment. The thermal resistance matching analysis area shows a temperature positioning overlap rate of 72% and a target overlap rate of ≥85%. It also provides temperature and temperature trend charts in the thermal anomaly area, making it easier to understand the dynamics of temperature changes. The parameter adjustment section can adjust the thickness of the circuit copper foil, with a clear comparison between the set target value and the current value. The recommended optimization direction clearly provides adjustment suggestions for the forming pressure and sintering cooling rate, and can also generate a detailed optimization plan. The overall interface helps to accurately control the temperature field distribution and improve the quality and efficiency of ceramic circuit board production.

[0059] like Figure 7 The figure shows the interface of the temperature field distribution optimization section in the ceramic circuit board production optimization system provided by an embodiment of the present invention. The image viewing section provides the function of viewing industrial CT scan images and substrate internal structure images, providing an intuitive basis for defect identification. The data monitoring section displays key indicators such as crack recognition rate and pore recognition rate in real time, as well as parameters such as interference threshold and thermal expansion value deviation, allowing users to fully understand the production status. The operation control area can accurately control the adjustment of sintering aids, set target values ​​and display current values, making it easy to adjust production parameters. The status warning can promptly remind the remaining number of thermal cycle tests and sintering aid adjustment suggestions, ensuring production stability and data reliability. The historical data record details the batch number, date, and various recognition rate data for easy traceability and analysis. The overall interface effectively improves the efficiency and accuracy of defect identification, helping to optimize the ceramic circuit board production process.

[0060] The above-described embodiments can be implemented in part or in whole through software, hardware (e.g., circuitry), firmware, or any combination thereof. When implemented in software, the above-described embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When loaded and executed by a computer, the computer instructions or computer programs can produce the flow or function described above in accordance with the embodiments of the present application. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable apparatus. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, such as from a website, a computer, a server, or a data center to another website, computer, server, or data center through a wired (e.g., infrared, wireless, microwave, or the like) manner. The computer-readable storage medium can be any available medium or a collection of medium accessible by a computer or a data storage device such as a server, data center, or the like, which includes one or more medium. The medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state hard disk.

[0061] It should be understood that the term "and / or" in this document is merely used to describe associated objects, and can represent three conditions: A and / or B, which can mean that A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. In addition, the character " / " in this document generally represents an "or" relationship between the associated objects, but can also represent an "and / or" relationship. The specific meaning can be understood according to the context before and after.

[0062] It should be understood that in various embodiments of the present application, the size of the sequence number of each process does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0063] Those of ordinary skill in the art can realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be realized in electronic hardware, or a combination of computer software and electronic hardware. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. A person skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0064] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the devices, apparatuses and units described above can refer to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0065] In several embodiments provided by the present application, it should be understood that the disclosed devices, apparatuses and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, another division mode can be used. For example, a plurality of units or components can be combined or integrated into another device, or some features can be omitted or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical, mechanical or other forms.

[0066] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., can be located in one place or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0067] In addition, each functional unit in each embodiment of the present application can be integrated into a processing unit, or each unit can exist physically independently, or two or more units can be integrated into one unit.

[0068] If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application or the parts of the technical solutions that essentially contribute to the prior art can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various program code storage media.

[0069] The above merely illustrates the specific embodiments of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for optimizing production parameters of ceramic circuit boards, characterized in that: The method comprises: Step 1: During the trial production phase of ceramic circuit boards, internal structure images of a specified batch of ceramic insulating substrate samples are obtained, and the degree of interference in defect feature recognition of the specified batch of ceramic insulating substrate samples under thermal conductivity conditions is quantified to determine whether to perform first production parameter optimization. The defect feature recognition includes crack recognition and pore recognition. The first production parameter optimization is used to improve the recognition rate of cracks and pores in the specified batch of ceramic insulating substrate samples under thermal conductivity conditions. Step 2: Obtain a temperature distribution image of a specified batch of ceramic insulating substrate samples after qualified defect identification, and quantify the degree to which the temperature positioning difference data interferes with feature point extraction from the temperature distribution image to determine whether to perform a second production parameter optimization. The feature point extraction includes explicit feature point extraction and implicit feature point extraction. The second production parameter optimization is used to reduce the degree to which the heat of the conductive circuit interferes with the efficiency of feature point extraction. Step three, obtain the corresponding feature point temperature after the feature point extraction is qualified, and input it into the temperature field in the constructed three-dimensional thermal structure model of the ceramic circuit board for temperature defect matching to obtain the thermal anomaly area, and at the same time quantify the overlap between the thermal anomaly area and the thermal resistance defect of the heat-generating electronic component to determine whether to perform the third production parameter optimization. The third production parameter optimization is used to improve the temperature position positioning accuracy of the three-dimensional thermal structure model of the ceramic circuit board.

2. A method for optimizing production parameters of a ceramic circuit board according to claim 1, characterized in that: The quantification of the interference degree of defect feature identification of a specified batch of ceramic insulating substrate samples under thermal conductivity conditions specifically includes: Based on the internal structure image, the crack identification interference degree and the pore identification interference degree of the specified batch of ceramic insulating substrate samples at the end of the defect feature identification period are obtained, and the set crack identification interference degree and the pore identification interference degree are simultaneously obtained from the database. The interference degree ratio calculation is performed respectively to obtain the crack identification interference score and the pore identification interference score; The harmonic mean of the obtained crack identification interference score and the pore identification interference score is recorded as the defect identification interference degree value, which is used to quantify the interference degree of the crack identification interference degree and the pore identification interference degree on the defect identification accuracy.

3. A method for optimizing production parameters of a ceramic circuit board according to claim 2, characterized in that: The determination of whether to perform the first production parameter optimization is specifically as follows: If the obtained defect recognition interference level value meets the first determination condition, it is recorded as defect recognition failure and the first production parameter optimization is performed, wherein the first determination condition indicates that the obtained defect recognition interference level value is greater than the defect recognition interference level value set in the database; If the obtained defect recognition interference level value meets the second determination condition, the defect recognition is deemed qualified and feature point extraction is performed. The second determination condition indicates that the obtained defect recognition interference level value is not greater than the defect recognition interference level value set in the database. The first production parameter optimization includes determining the direction of sintering aid dosage adjustment, adjusting the sintering aid dosage, and thermal cycle stability testing; The sintering aid dosage adjustment direction is determined as follows: the sintering aid dosage of a specified batch of ceramic insulating substrate samples at the end of the defect feature recognition period is obtained; if the obtained sintering aid dosage is greater than the sintering aid dosage set in the database, it is determined that the sintering aid dosage is reduced; if the obtained sintering aid dosage is less than the sintering aid dosage set in the database, it is determined that the sintering aid dosage is increased; if the obtained sintering aid dosage is equal to the sintering aid dosage set in the database, the current sintering aid dosage is maintained.

4. A method for optimizing production parameters of a ceramic circuit board according to claim 3, characterized in that: The sintering aid dosage adjustment means mapping the obtained defect recognition interference degree value deviation in the database to obtain a sintering aid ratio adjustment value, and prompting the PID controller to dynamically adjust the sintering aid ratio based on the obtained sintering aid ratio adjustment value; The thermal cycling stability test is specifically as follows: After the sintering aid ratio is adjusted, monitoring whether the corresponding thermal expansion coefficient deviation is no greater than the thermal expansion coefficient deviation set in the database; if the obtained thermal expansion coefficient deviation is no greater than the thermal expansion coefficient deviation set in the database, obtaining a ceramic insulating substrate sample with the sintering aid ratio adjusted, and performing a preset number of thermal cycle tests at different thermal cycle test temperature points to simulate thermal stress shock of the specified ceramic substrate sample under different thermal conductivity conditions; After the thermal cycle test is completed, if the re-acquired defect recognition interference level value is greater than the defect recognition interference level value set in the database, a first production parameter warning is issued; otherwise, the first production parameter optimization is completed and feature point extraction is performed.

5. A method for optimizing production parameters of a ceramic circuit board according to claim 1, characterized in that: The interference degree of the quantized temperature location difference data on the feature point extraction of the temperature distribution image specifically includes: Acquire temperature location difference data of a specified batch of ceramic insulating substrate samples at the end of a feature point extraction period based on the temperature distribution image, the temperature location difference data including a coordinate deviation of a conductive circuit inflection point and a temperature deviation of a temperature extreme point, the coordinate deviation of the conductive circuit inflection point being the Euclidean distance between a horizontal coordinate deviation and a vertical coordinate deviation of the conductive circuit inflection point in the temperature distribution image, and the temperature deviation of the temperature extreme point being the absolute value of a difference between a temperature extreme point of the corresponding conductive circuit in the temperature distribution image and a reference temperature set in a database; The harmonic mean of the coordinate deviation of the conductive line inflection point and the temperature deviation of the temperature extreme point is recorded as the feature point extraction interference degree value, which represents the interference degree of the temperature positioning difference data on the feature point recognition accuracy.

6. A method for optimizing production parameters of a ceramic circuit board according to claim 5, characterized in that: The determination of whether to perform the second production parameter optimization is specifically as follows: If the obtained feature point extraction interference degree value is greater than the feature point extraction interference degree value set in the database, it is recorded as unqualified feature point extraction and the second production parameter optimization is performed; otherwise, it is recorded as qualified feature point extraction and temperature defect matching is performed; The second production parameter optimization includes: The first step is to adjust the copper foil thickness of the circuit: Based on the obtained feature points, the interference degree value deviation is extracted and mapped into the database to obtain the circuit copper foil thickness adjustment value. The PID controller is prompted to dynamically adjust the circuit copper foil thickness based on the obtained circuit copper foil thickness adjustment value to reduce the interference of the conductive circuit heat on the temperature distribution state. The second step is to verify the coordinates of the feature points: obtain the temperature field in the temperature distribution image corresponding to the circuit copper foil thickness adjustment, and at the same time obtain the explicit feature point coordinate deviation and the implicit feature point temperature deviation. If the obtained explicit feature point coordinate deviation is not greater than the explicit feature point coordinate deviation set in the database, and the obtained implicit feature point temperature deviation is not greater than the implicit feature point temperature deviation set in the database, then the second production parameter optimization is completed and temperature defect matching is performed, otherwise a second production parameter warning is issued.

7. A method for optimizing production parameters of a ceramic circuit board according to claim 1, characterized in that: The specific process of obtaining the thermal anomaly area is as follows: Obtain the located temperature extreme points in the temperature distribution image, input the image pixel values ​​in the temperature distribution image and the obtained characteristic point temperatures into the database, and obtain the corresponding actual temperature values ​​based on the mapping relationship between the image pixel values ​​and the characteristic point temperatures; The actual temperature value obtained is input as the temperature boundary condition into the constructed three-dimensional thermal structure model of the ceramic circuit board. At the same time, the spatial temperature gradient field is generated by combining the built-in temperature field to screen out the areas corresponding to the actual temperature value and record them as thermal anomaly areas; The quantitative overlap between the thermal anomaly area and the thermal resistance defect of the heat-generating electronic component specifically includes: Based on the intersection of the acquired thermal anomaly region and the thermal anomaly region set in the database, the area of ​​the first thermal anomaly region is obtained; and based on the union of the acquired thermal anomaly region and the thermal anomaly region set in the database, the area of ​​the second thermal anomaly region is obtained. The obtained ratio calculation result of the first thermal anomaly area and the second thermal anomaly area is recorded as the temperature positioning coincidence rate, which is used to quantify the degree of spatial overlap between the actual thermal anomaly in the temperature distribution image and the position of the heat-generating electronic component.

8. A method for optimizing production parameters of a ceramic circuit board according to claim 7, characterized in that: The determination of whether to perform the third production parameter optimization is specifically as follows: Determine whether the obtained temperature positioning coincidence rate is greater than the temperature positioning coincidence rate set in the database. If so, record the temperature positioning as unqualified and perform the third production parameter optimization. Otherwise, record the temperature positioning as qualified and perform the production parameter optimization of the next ceramic circuit board trial production stage. The third production parameter optimization includes temperature parameter adjustment and material thermal resistance parameter update. The temperature parameter adjustment is specifically as follows: mapping the obtained temperature positioning coincidence rate deviation in a database to obtain a molding pressure adjustment value and a sintering temperature drop rate adjustment value, prompting a PID controller to dynamically adjust the molding pressure and the sintering temperature drop rate based on the obtained molding pressure adjustment value and the sintering temperature drop rate adjustment value; The material thermal resistance parameter update represents an automatic update process of the three-dimensional thermal structure model of the ceramic circuit board to verify the effectiveness of the temperature parameter adjustment.

9. A method for optimizing production parameters of a ceramic circuit board according to claim 8, characterized in that: The material thermal resistance parameters are updated as follows: The molding pressure and sintering cooling rate corresponding to the temperature parameters after adjustment are input into the three-dimensional thermal structure model of the ceramic circuit board. At the same time, it is determined whether the temperature drop in the thermal abnormality area is greater than the temperature drop in the thermal abnormality area set in the database. If so, the material thermal resistance parameters are updated for a preset number of times until the obtained temperature positioning overlap rate is no greater than the temperature positioning overlap rate set in the database. The third production parameter optimization is completed and the production parameter optimization of the next ceramic circuit board trial production stage is carried out. Otherwise, a third production parameter warning is issued.

10. A device for optimizing production parameters of a ceramic circuit board, applying the method for optimizing production parameters of a ceramic circuit board according to any one of claims 1 to 9, characterized in that: include: Industrial CT scanners, material measurement sensors, infrared thermal imagers, infrared temperature sensors, laser positioning devices and PID controllers; The industrial CT scanner is used to obtain images of internal structures and thermal anomaly areas; The material metering sensor is used to obtain the amount of sintering aid; The infrared thermal imager is used to obtain temperature distribution images, thermal anomaly area and temperature field; The infrared temperature sensor is used to obtain characteristic point temperature, temperature extreme point and actual temperature value; The laser locator is used to obtain the horizontal coordinate deviation and the vertical coordinate deviation; The PID controller is used to dynamically control the proportion of sintering aids, the thickness of the circuit copper foil, the forming pressure and the sintering cooling speed.

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