Through silicon via inspection circuit with replica path

Abstract

The invention relates to a through silicon via inspection circuit with replica paths. Disclosed herein is an apparatus comprising: a first semiconductor chip; a first TSV and a second TSV penetrating the first semiconductor chip; a first path including the first TSV; a second path including the second TSV; a first charging circuit configured to charge the first path; a second charging circuit configured to charge the second path; a first discharge circuit configured to discharge the first path; a second discharge circuit configured to discharge the second path; and a comparator circuit configured to compare a potential of the first path with a potential of the second path.

Description

[0001] Related application information of division

[0002] This application is a divisional application. The parent application of this divisional application is the invention patent application with application number 202010952553.2 and application date September 11, 2020, entitled “TSV inspection circuit with replication path”. TECHNICAL FIELD

[0003] The present application relates to memory devices, and in particular to a TSV inspection circuit with replication path in a memory device. BACKGROUND

[0004] Semiconductor chips for use in memory devices, such as HBM (high bandwidth memory), include several TSVs (through-silicon vias), each of which is arranged to penetrate a semiconductor substrate in some cases. The TSVs arranged in each semiconductor chip are connected via micro bumps to the TSVs arranged at the same planar position in another semiconductor chip, so that a signal path penetrating several semiconductor substrates is formed. If a particular TSV has a conduction fault or a connection portion between two TSVs has a connection fault, the corresponding signal path becomes defective and practically unusable. In this case, a spare signal path is used to replace the signal path with a fault, so that the fault is recovered. The verification of each signal path and the replacement with a spare signal path can be performed not only in the manufacturing stage but also in actual use, i.e., in the initialization period after power-on. In the case where the verification of the signal path is performed in the initialization period, the verification time that can be assigned to each signal path can be extremely short. Therefore, it is not easy to perform correct verification for all signal paths. SUMMARY

[0005] One aspect of the present application is directed to an apparatus comprising: a first semiconductor chip; a first TSV and a second TSV penetrating the first semiconductor chip; a first path including the first TSV; a second path including the second TSV; a first charging circuit configured to charge the first path; a second charging circuit configured to charge the second path; a first discharging circuit configured to discharge the first path; a second discharging circuit configured to discharge the second path; and a comparator circuit configured to compare a potential of the first path with a potential of the second path.

[0006] Another aspect of this application is directed to an apparatus comprising a plurality of first semiconductor chips stacked on top of one another, the plurality of first semiconductor chips including each by a first path and a second path of the plurality of first semiconductor chips; and an interface chip stacked on the plurality of first semiconductor chips such that the interface chip is coupled to each of first ends of the first path and the second path, the interface chip configured to control: charging each of second ends of the first path and the second path with a first voltage; and comparing a potential of the first ends of the first path and the second path after charging each of second ends of the first path and the second path with the first voltage.

[0007] Yet another aspect of this application is directed to an apparatus comprising: a semiconductor chip; a plurality of first TSVs penetrating the semiconductor chip; a second TSV penetrating the semiconductor chip; first circuitry configured to select one of the plurality of first TSVs; second circuitry configured to apply a first potential to the selected one of the first TSVs and the second TSV in response to a first timing signal; third circuitry configured to apply a second potential different from the first potential to the selected one of the first TSVs and the second TSV in response to a second timing signal; and fourth circuitry configured to compare a potential of the selected one of the first TSVs to a potential of the second TSV. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a schematic diagram showing a configuration of a semiconductor device according to the present application.

[0009] Figure 2 is a schematic plan view showing a layout of a plurality of TSVs.

[0010] Figure 3 is a circuit diagram showing circuitry connected to TSVs in a memory core chip.

[0011] Figure 4 is a circuit diagram showing circuitry connected to TSVs in an interface chip.

[0012] Figure 5 is a circuit diagram showing a first circuit instance of a verify signal path.

[0013] Figure 6 and Figure 7 is a timing diagram showing operation of the circuitry shown in Figure 5

[0014] Figure 8 is a circuit diagram showing a second circuit instance of a verify signal path.​

[0015] Figure 9 is a circuit diagram showing a third circuit example in which a signal path is checked.

[0016] Figure 10 is a circuit diagram showing a fourth circuit example in which a signal path is checked. DETAILED DESCRIPTION

[0017] Various embodiments of the present invention will be explained in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings, which illustrate specific aspects and embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0018] Figure 1The semiconductor device shown in FIG. 1 is an HBM having a configuration in which eight memory core chips 20 to 27 are stacked on an interface chip 10. However, the semiconductor device to which the present application is applicable is not limited to an HBM. The memory core chips 20 to 27 are each a semiconductor chip in which a memory core including an array of memory cells is integrated. The interface chip 10 is a semiconductor chip that controls the memory core chips 20 to 27. The interface chip 10 and the memory core chips 20 to 26 each have a plurality of TSVs 30 provided to penetrate the semiconductor substrate. All of the interface chip 10 and the memory core chips 20 to 27 are stacked in a face-down manner, that is, in a manner such that the main surface on which a pattern of transistors and wiring (neither shown) is formed faces downward. Therefore, in the memory core chip 27 located in the uppermost layer, the TSVs 30 are not needed. However, the memory core chip 27 located in the uppermost layer can have the TSVs 30. Almost all of the TSVs 30 provided in the memory core chips 20 to 26 are respectively connected to front surface TSV pads 31A located at the same planar position. Meanwhile, most of the TSVs 30 provided in the interface chip 10 and most of the front surface TSV pads 31A provided on the interface chip 10 exist at planar positions different from each other. Among the TSVs 30 provided in the interface chip 10 and the memory core chips 20 to 26, the TSVs 30 located at the same planar position are connected to each other in a cascade connection manner via the front surface TSV pads 31A, TSV bumps 31B, and rear surface TSV pads 31C. In this way, a plurality of signal paths 32 are formed. Commands and write data output from the interface chip 10 are supplied to the memory core chips 20 to 27 via the signal paths 32. Read data output from the memory core chips 20 to 27 is supplied to the interface chip 10 via the signal paths 32. External terminals 33 are provided on the interface chip 10 via which signal transmission to and signal reception from external circuits are performed.

[0019] As Figure 2 In each of the interface chip 10 and the memory core chips 20 to 26, the TSVs 30 are arranged in a matrix form as shown in FIG. 1. A selection circuit 34 is assigned to each TSV 30. The selection circuit 34 is used in inspection of the signal paths 32, which is performed in a manufacturing stage and in an initialization period after power is turned on. As Figure 2As shown in FIG, a corresponding one of the selection signal lines Y0, Y1, Y2, Y3, ... is assigned to the TSVs 30 arranged in the x-direction. A corresponding one of the selection signal lines X0, X1, X2, X3, ... is assigned to the TSVs 30 arranged in the y-direction. The selection signal lines Y0, Y1, Y2, Y3, ... respectively supply selection signals Ysel0, Ysel1, Ysel2, Ysel3, ... to the corresponding selection circuits 34. The selection signal lines X0, X1, X2, X3, ... respectively supply selection signals Xsel0, Xsel1, Xsel2, Xsel3, ... to the corresponding selection circuits 34. The selection circuit 12 activates any one of the selection signals Ysel0, Ysel1, Ysel2, Ysel3, ... and deactivates all the remaining signals. The selection circuit 14 activates any one of the selection signals Xsel0 , Xsel1 , Xsel2 , Xsel3 , ... and deactivates all the remaining signals. In this way, activating any one of the selection circuits 34 causes one of the TSVs 30 corresponding thereto to be selected.

[0020] Each selection circuit 34 included in each of the memory chips 20 to 27 includes a P-channel MOS transistor 41 and a NAND gate circuit 42 that controls the transistor 41, as shown in FIG. Figure 3 As shown in FIG. NAND gate circuit 42 receives a corresponding one of selection signals Xsel0, Xsel1, Xsel2, Xsel3, ..., a corresponding one of selection signals Ysel0, Ysel1, Ysel2, Ysel3, ..., and a selection signal SliceEn (which selects one of the memory core chips 20 to 27 that includes NAND gate circuit 42), and activates selection signal XYselF to a low level when all received signals are at an active level (high level). In each of memory core chips 20 to 27, P-channel MOS transistor 43 and P-channel MOS transistor 41 are connected in series between power supply VDD and TSV 30. A test signal TESTF is supplied to the gate electrode of transistor 43. Therefore, when both test signal TESTF and selection signal XYselF are activated to a low level, TSV 30 is connected to power supply VDD. For example, power supply VDD is a high-potential-side power supply. In this case, when both the test signal TESTF and the selection signal XYselF are activated, the signal path 32 is charged through the TSV 30 .

[0021] The selection circuit 34 included in the interface chip 10 has the same circuit configuration as the selection circuit 34 included in the memory core chips 20 to 27, such as Figure 4As shown in FIG. In the interface chip 10, transistor 41 and N-channel MOS transistor 47 are connected in series between TSV 30 and power supply VSS. A test clock signal CLK is supplied to the gate electrode of transistor 47. Therefore, when the test clock signal CLK is activated to a high level and the select signal XYselF is activated to a low level, TSV 30 is connected to power supply VSS. For example, power supply VSS is a low-potential power supply. In this case, when both the test clock signal CLK and the select signal XYselF are activated, signal path 32 is discharged through TSV 30.

[0022] like Figure 3 and 4 , an output buffer 45 and an input receiver 46 are connected in parallel between the internal circuit 44 and the TSVs 30 included in each of the interface chip 10 and the memory core chips 20 to 27. Therefore, data, commands, and the like output from the internal circuit 44 are supplied to the signal path 32 via the output buffer 45 and the TSVs 30. In addition, data, commands, and the like supplied from the signal path 32 are input to the internal circuit 44 via the TSVs 30 and the input receiver 46.

[0023] like Figure 5 As shown in FIG, a plurality of signal paths 32 include a replica path 32R. Replica path 32R serves as a reference for testing other signal paths 32 and has the same configuration as signal path 32, except that transistor 41 is replaced with transistor 48 for receiving enable signal EnF, and a dummy resistor Rd is inserted in series. Enable signal EnF is always activated during the test cycle. The parasitic capacitance C1 added to each signal path 32 and the parasitic capacitance C2 added to replica path 32R are designed to have substantially the same value. Each signal path 32 is connected to node N1 via transistor 41 provided on interface chip 10, and replica path 32R is connected to node N2 via transistor 48 provided on interface chip 10. Interface chip 10 includes a comparator circuit 49 that compares the voltage level at node N1 with the voltage level at node N2 in response to a comparison signal COMP.

[0024] refer to Figure 6 and 7 To describe Figure 5 The operation of the circuit shown in FIG. Figure 6 shows the waveforms for a case where there is no fault in each signal path 32, and Figure 7 The waveforms are shown in the case where there is a fault in a portion of the signal path 32. First, any one of the selection signals Xsel0, Xsel1, Xsel2, Xsel3, ... is selected (in Figure 6and 7 In the example shown in Fig. 6, the selection signal Xsel0) is activated into a state in which the selection signals Ysel0, Ysel1, Ysel2, Ysel3,... are sequentially activated into a high level. Thus, the TSVs 30 are sequentially selected as Figure 2 The TSVs 30 are arranged in a matrix form as shown in Fig. 6, and via the selected TSVs 30, a corresponding one of the signal paths 32 is charged. It is sufficient that the charging of the signal paths 32 is performed in any one of the memory core chips 20 to 27, and no charging in the other memory core chips is needed. The charging of each signal path 32 is preferably performed in the memory core chip 27 in the uppermost layer. By charging each signal path 32 in the memory core chip 27 in the uppermost layer, all TSVs 30 included in the signal path 32 can be tested. At the same time, in the case where there is a fault in the signal path 32, by charging each signal path 32 in any one of the memory core chips 20 to 26 which are not located in the uppermost layer, it is possible to specify which one of the memory core chips 20 to 26 includes a defective TSV 30. In the case where each signal path 32 is charged in the memory core chip 27 in the uppermost layer, it is sufficient that the selection signal SliceEn corresponding to the memory core chip 27 in the uppermost layer is activated into a high level and the selection signals SliceEn corresponding to the other memory core chips 20 to 26 are deactivated into a low level. Also for the interface chip 10, the corresponding selection signal SliceEn is activated into a high level. The replica path 32R is also charged by activating the enable signal EnF for the memory core chip 27 in the uppermost layer as well as the interface chip 10.

[0025] As Figure 6 and 7As shown in the middle, one cycle of the test clock signal CLK coincides with the activation period of the selection signals Ysel0, Ysel1, Ysel2, Ysel3,.... Thus, during the first half of the period, during which one of the selection signal paths 32, the transistor 47 is on, and thus discharges the selected signal path 32 and the replica path 32R and puts the nodes N1 and N2 at the VSS level. At the same time, during the second half of the period, during which one of the selection signal paths 32, the transistor 47 is off, and thus the discharge of the selected signal path 32 and the replica path 32R stops. When the discharge of the selected signal path 32 and the replica path 32R stops, the selected signal path 32 and the replica path 32R are charged via the transistors 41 and 48, respectively, so that the levels at the nodes N1 and N2 rise. At this time, the rising rate of the level at the node N1 is determined by the resistance value and the parasitic capacitance CI of the signal path 32. Also, the rising rate of the level at the node N2 is determined by the resistance value and the parasitic capacitance C2 of the replica path 32R. Although the parasitic capacitance C2 of the replica path 32R is substantially the same as the parasitic capacitance CI of the signal path 32 as described above, the charging rate of the replica path 32R is lower than that of the signal path 32 unless the signal path 32 has a fault, because a dummy resistor Rd is inserted in series to the replica path 32R. Figure 6 The waveforms in the case where each of the signal paths 32 has no fault are shown in the middle, and the level at the node N1 rises faster than the level at the node N2. The comparison signal COMP is activated at the timing after the test clock signal CLK is changed from the high level to the low level and before the test clock signal CLK is changed to the high level again. When the comparison signal COMP is activated, the comparator circuit 49 performs the operation of comparing the level at the node N1 with the level at the node N2 with each other, and puts the output signal OUT of the comparator circuit at the high level when the level at the node N1 is higher. This means that the signal path 32 has no fault, and the fault signal FAIL remains non-active.

[0026] At the same time, Figure 7The waveform in a case where the signal path 32 corresponding to the selection signals XselO and Ysel2 has a failure is shown. When there is a failure in the signal path 32, the resistance value of the signal path is high and the charging rate of the signal path 32 decreases. Due to the failure in the signal path 32, a case can be considered where the resistance of the TSV 30 itself becomes high due to a failure in the connecting portion of the TSV bump 31B and the resistance of the signal path 32 becomes high. If the resistance value of the signal path 32 is higher than the resistance value of the replica path 32R, the level at the node Nl rises more slowly than the level at the node N2. In this case, when the comparison signal COMP is activated, the comparator circuit 49 places its output signal OUT at a low level. This means that the signal path 32 has a failure and the failure signal FAIL is activated. When the failure signal FAIL is activated, the corresponding signal path 32 is deactivated and replaced with a spare signal path.

[0027] As a method of inspecting the signal paths 32, a method in which the replica path 32R is not used as a reference but a constant reference voltage is used can also be considered. That is, a method in which one of the input terminals of the comparator circuit 49 is connected to the node Nl and a constant reference voltage is applied to the other input terminal of the comparator circuit 49 is considered. However, in this method, the determination result of pass or failure can be changed by the frequency of the test clock signal CLK. For example, in a case where the actual frequency of the test clock signal CLK is higher than the designed value, the charging time of the signal path 32 is shorter than expected and thus a defectless signal path 32 can be determined as defective. Conversely, in a case where the actual frequency of the test clock signal CLK is lower than the designed value, the charging time of the signal path 32 is longer than expected and thus a defective signal path 32 is determined as defectless. Furthermore, off-leak current from the output buffer 45 also flows into the signal path 32. Thus, when the charging time of the signal path 32 becomes longer than expected, the risk of determining a defective signal path 32 as defectless increases and even a completely disconnected signal path 32 can be determined as defectless. Conversely, the semiconductor device according to the embodiment of the present application uses the replica path 32R as a reference. Thus, even if the actual frequency of the test clock signal CLK differs from the actual frequency of the designed value, this difference uniformly affects the signal path 32 and the replica path 32R. Furthermore, off-leak current from the output buffer 45 also uniformly affects the signal path 32 and the replica path 32R. Thus, correct inspection can be performed for each signal path 32. Furthermore, since correct inspection can be performed even if the frequency of the test clock signal CLK is designed to be higher, it is possible to complete the inspection of a number of signal paths 32 with sufficient margin in the initialization period after power-on (even in a case where the inspection is performed in the initialization period).

[0028] Furthermore, a plurality of dummy resistors RdO to Rd2 connected in parallel can be inserted into the replica path 32R, as shown in Figure 8 By further inserting transistors 50 to 52 in series into the respective dummy resistors RdO to Rd2 and by using one or two or more than two of the selection signals SO to S2 to turn on one or two or more than two of the transistors 50 to 52, it is possible to change the resistance value of the replica path 32R. Thus, it is possible to switch the resistance value in which the signal path 32 is determined to be defective by the selection signals SO to S2. In this case, it is preferred that the resistance values of the dummy resistors RdO to Rd2 differ from each other.

[0029] Furthermore, as shown in Figure 9 In each of the memory core chips 20 to 26 and the interface chip 10, two TSVs 30 can be used to configure the replica path 32R, while the two TSVs 30 are connected in parallel. With this configuration, even in the case where there is a failure in a part of the TSVs 30 configuring the replica path 32R, the verification of the signal path 32 can be correctly performed. In this case, the resistance value of the replica path 32R is slightly lowered due to the parallel connection of the two TSVs 30. However, the total resistance value of the eight TSVs 30 included in the replica path 32R is about 1 Ω and is sufficiently low compared to the on-resistance of the transistor 48. Thus, the lowering of the resistance value of the replica path 32R has little influence on the verification. Furthermore, three or more than three of the TSVs 30 can be connected in parallel.

[0030] Furthermore, a dummy capacitor Cd can be connected to the replica path 32R instead of inserting a dummy resistor Rd into the replica path 32R, as shown in Figure 10 Also in this case, substantially the same operation as that of the circuit shown in Figure 5

[0031] ​While this application has been disclosed in the context of certain preferred embodiments and examples, it will be understood by those skilled in the art that the application extends beyond the specifically disclosed embodiments to other alternative embodiments and / or uses of the application and obvious modifications and equivalents thereof. Further, it will be understood by those skilled in the art that other modifications beyond the scope of the specific disclosed embodiments will occur to persons having ordinary skill in the art upon an understanding of the application. Still further, it is intended that certain features and aspects of the disclosed embodiments can be combined with or substituted for other features and aspects of the disclosed embodiments and vice versa. It is therefore intended that the scope of the application herein disclosed should be limited only by the claims.

Claims

1. A method comprising: charging the first path and the second path with a first voltage; comparing the potential of the first path and the potential of the second path after charging; activating an output signal at a low level in response to the potential of the first path being lower than the potential of the second path; as well as The first path is replaced with the second path.

2. The method of claim 1, further comprising: In response to the output signal being at the low level, a fault signal is activated.

3. The method of claim 1 , further comprising: The first path and the second path are charged simultaneously with the first voltage.

4. The method of claim 3, further comprising: discharging the first path and the second path simultaneously during a first period of an activation cycle of a selection signal; as well as The first path and the second path are charged simultaneously in a second time period after the first time period. The method of claim 4 , wherein comparing the potential of the first path and the potential of the second path occurs during the second period.

6. The method of claim 1, further comprising: providing an enable signal to the second signal path; as well as The enable signal is activated during a test cycle. The method of claim 1 , wherein replacing the first path with the second path comprises using the second path in place of the first path.

8. A device comprising: a first signal path comprising a first TSV; a first node coupled to the first signal path; a second signal path comprising a second TSV; a second node coupled to the second signal path; as well as A comparator is configured to compare a level at the first node and a level at the second node with each other in response to a comparison signal.

9. The device according to claim 8, wherein the first signal path includes a first transistor configured to receive a select signal, wherein the first node is coupled to the first signal path via the first transistor, wherein the second signal path includes a second transistor configured to receive an enable signal and a resistor inserted in series, and The second node is coupled to the second signal path via the second transistor.

10. The apparatus of claim 8, wherein the comparator is configured to set an output signal to a low level in response to the level at the first node being lower than the level at the second node, wherein a fault signal is activated, and wherein in response to the activation of the fault signal, the first signal path is replaced by the second signal path. 11 . The apparatus of claim 10 , wherein the comparator is configured to set an output signal to a high level in response to the level at the first node being higher than the level at the second node.

12. The apparatus of claim 8, wherein the first signal path includes a first parasitic capacitance and the second signal path includes a second parasitic capacitance, wherein the first parasitic capacitance and the second parasitic capacitance have the same value.

13. The apparatus of claim 8 , wherein the comparison signal is activated at a timing after a test clock signal provided to each of the first signal path and the second signal path changes from a first level to a second level and before the test clock signal changes from the second level to the first level.

14. The apparatus of claim 9, wherein the resistor comprises a plurality of resistors connected in parallel.

15. The apparatus of claim 14, wherein each resistor of the plurality of resistors is configured to turn on a corresponding transistor by using a corresponding selection signal.

16. The apparatus of claim 14, wherein each of the plurality of resistors has a resistance value different from one another.

17. An apparatus comprising: a first signal path comprising a first TSV and a first transistor configured to receive a select signal; a first node coupled to the first signal path; a second signal path comprising a second TSV and a second transistor, the second transistor configured to receive an enable signal; a second node coupled to the second signal path; as well as a comparator configured to: comparing the level at the first node and the level at the second node with each other; If the level at the second node is higher than the level at the first node, setting the output signal to a low level; as well as In response to the output signal being at the low level, a fault signal is activated. 18 . The apparatus of claim 17 , wherein the second signal path further comprises a third TSV connected in parallel with the second TSV, and wherein a resistance value of the second signal path is lower than a resistance value of the first signal path.

19. The apparatus of claim 17, wherein the second signal path further comprises a plurality of resistors connected in parallel and a series of transistors connected in series with corresponding ones of the plurality of resistors, wherein each transistor in the series of transistors is turned on by a corresponding select signal.

20. The apparatus of claim 17, wherein the first path further comprises a first capacitor and the second path further comprises a second capacitor and a third capacitor, wherein the first capacitor and the second capacitor have the same value as each other, and wherein a time constant of the second path is greater than a time constant of the first signal path.

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