Energetic CMOS (complementary metal oxide semiconductor) transistor structure and preparation method thereof

Abstract

The invention belongs to the field of self-destruction chips, and particularly relates to an energetic CMOS (complementary metal oxide semiconductor) transistor applied to a self-destruction chip and a preparation method of the energetic CMOS transistor. Comprising a substrate, a grid electrode, an energetic layer composed of an oxide layer and a metal layer, an insulating layer, a semiconductor region and a source and drain electrode which are sequentially arranged, the energetic layer is a thermite system, and the energetic CMOS transistor has switching performance, logicality and self-destruction performance. According to the invention, the basic switching and logic functions of the MOS tube can be realized, and when certain excitation energy is applied, the energy-containing layer releases energy to complete the damage of key logic unit devices in the chip, thereby causing the failure of the operation function of the chip.

Description

Technical Field

[0001] The present invention belongs to the field of self-destruct chips, and in particular relates to an energetic CMOS transistor applied to self-destruct chips and a preparation method thereof. Background Art

[0002] To prevent information leaks, chip self-destruct technology is constantly evolving. Physical and chemical chip self-destruction methods not only prevent information leaks but also completely destroy the chip, preventing leakage of electronic circuit structures. Self-destruct chips can also be used to build neural networks for artificial intelligence, addressing ethical issues facing the development of artificial intelligence.

[0003] Physical damage is the most thorough method of chip self-destruction. Current chip self-destruction technologies include transient electronics, stress destruction, chemical corrosion, and energetic material destruction. Transient electronics is an environmentally friendly self-destruction technology based on biodegradable materials. These materials can undergo instant degradation under specific external stimuli, causing the device to self-destruct. However, this approach is incompatible with traditional chip integration processes. Stress destruction, by manipulating the microstructure and application conditions, amplifies the stress effects within the device to a certain degree, potentially causing irreparable physical damage. However, both the microstructure design and the process are relatively complex. Chemical corrosion uses chemical reagents to corrode the conductors or substrate materials of electronic devices. The difficulty with this technology lies in the need to maintain absolute isolation between the chemical etchant and the circuitry during device operation. Energetic material self-destruction utilizes a self-propagating reaction in thermite system to produce more rapid damage, but the activation conditions are more stringent, requiring an additional power supply module, making it incompatible with traditional integrated circuit technology.

[0004] None of the above methods are fully adaptable to the traditional integrated circuit (IC) manufacturing process and can only be used for chips with special structures. Summary of the Invention

[0005] The purpose of the present invention is to provide an energetic self-destruct device that has a simple structure, reliable self-destruction, safe operation, logical judgment capability and switching function, and is compatible with integrated circuit (IC) processes. The device can realize the basic switching and logic functions of a MOS tube and self-destruct under a certain energy excitation.

[0006] The technical solution for achieving the objectives of the present invention is: an energetic CMOS transistor for use in a self-destruct chip, comprising a substrate, a gate, an energetic layer composed of an oxide layer and a metal layer, an insulating layer, a semiconductor region, and a source-drain electrode, which are arranged in sequence. The energetic layer is a thermite system. The energetic CMOS transistor has switching, logic, and self-destruct properties.

[0007] Furthermore, the composition of the metal layer in the energetic layer is any one of Al, B, Be, La, Li, Mg, Nd, Ta, Th, Ti, Y, and Zr, or a mixture of any of the above; the composition of the oxide layer in the energetic layer is Cu x O, Fe x O y Cr x O y 、Ni x O y 、Ag x O, B2O3, Co x O y 、I2O5、HgO、MnO2、Pb x O y 、Nb2O5、SiO2、SnO x 、TiO2、V2O5、WO x , U3O8, Bi2O3, MoO3 or a mixture of any of them.

[0008] Furthermore, the gate and the source-drain electrodes are made of active metals such as Al, Mg, Ni, Ti, Au, Ag, Cu or ITO.

[0009] Furthermore, the insulating layer is composed of CuO, FeO, NiO, SiO2, HfO2, Al2O3 or TiO2.

[0010] Furthermore, the semiconductor region is composed of any one of In2O3, Ga2O3, ZnO, and SnO2, or a mixture of any of them.

[0011] A method for preparing the above-mentioned energetic CMOS transistor comprises the following steps:

[0012] Step (1): ultrasonically clean the silicon oxide wafer with acetone, ethanol and deionized water respectively, and then dry it in an oven for later use;

[0013] Step (2): adjusting the speed and time of the coating machine, coating the photoresist on the silicon oxide wafer, and placing it in an oven to remove the solvent in the photoresist;

[0014] Step (3): Installing a mask: exposing the silicon oxide wafer coated with photoresist to ultraviolet light, and then placing the exposed silicon oxide wafer in an oven for reverse baking;

[0015] Step (4): The reverse baked silicon oxide wafer is exposed to ultraviolet light;

[0016] Step (5): preparing a developing solution, placing the exposed silicon oxide wafer in the developing solution for development, and completing the pattern engraving;

[0017] Step (6): placing the developed silicon oxide wafer in an oven to solidify the photoresist on the surface and prevent deformation, thus completing the photolithography step;

[0018] Step (7): After the photolithography is completed, the silicon oxide wafer is subjected to magnetron sputtering to prepare a gate;

[0019] Step (8): stripping the sample obtained in step (7) to remove excess photoresist and sputtered material to obtain a gate structure;

[0020] Step (9): Repeat steps (1) to (8), using different masks to prepare metal layers, oxide layers, insulating layers, semiconductor layers and source / drain electrodes of different shapes and structures, and the preparation of each layer structure of the CMOS transistor sample is completed;

[0021] Step (10): The sample prepared in step (9) is placed in a tube furnace and annealed in an inert gas atmosphere so that the semiconductor layer oxide is recrystallized and has semiconductor properties.

[0022] Furthermore, the thickness of the oxide layer of the oxidized silicon wafer in step (1) is 200 to 1000 μm.

[0023] Furthermore, the speed of the glue spreader in step (2) is 500 to 2500 rps, and the time is 10 to 30 seconds.

[0024] Furthermore, the exposure UV energy in step (3) is 20 to 30 mJ, and the exposure UV energy in step (4) is 250 to 300 mJ;

[0025] In step (5), the developer solution has a volume ratio of 5:1 to 10:1, and the development time is 130 to 300 seconds.

[0026] In step (6), the oven temperature is 100-120° C. and the drying time is 1-2 min;

[0027] The inert gas in step (10) is Ar or N2; the annealing temperature is 300-500°C, and the time is 1-4 hours.

[0028] The above-mentioned energetic CMOS transistor is used to connect to the chip circuit and is used to self-destruct the chip.

[0029] Compared with the prior art, the present invention has the following significant advantages:

[0030] (1) The combination of energetic CMOS transistors and electronic devices does not affect the selection of energetic layer materials. An energetic layer capable of forming an energetic thermite system can be selected to ensure the reliability of self-destruction.

[0031] (2) The existence of the insulating layer isolates part of the heat from being transferred to the energetic layer, preventing the energetic layer from being accidentally damaged due to heat accumulation, thus ensuring the safety of the device;

[0032] (3) Energy-containing CMOS transistors control the switching of the device by controlling the gate voltage, and adding an energy-containing layer to it, so that the device has both switching and logic judgment functions as well as explosive self-destruction performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 This is a schematic structural diagram of the energetic self-destruct chip device of the present invention.

[0034] Figure 2 This is a schematic diagram of the principle of the energetic self-destruct chip device described in the present invention.

[0035] Figure 3 This is a flow chart of an energetic CMOS transistor prepared by the magnetron sputtering method according to Example 1 of the present invention. DETAILED DESCRIPTION

[0036] The present invention is further described in detail below with reference to the accompanying drawings.

[0037] An energetic CMOS transistor with both switching logic and destructive properties, including an energetic layer using a thermite system and a transistor system using metal oxide semiconductor materials. The entire energetic CMOS transistor is divided into six layers, from bottom to top: the first layer is the gate, the second layer is the reducing agent component of the thermite, i.e., the metal layer, the third layer is the oxidizing agent component of the thermite, i.e., the oxide layer, the fourth layer is both an insulating layer, and the fifth layer is a metal oxide or sulfide semiconductor layer, which is a semiconductor region. The metal layer and the oxide layer are inserted into the structure of the transistor to form an energetic layer. When a gate voltage (V gs ), charges are induced in the semiconductor layer near the insulating layer. When the gate voltage is low, the induced charges are too small to form channel current. As the gate voltage increases to a certain threshold V th When the device senses the charge to form a conductive channel, a voltage V is applied between the source and drain electrodes. ds Current can be generated. When the gate voltage changes, the carrier density in the accumulation layer changes, causing the current in the channel formed by the active layer to change. Further increasing the gate voltage will cause the current to increase rapidly. By controlling the gate, the density of the induced charge in the semiconductor layer can be regulated, thereby regulating the source-drain current. The gate acts as a "switch," and by introducing an energy-containing layer into the gate structure, the "on" and "off" control of the CMOS transistor is achieved.

[0038] The reducing agent components of thermite are Al, B, Be, La, Li, Mg, Nd, Ta, Th, Ti, Y, Zr, and the oxidizing agent components are Cu x O, Fex O y Cr x O y 、Ni x O y 、Ag x O, B2O3, Co x O y 、I2O5、HgO、MnO2、Pb x O y 、Nb2O5、SiO2、SnO x 、TiO2、V2O5、WO x , one or more mixed components of U3O8, Bi2O3, MoO3;

[0039] The gate and source / drain electrodes are made of active metals such as Al, Mg, Ni, Ti, Au, Ag, Cu, or ITO; the insulating layer is made of CuO, FeO, NiO, SiO2, HfO2, Al2O3, TiO2, etc.

[0040] The semiconductor region is a mixed component of one or more of In2O3, Ga2O3, ZnO, and SnO2.

[0041] The principle of fabricating an energetic CMOS transistor device is to sequentially epitaxially grow six layers of the main material on a substrate. Epitaxial growth methods can include hydrothermal, sol-gel, magnetron sputtering, vapor phase physical deposition, electrochemical deposition, laser pulse deposition, and other methods. To better understand the energetic CMOS transistor described herein, a method for fabricating an energetic CMOS transistor using photolithography and magnetron sputtering is provided, comprising the following steps:

[0042] Step 1: ultrasonically clean the silicon oxide wafer with acetone, ethanol and deionized water for a period of time, and dry the solvent in an oven for later use;

[0043] Step 2: Adjust the speed and time of the coating machine to coat the photoresist on the cleaned silicon oxide wafer, and place it in an oven to remove the solvent in the photoresist;

[0044] Step 3: Install a mask, expose the silicon oxide wafer coated with photoresist in step 2 to ultraviolet light of a certain energy, and place the exposed silicon oxide wafer in an oven for reverse baking;

[0045] Step 4: The silicon oxide wafer after inversion baking is exposed to ultraviolet light of a certain energy;

[0046] Step 5: Prepare a developer of a certain concentration, place the silicon oxide wafer exposed in step 4 in the developer for a period of time to complete the pattern engraving;

[0047] Step 6: The developed silicon oxide wafer is placed in an oven at a certain temperature for a period of time to prevent the photoresist on its surface from deforming, thus completing the photolithography step;

[0048] Step 7: After the photolithography is completed, the silicon oxide wafer is subjected to a magnetron sputtering process to prepare a gate;

[0049] Step 8: stripping the sample in step 7 to remove excess photoresist and sputtered material to obtain a gate structure of a certain shape;

[0050] Step 9: Repeat steps 1 to 8 above, using different masks to prepare metal layers, oxide layers, insulating layers, semiconductor layers, and source / drain electrodes of different shapes and structures, and the structure of each layer of the CMOS transistor sample is completed;

[0051] Step 10: The sample prepared in steps 1 to 9 is placed in a tube furnace and annealed in an inert gas atmosphere so that the oxide in the semiconductor layer is recrystallized and has semiconductor properties.

[0052] The thickness of the oxide layer of the silicon oxide wafer is 200 to 1000 μm;

[0053] The speed of the glue roller in step 2 is 500-2500 rps, and the time is 10-30 seconds;

[0054] The exposure UV energy in step 3 is 20-30 mJ, and the exposure UV energy in step 4 is 250-300 mJ;

[0055] In step 5, the developer concentration is configured at a volume ratio of 5:1 to 10:1, and the developing time is 130 to 300 seconds;

[0056] The oven temperature is 100-120°C and the drying time is 1-2 minutes;

[0057] The inert gas in step 10 can be Ar, N2, etc.; preferably, the annealing temperature is 300-500° C., and the time is 1-4 hours.

[0058] The present invention combines an energetic thermite system with a transistor structure. In previous energetic electronic devices, the oxidant component of the thermite system not only had to form an energetic damage system with the reducing agent component but also form a PN junction with the metal oxide semiconductor component. Not all oxidants capable of a thermite reaction could be used; only those that could undergo certain processing to develop semiconductor properties could be used. This limited the choice of oxidant components in the energetic system, impacting the damage performance of the energetic electronic device. In an energetic CMOS transistor, the energetic system and the MOS transistor electronic device are structurally integrated, yet their functions do not affect each other. Each component is independent yet synergistic, unaffecting the choice of materials for each component. In particular, for the energetic layer, any energetic system component can be selected to ensure damage performance and improve self-destruction reliability. Furthermore, in an energetic CMOS transistor, the insulating layer provides insulation and thermal insulation, not only separating the semiconductor layer from the energetic layer to ensure stable function, but also isolating the heat generated during electronic device operation, preventing accidental damage to the energetic layer and enhancing device safety.

Claims

1. An energetic CMOS transistor for use in a self-destruct chip, characterized in that: It includes a substrate, a gate, an energetic layer composed of an oxide layer and a metal layer, an insulating layer, a semiconductor region and a source-drain electrode arranged in sequence. The energetic layer is a thermite system. The energetic CMOS transistor has switching, logic and self-destructive properties.

2. The energetic CMOS transistor according to claim 1, wherein: The metal layer in the energetic layer is composed of any one of Al, B, Be, La, Li, Mg, Nd, Ta, Th, Ti, Y, and Zr, or a mixture of any of them; the oxide layer in the energetic layer is composed of Cu x O, Fe x O y Cr x O y 、Ni x O y 、Ag x O, B2O3, Co x O y 、I2O5、HgO、MnO2、Pb x O y 、Nb2O5、SiO2、SnO x 、TiO2、V2O5、WO x , U3O8, Bi2O3, MoO3 or a mixture of any of them.

3. The energetic CMOS transistor according to claim 2, wherein: The gate and source / drain electrodes are made of active metals such as Al, Mg, Ni, Ti, Au, Ag, Cu, or ITO.

4. The energetic CMOS transistor according to claim 3, wherein: The insulating layer composition is CuO, FeO, NiO, SiO2, HfO2, Al2O3 or TiO2.

5. The energetic CMOS transistor according to claim 4, wherein: The semiconductor region is composed of any one of In2O3, Ga2O3, ZnO, and SnO2, or a mixture of any of them.

6. A method for preparing an energetic CMOS transistor according to any one of claims 1 to 5, characterized in that: The steps include: Step (1): ultrasonically clean the silicon oxide wafer with acetone, ethanol and deionized water respectively, and then dry it in an oven for later use; Step (2): adjusting the speed and time of the coating machine, coating the photoresist on the silicon oxide wafer, and placing it in an oven to remove the solvent in the photoresist; Step (3): Installing a mask: exposing the silicon oxide wafer coated with photoresist to ultraviolet light, and then placing the exposed silicon oxide wafer in an oven for reverse baking; Step (4): The reverse baked silicon oxide wafer is exposed to ultraviolet light; Step (5): preparing a developing solution, placing the exposed silicon oxide wafer in the developing solution for development, and completing the pattern engraving; Step (6): placing the developed silicon oxide wafer in an oven to solidify the photoresist on the surface and prevent deformation, thus completing the photolithography step; Step (7): After the photolithography is completed, the silicon oxide wafer is subjected to magnetron sputtering to prepare a gate; Step (8): stripping the sample obtained in step (7) to remove excess photoresist and sputtered material to obtain a gate structure; Step (9): Repeat steps (1) to (8), using different masks to prepare metal layers, oxide layers, insulating layers, semiconductor layers and source / drain electrodes of different shapes and structures, and the preparation of each layer structure of the CMOS transistor sample is completed; Step (10): The sample prepared in step (9) is placed in a tube furnace and annealed in an inert gas atmosphere so that the semiconductor layer oxide is recrystallized and has semiconductor properties.

7. The method according to claim 6, characterized in that The thickness of the oxide layer of the silicon oxide wafer in step (1) is 200 to 1000 μm.

8. The method according to claim 7, characterized in that The speed of the glue spreader in step (2) is 500 to 2500 rps, and the time is 10 to 30 seconds.

9. The method according to claim 8, characterized in that The exposure UV energy in step (3) is 20 to 30 mJ, and the exposure UV energy in step (4) is 250 to 300 mJ; In step (5), the developer solution has a volume ratio of 5:1 to 10:1, and the development time is 130 to 300 seconds. In step (6), the oven temperature is 100-120° C. and the drying time is 1-2 min; The inert gas in step (10) is Ar or N2; the annealing temperature is 300-500°C, and the time is 1-4 hours.

10. Use of the energetic CMOS transistor according to any one of claims 1 to 5, characterized in that: Access the chip circuit to self-destruct the chip.

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