Semiconductor wafer bonding device and bonding method

Abstract

According to the invention, the bonding strength between wafers in the semiconductor manufacturing process is improved through a simple structure. Provided is a vacuum chamber (14) for bonding semiconductor wafers (W1, W2) to each other, one using a silicon electrode (G1) and the other using a semiconductor wafer (W2) before bonding crystalline silicon circles (W1, W2) facing each other; after the silicon electrode G1 and the semiconductor wafer W2 are processed for the first time, the silicon electrode G1 is replaced by the bonding wafer G2, and then the bonding wafer G2 and the semiconductor wafer W2 are processed for the second time. Then, the pair of wafers W1 and W2, which are opposite to each other, are bonded together by electrostatic force in a vacuum environment.

Description

TECHNICAL FIELD

[0001] The present application relates to a bonding apparatus and bonding method for semiconductor wafers, in which homogenous or heterogeneous semiconductor wafers are bonded to each other in a semiconductor manufacturing process, for example, by a high frequency ion flow activated bonding (RFIFB) method. BACKGROUND

[0002] Hybrid bonding is part of the conventional semiconductor manufacturing process, which includes a plasma treatment process, a cleaning process, a drying process, and a bonding process.

[0003] In the plasma treatment process, for example, atmospheric pressure plasma or vacuum plasma is used to activate the surface of the semiconductor wafer. In the cleaning process, for example, the semiconductor wafer is rotated around its central axis while controlling the flow rate and position of the cleaning liquid (pure water or chemical liquid) to achieve uniform cleaning of the wafer surface. In the drying process, for example, the semiconductor wafer is rotated at high speed around its central axis to scatter water droplets on the wafer surface. In the bonding process, for example, the upper and lower semiconductor wafers subjected to the plasma treatment process to the drying process are arranged opposite to each other, and finally the wafer bonding is performed by a bonding apparatus.

[0004] In the conventional bonding apparatus, two semiconductor wafers are placed in a face-to-face manner on a planar stage arranged opposite to each other, and a pair of semiconductor wafers in opposite positions are bonded by a surface activated bonding (SAB) method (hereinafter referred to as "SAB method") of a normal temperature bonding process.

[0005] Surface activated bonding is a method of generating an ion beam by ionizing an inert gas such as argon, and irradiating the ion beam or plasma to the surface of the material to be bonded to remove the oxide film and contamination layer present on the surface of the material, form a dangling bond, and achieve bonding of the material at low temperature or normal temperature by pressurization.

[0006] However, in the SAB method, since the irradiation area is small, it is not possible to uniformly activate and remove the oxide film on the entire wafer surface at once, and the surface is processed by moving the wafer or the beam source, but the uniformity of the activated material surface is poor by this moving method, and the surface of the overlapping portion becomes rough, resulting in a decrease in the bonding strength between the semiconductor wafers. Furthermore, when the wafer or the beam is moved by point irradiation of the Ar ion beam, particles are generated, and void bubbles are generated in the bonding intermediate layer.

[0007] CITED PATENT LITERATURE

[0008]

Patent Literature 1

[0009] SUMMARY OF THE INVENTION

[0010] Problem to be solved by the invention

[0011] Therefore, the present invention provides a bonding device and a bonding method with simple structure design, which can simplify the complexity of the device and improve the bonding strength of the wafer.

[0012] Method for solving the problem

[0013] The present invention relates to a bonding device and a bonding method for semiconductor wafers. After plasma activation on the surface of a semiconductor wafer, a pair of wafers facing each other are bonded using Coulomb force (electrostatic force), thereby improving the bonding strength. The device can also be used as a bonding method for semiconductor wafers.

[0014] Before bonding the wafers facing each other to each other, a silicon electrode is prepared for one of the wafers, and a semiconductor wafer is used for the other of the wafers. After performing a first plasma activation process on the silicon electrode and the other semiconductor wafer, the silicon electrode is changed to a bonding wafer, and a second plasma activation process is performed on the bonding wafer and the semiconductor wafer.

[0015] A pair of wafer fixing mechanisms are provided in an up-and-down opposing position. In a state where the wafer fixing mechanisms adsorb the wafers, plasma is applied between the wafers, and at least one wafer fixing mechanism is moved, thereby bonding the wafers facing each other to each other.

[0016] Effects of the invention

[0017] According to the present invention, the bonding strength between semiconductor wafers in a semiconductor manufacturing process can be improved by a simple structure.

[0018] Brief description of the drawings

[0019] Figure 1 is a configuration diagram of a semiconductor wafer bonding device according to an embodiment of the present invention.

[0020] Figure 2 is a configuration diagram of a semiconductor wafer bonding device according to an embodiment of the present invention, which performs plasma processing and bonding processing on semiconductor wafers.

[0021] Figure 3 is an engineering diagram of a semiconductor wafer bonding device according to an embodiment of the present invention, which performs plasma processing and bonding processing on semiconductor wafers.

[0022] Figure 4 is an example flowchart of a high-frequency ion flow activation bonding process.

[0023] Figure 5is a plan view of a semiconductor wafer bonding apparatus assembled into a semiconductor manufacturing system according to an embodiment of the present application.

[0024] Figure 6 is a side view of a semiconductor wafer bonding apparatus assembled into a semiconductor manufacturing system according to an embodiment of the present application.

[0025] Figure 7 is a configuration view of a single-pole electrostatic chuck structure.

[0026] Figure 8 is a configuration view of a double-pole electrostatic chuck structure.

[0027] Figure 9 is a configuration view of a double-pole electrostatic chuck structure.

[0028] Embodiment of the Invention

[0029] First, a semiconductor wafer bonding apparatus and a bonding method according to an embodiment of the present application will be described.

[0030] A semiconductor wafer bonding apparatus and a bonding method according to an embodiment of the present application. A plasma chamber or a vacuum chamber is used to perform bonding between semiconductor wafers. The plasma chamber or the vacuum chamber can also be referred to as a bonding chamber, a bonding apparatus, a bonding device, etc.

[0031] Technical Logic of the Invention

[0032] The technical logic of the present application is a semiconductor wafer bonding apparatus that improves bonding strength by bonding a pair of wafers opposite to each other using radio frequency high frequency ion flow and Coulomb force (also referred to as "electrostatic force" hereinafter) in a vacuum chamber in which a wafer is subjected to plasma processing, i.e., in a vacuum environment (in a plasma environment).

[0033] A pair of wafer fixing mechanisms are provided in the vacuum chamber. The wafer fixing mechanisms are provided opposite to each other on a stage. In a state in which the wafer fixing mechanisms adsorb wafers, plasma is applied between the wafers, and at least one of the wafer fixing mechanisms is moved, thereby bonding the wafers opposite to each other to each other.

[0034] Here, before bonding the wafers opposite to each other to each other, a silicon electrode is prepared for one of the wafers, and a semiconductor wafer is used for the other of the wafers. After performing a first plasma activation process on the silicon electrode and the semiconductor wafer, the silicon electrode is changed to a bonding wafer, and a second plasma activation process is performed on the bonding wafer and the semiconductor wafer, thereby obtaining a desired state.

[0035] Between the first plasma treatment and the second plasma treatment, the oxide film formed on the surface of the semiconductor wafer facing each other can be removed by supplying an etching gas.

[0036] The technical idea of the present application described above is not limited to the semiconductor wafer bonding apparatus, but is also applicable to a semiconductor wafer bonding method having the same features as described above.

[0037] [Structure of Semiconductor Wafer Bonding Apparatus]

[0038] As shown in Figure 1 , the semiconductor wafer bonding apparatus 34 of the present embodiment is used to bond various wafers to each other. Note that the semiconductor wafers and the bonded wafers can be, for example, silicon wafers, but are not limited to silicon wafers. Different kinds of semiconductor wafers conventionally used can be used, or semiconductor wafers of different kinds can be bonded to each other.

[0039] As shown in Figure 1 , the semiconductor wafer bonding apparatus 34 has a chamber 14 as a housing, a first stage 36 on the upper side inside the chamber, and a second stage 38 on the lower side inside the chamber. The first stage 36 is provided with a first wafer holding mechanism 102 capable of holding a semiconductor wafer or an electrode (e.g., a silicon target). The second stage 38 is provided with a second wafer holding mechanism 104 capable of holding a semiconductor wafer or an electrode (e.g., a silicon target).

[0040] In addition, the chamber 14 as a housing or the bonding apparatus 34 can be referred to as a "vacuum chamber".

[0041] Here, the first stage 36 and the second stage 38, or the first wafer holding mechanism 102 and the second wafer holding mechanism 104, for example, use an electrostatic chuck or a mechanical chuck, etc. Note that the electrostatic chuck can use, for example, the electrostatic chucks 78, 80 shown in Figures 7 to 9 . The structure of the electrostatic chucks 78, 80 will be described later. Figures 7 to 9

[0042] In addition, as shown in Figure 2 ​As shown, the first stage 36 or the vicinity thereof on the upstream side in the direction of the gravitational force is provided with a first exchange device 106 for exchanging the first wafer holding mechanism 102 and the semiconductor wafer Wl or the silicon target material Gl held by the first wafer holding mechanism 102, with a semiconductor wafer or a silicon target material held by another wafer holding mechanism. Note that the exchange process of the silicon target material G l and the semiconductor wafer Wl is preferably performed in units of groups in which the silicon target material G l and the first wafer holding mechanism 102 holding the silicon target material G l are one group, and the semiconductor wafer Wl and the first wafer holding mechanism 102 holding the semiconductor wafer Wl are one group, but is not limited to this manner.

[0043] The silicon target material G l is known as, for example, a dummy wafer or a bare silicon wafer.

[0044] The semiconductor wafer Wl held by the first wafer holding mechanism 102 includes, for example, a silicon wafer electrode G l and a bonding wafer G2.

[0045] The first exchange device 106 is not limited to the structure provided on the side of the first stage 36, but can be another structure of the bonding device 34 or can be provided outside the bonding device 34.

[0046] In addition, the second stage 38 or the vicinity thereof on the downstream side in the direction of the gravitational force can be provided with a second exchange device 108 for exchanging the second wafer holding mechanism 38 and the semiconductor wafer W2 or the silicon target material held by the second wafer holding mechanism 38, with a semiconductor wafer W2 or a silicon target material held by another wafer holding mechanism. Note that the exchange process of the silicon target and the semiconductor wafer W2 is preferably performed in units of groups in which the silicon target and the second wafer holding mechanism 104 holding the silicon target are one group, and the semiconductor wafer W2 and the second wafer holding mechanism 104 holding the semiconductor wafer W2 are one group, but is not limited to this manner.

[0047] The second exchange device 108 is not limited to the structure provided on the side of the second stage 38, but can be another structure of the bonding device 34 or can be provided outside the bonding device 34.

[0048] In addition, the first exchange device 106 or the second exchange device 108 is preferably at least one of them.

[0049] Here, as the first exchange device 106 and the second exchange device 108, for example, a robot arm is used, but is not limited thereto.

[0050] As the semiconductor wafer Wl held by the first wafer holding mechanism 102 and the semiconductor wafer W2 held by the second wafer holding mechanism 104, for example, a Si wafer or a SiC wafer can be cited, but is not limited thereto.

[0051] As shown in Figure 1 FIG. 1, a high frequency power source 110 is connected to the first stage 36 and the second stage 38, respectively. The high frequency power source 110 has a performance capable of realizing a high frequency electric field (13.56 MHz, 200 W). By applying the high frequency power source 110, the electric field promotes the flow and diffusion of atoms, and improves the adhesion of the bonding surface of the semiconductor wafers Wl, W2.

[0052] The semiconductor wafer bonding apparatus 34 is provided with an automatic pressure control device 112 (APC) capable of controlling the pressure inside the box. The pressure inside the box is controlled by the automatic pressure control device 112.

[0053] The semiconductor wafer bonding apparatus 34 is provided with a turbo molecular pump 114 (TMP). The turbo molecular pump 114 is, for example, composed of a rotor (moving blade) and a stator (stationary blade) having a turbo type blade. The turbo molecular pump 114 is a high performance pump having a high exhaust speed in a high vacuum environment of 1 x 10 - 6 Pa.

[0054] [Effects of the semiconductor wafer bonding apparatus]

[0055] The bonding between the respective wafers becomes more robust.

[0056] When the semiconductor wafers require different plasma processing times for bonding, by replacing the silicon target with the semiconductor wafer of the specification requiring a short plasma processing time as the bonding wafer, the plasma processing time can be shortened. Thus, the bonding wafer can be subjected to a short time plasma processing. Therefore, the surface of the bonding wafer will not deteriorate due to a longer plasma processing time, and the quality of the semiconductor product (semiconductor device, etc.) formed by the bonding of the respective wafers can be prevented from deteriorating.

[0057] [Execution of the first plasma processing]

[0058] As shown in Figure 1 and Figure 2As shown, according to the bonding apparatus 34 of the semiconductor wafer, which is a parallel flat electrode structure, the inside of the housing is placed in a vacuum, and in a state where the silicon target G1 (for example, also referred to as a "silicon wafer electrode") is held by the first wafer holding mechanism 102 and the semiconductor wafer W2 (for example, a silicon wafer) is held by the second wafer holding mechanism 104, a first plasma treatment is performed by argon plasma or the like. Thus, in the inside of the vacuum chamber 14, silicon is sputtered from the silicon target G1 using argon plasma, and the surface of the semiconductor wafer W2 held by the second wafer holding mechanism 104 is activated by the plasma, and an evaporation film X composed of silicon is formed on the surface of the semiconductor wafer W2. In addition, when the surface of the semiconductor wafer W2 is activated by the plasma, argon (Ar) or nitrogen (N2) or the like is used to remove an oxide film and contaminants on the surface of the semiconductor wafer W2, respectively. The same effect is obtained when the surface of the semiconductor wafer W2 is activated in a second plasma treatment.

[0059] Here, since the high-frequency power source 110 is used, the energy is small, and plasma damage to the surface of the semiconductor wafer W2 can be reduced. In addition, by sputtering the plasma electrode G1, which is a silicon wafer electrode, a thin evaporation film X is formed on the semiconductor wafer W2.

[0060] [Isotropic etching]

[0061] In addition, between the first plasma treatment and the second plasma treatment described below, an isotropic etching process can be performed to remove an oxide film formed on the surface of the semiconductor wafer W2 by supplying an etching gas such as SF6. After the isotropic etching process, the plasma gas is switched to argon gas (gas replacement), and the surface of the wafer is activated in the second plasma treatment.

[0062] [Execution of the second plasma treatment]

[0063] Next, the silicon target G1 is replaced with the bonding wafer G2, i.e., a semiconductor wafer W1. The semiconductor wafer is, for example, a silicon wafer, but is not limited to silicon. The replacement process of the silicon target G1 with the bonding wafer W1 is performed, for example, by replacing the silicon target G1 and the first wafer holding mechanism 102 that holds the silicon target G1 as a set of components with another set of components composed of the bonding wafer G2 and the first wafer holding mechanism 102 that holds the bonding wafer G2. Alternatively, the silicon target G1 can be separated from the first wafer holding mechanism 102 while keeping the state of the first wafer holding mechanism 102 unchanged, and the first wafer holding mechanism 102 can be caused to hold the bonding wafer G2 after the separation of the silicon target G1. During and after the replacement process, plasma processing is performed to activate the surfaces of the bonding wafer G2 held by the first wafer holding mechanism 102 and the semiconductor wafer W2 held by the second wafer holding mechanism 104, using a gas such as argon (Ar) or nitrogen (N2). Oxidized films and contaminants on the surfaces of the bonding wafer G2 held by the first wafer holding mechanism 102 and the semiconductor wafer W2 held by the second wafer holding mechanism 104 are removed, respectively. Then, under the environment in which the high-frequency power source 110 is continuously applied, the supply of the gas such as argon (Ar) or nitrogen (N2) is stopped, and the automatic pressure control device 112 is driven at a high output to, for example, bring the degree of vacuum inside the chamber 14 to a target degree of vacuum (for example, 1 x 10 -6 Pa) within about 10 seconds. At this time, the plasma disappears, but the surfaces of the bonding wafer G2 held by the first wafer holding mechanism 102 and the semiconductor wafer W2 held by the second wafer holding mechanism 104 are in a state of being ion-polarized.

[0064] The time required for the degree of vacuum inside the chamber 14 to be reached is not limited to about 10 seconds, and can be set, for example, in the range of 1 second to 30 seconds, more preferably in the range of 1 second to 15 seconds, and further more preferably in the range of 1 second to 10 seconds. The time required for the degree of vacuum inside the chamber 14 to be reached is preferably shorter.

[0065] [Execution of wafer-to-wafer bonding processing]

[0066] In this state, for example, as Figure 3As shown, by moving the first stage 36 and / or the second stage 38 closer to each other, the distance between the bonding wafer G2 held by the first wafer holding mechanism 102 and the semiconductor wafer W2 held by the second wafer holding mechanism 104 is reduced, and due to the Coulomb force (electrostatic force) generated on the surfaces of both, the atomic spacing between the wafers is reduced and they soon come into contact. At this time, the first stage 36 can be fixed and the second stage 38 can be moved closer to the first stage 36. Alternatively, the second stage 38 can be fixed and the first stage 36 can be moved closer to the second stage 38. The initial bonding force between the bonding wafer G2 held by the first wafer holding mechanism 102 and the semiconductor wafer W2 held by the second wafer holding mechanism 104 is increased, but even after the wafers G2, W2 come into contact with each other, by continuing to apply the high-frequency power source 110, RF high frequencies flow between the surfaces of the wafers G2, W2, and due to the ion flow (atomic diffusion) generated by the electric field, the bonding between the wafers is made more robust.

[0067] The semiconductor wafer manufacturing method of the present embodiment is a manufacturing method that is the first of its kind, and is referred to as RF Ion Flow Bonding (RFIFB).

[0068] In addition, the plasma treatment is performed only once for the bonding wafer G2 held by the first wafer holding mechanism 102, but is performed twice for the semiconductor wafer W2 held by the second wafer holding mechanism 104.

[0069] In addition, instead of the first wafer holding mechanism 102 and the silicon target G1 held by the first wafer holding mechanism 102, a structure in which the bonding wafer G2 held by the first wafer holding mechanism 102 is bonded to the semiconductor wafer W2 held by the second wafer holding mechanism 104 after being replaced by another bonding wafer G2 held by the first wafer holding mechanism 102 is preferable, but is not limited thereto. Furthermore, it is preferable that the first wafer holding mechanism 102 be located on the upstream side (upper side) of the direction of the action of gravity and the second wafer holding mechanism 104 be located on the downstream side (lower side) of the direction of the action of gravity.

[0070] On the other hand, as a related art, there is Atomic Diffusion Bonding (ADB). Atomic Diffusion Bonding is a technique known as room-temperature activated bonding, and is known to activate the surface of a semiconductor wafer by an Ar beam or to activate the surface of a semiconductor wafer by Si sputtering, but in either case, several minutes are required to bond the activated semiconductor wafers to each other.

[0071] In general, since the activated state of the surface of a semiconductor wafer deteriorates in a short time, it is necessary to quickly perform vacuuming and bonding.

[0072] Therefore, according to the present embodiment, after the plasma treatment activates the wafer surface, for example, within about 10 seconds, the activated wafer surface is suppressed to the minimum limit by bonding each wafer to each other, while the vacuum is drawn to the limit pressure by the turbo molecular pump 114, thereby realizing a bonding interface with an atomic diffusion effect to the extreme.

[0073] That is, the present embodiment provides a parallel-plate plasma electrode device in the up-down direction, characterized by providing an up-down electrode, a structure for holding a wafer (for example, an electrostatic chuck, a mechanical clamp, or the like), in which one electrode is designed to be replaceable with a bonding wafer.

[0074] According to the present embodiment, since the electrode surface is roughened due to sputtering of the silicon target G1, particles appear in the parallel-plate wafer plasma, thereby forming a void, and in addition, secondary sputtered silicon grows and falls off from the surface of the silicon target G1. The fallen silicon continues to perform Brownian motion and suspends as particles, which become a cause of forming a void defect in the wafer. However, in the present embodiment, since the silicon target G1 (for example, a silicon bare wafer or the like) is used instead of the bonding wafer G2 in the initial stage, damage to the bonding wafer G2 by the void can be reduced. Thus, this method can avoid a decrease in quality and deterioration of quality of a semiconductor product obtained by bonding of the bonding wafer G2 and the semiconductor wafer W2. In addition, the silicon target G1 is preferably replaced periodically each time or each multiple of times.

[0075] As described above, by surface-activating the wafer for one side or both sides of the parallel-plate, and by applying the high-frequency power source 110 to the silicon target G1 to perform soft sputtering, an extremely thin evaporation film X of high-purity Si is generated on the processing surface of the semiconductor wafer W2 opposite to the silicon target G1.

[0076] In the plasma environment, the surface of the semiconductor wafer W2 is hit by ions, thereby exposing a clean surface. After the surface of the semiconductor wafer W2 is cleaned, the high-frequency power source 110 of a different frequency is applied to the silicon target G1 (for example, a silicon wafer) located at the upper portion (upper side). Thus, minute Si flies out from the silicon target G1, and the Si is deposited on the surface of the semiconductor wafer W2 located at the lower portion (lower side), thereby forming an evaporation film X by evaporation.

[0077] In addition, in a case where a thin film is not required to be formed by evaporation, this process can be omitted.

[0078] Second, in the bonding process of the bonding wafer G2 and the semiconductor wafer W2, for example, in the state where the bonding wafer G2 is disposed on the upper (upper side) electrode, the surface of the bonding wafer G2 is activated using a gas such as argon (Ar) or nitrogen (N2). At this time, the surface of the semiconductor wafer W2 disposed on the lower (lower side) is also activated. Thus, the surface activation of the bonding wafer G2 is performed only once, and the surface activation of the semiconductor wafer W2 is performed only twice.

[0079] Inside the chamber 14 as one housing, electrodes are disposed to be able to apply a pressure of plasma and to be able to maintain the pressure of plasma at a high degree of vacuum as much as possible, and to activate the surfaces of the two wafers (the bonding wafer G2 and the semiconductor wafer W2) respectively. As the electrode structure, in order to be able to maintain the plasma at a high degree of vacuum, a structure such as a magnetron, an ICP coil, or the like can be added.

[0080] In addition, after the plasma surface activation is completed, the interval distance between the bonding wafer G2 disposed on the upper side and the semiconductor wafer W2 disposed on the lower side is preferably as narrow as possible. Further, the interval distance between the silicon target G1 disposed on the upper side and the semiconductor wafer W2 disposed on the lower side is also preferably as narrow as possible. As the interval distance, for example, during the plasma processing, the interval distance is the minimum interval between the electrodes at which the plasma is uniformly applied, and after the processing, when the pressure is changed to a high degree of vacuum, the interval distance can be in the range of 10 μm or more and 50 μm or less. This is because, by narrowing the interval distance, particles or the like from the outside are less likely to intrude between the electrodes, and particles are less likely to be mixed in the bonding process of the wafers, and at the same time, the time from the achievement of the vacuum state to the bonding can be shortened.

[0081] After the plasma processing of the bonding wafer G2 and the semiconductor wafer W2, the supply of the gas such as argon (Ar) or nitrogen (N2) is stopped, and the automatic pressure control device 112 is driven to control the pressure to reach the limit vacuum pressure of the turbo molecular pump 114 (or a cryogenic pump) in, for example, about 10 seconds. At this time, the high-frequency power source 110 is continuously applied, but is not limited thereto.

[0082] Thus, the polarized ions (electrons) are left on the respective surfaces of the bonding wafer G2 and the semiconductor wafer W2, and when the bonding of the bonding wafer G2 and the semiconductor wafer W2 is performed in a high vacuum, the movement of atoms increases due to the electric potential of the charged ions on the respective surfaces of the bonding wafer G2 and the semiconductor wafer W2, so that the atoms on the respective surfaces of the bonding wafer G2 and the semiconductor wafer W2 are more easily temporarily moved. In addition, by applying the high-frequency power source 110 after the bonding of the bonding wafer G2 and the semiconductor wafer W2, the movement of atoms also increases, so that the atoms on the respective surfaces of the bonding wafer G2 and the semiconductor wafer W2 are more easily temporarily moved. By these synergistic effects, the atoms are rearranged to a more stable energy state. In particular, in the state where the respective surfaces of the bonding wafer G2 and the semiconductor wafer W2 are activated, the atoms are more easily rearranged to a more ideal position. As a result, the energy of the respective surfaces of the bonding wafer G2 and the semiconductor wafer W2 is minimized, and the bonding strength of the bonding wafer G2 and the semiconductor wafer W2 is improved.

[0083] Here, in general, the time for which the wafer surfaces are activated using plasma until the wafers are bonded to each other, the time for which the semiconductor wafer is transferred from the plasma processing chamber to the bonding chamber, and the time for which the second semiconductor wafer is subjected to plasma processing and handling are added to produce a waiting time of several minutes. During this period, the activity of the surface of the semiconductor wafer deteriorates (decreases at a rate of 10% to 50%) from the time immediately after the plasma processing is completed.

[0084] In contrast, in the present embodiment, since the instantaneous bonding is performed immediately after the semiconductor wafer W2 and the bonding wafer G2 are subjected to plasma processing, the semiconductor wafer W2 and the bonding wafer G2 are bonded in a state where the activated state of the respective surfaces of the semiconductor wafer W2 and the bonding wafer G2 is maintained at a rate of decrease of 1% or less. As a result, the bonding of the semiconductor wafer W2 and the bonding wafer G2 becomes strong.

[0085] [Void-free bonding]

[0086] Most of the voids are fragments generated by sputtering of silicon and particles in the chamber. By frequently replacing the silicon target G1, the fragments and particles formed by sputtering can be eliminated, thereby reducing the voids. Furthermore, in the vacuum plasma, organic matter that is a seed for forming intrusion voids between the bonding wafer G2 and the semiconductor wafer W2 is removed by the plasma. Also, the plasma can prevent organic matter from intruding between the wafers from the outside. By these measures, void-free bonding is achieved.

[0087] [Characteristics of high-frequency ion flow activation bonding]

[0088] The high-frequency ion flow activation bonding has the following characteristics.

[0089] (1) By plasma treatment and management control of instantaneous vacuum degree, the activation and cleaning of wafer surface can be realized.

[0090] (2) By Coulomb force (electrostatic force), the initial bonding force between wafers can be strengthened.

[0091] (3) By high frequency power (RF high frequency), the flow and diffusion of atoms are promoted, and the bonding strength between wafers can be improved.

[0092] [Flow of high frequency ion flow activation bonding process]

[0093] An example of the flow of high frequency ion flow activation bonding process is described below.

[0094] As shown in Figure 4 , for example, a wafer is taken out from a wafer cassette (S100), and alignment of the wafer is performed (S200). The wafer is subjected to cleaning treatment (S300), and is carried to a load lock chamber (S400). The wafer is subjected to plasma treatment (S500), and is bonded to each other (S600). Thereafter, a semiconductor product formed by the wafer bonded to each other is taken out from the load lock chamber (S700), and is subjected to inspection (S800).

[0095] Here, for example, the time required from the end of the plasma treatment process (S500) of the wafer to the end of the bonding process (S600) is preferably 10 seconds or less.

[0096] As described above, for example, by using Coulomb force control assisted bonding using an ESC chuck, misalignment at the time of contact of the opposing wafers to each other can be prevented, and high strength bonding can be realized by high frequency ion flow activation bonding technology. Embodiment

[0097] Next, an embodiment of high frequency ion flow activation bonding is described.

[0098] [Summary]

[0099] (1) In a parallel flat electrode configuration, two silicon wafers are placed in a vacuum.

[0100] (2) A replaceable silicon wafer electrode is used on one side, and the surface of the silicon wafer electrode is subjected to activation treatment by argon plasma.

[0101] (3) Silicon sputtered from the surface of the silicon wafer electrode is attached to the surface of the semiconductor wafer opposite to the silicon wafer electrode in a sputter evaporation manner.

[0102] [Engineering]

[0103] (1) Surface activation by silicon wafer electrode

[0104] Plasma processing (1st) is performed using argon plasma to activate the surfaces of the silicon wafer electrode and the semiconductor wafer opposite the silicon wafer electrode, and to sputter silicon from the silicon wafer electrode.

[0105] The silicon wafer electrode is replaced with a bonding target wafer.

[0106] Argon plasma processing (2nd) is performed on the bonding wafer and the semiconductor wafer, and after stopping the supply of gas, a limit vacuum is achieved, for example, in about 10 seconds, using a turbo molecular pump or the like.

[0107] By vacuuming, the plasma disappears, but ions remain in a polarized state on the surfaces of the bonding wafer and the semiconductor wafer opposite each other.

[0108] (2) Bonding between wafers

[0109] The ions remaining on the surfaces of the bonding wafer and the semiconductor wafer in a polarized state due to the bonding wafer and the semiconductor wafer generate a Coulomb force (electrostatic force), causing the interatomic distance between the wafers to decrease and come into contact with each other.

[0110] A radio frequency high frequency current flows on the surfaces of the wafers, and the electric field causes ion flow (atomic diffusion), thereby achieving strong bonding between the wafers.

[0111] [Specific structure]

[0112] (1) Parallel plate plasma electrode structure

[0113] (1-1) Wafer holding mechanism

[0114] As a wafer fixing mechanism, an electrostatic chuck or a mechanical clamp is used to enable the upper and lower electrodes to hold each wafer, respectively.

[0115] At least one of the upper or lower electrodes should be designed to be replaceable with a bonding wafer. The replacement operation is preferably performed by a robot arm or the like. In addition, it is preferable to replace the bonding wafer of the upper electrode. This makes it possible to suppress particles generated due to the roughness of the electrode surface.

[0116] (1-2) Sputtering of electrodes

[0117] As the electrodes, a silicon target made of a silicon bare wafer is used to control particles during plasma processing. Thus, it is possible to reduce voids generated when the bonding wafer is bonded to the semiconductor wafer.

[0118] (1-3) Activation of the surfaces of the single-sided or double-sided wafers opposite each other

[0119] By applying a high frequency power to each electrode, soft sputtering is performed, and silicon sputtered from the electrode is deposited on the opposite wafer surface to form a thin silicon film of high purity. Alternatively, the process of forming a high purity silicon film (a silicon thin film) can be omitted as needed.

[0120] A high frequency power of a different frequency can be applied to the upper electrode to sputter silicon (Si).

[0121] (2) Setting of bonded wafers

[0122] (2-1) Activation of wafer surface using a gas

[0123] The wafer surface is activated using Ar (argon) or N2 (nitrogen) gas.

[0124] For two wafers placed on top and bottom, plasma treatment is performed simultaneously in one chamber.

[0125] (2-2) Plasma treatment

[0126] Plasma treatment is performed in a high vacuum. A magnetron or an ICP coil or the like can be used.

[0127] A structure is employed in which plasma is uniform between the electrodes and is not affected by external influences such as entry of external dust.

[0128] (2-3) Evacuation after plasma treatment

[0129] Supply of argon and nitrogen gas into the chamber is stopped, and an automatic pressure control device (APC) is driven to control the pressure in the chamber to an ultimate vacuum pressure by a turbo molecular pump, for example, in about 10 seconds or so.

[0130] Depending on the product, a high frequency power can be continuously applied to the upper and lower electrodes, or the application can be stopped.

[0131] (2-4) Vacuum lamination (vacuum bonding)

[0132] Wafers in a surface-charged state are brought close to each other, and contact is made by Coulomb force (electrostatic force). Since Coulomb force is utilized, the initial bonding force between the wafers is improved. Also, since Coulomb force is utilized, the movement of atoms increases, and the atoms remaining on each wafer surface are more easily moved.

[0133] By applying a high frequency power to each electrode, atoms are rearranged to a stable energy state, and thus a strong bond is formed between the wafers.

[0134] (3) Instant lamination (instant bonding) of wafers after plasma treatment

[0135] After the surface of each wafer is activated, bonding is performed for about 10 seconds, for example, to minimize deterioration of the activated state of the wafer surface.

[0136] In contrast, in general room-temperature activation bonding or atomic diffusion bonding, time is required for the wafer-to-wafer bonding. Specifically, if a waiting time of several minutes is allowed, the activated state deteriorates by about 20%. Quality deterioration of semiconductor wafer products has been a problem, but this problem is solved by the high-frequency ion flow activation bonding of the present embodiment.

[0137] [Decay rate after surface activation in high vacuum (1 x 10 -6 Pa)]

[0138] Decay rate after 10 seconds in vacuum: A(10 seconds) = 99.83%, A(10 seconds) = 99.83%, i.e., decay rate = 0.17%

[0139]

[0140] Decay rate after 2 minutes in vacuum: A(2 minutes) = 81.87%, A(2 minutes) = 81.87%, i.e., decay rate = 18.13%

[0141] As described above, rapid vacuuming and wafer-to-wafer bonding are important for maintaining the activated state of the surface, and the results show that firm wafer-to-wafer bonding is achieved.

[0142] Next, the silicon wafers are subjected to plasma treatment in vacuum to activate the surfaces, and then the gas supply is stopped and the activated state of the surfaces is maintained in high-speed vacuum. The wafers are bonded to each other, and a high-frequency power source is applied to analyze the ion diffusion in the high-frequency ion flow activation bonding process.

[0143] [High-frequency ion flow activation bonding process]

[0144] (1) Plasma surface activation

[0145] By using plasma etching of fluorine-based gas, organic contaminants and oxides on the wafer surface are chemically removed. By argon sputtering, possible remaining minute contaminants and uneven chemical residues are removed. By the activation of the wafer surface and the plasma etching, the wafer surface is cleaned, and by the argon sputtering, the wafer surface is further physically impacted to activate the atoms of the wafer surface, thereby improving the bonding efficiency between the wafers.

[0146] Due to the dual effects of cleaning and activation of the wafer surface, the atoms are diffused, and high bonding strength between the wafers is obtained.

[0147] (2) Gas stop and high-speed vacuum pumping ​

[0148] After the plasma treatment of the wafers, the supply of argon and nitrogen is stopped, and a turbo molecular pump is used to control the high vacuum (1 x 10 -6 Pa) at a high speed.

[0149] By reaching the ultimate vacuum level in about 10 seconds, the activated state of the wafer surface is maintained.

[0150] (3) Bonding of wafers to each other

[0151] The wafers are bonded to each other in a state where the polarized ions remain on the surfaces of the wafers, respectively.

[0152] Due to the Coulomb force (electrostatic force), the atomic spacing of the surfaces of the wafers that are close to each other becomes small, and the contact between the wafers is strengthened.

[0153] (4) Application of high frequency power

[0154] After the wafers are bonded to each other, high frequency power is applied to generate an electric field on the surfaces of the wafers.

[0155] The ions on the surfaces of the wafers are made to flow by the electric field, and the bonding between the atoms is strengthened.

[0156] [Discussion of ion diffusion]

[0157] (1) State of ions on the surfaces of wafers

[0158] Due to the activation effect of the plasma treatment, the ions remaining on the surfaces of the wafers are in a polarized state.

[0159] The ions in the polarized state are strongly adsorbed on the surfaces of the wafers, so the movement of the ions becomes easy.

[0160] In a high vacuum environment, the electrodes are in an insulating state, and the ions are not ionized (discharged) but remain on the surfaces of the wafers.

[0161] (2) High vacuum state

[0162] In a high vacuum, the activated state of the surfaces of the wafers is maintained, and the recontamination of the surfaces of the wafers is suppressed.

[0163] (3) Effect of high frequency power

[0164] The high frequency electric field (13.56 MHz, 200 W) has the following effects on the surfaces of the wafers and the interface.

[0165] (3-1) Fluctuation of surface potential

[0166] Due to the high frequency electric field, an alternating electric field is generated on the surfaces of the wafers. As a result, the potential of the surfaces of the wafers fluctuates, and the following effects are induced.

[0167] Fluctuation of surface potential: A potential of ±200 V is fluctuated at a frequency of 13.56 MHz, causing movement of electrons and ions on the wafer surface.

[0168] Effect of high-frequency electric field: Due to the high-frequency electric field (alternating electric field), atoms and ions on the wafer surface are rearranged.

[0169] (3-2) Facilitation of atomic diffusion at the interface

[0170] The high-frequency electric field has the following effects on the wafer surface.

[0171] Movement of ions: The alternating electric field makes it easier for ions on the wafer surface to move.

[0172] Changes in interatomic forces: The alternating electric field causes changes in interatomic forces between atoms on the wafer, resulting in stronger bonding.

[0173] Reduction of activation energy: The alternating electric field reduces the energy required for atomic diffusion, facilitating the bonding between atoms.

[0174] [Mechanism of ion diffusion]

[0175] By applying a high-frequency power source, ions will diffuse in the following mechanism.

[0176] (1) Ion movement induced by electric field

[0177] Due to the high-frequency electric field (effect caused by the high-frequency electric field), ions on the wafer surface are attracted or pushed out. As a result, ions on the wafer surface move uniformly as a whole.

[0178] (2) Surface diffusion

[0179] Ions move on the wafer surface, causing atoms to rearrange.

[0180] Through the rearrangement of atoms on the wafer surface, a more stable energy state is formed.

[0181] (3) Strengthening of interatomic bonding

[0182] Through the rearrangement of atoms on the wafer surface, the bonding between atoms is strengthened. As a result, the bonding between wafers becomes strong.

[0183] According to the high-frequency ion flow activation bonding process, in particular, the silicon wafers are chemically reacted in vacuum, the oxide film on the wafer surface is isotropically etched, and the wafer surface is activated by soft sputtering of argon. Thereafter, a high-vacuum environment is formed at a high speed of about 10 seconds, for example, while maintaining the wafer surface in an activated state, the wafers are adhered to each other. Further, by continuously applying a high-frequency power between the wafers, ions on the wafer surface are moved due to diffusion of the ions, and the interatomic bonding is strengthened. Thus, the high-frequency ion flow activation bonding technique is very effective in wafer bonding technology, and can simultaneously improve the bonding strength and the bonding quality between the wafers.

[0184] In addition, frequent automatic replacement of the electrodes and use of the die contribute to reduction of flakes and particles formed by silicon sputtering, and realization of void-free bonding. Thus, the cleaning frequency in the chamber can be greatly reduced, and the time required for equipment maintenance can be reduced and the operation rate of the equipment can be improved.

[0185] [Example of semiconductor manufacturing system]

[0186] An example of assembling the semiconductor wafer bonding apparatus of the present embodiment and the examples into a semiconductor manufacturing system is described.

[0187] As shown in Figure 5 and Figure 6 , the semiconductor wafer bonding apparatus 34 can be assembled into a semiconductor manufacturing system 200 instead of the plasma chamber 10 of a conventional system. Figure 5 and Figure 6 The semiconductor manufacturing system 200 shown in

[0188] [Example of wafer holding mechanism]

[0189] Next, an example of a wafer holding mechanism for holding each wafer is described.

[0190] Regarding the semiconductor wafer bonding apparatus and the bonding method of the present embodiment, electrostatic chucks 80 (see Figures 7 to 9 ) as wafer holding mechanisms are provided on the first stage 36 and the second stage 38 for holding the semiconductor wafers W1, W2. Alternatively, instead of the electrostatic chucks 80 (see Figures 7 to 9The structure in which the single wafer bonding apparatus 10, the first wafer fixing mechanism 102, and the second wafer fixing mechanism 104 are arranged.

[0191] Figure 7 and Figure 8 The structures of the single-pole electrostatic chuck 78 and the double-pole electrostatic chuck 80 are shown. The material of each electrostatic chuck 78, 80 uses an insulating material such as alumina (AI2O3) or aluminum nitride (ALN). The structure is that an electrode is built in an insulator, and a semiconductor wafer Wl, W2 or the like as an adsorbed body 86, 92 is adsorbed by applying a voltage to the electrode.

[0192] Figure 7 The single-pole electrostatic chuck 78 shown is of a single-pole type, and has a base substrate 82 and an internal electrode (also called an electrode sheet or a polyimide film electrode layer) 84 arranged on the base substrate 82. The base substrate 82 applies one of positive (+) or negative (-) voltage to the internal electrode 84. For example, when a positive (+) voltage is applied to the internal electrode 84, negative (-) charges move to the surface of the adsorbed body 86, and the adsorbed body 86 is adsorbed by the single-pole electrostatic chuck 78. Also, when a negative (-) voltage is applied to the internal electrode 84, positive (+) charges move to the surface of the adsorbed body 86, and the adsorbed body 86 is adsorbed by the single-pole electrostatic chuck 78.

[0193] Figure 8 The electrostatic chuck 80 shown is of a double-pole type, and has a base substrate 88 and an internal electrode (also called an electrode sheet or a polyimide film electrode layer) 90 arranged on the base substrate 88. The base substrate 88 applies both positive (+) and negative (-) voltage to the internal electrode 90. For example, negative (-) charges move to the surface of the adsorbed body 92 opposite to the internal electrode 90 to which a positive (+) voltage is applied, and positive (+) charges move to the surface of the adsorbed body 92 opposite to the internal electrode 90 to which a negative (-) voltage is applied, so that the adsorbed body 92 is adsorbed by the double-pole electrostatic chuck 80.

[0194] An example in which the double-pole electrostatic chuck is used in a bonding apparatus for a semiconductor wafer is described. As shown in FIG. 1, the bonding apparatus 10 has a first stage 36 and a second stage 38. The first stage 36 and the second stage 38 are arranged so as to face each other. The first stage 36 and the second stage 38 are arranged so as to be movable in the vertical direction. Figure 9 As shown, the electrostatic chuck 80 is preferably built in the first stage 36 and the second stage 38, respectively. For the convenience of explanation, the electrostatic chuck 80 built in the first stage 36 is called a first electrostatic chuck 80A, and the electrostatic chuck 80 built in the second stage 38 is called a second electrostatic chuck 80B. Each electrostatic chuck 80A, 80B is, for example, of a double-pole type. Since the first stage 36 and the second stage 38 are arranged so as to face each other, each electrostatic chuck 80A, 80B is arranged at a position opposite to each other, thereby constituting a pair of electrostatic chucks.

[0195] The first electrostatic chuck 80A has a first base substrate 88A and a first internal electrode 90A disposed on the first base substrate 88A. The first internal electrode 90A is grounded. The first base substrate 88A controls the voltage applied to the first internal electrode 90A. The first internal electrode 90A is composed of two or more adjacent first unit electrodes 91A, and positive and negative voltages are respectively applied between mutually adjacent first unit electrodes 91A.

[0196] The second electrostatic chuck 80B is disposed at a position opposite the first electrostatic chuck 80A. The second electrostatic chuck 80B has the same configuration as the first electrostatic chuck 80A, and has a second base substrate 88B and a second internal electrode 90B disposed on the second base substrate 88B. The second internal electrode 90B is grounded. The second base substrate 88B controls the voltage applied to the second internal electrode 90B. The second internal electrode 90B is composed of two or more adjacent second unit electrodes 91B, and positive and negative voltages are respectively applied between mutually adjacent second unit electrodes 91B.

[0197] Here, the first unit electrode 91A on the first electrostatic chuck 80A side and the second unit electrode 91B on the second electrostatic chuck 80B side opposite the first unit electrode 91A are respectively controlled by the first base substrate 88A and the second base substrate 88B to apply voltages of opposite polarity (positive and negative). Therefore, the first unit electrode 91A in the first internal electrode 90A of the first electrostatic chuck 80A to which a negative (-) voltage is applied is positioned opposite the second unit electrode 91B in the second internal electrode 90B of the second electrostatic chuck 80B to which a positive (+) voltage is applied. Similarly, the first unit electrode 91A in the first internal electrode 90A of the first electrostatic chuck 80A to which a positive (+) voltage is applied is positioned opposite the second unit electrode 91B in the second internal electrode 90B of the second electrostatic chuck 80B to which a negative (-) voltage is applied.

[0198] As the general principle of the bipolar electrostatic chuck 80, positive and negative voltages are respectively applied to the first internal electrode 90A and the second internal electrode 90B in a state in which the semiconductor wafer Wl is placed on the first electrostatic chuck 80A and the semiconductor wafer W2 is placed on the second electrostatic chuck 80B. As a result, positive and negative charges of the semiconductor wafers Wl, W2 move in directions in which they are attracted toward the respective internal electrodes 90A, 90B opposite them (dielectric polarization). As a result, an attractive force is generated between the first internal electrode 90A and the semiconductor wafer Wl and between the second internal electrode 90B and the semiconductor wafer W2, thereby fixing the semiconductor wafers Wl, W2.

[0199] As Figure 7As shown, in general, in a monopolar electrostatic chuck 78, by applying a voltage between the adsorbed body (such as a semiconductor wafer, etc.) 86 and the internal electrode 84 (also called a chuck, holding device), an electric charge is generated on the surface of the adsorbed body (such as a semiconductor wafer, etc.) 86. Specifically, if the internal electrode 84 is positively (+) charged, the surface of the adsorbed body (such as a semiconductor wafer, etc.) 86 opposite thereto is negatively (-) charged; and if the internal electrode 84 is negatively (-) charged, the surface of the adsorbed body (such as a semiconductor wafer, etc.) 86 opposite thereto is positively (+) charged. This principle is Figure 8 The same is true for the bipolar electrostatic chuck 80 shown.

[0200] Typically, the surfaces of semiconductor wafers W1 and W2 that have been plasma-treated and activated become negatively charged (or possibly positively charged). Therefore, when attempting to bond semiconductor wafers W1 and W2 with both negatively charged (or positively charged) surfaces, they will experience electrical repulsion. In this state, if the semiconductor wafers W1 and W2 are forcibly bonded together, they will repel each other, causing positional shifts and reducing the bonding accuracy of the semiconductor wafers W1 and W2.

[0201] like Figure 9 As shown, by charging the surface of the opposing semiconductor wafer W1 with a positive (negative) charge and the surface of the opposing semiconductor wafer W2 with a negative (positive) charge, the semiconductor wafers to be bonded are intentionally placed in a state of opposite polarity. This, for example, utilizes the van der Waals force (intermolecular force) and Coulomb force (electrostatic force) generated between the two to enhance the adhesion and assist in bonding the semiconductor wafers W1 and W2.

[0202] Generally speaking, objects with negative static electricity (or objects with positive static electricity) repel each other when brought close together. This is one of the fundamental properties of static electricity: charges of the same sign (for example, both negatively charged) repel each other, while charges of opposite polarity (for example, one positive and the other negative) attract each other.

[0203] By making the semiconductor wafers W1 and W2 have opposite polarities (opposite polarities) and controlling the voltage between their surfaces to prevent discharge, when the positively (+) charged semiconductor wafer W1 (or W2) comes into contact with the negatively (-) charged semiconductor wafer W2 (or W1), electrons migrate from the positively (+) charged object to the negatively (-) charged object, neutralizing the charges. This reduces the effects of static electricity and increases the bonding strength during bonding.

[0204] In a general bipolar electrostatic chuck (ESC), an electrical balance state of a semiconductor wafer surface is maintained by applying voltages of the same magnitude (absolute value magnitude) on the positive (+) side and the negative (-) side.

[0205] In contrast, instead of applying voltages of the same magnitude (absolute value magnitude) on the positive (plus sign) and negative (minus sign) sides, voltages of different magnitudes are intentionally applied, and the balance of the positive (plus sign) or negative (minus sign) is intentionally broken. In other words, from the viewpoint of the magnitude of the applied voltage, an unbalanced state is created between the positive (plus sign) voltage and the negative (minus sign) voltage.

[0206] As shown in FIG. 1, for example, a voltage of -400 volts is applied to one side of the first unit electrode 91A constituting the first internal electrode 90A of the first electrostatic chuck 80A, and a voltage of +500 volts is applied to the other side of the first unit electrode 91A. At the same time, a voltage of +400 volts is applied to one side of the second unit electrode 91B constituting the second internal electrode 90B of the second electrostatic chuck 80B, and a voltage of -500 volts is applied to the other side of the second unit electrode 91B. Figure 9 Here, in the first internal electrode 90A of the first electrostatic chuck 80A, the first unit electrode 91A on the side to which a voltage of -400 volts is applied is disposed in an opposing position to the second unit electrode 91B of the second internal electrode 90B of the second electrostatic chuck 80B, to which a voltage of +400 volts is applied. Although they differ in polarity, the absolute value magnitudes are the same.

[0207] In addition, in the first internal electrode 90A of the first electrostatic chuck 80A, the first unit electrode 91A on the other side to which a voltage of +500 volts is applied is disposed in an opposing position to the second unit electrode 91B of the second internal electrode 90B of the second electrostatic chuck 80B, to which a voltage of -500 volts is applied. Although they differ in polarity, the absolute value magnitudes are the same.

[0208] Through these, the surface of the semiconductor wafer Wl opposing the first electrostatic chuck 80A is in a state of being charged with a charge of +100 volts, which is the difference between +500 volts and -400 volts of the first electrostatic chuck 80A. Similarly, the surface of the semiconductor wafer W2 opposing the second electrostatic chuck 80B is in a state of being charged with a charge of -100 volts, which is the difference between +400 volts and -500 volts of the second electrostatic chuck 80B.

[0209]

[0210] ​At this time, floating charges are generated on the surfaces of the semiconductor wafers Wl, W2. Thus, by applying a reverse voltage between the mutually opposing internal electrodes 90A, 90B (or between unit electrodes), the semiconductor wafers Wl, W2 are strongly attracted to each other by the Coulomb force and are bonded. As a result, the generation of bubbles at the time of bonding of the semiconductor wafers Wl, W2 can be suppressed.

[0211] Here, the semiconductor wafers Wl, W2 held by the pair of electrostatic chucks 80A, 80B are preferably in a micro space (minimum space) environment of 10 μm or more and 50 μm or less. In the micro space, the semiconductor wafers Wl, W2 are bonded while maintaining a planar posture.

[0212] In addition, the present embodiment and the present example only show one mode of the present application, and the present application is not limited thereto. Variations such as design changes to the present embodiment and the present example are of course included within the technical scope of the present application.

[0213] Explanation of Symbols

[0214] 14 chamber

[0215] 16 stage

[0216] 34 semiconductor wafer bonding apparatus

[0217] 36 first stage

[0218] 38 second stage

[0219] 78 unipolar electrostatic chuck

[0220] 80 bipolar electrostatic chuck

[0221] 80A first electrostatic chuck

[0222] 80B second electrostatic chuck

[0223] 82 base substrate

[0224] 84 internal electrode

[0225] 86 adsorbed body

[0226] 88 base substrate

[0227] 88A first base substrate

[0228] 88B second base substrate

[0229] 90 internal electrode

[0230] 90A first internal electrode

[0231] 90B second internal electrode

[0232] 91A first unit electrode

[0233] 91B second unit electrode

[0234] 92 adsorbate

[0235] 102 first wafer fixing mechanism

[0236] 104 second wafer fixing mechanism

[0237] 106 first replacement device

[0238] 108 second replacement device

[0239] 110 high-frequency power supply

[0240] 112 automatic pressure control device

[0241] 114 turbo molecular pump

[0242] 200 semiconductor manufacturing system

[0243] 202 central chamber

[0244] 204 vacuum bonding chamber

[0245] 206 atomic bonding chamber

[0246] 208 spin cleaning chamber

[0247] 210 standby chamber

[0248] 212 load lock chamber

[0249] 214 wafer transfer mechanism

[0250] 216 wafer cassette

[0251] G1 silicon wafer

[0252] G2 bonded wafer

[0253] W1 semiconductor wafer

[0254] W2 semiconductor wafer

Claims

1. A semiconductor wafer bonding apparatus, characterized by comprising: After the surface of a semiconductor wafer is activated by plasma in a vacuum environment, a pair of wafers facing each other are bonded by electrostatic force to improve the bonding strength.

2. The semiconductor wafer bonding apparatus according to claim 1, wherein Before a pair of wafers facing each other are bonded, one uses a silicon electrode and the other uses a semiconductor wafer; after the silicon electrode and the semiconductor wafer are processed for the first time, the electrode is replaced by a bonding wafer, and the bonding wafer and the semiconductor wafer are processed for the second time.

3. The semiconductor wafer bonding apparatus according to claim 1 and claim 2, characterized by A pair of wafer fixing mechanisms are arranged in an up-and-down opposite position, plasma is applied between the wafers in the state that the wafer fixing mechanisms adsorb the wafers, and at least one wafer fixing mechanism is moved to bond the wafers facing each other to each other.

4. A semiconductor wafer bonding method characterized by, After the surface of a semiconductor wafer is activated by plasma in a vacuum environment, a pair of wafers facing each other are bonded by electrostatic force to improve the bonding strength.

5. The semiconductor wafer bonding method according to claim 4, wherein Before a pair of wafers facing each other are bonded, one uses a silicon electrode and the other uses a semiconductor wafer; after the silicon electrode and the semiconductor wafer are processed for the first time, the electrode is replaced by a bonding wafer, and the bonding wafer and the semiconductor wafer are processed for the second time.

6. The method of bonding a semiconductor wafer according to claim 4 and claim 5, wherein A pair of wafer fixing mechanisms are arranged in an up-and-down opposite position, plasma is applied between the wafers in the state that the wafer fixing mechanisms adsorb the wafers, and at least one wafer fixing mechanism is moved to bond the wafers facing each other to each other.

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