Pulse width modulation signal capturing method and device and electronic equipment

Abstract

The invention provides a pulse width modulation (PWM) signal capturing method and device and electronic equipment, and belongs to the technical field of electronic signals.The pulse width modulation (PWM) signal capturing method comprises the steps that when it is detected that the duty ratio of a pulse width modulation (PWM) signal is within an extreme duty ratio range, the PWM signal is captured; predicting an expected arrival time interval of the next expected edge according to a plurality of historical period parameters of the PWM signal in the sliding window; before the expected arrival time interval, the level state of the PWM signal is obtained according to a preset frequency, the synchronous count value of the timer when the expected level state is collected is recorded, and the preset frequency is higher than the timing frequency of the timer; and determining a current period parameter of the PWM signal according to the synchronous count value. The missed capture rate can be reduced when a single-channel timer is adopted to capture a PWM signal.

Description

Technical Field

[0001] This disclosure relates to the field of electronic signal technology, and in particular to a pulse width modulation signal acquisition method, apparatus and electronic device. Background Technology

[0002] Pulse Width Modulation (PWM) is a technique that controls analog signals by modulating the width of pulses. It converts digital signals into analog signals and controls the average voltage or current of the output signal by changing the duty cycle of the pulses (the ratio of the high-level pulse width to the total pulse width), thereby controlling various devices such as motor speed control, light brightness adjustment, and audio signal processing.

[0003] A PWM controller generates a square wave signal with a specific frequency and different duty cycles based on the input control signal. This square wave signal consists of alternating high and low levels; its frequency determines the signal's rate of change, while the duty cycle is the ratio of the high-level pulse width to the total pulse width. When the square wave signal is high, the load is switched on, and current or voltage is applied to it; when the square wave signal is low, the load is switched off. By adjusting the duration of the high level, i.e., the pulse width, the average power received by the load is changed, thereby achieving precise control of the load.

[0004] When using a traditional single-channel timer to capture PWM signals, if there are extreme duty cycles, such as a duty cycle close to 0% (extremely low) or 100% (extremely high), the timer needs a certain amount of time to switch capture modes (e.g., from capturing the rising edge to capturing the falling edge). During the switching capture mode process, the edge may be missed. Summary of the Invention

[0005] This disclosure provides a pulse width modulation signal capture method, apparatus, and electronic device; which can reduce the missed capture rate when capturing PWM signals using a single-channel timer.

[0006] The technical solution disclosed herein is implemented as follows: In a first aspect, this disclosure provides a pulse width modulation (PWM) signal acquisition method, which includes: when the duty cycle of a PWM signal is detected to be in an extreme duty cycle range, predicting the expected arrival time interval of the next desired edge based on multiple historical period parameters of the PWM signal within a sliding window; before the expected arrival time interval, acquiring the level state of the PWM signal at a preset frequency, and recording the synchronization count value of a timer when the desired level state is acquired, wherein the preset frequency is higher than the timing frequency of the timer; and determining the current period parameters of the PWM signal based on the synchronization count value.

[0007] Secondly, this disclosure provides a pulse width modulation (PWM) signal acquisition device, comprising: a prediction module, an acquisition module, and a determination module; the prediction module is configured to predict the expected arrival time interval of the next desired edge based on multiple historical period parameters of the PWM signal within a sliding window when the duty cycle of the PWM signal is detected to be in an extreme duty cycle range; the acquisition module is configured to acquire the level state of the PWM signal at a preset frequency before the expected arrival time interval, and record the synchronization count value of a timer when the desired level state is acquired, wherein the preset frequency is higher than the timing frequency of the timer; the determination module is configured to determine the current period parameters of the PWM signal based on the synchronization count value.

[0008] Thirdly, this disclosure provides an electronic device including a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the pulse width modulation signal acquisition method as described in the first aspect.

[0009] Fourthly, this disclosure provides a computer-readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the steps of the pulse width modulation signal acquisition method as described in the first aspect.

[0010] Fifthly, this disclosure provides a computer program product, wherein the computer program product includes a computer program or instructions, which, when run on a processor, cause the processor to execute the computer program or instructions to implement the steps of the pulse width modulation signal acquisition method as described in the first aspect.

[0011] In a sixth aspect, this disclosure provides a chip including a processor and a communication interface coupled to the processor, the processor being used to run programs or instructions to implement the pulse width modulation signal acquisition method as described in the first aspect.

[0012] This disclosure provides a pulse width modulation (PWM) signal capture method. When a PWM signal is detected to be at an extreme duty cycle, the expected arrival time interval of the next desired edge is predicted by combining multiple historical period parameters of the PWM signal. Within this interval, the level state of the PWM signal is monitored at a preset frequency higher than the timing frequency of the timer. When a state change is detected, the count value of the timer is recorded synchronously. The current period parameter of the PWM signal is determined by the count value, thereby avoiding the missed detection of rising or falling edges under extreme duty cycles. Attached Figure Description

[0013] Figure 1 This is a schematic diagram illustrating the principle of capturing PWM signals using a single-channel timer, as provided in this disclosure.

[0014] Figure 2 This is a schematic diagram illustrating missed detection under extremely low duty cycles provided in this disclosure.

[0015] Figure 3 This is a schematic diagram illustrating missed detection under extremely high duty cycles provided in this disclosure.

[0016] Figure 4 This is a flowchart illustrating a pulse width modulation signal acquisition method provided in this disclosure.

[0017] Figure 5 This is a flowchart illustrating another pulse width modulation signal acquisition method provided in this disclosure.

[0018] Figure 6 This is a flowchart illustrating another pulse width modulation signal acquisition method provided in this disclosure.

[0019] Figure 7 This is a flowchart illustrating yet another pulse width modulation signal acquisition method provided in this disclosure.

[0020] Figure 8 This is a schematic diagram of missed detection under normal duty cycle provided in this disclosure.

[0021] Figure 9 This is a structural block diagram of a pulse width modulation signal acquisition device provided in this disclosure.

[0022] Figure 10 This is a schematic diagram of the hardware structure of an electronic device provided in this disclosure. Detailed Implementation

[0023] The technical solutions in the embodiments of this disclosure will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure are within the scope of protection of this disclosure.

[0024] In the field of PWM signal measurement technology, traditional methods typically rely on a dual-channel timer architecture to accurately capture signal parameters. One channel is dedicated to detecting the rising edge, and the other is responsible for detecting the falling edge. By calculating the time difference between the captured events of the two channels, the total pulse width (period) and the high-level pulse width (duty cycle, a key parameter) can be calculated simultaneously. While this architecture ensures measurement accuracy, it significantly increases hardware costs and system complexity. For resource-constrained applications (such as low-cost motor controllers and portable devices), a more streamlined solution is urgently needed. Single-channel timer capture technology has emerged to address this need. It utilizes only a single hardware channel to complete the entire signal analysis, significantly reducing hardware resource requirements and design complexity while maintaining functional integrity.

[0025] The single-channel timer capture scheme achieves full-cycle signal analysis by dynamically switching capture modes.

[0026] Specifically, in the microcontroller unit (MCU), pin P3.9 is the pulse-width modulation (PWM) input pin. Setting pin P3.9 to input mode allows it to receive PWM signals. Hardware initialization is required. First, pin configuration is performed, designating pin P3.9 in the microcontroller unit (MCU) as the PWM signal input pin. It needs to be set to input mode, specifically by setting bit 9 of address 0x4001_0DC0 to 1, ensuring the pin can correctly receive external PWM signals. Next, the timer configuration begins. The secondary function of pin P3.9 is defined as TIM3_CH1 (channel 1 of timer TIM3), indicating the binding relationship between this pin and the timer resource, laying the foundation for subsequent capture functions. Next, in the channel configuration, the operating mode of TIM3 channel 1 is set to capture mode. This is done by setting bits [3:0] of address 0x4001_0DE8 to 1, making this channel dedicated to capturing specific edges of external signals.

[0027] like Figure 1 As shown, first initialize the timer to rising edge capture mode (e.g., Figure 1 The dashed arrow indicates a rising edge. When a rising edge triggers a capture event, the timer counter is reset to zero, and the capture mode is switched to capture falling edges. The first falling edge captured subsequently (e.g., ...) Figure 1The count value corresponding to the falling edge (indicated by the solid arrow) is the high-level pulse width. At this point, the timer is reset again. The count value obtained from the second falling edge capture is the total pulse width. After two falling edge captures, the timer is switched back to rising edge capture mode, forming a periodic capture cycle of "rising edge, falling edge, falling edge".

[0028] However, for PWM signals with extreme duty cycles, the timer requires a certain amount of time to switch modes. During this time, the timer cannot capture edge changes. If the expected edge has already arrived during the mode switching process, it will result in the expected edge being missed after the switch is completed. Specifically, for example... Figure 2 As shown, under extremely low duty cycles (the high-level duration after the rising edge is extremely short), after capturing the rising edge, it is necessary to switch to capturing the falling edge. This process may miss capturing the first falling edge (the falling edge marked with an "×" in the figure); similarly, as... Figure 3 As shown, under extremely high duty cycles, after capturing the second falling edge, it is necessary to switch to capturing rising and falling edges. This process may miss capturing the next rising edge (the rising edge marked with an "×" in the figure). This missed capture will lead to inaccurate calculation of the total pulse width of the PWM signal and distortion of the duty cycle.

[0029] Based on this, the present disclosure aims to provide a pulse width modulation signal capture method that reduces the missed capture rate when capturing PWM signals using a single-channel timer.

[0030] The pulse width modulation signal acquisition method provided in this disclosure will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios. For example... Figure 4 As shown, the pulse width modulation signal acquisition method may include the following steps S401 to S403.

[0031] In step S401, when the duty cycle of the PWM signal is detected to be in an extreme duty cycle range, the expected arrival time interval of the next desired edge is predicted based on multiple historical cycle parameters of the PWM signal within the sliding window.

[0032] The extreme duty cycle range refers to the range where the PWM signal duty cycle is close to 0% or close to 100%. A threshold A is set, and the extreme duty cycle range refers to the duty cycle being greater than A or less than 100-A. The threshold A can be 5%, 2%, 1%, etc. The specific threshold A is determined according to the frequency of the timer. The higher the frequency, the smaller the value of A, and the lower the frequency, the larger the value of A.

[0033] A sliding window is a fixed-size data buffer in a time series used to store relevant information of the most recent N consecutive cycles of a PWM signal. When new data enters, the oldest data is removed and the window slides forward. N is an integer greater than 1, and its specific value is determined according to actual needs.

[0034] The parameters of a PWM signal refer to key feature quantities extracted from the historical cycles of the captured PWM signal stored in a sliding window, such as the high-level pulse width, total pulse width, and duty cycle of the historical cycle.

[0035] The expected arrival time interval refers to the time range of the next expected edge to be captured, calculated by a prediction model based on the historical period parameters of the PWM signal within the sliding window.

[0036] The prediction model determines the variation pattern of the PWM signal based on the historical period parameters of the PWM signal within the sliding window, and then predicts the expected arrival time interval of the next desired edge to be captured based on the variation pattern.

[0037] In step S402, before the expected arrival time interval, the level state of the PWM signal is acquired at a preset frequency, and the synchronization count value of the timer is recorded when the expected level state is acquired.

[0038] The preset frequency is the sampling frequency set to capture extreme PWM signals. This preset frequency is higher than the timer's timing frequency. Timer edge capture is clock-synchronized sampling, meaning the signal state is checked only at the edge of the timer clock (e.g., the rising edge). This may lead to failure in capturing extreme PWM signals if the timer's timing frequency is insufficient. Therefore, setting the preset frequency higher than the timer's timing frequency ensures that extreme PWM signals are sampled without omission. For example, for an 80 MHz timer that samples the PWM signal level every 12.5 ns, setting the preset frequency to 100 MHz would sample the PWM signal level every 10 ns.

[0039] The level state of a PWM signal refers to the logic state represented by the voltage value of the PWM signal at a certain moment, including high level (logic 1) and low level (logic 0).

[0040] The PWM signal level is detected according to a preset frequency. For example, if the preset frequency is 100 MHz, the PWM signal level is detected once every 10 ns. If the PWM signal is detected to be high in the first 10 ns, high in the second 10 ns, and low in the third 10 ns, the timer count value at the third 10 ns time is recorded synchronously.

[0041] In step S403, the current period parameters of the PWM signal are determined according to the synchronization count value.

[0042] This synchronization count value is used as the duration for the timer to capture the desired edge; that is, if the desired edge is a rising edge, the current period parameter is a low-level pulse width; if the desired edge is a falling edge, the current period parameter is a high-level pulse width. For extremely low duty cycles, this is combined with... Figure 2 It is easy to miss the first falling edge after the rising edge; the synchronization count value is the corresponding high-level pulse width. For extremely high duty cycles, combined with... Figure 3 It is easy to miss the rising edge after the second falling edge, and the synchronous count value is the corresponding low-level pulse width.

[0043] In this disclosure, when the PWM signal is detected to be at an extreme duty cycle, the expected arrival time interval of the next desired edge is predicted by combining multiple historical period parameters of the PWM signal. Within this interval, the level state of the PWM signal is monitored at a preset frequency higher than the timing frequency of the timer. When a change in state is detected, the count value of the timer is recorded synchronously. The current period parameter of the PWM signal is determined by the count value, thereby avoiding the missed detection of rising or falling edges under extreme duty cycles.

[0044] In some embodiments, such as Figure 5 As shown, the pulse width modulation signal acquisition method may include the following steps S501 to S505.

[0045] In step S501, when the duty cycle of the PWM signal is detected to be in an extreme duty cycle range, the expected arrival time interval of the next desired edge is predicted based on multiple historical cycle parameters of the PWM signal within the sliding window.

[0046] In step S502, before the expected arrival time interval, the level state of the PWM signal is acquired at a preset frequency, and the synchronization count value of the timer is recorded when the expected level state is acquired.

[0047] It should be noted that steps S501 and S502 can be referred to the descriptions of steps S401 and S402 above. To avoid repetition, they will not be repeated here.

[0048] In step S503, the desired edge capture mode of the timer is pre-configured before the expected arrival time interval.

[0049] In step S504, when the preceding edge of the desired edge is captured, the desired edge capture mode of the timer is synchronously activated.

[0050] Specifically, in some feasible methods, the expected edge capture mode of the timer can be pre-configured at time T / 2 before the expected arrival time interval. Specifically, the register corresponding to the timer capture mode is modified, including: enabling expected edge capture (e.g., falling edge bit[9]=1), disabling edge capture before the rising edge (e.g., rising edge: bit[8]=0), and setting the capture clear function (e.g., bit

[29] =1). The capture clear function refers to clearing the timer count value to zero. Since modifying the register takes a lot of time, most of the time in mode switching is spent on configuring the register. Therefore, pre-configuring the expected edge capture mode of the timer can shorten the time from the final cutting mode to the expected edge capture mode. Here, T is the average of multiple historical periods within the sliding window. Pre-configuring T / 2 is just an example. It can also be pre-configured T / 3, T / 4, etc., without limitation.

[0051] Pre-configuration does not affect the capture of the preceding edge of the desired edge, because pre-configuration does not activate the timer's desired edge capture mode; it only configures the registers. After a successful capture of the preceding edge, the desired edge capture mode is activated synchronously, making the pre-configuration effective and switching the timer capture mode to the desired edge capture mode.

[0052] For example, taking an extremely low duty cycle as an example, the high level is maintained for 10ns, and the mode switch requires 20ns. In the conventional method, since the mode switch duration is longer than the high level maintenance duration, it will lead to missed capture. In this disclosure, the earliest time of the predicted expected arrival time interval is 100ns, T is 100ns, and the time T / 2 before the expected arrival time interval is 100ns − 50ns = 50ns. That is, pre-configuration is started at 50ns, at which time the rising edge (90ns) has not yet arrived. Pre-configuration is completed at 70ns. When the rising edge is captured at 90ns, the falling edge capture mode is activated, the timer starts counting from 0, and the falling edge arrives at 100ns, and the capture is successful.

[0053] In step S505, if the timer fails to capture the desired edge within the expected arrival time interval, the current period parameter of the PWM signal is determined according to the synchronization count value.

[0054] In this disclosure, the time-consuming work during mode switching is pre-completed, and the desired edge capture mode is synchronously triggered after the preceding edge is captured, thereby avoiding missed captures due to the time consumption of mode switching. Furthermore, both hardware timers and software PWM signal level status monitoring are employed. If the timer captures the desired edge within the expected arrival time interval, the current period parameter is determined by the timer's count value; if the timer fails to capture the desired edge within the expected arrival time interval, a missed capture is determined, and the current period parameter is determined by the synchronization count value of the timer synchronized with the monitored desired level status. Thus, this dual monitoring mechanism reduces the missed capture of PWM signals with extreme duty cycles.

[0055] In some embodiments, such as Figure 6 As shown, the pulse width modulation signal acquisition method may include the following steps S601 to S606.

[0056] In step S601, it is determined whether the timer has captured the expected edge within the expected arrival time interval.

[0057] If yes, proceed to step S602; otherwise, proceed to step S603.

[0058] In step S602, the current cycle parameter is determined based on the timer's count value.

[0059] In step S603, it is determined whether the desired level state has been acquired within the expected arrival time interval.

[0060] If yes, proceed to step S604; otherwise, proceed to step S605.

[0061] In step S604, the current cycle parameter is determined based on the synchronization count value of the timer when the desired level state is acquired.

[0062] It should be noted that the relevant descriptions of steps S601 to S604 can be referred to steps S501 to S504 above. To avoid repetition, they will not be repeated here.

[0063] In step S605, when the duty cycle of the PWM signal is in an extremely low duty cycle range, the current period parameter of the PWM signal is determined based on the actual capture time and the low-level pulse width within the sliding window.

[0064] Extremely low duty cycle means that the duty cycle in step S401 above is less than the threshold A. Combined with... Figure 2At extremely low duty cycles, the first falling edge of two consecutive falling edges is missed. Therefore, if the falling edge captured after the expected arrival time interval is actually the second falling edge, the timer count corresponds to the pulse width from the rising edge to the second falling edge. That is, the actual capture time is one high-level pulse width and one total pulse width. Since the period parameters of two adjacent cycles of a PWM signal are usually small, the low-level pulse width of the previous cycle adjacent to the current cycle within the sliding window can be used as the low-level pulse width of the current cycle; or, the average of the low-level pulse widths within the sliding window can be used as the low-level pulse width of the current cycle; or, the minimum of the low-level pulse widths within the sliding window can be used as the low-level pulse width of the current cycle. The actual capture time minus the current cycle low-level pulse width is the two current cycle high-level pulse widths, and the actual capture time minus the current cycle high-level pulse width is the current cycle total pulse width.

[0065] In step S606, when the duty cycle of the PWM signal is in an extremely high duty cycle range, the current period parameter of the PWM signal is determined based on the actual capture time and the low-level pulse width within the sliding window.

[0066] Extremely high duty cycle means that the duty cycle in step S401 above is greater than the threshold A, combined with Figure 3 At extremely high duty cycles, the missed edge is the rising edge following the falling edge. Therefore, if the rising edge captured after the expected arrival time interval is actually the expected rising edge followed by a falling edge, the timer count value corresponds to the pulse width from the falling edge to the expected rising edge followed by a falling edge. That is, the actual capture time is one low-level pulse width and one total pulse width. Since the period parameters of two adjacent cycles of a PWM signal are usually small, the low-level pulse width of the previous cycle adjacent to the current cycle within the sliding window can be used as the low-level pulse width of the current cycle; or, the average low-level pulse width within the sliding window can be used as the low-level pulse width of the current cycle; or, the minimum low-level pulse width within the sliding window can be used as the low-level pulse width of the current cycle. The actual capture time minus the current cycle low-level pulse width is the current cycle total pulse width, and the current cycle total pulse width minus the current cycle low-level pulse width is the current cycle high-level pulse width.

[0067] The exception handling mechanism provided in this disclosure constructs the current cycle parameters based on the previous cycle parameters, thereby avoiding significant abnormalities in the PWM signal waveform caused by a single missed capture.

[0068] In some embodiments, predicting the expected arrival time interval of the next desired edge based on multiple historical period parameters of the PWM signal within a sliding window when the duty cycle of the PWM signal is detected to be in an extreme duty cycle range includes: predicting the expected arrival time interval based on the mean or the mean and variance of multiple historical high-level pulse widths or low-level pulse widths of the PWM signal within a sliding window when the duty cycle of the PWM signal is detected to be in an extreme duty cycle range.

[0069] Specifically, when the duty cycle of the PWM signal is in an extremely high duty cycle range, the expected arrival time interval is determined based on the mean and variance of multiple historical high-level pulse widths. The mean of the multiple historical high-level pulse widths is: The variance is ,in, t high This represents the historical high-level pulse width, N is the size of the sliding window, i is the i-th cycle within the sliding window, and the expected arrival time interval is... k is the confidence coefficient (usually 2 or 3, covering 95% to 99% probability). When the duty cycle of the PWM signal is in an extremely low duty cycle range, the expected arrival time interval is determined based on the mean and variance of multiple historical low-level pulse widths. The mean of the multiple historical low-level pulse widths is: The variance is ,in, t low This represents the historical low-level pulse width, N is the size of the sliding window, i is the i-th cycle within the sliding window, and the expected arrival time interval is... k is the confidence coefficient (usually taken as 2 or 3, covering 95% to 99% probability).

[0070] The prediction mechanism disclosed herein distinguishes between extreme high and low duty cycle scenarios. At extremely high duty cycles, it uses historical high-level pulse width statistics, and at extremely low duty cycles, it uses historical low-level pulse width statistics. This ensures that the expected arrival time interval of the next desired edge conforms to statistical laws and avoids the problem of a single statistical model failing under extreme duty cycles. When the PWM signal is in an extremely high duty cycle state for a long time, the low-level duration is too short and easily affected by noise. Selecting the high-level pulse width as the core observation object can more reliably reflect the periodic change trend. Conversely, in an extremely low duty cycle state, the high-level pulse width is extremely compressed, causing its statistics to be distorted. Effective timing information can be extracted through the low-level pulse width.

[0071] In some embodiments, when the duty cycle of the PWM signal is detected to be in an extreme duty cycle range, predicting the expected arrival time interval based on the mean or variance of multiple historical high-level pulse widths or low-level pulse widths of the PWM signal within a sliding window includes: predicting an initial time interval based on the mean or variance of multiple historical high-level pulse widths or low-level pulse widths of the PWM signal within a sliding window when the duty cycle of the PWM signal is detected to be in an extreme duty cycle range; and correcting the initial time interval to the expected arrival time interval based on the rate of change of the historical high-level pulse width or the rate of change of the historical low-level pulse width of the PWM signal in adjacent cycles within the sliding window.

[0072] Specifically, when the duty cycle of the PWM signal is in an extremely high duty cycle range, the rate of change of the high-level pulse width or the rate of change of the low-level pulse width in each adjacent period of multiple historical periods is determined, and the change law of the high-level pulse width or the low-level pulse width is determined according to the rate of change, thereby expanding or shrinking the initial time interval.

[0073] In some feasible implementations, when the duty cycle of the PWM signal is in an extremely high duty cycle range, the initial interval is [ , The k value is corrected based on the rate of change. Specifically, a high rate of change indicates severe fluctuations in the PWM signal, requiring a wider confidence interval, thus increasing the k value. A low rate of change indicates a stable PWM signal, allowing for a narrower confidence interval and a smaller k value. For example, k = 3 + β × |r|, where r represents the mean of the rate of change, and β is a sensitivity coefficient (determined empirically). If |r| = 0 (no change), k = 3; if |r| = 0.1 (10% jump), k = 4 when β = 10. When the duty cycle of the PWM signal is in an extremely high duty cycle range, the rate of change of the low-level pulse width is used to correct k. The correction process is similar to that for extremely high duty cycles and will not be elaborated here.

[0074] Thus, for stable PWM signals, narrowing the monitoring window can reduce the consumption of software polling resources; for PWM signals with drastic fluctuations, expanding the monitoring range can prevent missed detection.

[0075] In some embodiments, such as Figure 7 As shown, the pulse width modulation signal acquisition method can be implemented through the following steps S701 to S706.

[0076] In step S701, the timer's capture mode is set to capture the first edge.

[0077] In step S702, after the timer captures the first edge, the capture mode is switched to capture the second edge.

[0078] In step S703, after the timer captures the second edge twice consecutively, the total pulse width, high-level pulse width, and duty cycle of the PWM signal are determined based on the count value of the captured first edge and the count value of the two captured second edges.

[0079] The first and second edges are different edges. In some implementations, the first edge is a rising edge and the second edge is a falling edge. After capturing the rising edge, the capture mode is switched to capture the falling edge. The timer count value when the first falling edge is captured is the corresponding high-level pulse width, and the timer count value when the second falling edge is captured is the corresponding total pulse width. In other implementations, the first edge is a falling-rising edge and the second edge is a rising edge. After capturing the falling-rising edge, the capture mode is switched to capture the rising-falling edge. The timer count value when the falling edge is captured is the corresponding high-level pulse width, and the timer count value when the second falling edge is captured is the corresponding total pulse width. It should be noted that the timer is reset synchronously each time the capture mode is switched and each time a corresponding edge is successfully captured. In this way, PWM signal capture can be achieved using only one timer.

[0080] In step S704, when the duty cycle of the pulse width modulation (PWM) signal is detected to be in an extreme duty cycle range, the expected arrival time interval of the next desired edge is predicted based on multiple historical cycle parameters of the PWM signal within the sliding window.

[0081] In step S705, before the expected arrival time interval, the level state of the PWM signal is acquired at a preset frequency, and the synchronization count value of the timer is recorded when the expected level state is acquired.

[0082] In step S706, the current period parameters of the PWM signal are determined according to the synchronization count value.

[0083] It should be noted that steps S704 to S706 can be referred to the descriptions of steps S401 and S403 above, and will not be repeated here.

[0084] In some embodiments, the above-described determination of the total pulse width, high-level pulse width, and duty cycle of the PWM signal based on the count value of the captured first edge and the count values ​​of the two captured second edges after the timer captures the second edge twice includes: determining the high-level pulse width based on the difference between the count value of the previous count and the count value of the next count when the count value of the previous count is greater than the count value of the next count in the two consecutive second edges.

[0085] The first edge is a rising edge, and the second edge is a falling edge. If, in two consecutive second edges, the timer's first count value when the first second edge is captured is greater than the timer's second count value when the second second edge is captured, it means that a second edge was missed. In this case, if... Figure 8 As shown, the first count value corresponds to a high-level pulse width and a total pulse width, and the second count value corresponds to a total pulse width. Therefore, the difference between the two corresponds to the high-level pulse width. Similarly, the first edge is a rising edge, and the second edge is a falling edge. At the first and second edges, the timer count value corresponds to a low-level pulse width and a total pulse width, and at the second edge, the timer count value corresponds to the total pulse width. The difference between the two corresponds to the low-level pulse width. The total pulse width minus the low-level pulse width is the high-level pulse width.

[0086] Thus, for PWM signals whose duty cycles are not in the extreme duty cycle range, the current period parameter of the PWM signal can be calibrated even when there is a missed capture due to abnormal conditions, so as to avoid affecting the overall captured PWM signal.

[0087] Figure 9 This is a structural block diagram of a pulse width modulation signal acquisition device disclosed herein, such as... Figure 9 As shown, it includes: a prediction module 901, an acquisition module 902, and a determination module 903; the prediction module 901 is configured to predict the expected arrival time interval of the next desired edge based on multiple historical period parameters of the PWM signal within a sliding window when the duty cycle of the PWM signal is detected to be in an extreme duty cycle range; the acquisition module 902 is configured to acquire the level state of the PWM signal at a preset frequency before the expected arrival time interval, and record the synchronization count value of the timer when the desired level state is acquired, the preset frequency being higher than the timing frequency of the timer; the determination module 903 is configured to determine the current period parameters of the PWM signal based on the synchronization count value.

[0088] In some embodiments, the pulse width modulation signal capture device further includes: a pre-configuration module and an activation module. The pre-configuration module is configured to pre-configure the desired edge capture mode of the timer before the expected arrival time interval. The activation module is configured to synchronously activate the desired edge capture mode of the timer when the preceding edge of the desired edge is captured. The determination module 903 is configured to determine the current period parameter of the PWM signal according to the synchronization count value if the timer fails to capture the desired edge within the expected arrival time interval.

[0089] In some embodiments, the determining module 903 is further configured to determine the current period parameter of the PWM signal based on the actual capture time and the low-level pulse width within the sliding window when the timer fails to capture the desired edge and the desired level state is not acquired within the expected arrival time interval, and the duty cycle of the PWM signal is in an extremely low duty cycle range.

[0090] In some embodiments, the determining module 903 is further configured to determine the current period parameter of the PWM signal based on the actual capture time and the low-level pulse width within the sliding window when the timer fails to capture the desired edge and the desired level state is not acquired within the expected arrival time interval, and the duty cycle of the PWM signal is in an extremely high duty cycle range.

[0091] In some embodiments, the prediction module 901 is configured to predict the expected arrival time interval based on the mean or variance of multiple historical high-level pulse widths or low-level pulse widths of the PWM signal within a sliding window when the duty cycle of the PWM signal is detected to be in an extreme duty cycle range.

[0092] In some embodiments, the prediction module 901 is configured to, when the duty cycle of the PWM signal is detected to be in an extreme duty cycle range, predict an initial time interval based on the mean or variance of multiple historical high-level pulse widths or low-level pulse widths of the PWM signal within a sliding window; and correct the initial time interval to the expected arrival time interval based on the rate of change of the historical high-level pulse width or the rate of change of the historical low-level pulse width of the PWM signal in adjacent cycles within the sliding window.

[0093] In some embodiments, the pulse width modulation signal capture device further includes: a setting module and a switching module, the setting module being configured to set the capture mode of the timer to capture a first edge; the switching module being configured to switch the capture mode to capture a second edge after the timer captures the first edge; and the determining module 903 being configured to determine the total pulse width, high-level pulse width, and duty cycle of the PWM signal based on the count value of the captured first edge and the count value of the two captured second edges after the timer captures the second edge twice consecutively.

[0094] In some embodiments, the determining module 903 is configured to determine the high-level pulse width based on the difference between the count values ​​of the preceding and following count values ​​when the count value of the preceding count value is greater than the count value of the following count value in two consecutive second edges.

[0095] In this embodiment, each module can implement the pulse width modulation signal capture device method provided in the above method embodiment and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0096] Please refer to Figure 10This illustration shows a schematic diagram of the hardware structure of an electronic device provided in an exemplary embodiment of this disclosure. In some examples, the electronic device may be at least one of devices such as a smartphone, smartwatch, desktop computer, laptop, virtual reality terminal, augmented reality terminal, wireless terminal, and laptop computer. The electronic device has communication capabilities and can access wired or wireless networks. The term "electronic device" can refer to one of multiple terminals; those skilled in the art will understand that the number of such terminals may be more or less.

[0097] like Figure 10 As shown, the electronic device in this disclosure may include one or more of the following components: processor 1010 and memory 1020.

[0098] Optionally, the processor 1010 connects various parts within the electronic device using various interfaces and lines. It executes various functions and processes data by running or executing instructions, programs, code sets, or instruction sets stored in the memory 1020, and by calling data stored in the memory 1020. Optionally, the processor 1010 can be implemented using at least one hardware form of Digital Signal Processing (DSP), Field Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 1010 can integrate one or more of the following: Central Processing Unit (CPU), Graphics Processing Unit (GPU), Neural-network Processing Unit (NPU), and baseband chip. Specifically, the CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the content displayed on the touchscreen; the NPU implements Artificial Intelligence (AI) functions; and the baseband chip handles wireless communication. It is understandable that the aforementioned baseband chip may not be integrated into the processor 1010, but may be implemented using a separate chip.

[0099] The memory 1020 may include random access memory (RAM) or read-only memory (ROM). Optionally, the memory 1020 may include a non-transitory computer-readable storage medium. The memory 1020 may be used to store instructions, programs, code, code sets, or instruction sets. The memory 1020 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the various method embodiments described above, etc.; the data storage area may store data created based on the use of the electronic device, etc.

[0100] In addition, those skilled in the art will understand that the structure of the electronic device shown in the above figures does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown, or combine certain components, or have different component arrangements. For example, the electronic device may also include a display screen, camera assembly, microphone, speaker, radio frequency circuit, input unit, sensors (such as accelerometer, angular velocity sensor, light sensor, etc.), audio circuit, WiFi module, power supply, Bluetooth module, etc., which will not be described in detail here.

[0101] This disclosure also provides a computer-readable storage medium storing at least one instruction that is executed by a processor to implement the pulse width modulation signal acquisition method as described in the above embodiments.

[0102] This disclosure also provides a computer program product including computer instructions stored in a computer-readable storage medium; a processor of an electronic device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the electronic device to perform the pulse width modulation signal acquisition method described in the above embodiments.

[0103] This disclosure also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the above-described pulse width modulation signal acquisition method embodiments and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0104] It should be understood that the chip mentioned in the embodiments of this disclosure may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0105] In the several embodiments provided in this disclosure, it should be understood that the disclosed systems, apparatuses, servers, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between apparatuses or units through some interfaces, and may be electrical, mechanical, or other forms.

[0106] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0107] Furthermore, the functional units in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0108] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0109] Those skilled in the art will recognize that the functions described in this disclosure in one or more of the examples above can be implemented using hardware, software, firmware, or any combination thereof. When implemented in software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium accessible to a general-purpose or special-purpose computer.

[0110] It should be noted that the technical solutions described in this disclosure can be combined arbitrarily as long as they do not conflict.

[0111] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for capturing pulse width modulation signals, characterized in that, The pulse width modulation signal acquisition method includes: When the duty cycle of the pulse width modulation (PWM) signal is detected to be in an extreme duty cycle range, the expected arrival time interval of the next desired edge is predicted based on multiple historical cycle parameters of the PWM signal within the sliding window. Before the expected arrival time interval, the level state of the PWM signal is acquired at a preset frequency, and the synchronization count value of the timer when the expected level state is acquired is recorded. The preset frequency is higher than the timing frequency of the timer. The current period parameter of the PWM signal is determined based on the synchronization count value.

2. The pulse width modulation signal acquisition method according to claim 1, characterized in that, The pulse width modulation signal acquisition method further includes: The desired edge capture mode of the timer is pre-configured before the expected arrival time interval; When the preceding edge of the desired edge is captured, the desired edge capture mode of the timer is synchronously activated; Determining the current period parameter of the PWM signal according to the synchronization count value includes: If the timer fails to capture the desired edge within the expected arrival time interval, the current period parameter of the PWM signal is determined according to the synchronization count value.

3. The pulse width modulation signal acquisition method according to claim 2, characterized in that, The pulse width modulation signal acquisition method further includes: If the timer fails to capture the desired edge and acquire the desired level state within the expected arrival time interval, and the duty cycle of the PWM signal is in an extremely low duty cycle range, the current period parameter of the PWM signal is determined based on the actual capture time and the low-level pulse width within the sliding window.

4. The pulse width modulation signal acquisition method according to claim 2, characterized in that, The pulse width modulation signal acquisition method further includes: If the timer fails to capture the desired edge and acquire the desired level state within the expected arrival time interval, and the duty cycle of the PWM signal is in an extremely high duty cycle range, the current period parameter of the PWM signal is determined based on the actual capture time and the low-level pulse width within the sliding window.

5. The pulse width modulation signal acquisition method according to claim 2, characterized in that, The step of predicting the expected arrival time interval of the next desired edge based on multiple historical period parameters of the PWM signal within a sliding window when the duty cycle of the detected pulse width modulation (PWM) signal is in an extreme duty cycle range includes: When the duty cycle of the PWM signal is detected to be in an extreme duty cycle range, the expected arrival time interval is predicted based on the mean or variance of multiple historical high-level pulse widths or low-level pulse widths of the PWM signal within the sliding window.

6. The pulse width modulation signal acquisition method according to claim 5, characterized in that, When the duty cycle of the PWM signal is detected to be within an extreme duty cycle range, the expected arrival time interval is predicted based on the mean or variance of multiple historical high-level pulse widths or low-level pulse widths of the PWM signal within a sliding window, including: When the duty cycle of the PWM signal is detected to be in an extreme duty cycle range, the initial time interval is predicted based on the mean or variance of multiple historical high-level pulse widths or low-level pulse widths of the PWM signal within the sliding window. The initial time interval is corrected to the expected arrival time interval based on the rate of change of the historical high-level pulse width or the rate of change of the historical low-level pulse width of the PWM signal in adjacent cycles within the sliding window.

7. The pulse width modulation signal acquisition method according to claim 1, characterized in that, The pulse width modulation signal acquisition method further includes: Set the timer's capture mode to capture the first edge; After the timer captures the first edge, the capture mode is switched to capture the second edge; After the timer captures the second edge twice consecutively, the total pulse width, high-level pulse width, and duty cycle of the PWM signal are determined based on the count value of the captured first edge and the count value of the two captured second edges.

8. The pulse width modulation signal acquisition method according to claim 7, characterized in that, After the timer captures the second edge twice consecutively, the total pulse width, high-level pulse width, and duty cycle of the PWM signal are determined based on the count value of the captured first edge and the count values ​​of the two captured second edges, including: If the count value of the second edge is greater than the count value of the second edge in two consecutive counts, the high-level pulse width is determined based on the difference between the count value of the first count and the count value of the second count.

9. A pulse width modulation signal acquisition device, characterized in that, The pulse width modulation signal acquisition device includes: a prediction module, an acquisition module, and a determination module; The prediction module is configured to predict the expected arrival time interval of the next desired edge based on multiple historical period parameters of the PWM signal within a sliding window when the duty cycle of the pulse width modulation (PWM) signal is detected to be in an extreme duty cycle range. The acquisition module is configured to acquire the level state of the PWM signal at a preset frequency before the expected arrival time interval, and record the synchronization count value of the timer when the expected level state is acquired, wherein the preset frequency is higher than the timing frequency of the timer. The determining module is configured to determine the current period parameter of the PWM signal according to the synchronization count value.

10. An electronic device, characterized in that, It includes a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the pulse width modulation signal acquisition method as described in any one of claims 1 to 8.

Images