Data transmission method, terminal equipment and data transmission device

Abstract

The invention provides a data transmission method, terminal equipment and a data transmission device.The method is applied to a first field programmable gate array (FPGA) module of the terminal equipment, and the method comprises the steps that first data sent by a first circuit module at a first moment are received, and the first data are sent to a second circuit module through a second FPGA module, the first data is used for requesting the second circuit module to feed back data; receiving second data from a second circuit module through a second FPGA module, and storing third data in the second data at a second moment; and sending third data to the first circuit module at a third moment determined by the first circuit module, wherein the duration between the third moment and the second moment is greater than or equal to the data delay of the terminal equipment. In the application, by adjusting the moment of sending the third data to the first circuit module, the delay influence is avoided, and the transmission accuracy is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data transmission, and particularly relates to a data transmission method, a terminal device and a data transmission apparatus. BACKGROUND

[0002] A terminal device, in particular a folding mobile phone or a folding computer and the like, is more compact and portable compared with a normal terminal device of the same volume due to its foldable structure, and meets the communication and entertainment needs of users. However, the existing terminal device includes multiple circuit boards, and frequent information interaction is required between different circuit boards, so multiple cables need to be connected to ensure the efficiency and quality of data transmission between different circuit boards. However, multiple cables will cause the terminal device to become larger in size, and interference will also occur between the cables. If the number of cables is reduced to maintain a small size of the terminal device, the transmission efficiency of data between the circuit boards will be reduced, causing time delay and thus reducing the accuracy of data transmission. SUMMARY

[0003] The present application provides a data transmission method, a terminal device and a data transmission apparatus. In the present application, the time of transmitting data by the first FPGA module is adjusted to avoid time delay and improve transmission accuracy.

[0004] In a first aspect, the present application provides a data transmission method applied to a first field programmable gate array (FPGA) module of a terminal device, wherein the terminal device further includes a first circuit module connected with the first FPGA module, a second FPGA module connected with the first FPGA module, and a second circuit module connected with the second FPGA module, and the method comprises the following steps:

[0005] receiving first data sent by the first circuit module at a first time, and sending the first data to the second circuit module through the second FPGA module, wherein the first data is used to request the second circuit module to feed back data;

[0006] receiving second data from the second circuit module through the second FPGA module, and saving third data in the second data at a second time;

[0007] sending the third data to the first circuit module at a third time, wherein the third time is determined by the first circuit module, and the time length between the third time and the second time is greater than or equal to the data time delay of the terminal device.

[0008] In a second aspect, the present application provides a data transmission method applied to a first circuit module of a terminal device, the terminal device further comprising a first field programmable gate array (FPGA) module connected to the first circuit module, a second FPGA module connected to the first FPGA module, and a second circuit module connected to the second FPGA module, and the method comprising:

[0009] sending first data to the first FPGA module at a first time, the first data being transmitted to the second circuit module through the first FPGA module and the second FPGA module to request the second circuit module to feed back data;

[0010] inserting Y bytes of empty packet data into the data received from the first FPGA module, Y being a positive integer, and the length of the Y bytes being determined by taking an upper limit of the length of bytes occupied by a data time delay of the terminal device;

[0011] receiving third data sent by the first FPGA module at a third time, the third data belonging to the second data, the third time being determined by the first circuit module, and the length of time between the third time and a second time being greater than or equal to the data time delay, the second time being the time at which the first FPGA module receives second data from the second circuit module through the second FPGA module and saves the third data.

[0012] In a third aspect, the embodiments of the present application provide a data transmission method applied to a terminal device, the terminal device comprising a first field programmable gate array (FPGA) module, a second FPGA module, a first circuit module, and a second circuit module, the first circuit module, the first FPGA module, the second FPGA module, and the second circuit module being connected in sequence, and the method comprising:

[0013] the first circuit module sending first data to the first FPGA module at a first time, the first data being used to request the second circuit module to feed back data;

[0014] the first FPGA module receiving the first data and sending the first data to the second circuit module through the second FPGA module;

[0015] the second circuit module sending second data to the first FPGA module through the second FPGA module after receiving the first data;

[0016] the first FPGA module receiving the second data and saving third data in the second data at a second time;

[0017] The first FPGA module sends the third data to the first circuit module at a third time, the third time is determined by the first circuit module, and a time length between the third time and the second time is greater than or equal to a data time delay of the terminal device.

[0018] In a fourth aspect, an embodiment of the present application provides a terminal device, which comprises a first field programmable gate array (FPGA) module, a second FPGA module, a first circuit module and a second circuit module, the first circuit module, the first FPGA module, the second FPGA module and the second circuit module are connected in sequence, and the terminal device is configured to execute the data transmission method in the first aspect, the second aspect or the third aspect.

[0019] In a fifth aspect, an embodiment of the present application provides an electronic device, which comprises a processor, a communication module, a memory, a communication interface and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the processor, and the programs comprise instructions for executing steps in any method in the first aspect, the second aspect or the third aspect.

[0020] In a sixth aspect, an embodiment of the present application provides a computer readable storage medium, which stores a computer program for electronic data exchange, wherein the computer program causes a computer to execute some or all steps described in any method in the first aspect, the second aspect or the third aspect.

[0021] In a seventh aspect, the present application provides a computer program, which is operable to cause a computer to execute some or all steps described in any method in the first aspect, the second aspect or the third aspect. The computer program can be a software installation package.

[0022] It can be seen that, in the embodiment of the present application, the first data is used to request the second circuit module to feed back data, the first FPGA module receives the first data sent by the first circuit module at the first time, and sends the first data to the second circuit module through the second FPGA module; the second FPGA module receives the second data from the second circuit module, and saves the third data in the second data at the second time; the third data is sent to the first circuit module at the third time, the third time is determined by the first circuit module, and a time length between the third time and the second time is greater than or equal to a data time delay of the terminal device, so as to avoid the time delay of the internal device of the terminal device and the transmission time delay in data transmission, and improve the accuracy of transmission. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the accompanying drawings in the following description only only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0024] Figure 1 A structural schematic diagram of a terminal device provided by the embodiment of the present application is provided.

[0025] Figure 2 A flowchart of a data transmission method provided by the embodiment of the present application is provided.

[0026] Figure 3 A time comparison diagram of the first circuit module transmitting data and the first FPGA receiving data provided by the embodiment of the present application is provided.

[0027] Figure 4 Another time comparison diagram of the first circuit module transmitting data and the first FPGA receiving data provided by the embodiment of the present application is provided.

[0028] Figure 5 A flowchart of another data transmission method provided by the embodiment of the present application is provided.

[0029] Figure 6 A MISO data diagram provided by the embodiment of the present application is provided.

[0030] Figure 7 A waveform diagram of the first circuit module and the second circuit module transmitting and receiving data provided by the embodiment of the present application is provided.

[0031] Figure 8 A flowchart of another data transmission method provided by the embodiment of the present application is provided.

[0032] Figure 9 A flowchart of another data transmission method provided by the embodiment of the present application is provided.

[0033] Figure 10 A flowchart of another data transmission method provided by the embodiment of the present application is provided.

[0034] Figure 11 A structural schematic diagram of another terminal device provided by the embodiment of the present application is provided.

[0035] Figure 12 A structural schematic diagram of a terminal device provided by the embodiment of the present application is provided.

[0036] Figure 13A functional unit composition block diagram of a data transmission device provided by an embodiment of the present application is shown in FIG. 1.

[0037] Figure 14 A functional unit composition block diagram of another data transmission device provided by an embodiment of the present application is shown in FIG. 2.

[0038] Figure 15 A functional unit composition block diagram of still another data transmission device provided by an embodiment of the present application is shown in FIG. 3. DETAILED DESCRIPTION

[0039] In order to enable persons skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by persons skilled in the art without creative labor fall within the scope of protection of the present application.

[0040] The terms "first", "second", and the like in the specification and claims of the present application and the above-described drawings are used to distinguish different objects, and are not used to describe a specific order. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but can optionally include other steps or units not listed, or can optionally include other steps or units inherent to the process, method, product, or device.

[0041] In this document, the term "embodiment" means that a specific feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The phrase appears at various places in the specification does not necessarily all refer to the same embodiment, nor is it necessarily mutually exclusive of other embodiments. It is explicitly and implicitly understood that the embodiments described herein can be combined with other embodiments.

[0042] The related terms of the present application are described below.

[0043] Related terms:

[0044] Clock signal, clock signal is the basis of sequential logic, used to determine when the state in the logic unit is updated, is a fixed cycle and independent of the signal quantity. Clock signal has a fixed clock frequency.

[0045] Serial peripheral interface (SPI) is a kind of synchronous communication bus, with high speed, full duplex and simple and easy to use.

[0046] Field Programmable Gate Array (FPGA) device belongs to a kind of semi-custom circuit in special integrated circuit, it is programmable logic array, and the problem of the original device gate circuit number less can be effectively solved.

[0047] Please refer to Figure 1 , Figure 1 A kind of terminal equipment structure schematic diagram provided in the embodiment of the application;As Figure 1 Indicated in the terminal equipment, it includes first Field Programmable Gate Array (FPGA) module, first circuit module connected with the first FPGA module, second FPGA module connected with the first FPGA module and second circuit module connected with the second FPGA module.The terminal equipment can include but not limited to folding mobile phone, upright mobile phone, tablet computer, palm computer, notebook computer, video matrix Mobile Internet Devices (MID, Mobile Internet Devices) or wearable device with data processing function etc., not specifically limited here.It can be understood that the terminal equipment in the embodiment of the application is taken folding mobile phone as an example to explain.

[0048] The following please combine Figure 2 The terminal equipment in the embodiment of the application is introduced in detail:

[0049] Figure 2 A kind of data transmission method flow schematic diagram provided in the embodiment of the application, a kind of data transmission method, applied to the first FPGA module of terminal equipment, specifically including the following steps:

[0050] Step S201, the first data sent by the first circuit module at first time is received, and the first data is sent to the second circuit module by the second FPGA module.

[0051] Wherein, the first data is used to request the second circuit module feedback data.First circuit module and first FPGA module transmit data by serial peripheral interface, second circuit module and second FPGA module transmit data by serial peripheral interface, improve data transmission efficiency.In first time, first circuit module sends first data, first FPGA module receives first data and sends to second circuit module by second FPGA module, so that the second circuit module feedback data.

[0052] Step S202, the second data from the second circuit module is received by the second FPGA module, and the third data in the second data is saved at second time.

[0053] The first FPGA module receives the second data from the second circuit module through the second FPGA module, and stores third data in the second data into a first input first output (FIFO) of the first FPGA module at a second time, to wait for a time when the first circuit module receives data, to provide support for accurate data transmission.

[0054] At step S203, the third data is sent to the first circuit module at a third time.

[0055] The third time is determined by the first circuit module, and a time length between the third time and the second time is greater than or equal to a data time delay of the terminal device. Since the first circuit module and the first FPGA module transmit data through a serial peripheral interface, the first circuit module needs to receive or send data according to the SPI protocol, but due to the influence of internal devices in the terminal device and the time delay during data transmission, the first circuit module cannot accurately receive data. Therefore, when the third time is determined to arrive, the third data is sent to the first circuit module, and the time length between the third time and the second time is greater than or equal to the data time delay, so that the first circuit module can completely receive the third data sent by the first FPGA module, avoiding the influence of the performance of internal devices in the terminal device and the time delay during data transmission, thereby meeting the SPI protocol requirements.

[0056] It can be seen that, in the example, the time when the first FPGA module sends data to the first circuit module is adjusted, thereby avoiding the time delay and improving the accuracy of data transmission.

[0057] In a possible example, a time length between the third time and the first time is N byte time lengths, N is a positive integer. A time length between the second time and a time when the second data is received is M byte time lengths, M is a positive integer, and M < N. An end time of a sum of the M byte time lengths and the data time delay is the third time.

[0058] In a specific example, a time length between the third time and the first time is N byte time lengths, N is a positive integer. A time length between the second time and a time when the second data is received is M byte time lengths, M is a positive integer. The time length between the first time and the third time and the time length between the second time and the time when the data is received are complete byte time lengths, facilitating determination of the time when data is transmitted and received, thereby synchronizing the receiving operation of the first circuit module and the transmission operation of the first FPGA module, improving transmission accuracy, and ensuring the completeness of the transmission content. For example, refer to Figure 3 , Figure 3 A time comparison diagram for the first circuit module to transmit data and the first FPGA to receive data is provided for the embodiments of the present application. As shown in Figure 3As shown, if N is 9, the time length between the third time and the first time is 9 byte time lengths, Figure 3 The long box of one minimum unit represents one byte, so 9 bytes of data can be transmitted from the first time to the third time. Since the first circuit module and the second circuit module are separated by the first FPGA module and the second FPGA module, the first data is sent by the first circuit module, and the second data is fed back by the second circuit module after receiving the first data, so there is a time difference between the time when the first FPGA module receives the second data from the second circuit module and the first time, so that the data transmitted by the first FPGA module from the second circuit module cannot be correctly received by the first circuit module. To ensure that the third data transmitted by the first FPGA module to the first circuit module can be correctly received by the first circuit module, the second data is stored in the first FPGA module at the second time, and is sent to the first circuit module at the third time. The time length between the third time and the second time is greater than or equal to the data delay of the terminal device, so as to synchronize the receiving operation of the first circuit module and the sending operation of the first FPGA module.

[0059] As can be seen, in this example, the time length between the third time and the first time is N byte time lengths, the time length between the second time and the time when the second data is received is M byte time lengths, and M and N are positive integers, which facilitates synchronization of the receiving operation of the first circuit module and the sending operation of the first FPGA module, and improves the accuracy of data transmission.

[0060] In one possible example, the time length between the third time and the second time is less than 1 byte time length.

[0061] In a specific example, the time length between the third time and the second time is less than 1 byte time length. The third time is determined by the first circuit module, for example, please refer to Figure 3 If it is determined that the time length M between the second time and the time when the second data is received is 8 byte time lengths, it can be determined that the time length corresponding to the first circuit module from the first time to the second time is greater than 8 byte time lengths, then the time when the 9th byte time length corresponding to the first circuit module ends can be determined as the third time, so as to compensate for the data delay while ensuring transmission efficiency.

[0062] As can be seen, in this example, the time length between the third time and the second time is less than 1 byte time length, so that the first circuit module receives the third data in the next complete byte, ensuring the integrity of data reception and transmission efficiency.

[0063] In one possible example, the time length between the third time and the second time is greater than or equal to 1 byte time length.

[0064] In a specific example, please refer to Figure 4 ,Figure 4 Another time diagram for comparing the time of transmitting data by the first circuit module and the time of receiving data by the first FPGA is provided for the embodiment of the present application. As shown in Figure 4 , the time length between the third time and the second time is greater than or equal to 1 byte time length, Figure 4 a long box of 1 minimum unit represents 1 byte, and 1 byte corresponds to 1 byte time length. The third time is determined by the first circuit module. For example, if the time length M between the second time and the time of receiving the second data is determined to be 7 byte time lengths, the time length of the first circuit module from the first time to the second time is greater than 7 byte time lengths, and the time of the end of the 9th byte time length corresponding to the first circuit module can be determined as the third time to make up for the data delay. At this time, the time length between the second time and the third time is greater than 1 byte time length. Or, if the data transmission delay is equal to 1 byte time length, the time length M between the second time and the time of receiving the second data is 7 byte time lengths, the time length of the first circuit module from the first time to the second time is greater than 7 byte time lengths, and the time of the end of the 8th byte time length corresponding to the first circuit module can be determined as the third time.

[0065] It can be seen that in the present example, the time length between the second time and the third time can be greater than or equal to 1 byte time length to make up for the data delay and improve the accuracy of data transmission.

[0066] In a possible example, the third time is determined by the first circuit module according to the data delay.

[0067] In a specific example, the data delay can be greater than, less than or equal to 1 byte time length, and the first circuit module needs to determine the corresponding third time according to the data delay. For example, if the data delay is less than 1 byte time length, and if the time length M between the second time and the time of receiving the second data is determined to be 8 byte time lengths, the time of the end of the 9th byte time length corresponding to the first circuit module can be determined as the third time. If the data delay is greater than 1 byte time length, for example, 1.3 byte time lengths, and if the time length M between the second time and the time of receiving the second data is determined to be 8 byte time lengths, the time of the end of the 10th byte time length corresponding to the first circuit module can be determined as the third time to make up for the data delay.

[0068] It can be seen that in the present example, the first circuit module determines the third time according to the data delay, improves the rationality of the determined third time, and further guarantees the transmission efficiency.

[0069] In a possible example, please refer to Figure 5 , Figure 5 Another flow diagram of a data transmission method is provided for the embodiment of the present application. As shown in Figure 5As shown, specifically comprising the following steps:

[0070] Step S501, receiving the first data sent by the first circuit module at the first time, and sending the first data to the second circuit module through the second FPGA module.

[0071] Wherein, step S501 is the same as step S201, and will not be repeated here.

[0072] Step S502, the second FPGA module packs the second clock data and the MISO data from the second circuit module into the second data according to byte bits, and sends it to the first FPGA module.

[0073] Wherein, the second FPGA module receives the second clock data and the MISO data of the second circuit module, and packs the second clock data and the MISO data into the second data, and then sends it to the first FPGA module.

[0074] Step S503, the first FPGA module receives the second data.

[0075] Wherein, the first FPGA module receives the second data, which provides data support for subsequent data transmission.

[0076] Step S504, saving the third data in the second data at the second time.

[0077] Wherein, the first data includes first clock data and master output slave input MOSI data; the second data includes second clock data and master input slave output MISO data; and the third data is the MISO data.

[0078] Specifically, the first data includes first clock data and master output slave input MOSI data. The first clock data includes clock signals, one clock signal period corresponds to one byte time length, and one byte time length receives one byte of data. The first circuit module transmits the first clock data to the first FPGA module, the second FPGA module and the second circuit module, so as to unify the unit time length for determining the transmission time of each module, and improve the accuracy of transmission. Specifically, the second clock data is the clock data corresponding to the MISO data transmitted by the second circuit module. If the second circuit module transmits MISO data containing 8 bytes, the second clock data corresponding to the MISO data contains 8 clock signal periods. The period of the clock signal in the second clock data is the same as the period of the clock signal in the first clock data.

[0079] The first FPGA module receives the second data, determines whether the second time has arrived, and if so, stores the third data in the second data into the first FPGA module, the third data being MISO data. Specifically, a preset number of bytes of MISO data is set, and the time when the byte data of the MISO data reaches the preset number of bytes is determined as the second time. For example, if the time when 8 bytes of MISO data are received is the second time. After receiving the second data, the first FPGA module determines whether the MISO data reaches 8 bytes according to the second clock data in the second data, and if so, determines the time as the second time, and stores the MISO data into the first FPGA module.

[0080] It can be seen that the first data includes first clock data, and the first clock data is sent to each module to uniformly determine the unit time length of the time of data transmission, thereby improving the accuracy of data transmission.

[0081] In step S505, the third data is sent to the first circuit module at the third time.

[0082] The first FPGA module sends the third data to the first circuit module at the third time.

[0083] It can be seen that in the example, the unit time length of the transmission time determined by each module is based on the first clock data in the first data, so that the determined transmission time is more reasonable. The first FPGA module stores the third data at the second time, and transmits the third data to the first circuit module at the third time, thereby avoiding the influence of delay and improving the accuracy of data transmission.

[0084] In one possible example, after the first time, the first circuit module inserts Y bytes of empty packet data in the received data, Y being a positive integer, and the Y byte time length being determined by the byte time length occupied by the data delay.

[0085] Specifically, the first circuit module inserts Y bytes of empty packet data in the received data, and the Y byte time length is determined by the byte time length occupied by the data delay. For example, if the delay is 1 byte, Y is 1; if the delay is 1.5 bytes, Y is 2. By rounding up, the node for transmission can be determined, thereby improving the transmission accuracy.

[0086] It can be seen that in the example, the first circuit module increases the time length of waiting to receive the third data by inserting empty packet data in the received data, thereby avoiding the influence of delay caused by data transmission and hardware performance during the transmission of the third data, so that the first circuit module can accurately receive the third data, ensuring the data transmission efficiency and improving the transmission accuracy.

[0087] In one possible example, if the first data is not the first data from the first circuit module, invalid data is sent to the first circuit module before the third data is sent. The invalid data is inserted into the empty packet data by the first circuit module so that the first circuit module can determine that the received data is the third data when the third time point is reached.

[0088] For specific examples, please refer to Figure 6 , Figure 6 This is a schematic diagram of MISO data provided in an embodiment of this application. If the first data is not the first data from the first circuit module, that is, if there is data preceding the first data, then the first FPGA module sends invalid data to the first circuit module before sending the third data. Figure 6 As shown, the transmitted MISO data may include invalid data: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00. After receiving the invalid data, the first circuit module inserts empty packet data into the invalid data to prolong the waiting time for receiving the third data. Therefore, the data received by the first circuit module is: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, empty packet data, DATA-0, DATA-1, DATA-2, ..., DATA-n.

[0089] As can be seen, in this example, the first circuit module extends the waiting time for receiving the third data by inserting empty packet data into the invalid data received before receiving the third data, thereby improving the accuracy of the received data.

[0090] For example, please see Figure 7 , Figure 7 This is a waveform diagram illustrating the data transmission and reception between the first and second circuit modules provided in an embodiment of this application. Figure 7 As shown, for example, if the MOSI data sent by the first circuit module to the first FPGA module is in sequence: 00×F1, 0×00, 0×01, 0×01, 0×74, 0×FF, 0×FF, 0×FF, 0×FF, 0×00, 0×00, 0×00, 0×00, 0×00, 0×00, 0×00, 0×00, 0×00, 0×00, 0×00, 0×00, 0×00, 0×00, 0×00, 0×00 and 0×00.

[0091] The first circuit module provides clock data. Based on the clock data corresponding to when the first circuit module sends data, the first FPGA module sends 8 bytes of data to the first circuit module: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00. The first circuit module inserts empty packet data: 0x00, thereby extending the waiting time for the third data. Upon reaching the third moment, the first FPGA retrieves the received third data from memory: 0x80, 0x80, 0x00, 0x05, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, and 0x00. These are then sequentially sent to the first circuit module. Therefore, the MISO data received by the first circuit module is: 0×00, 0×00, 0×00, 0×00, 0×00, 0×00, 0×00, 0×00, 0×80, 0×80, 0×00, 0×05, 0×09, 0×00, 0×00, 0×00, 0×00, 0×00, 0×00, 0×00, 0×00, 0×00, 0×00, 0×00, and 0×00. Among them, the 0×00 at the ninth byte is empty packet data inserted by the first circuit module itself.

[0092] The first circuit module provides clock data based on the received clock data sent by the first FPGA module, and the second circuit module sends the following MOSI data to the second circuit module: 00×F1, 0×00, 0×01, 0×01, 0×74, 0×FF, 0×FF, 0×FF, 0×FF, 0×00, 0×00, 0×00, 0×00, 0×00, 0×00, 0×00, 0×00, 0×00, 0×00, 0×00, 0×00, 0×00, 0×00, 0×00, 0×00, 0×00 and 0×00. The second FPGA module receives MISO data from the second circuit module: 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x80, 0x00, 0x05, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, and 0x00. For example... Figure 7 As shown, since the first circuit module inserts an empty data packet, the second circuit module starts transmitting the third data within the byte duration corresponding to the empty data packet of the first circuit module. This allows the first FPGA module to receive the third data while the first circuit module receives the empty data packet, ensuring the integrity of the received data.

[0093] The last bit of data of the data sent by the second FPGA module to the second circuit module and the last bit of data of the data received by the second FPGA module from the second circuit module are invalid data because they are one byte of data transmitted multiple times.

[0094] In a possible example, refer to Figure 8 , Figure 8 Another flowchart of a data transmission method provided by an embodiment of the application is shown in FIG. 4. The application provides a data transmission method applied to a first circuit module of a terminal device. The terminal device further includes a first field programmable gate array (FPGA) module connected to the first circuit module, a second FPGA module connected to the first FPGA module, and a second circuit module connected to the second FPGA module. The method includes the following steps. Figure 8 Step S801: sending first data to the first FPGA module at a first time.

[0095] The first data is transmitted to the second circuit module through the first FPGA module and the second FPGA module to request the second circuit module to feed back data. The first data includes first clock data and master output slave input (MOSI) data. The first clock data includes a clock signal, one clock signal period corresponds to one byte time length, one byte time length receives one byte of data, the first circuit module transmits the first data to the first FPGA module, and then the first FPGA module transmits the first data to the second FPGA module and the second circuit module, thereby unifying the unit time length for determining the transmission time of each module and improving the accuracy of data processing.

[0096] Step S802: inserting Y bytes of empty packet data into the data received from the first FPGA module.

[0097] Y is a positive integer, and the Y bytes of time length is determined by taking the byte time length occupied by the data time delay of the terminal device up to the integer. The first circuit module inserts Y bytes of empty packet data into the received data, and the Y bytes of time length is determined by taking the byte time length occupied by the data time delay up to the integer, so as to facilitate the determination of the transmission node. The first circuit module inserts empty packet data into the received data to prolong the waiting time, thereby improving the accuracy of the received data.

[0098] Step S803: receiving third data sent by the first circuit module at a third time.

[0099]

[0100] ​The third data belongs to the second data, the third time is determined by the first circuit module, and the time length between the third time and the second time is greater than or equal to the data delay. The second time is the time when the first FPGA module receives the second data from the second circuit module and saves the third data in the second data.

[0101] Specifically, the first circuit module receives the third data from the first FPGA module, and the first circuit module determines the third time based on the data delay. At the third time, the first FPGA module sends the third data saved at the second time to the first circuit module. The third data is data in the second data received by the first FPGA module from the second circuit module through the second FPGA module.

[0102] It can be seen that in the present example, the first circuit module inserts empty packet data in the received data, prolongs the waiting time, so that the integrity of the data received by the first FPGA module from the second FPGA module is ensured, and the influence of the delay is avoided, and the integrity and accuracy of the data received by the first circuit module are improved.

[0103] In a possible example, the time length between the third time and the first time is N byte time lengths, N being a positive integer. The time length between the second time and the time when the second data is received is M byte time lengths, M being a positive integer, and M < N. The time end point of the sum of the M byte time lengths and the data delay is the third time.

[0104] In a specific example, the time length between the third time and the first time is N byte time lengths, N being a positive integer. The time length between the second time and the time when the second data is received is M byte time lengths, M being a positive integer. The time length between the first time and the third time and the time length between the second time and the time when the data is received are complete byte time lengths, which facilitates the determination of the data receiving and transmitting time, thereby synchronizing the receiving operation of the first circuit module and the transmitting operation of the first FPGA module, improving the transmission accuracy, and ensuring the integrity of the transmission content. For example, please refer to Figure 3 As Figure 3As shown, if N is 9, the time length between the third time and the first time is 9 byte time lengths. Since the first circuit module and the second circuit module are separated by the first FPGA module and the second FPGA module, the first data is sent by the first circuit module, and the second data is fed back by the second circuit module after receiving the first data, so that there is a time difference between the time when the first FPGA module receives the second data from the second circuit module and the first time, thereby making the data from the second circuit module transmitted by the first FPGA module unable to be correctly received by the first circuit module. To ensure that the third data transmitted by the first FPGA module to the first circuit module can be correctly received by the first circuit module, the second data is stored in the first FPGA module at the second time, and is sent to the first circuit module at the third time, the time length between the third time and the second time is greater than or equal to the data delay of the terminal device, thereby synchronizing the receiving operation of the first circuit module and the sending operation of the first FPGA module.

[0105] As can be seen, in the example, the time length between the third time and the first time is N byte time lengths, the time length between the second time and the time when the second data is received is M byte time lengths, and M and N are positive integers, facilitating synchronization of the receiving operation of the first circuit module and the sending operation of the first FPGA module, and improving the accuracy of data transmission.

[0106] In a possible example, the time length between the third time and the second time is less than 1 byte time length.

[0107] In a specific example, the time length between the third time and the second time is less than 1 byte time length. The third time is determined by the first circuit module, for example, please refer to Figure 3 , if it is determined that the time length M between the second time and the time when the second data is received is 8 byte time lengths, it can be determined that the time length of the first circuit module corresponding to the time from the first time to the second time is greater than 8 byte time lengths, then the time when the 9th byte time length of the first circuit module ends can be determined as the third time, to compensate for the data delay while ensuring transmission efficiency.

[0108] As can be seen, in the example, the time length between the third time and the second time is less than 1 byte time length, so that the first circuit module receives the third data in the next complete byte, ensuring the integrity of data reception and transmission efficiency.

[0109] In a possible example, the time length between the third time and the second time is greater than or equal to 1 byte time length.

[0110] In a specific example, please refer to Figure 4 , for example Figure 4As shown, the time length between the third time and the second time is greater than or equal to 1 byte time length. The third time is determined by the first circuit module. For example, if the time length M between the second time and the time when the second data is received is 7 byte time lengths, the time length from the first time to the second time for the first circuit module is greater than 7 byte time lengths, and the time when the 9th byte time length corresponding to the first circuit module ends can be determined as the third time to make up for the data delay. At this time, the time length between the second time and the third time is greater than 1 byte time length. Alternatively, if the data transmission delay is equal to 1 byte time length, the time length M between the second time and the time when the second data is received is 7 byte time lengths, and the time length from the first time to the second time for the first circuit module is greater than 7 byte time lengths, the time when the 8th byte time length corresponding to the first circuit module ends can be determined as the third time.

[0111] As can be seen, in the present example, the time length between the second time and the third time can be greater than or equal to 1 byte time length to make up for the data delay and improve the accuracy of data transmission.

[0112] In a possible example, the third time is determined by the first circuit module according to the data delay.

[0113] In a specific example, the data delay can be greater than, less than or equal to 1 byte time length, and the first circuit module needs to determine the corresponding third time according to the data delay. For example, if the data delay is less than 1 byte time length, and if the time length M between the second time and the time when the second data is received is 8 byte time lengths, the time when the 9th byte time length corresponding to the first circuit module ends can be determined as the third time. If the data delay is greater than 1 byte time length, for example, 1.3 byte time lengths, and if the time length M between the second time and the time when the second data is received is 8 byte time lengths, the time when the 10th byte time length corresponding to the first circuit module ends can be determined as the third time to make up for the data delay.

[0114] As can be seen, in the present example, the first circuit module determines the third time according to the data delay, improves the rationality of the determined third time, and further guarantees the transmission efficiency.

[0115] In a possible example, the first data includes first clock data and master output slave input (MOSI) data; the second data includes second clock data and master input slave output (MISO) data; and the third data is the MISO data.

[0116] Specifically, the first data includes first clock data and master output slave input (MOSI) data. The first clock data includes clock signals, one clock signal period corresponds to one byte time length, and one byte time length receives one byte of data. The first circuit module transmits the first clock data to the first FPGA module, the second FPGA module and the second circuit module, thereby unifying the unit time length for determining the transmission time of each module and improving the accuracy of transmission. Specifically, the second clock data is clock data corresponding to the transmission of MISO data by the second circuit module.

[0117] The first FPGA module determines whether the second time has arrived after receiving the second data, and if so, stores the third data in the first FPGA module, the third data being MISO data. Specifically, a preset number of bytes of MISO data is preset, and the time when the byte data of the MISO data reaches the preset number of bytes is determined as the second time. For example, if the time when 8 bytes of MISO data are received is the second time. After receiving the second data, the first FPGA module determines whether the MISO data reaches 8 bytes according to the second clock data in the second data, and if so, determines the time as the second time and stores the MISO data in the first FPGA module.

[0118] It can be seen that the first data includes first clock data, which is transmitted to each module to unify the unit time length for determining the transmission time of each module and improve the accuracy of data transmission.

[0119] In one possible example, refer to Figure 9 , Figure 9 Another data transmission method provided by the embodiment of the application is shown in the flowchart as Figure 9 applied to a terminal device including a first field programmable gate array (FPGA) module, a second FPGA module, a first circuit module and a second circuit module, the first circuit module, the first FPGA module, the second FPGA module and the second circuit module being connected in sequence, the method comprising:

[0120] In step S901, the first circuit module transmits first data to the first FPGA module at a first time.

[0121] The first data is used to request the second circuit module to feed back data. The first circuit module and the first FPGA module transmit data through a serial peripheral interface, and the second circuit module and the second FPGA module transmit data through a serial peripheral interface, thereby improving the data transmission efficiency. In the first time, the first circuit module transmits the first data, thereby providing data support for subsequent data transmission.

[0122] Step S902, the first FPGA module receives the first data, and transmits the first data to the second circuit module through the second FPGA module.

[0123] Wherein, the first FPGA module receives the first data, and transmits the first data to the second circuit module through the second FPGA module, to request the second circuit module to feedback data, so as to provide data support for subsequent data transmission.

[0124] Step S903, the second circuit module receives the first data, and transmits second data to the first FPGA module through the second FPGA module.

[0125] Wherein, the second circuit module receives the first data, and transmits the second data to the first FPGA module through the second FPGA module, so as to provide data support for subsequent data transmission.

[0126] Step S904, the first FPGA module receives the second data, and saves third data in the second data at a second time.

[0127] Wherein, the first FPGA module receives the second data, and saves the third data in the second data at the second time, so as to provide data support for subsequent data transmission.

[0128] Step S905, the first FPGA module transmits the third data to the first circuit module at a third time.

[0129] Wherein, the third time is determined by the first circuit module, and the time length between the third time and the second time is greater than or equal to the data delay of the terminal device. Since the first circuit module and the first FPGA module transmit data through the serial peripheral interface, the first circuit module needs to receive or transmit data according to the SPI protocol, but due to the influence of the internal device of the terminal device and the time delay during data transmission, the first circuit module cannot meet the SPI protocol requirements. Therefore, when the third time is determined to arrive, the third data is transmitted to the first circuit module, and the time length between the third time and the second time is greater than or equal to the data delay, so that the first circuit module can accurately receive the third data transmitted by the first FPGA module, avoiding the influence of the performance of the internal device of the terminal device and the time delay during data transmission.

[0130] It can be seen that in the present example, the time of transmitting data from the first FPGA module to the first circuit module is adjusted, so as to avoid the influence of delay and improve the accuracy of data transmission.

[0131] In a possible example, a time length between the third time and the first time is N byte time lengths, N being a positive integer. A time length between the second time and the time when the second data is received is M byte time lengths, M being a positive integer, and M < N, and an end time of a sum of the M byte time lengths and the data time delay is the third time.

[0132] In a specific example, a time length between the third time and the first time is N byte time lengths, N being a positive integer. A time length between the second time and the time when the second data is received is M byte time lengths, M being a positive integer. The time length between the first time and the third time and the time length between the second time and the time when the data is received are complete byte time lengths, facilitating determination of the time when the data is received, thereby synchronizing the receiving operation of the first circuit module and the transmission operation of the first FPGA module, improving transmission accuracy, and ensuring completeness of the transmission content. For example, refer to Figure 3 As shown in Figure 3 If N is 9, the time length between the third time and the first time is 9 byte time lengths. Since the first circuit module and the second circuit module are separated by the first FPGA module and the second FPGA module, the first data is sent by the first circuit module, and the second data is fed back by the second circuit module after the first data is received, so that there is a time difference between the time when the second data from the second circuit module is received by the first FPGA module and the first time, thereby causing the data from the second circuit module transmitted by the first FPGA module to be incorrectly received by the first circuit module. To ensure that the third data transmitted by the first FPGA module to the first circuit module can be correctly received by the first circuit module, the second data is stored in the first FPGA module at the second time, and is sent to the first circuit module at the third time, the time length between the third time and the second time being greater than or equal to the data time delay of the terminal device, thereby synchronizing the receiving operation of the first circuit module and the sending operation of the first FPGA module.

[0133] It can be seen that in the example, the time length between the third time and the first time is N byte time lengths, the time length between the second time and the time when the second data is received is M byte time lengths, and M and N are positive integers, facilitating synchronization of the receiving operation of the first circuit module and the sending operation of the first FPGA module, and improving the accuracy of data transmission.

[0134] In a possible example, a time length between the third time and the second time is less than 1 byte time length.

[0135] In a specific example, the time length between the third time and the second time is less than 1 byte time length. The third time is determined by the first circuit module, for example, refer again to Figure 3If it is determined that the time length M between the second time and the time when the second data is received is 8 byte time lengths, it can be determined that the time length from the first time to the second time corresponding to the first circuit module is greater than 8 byte time lengths, and the time when the 9th byte time length corresponding to the first circuit module ends can be determined as the third time, so as to compensate for the data time delay and ensure the transmission efficiency.

[0136] As can be seen, in this example, the time length between the third time and the second time is less than 1 byte time length, so that the first circuit module receives the third data in the next complete byte, ensuring the integrity of data reception and the transmission efficiency.

[0137] In a possible example, the time length between the third time and the second time is greater than or equal to 1 byte time length.

[0138] In a specific example, refer to Figure 4 As shown in Figure 4 , the time length between the third time and the second time is greater than or equal to 1 byte time length. The third time is determined by the first circuit module. For example, if it is determined that the time length M between the second time and the time when the second data is received is 7 byte time lengths, the time length from the first time to the second time corresponding to the first circuit module is greater than 7 byte time lengths, and the time when the 9th byte time length corresponding to the first circuit module ends can be determined as the third time, so as to compensate for the data time delay. At this time, the time length between the second time and the third time is greater than 1 byte time length. Alternatively, if the data transmission time delay is equal to 1 byte time length, the time length between the second time and the time when the second data is received is M is 7 byte time lengths, the time length from the first time to the second time corresponding to the first circuit module is greater than 7 byte time lengths, and the time when the 8th byte time length corresponding to the first circuit module ends can be determined as the third time.

[0139] As can be seen, in this example, the time length between the second time and the third time can be greater than or 1 byte time length, so as to compensate for the data time delay and improve the accuracy of data transmission.

[0140] In a possible example, the third time is determined by the first circuit module according to the data time delay.

[0141] In a specific example, the data delay can be greater than, less than or equal to one byte duration, and the first circuit module needs to determine the corresponding third time point according to the data delay. For example, if the data delay is less than one byte duration, and if it is determined that the duration between the second time point and the time point when the second data is received is M, which is 8 byte durations, then the time point when the 9th byte duration corresponding to the first circuit module ends can be determined as the third time point. If the data delay is greater than one byte duration, for example, 1.3 byte durations, and if it is determined that the duration between the second time point and the time point when the second data is received is M, which is 8 byte durations, then the time point when the 10th byte duration corresponding to the first circuit module ends can be determined as the third time point to compensate for the data delay.

[0142] In one possible example, please refer to Figure 10 , Figure 10 Another flowchart of a data transmission method provided by the embodiment of the present application is shown in FIG. 10. As shown in FIG. 10, the method specifically includes the following steps: Figure 10

[0143] Step S1001, the first circuit module sends first data to the first FPGA module at a first time point.

[0144] Wherein, step S1001 is the same as step S901, and will not be repeated here.

[0145] Step S1002, the first FPGA module receives the first data and sends the first data to the second circuit module through the second FPGA module.

[0146] Wherein, step S1002 is the same as step S902, and will not be repeated here.

[0147] Step S1003, the second FPGA module packs the second clock data and the MISO data from the second circuit module as the second data according to byte bits, and sends the second data to the first FPGA module.

[0148] Wherein, after receiving the first data, the second circuit module sends the second clock data and the MISO data to the second FPGA module, the second FPGA module packs the second clock data and the MISO data from the second circuit module as the second data according to byte bits, and sends the second data to the first FPGA module, thereby providing data support for subsequent data transmission.

[0149] Step S1004, the first FPGA module receives the second data and saves third data in the second data at a second time point.

[0150] ​The first data includes first clock data and master output slave input (MOSI) data; the second data includes second clock data and master input slave output (MISO) data; and the third data is the MISO data.

[0151] Specifically, the first clock data includes clock signals, one clock signal period corresponds to one byte time length, and one byte time length receives one byte of data. The first circuit module transmits the first clock data to the first FPGA module, the second FPGA module and the second circuit module, thereby unifying the unit time length for determining the transmission time of each module.

[0152] The second clock data is clock data corresponding to the MISO data transmitted by the second circuit module, and the period of the clock signal in the second clock data is the same as the period of the clock signal in the first clock data. After the first FPGA module receives the second data, it determines whether it is the second time. If so, the third data in the second data is stored in the first FPGA module. Specifically, a preset number of bytes of MISO data is preset, and the second time is determined when the received MISO data byte data reaches the preset number of bytes.

[0153] It can be seen that the first data includes first clock data, which is sent to each module to unify the unit time length for determining the transmission time of each module, thereby improving the accuracy of data transmission.

[0154] In step S1005, the first FPGA module sends the third data to the first circuit module at the third time.

[0155] In step S1005, the first FPGA module sends the third data to the first circuit module at the third time.

[0156] It can be seen that in this example, the unit time length for determining the transmission time of each module is unified, thereby improving the accuracy of determining the transmission time. Moreover, the first FPGA module transmits the received third data to the first circuit module at the third time, thereby avoiding the influence of delay and improving the accuracy of data transmission.

[0157] In one possible example, after the first time, the first circuit module inserts Y bytes of empty packet data in the received data, Y is a positive integer, and the Y byte time length is determined by rounding up the byte time length occupied by the data delay.

[0158] Specifically, the first circuit module inserts Y bytes of empty packet data in the received data, and the Y byte time length is determined by rounding up the byte time length occupied by the data delay. For example, if the delay is 1 byte, Y is 1; if the delay is 1.5 bytes, Y is 2. By rounding up, it is convenient to determine the transmission node, thereby improving the transmission accuracy.

[0159] It can be seen that, in this example, the first circuit module increases the time length of waiting for receiving the third data by inserting empty packet data in the received data, avoids the influence of the delay caused by data transmission and hardware performance in the transmission process of the third data, and enables the first circuit module to accurately receive the third data, ensures the data transmission efficiency, and improves the transmission accuracy.

[0160] In a possible example, referring to Figure 11 , Figure 11 Another structural schematic diagram of a terminal device provided by an embodiment of the present application is shown in the terminal device shown in Figure 11 , the terminal device includes a first field programmable gate array (FPGA) module, a second FPGA module, a first circuit module, and a second circuit module, the first circuit module, the first FPGA module, the second FPGA module, and the second circuit module are connected in sequence, and the terminal device is configured to perform the data transmission method described above.

[0161] In a possible example, the first FPGA module is connected with the first circuit module through a first SPI signal line group 1101, and the first SPI signal line group 1101 includes four signal lines.

[0162] The first circuit module is connected with the first FPGA module through the first SPI signal line group 1101, and the first SPI signal line group 1101 includes four signal lines, which are a first signal line for transmitting a connection signal of the first circuit module, a second signal line for transmitting first clock data of the first circuit module, a MOSI signal line for transmitting data of the first circuit module, and a MISO signal line for transmitting data of the first circuit module.

[0163] It can be seen that, in this example, the first circuit module and the second circuit module are connected through the first SPI signal line group 1101, and the data transmission efficiency is improved.

[0164] In a possible example, referring again to Figure 11 , the second FPGA module is connected with the second circuit module through a second SPI signal line group 1102, and the second SPI signal line group 1102 includes four signal lines.

[0165] The second circuit module is connected with the second FPGA module through the second SPI signal line group 1102, and the second SPI signal line group 1102 includes four signal lines, which are a fifth signal line for transmitting a connection signal of the second circuit module, a sixth signal line for transmitting second clock data of the second circuit module, a MOSI signal line for transmitting data of the second circuit module, and a MISO signal line for transmitting data of the second circuit module.

[0166] It can be seen that in the present example, the second circuit module is connected with the second FPGA module through the second SPI signal line group 1102, thereby improving the data transmission efficiency.

[0167] In a possible example, the first circuit module and the first FPGA module, or the second circuit module and the second FPGA module, can also be provided with other communication interfaces for communication, such as 12C communication, i.e., two-wire synchronous serial communication bus, or general purpose input / output (GPIO) for data transmission. Please refer to Figure 11 In a possible example, the first 12C communication line group 1103 and the first GPIO communication line group 1104 are arranged between the first circuit module and the first FPGA module, and the second 12C communication line group 1105 and the second GPIO communication line group 1106 are arranged between the second circuit module and the second FPGA module, thereby setting multiple communication interfaces and further improving the data transmission efficiency.

[0168] In a possible example, please refer to Figure 12 , Figure 12 A structural schematic diagram of a terminal device provided by the embodiment of the present application is provided, which includes a first shell, a second shell and a connecting assembly. The terminal device further includes a first shell 11, a second shell 12 and a connecting assembly arranged between the first shell 11 and the second shell 12. The first FPGA module and the first circuit module are arranged in the first shell 11, the second FPGA module and the second circuit module are arranged in the second shell 12, the first FPGA module is connected with the second FPGA module through a transmission line 13, part of the transmission line 13 is arranged in the connecting assembly, and the first shell 11 and the second shell 12 can rotate around the connecting assembly to switch between a folded state and an unfolded state, or the first shell 11 moves away from or relative to the second shell 12 under the guidance of the connecting assembly to switch between the unfolded state and the folded state.

[0169] In the present example, the terminal device includes a first shell 11, a second shell 12 and a connecting assembly arranged between the first shell 11 and the second shell 12. Part of the transmission line 13 is arranged in the connecting assembly, and is used to transmit data between devices in the first shell 11 and the second shell 12, thereby saving the internal space of the connecting assembly. Specifically, if the terminal device is a foldable device, such as a foldable computer, the first shell 11 and the second shell 12 can be folded to switch between the unfolded state and the folded state. Figure 12As shown, when the terminal device needs to be folded, the first shell 11 and the second shell 12 of the terminal device can be rotated around the connecting assembly to switch from the unfolded state to the folded state to reduce the screen of the terminal device and facilitate carrying. When the terminal device needs to be unfolded, the first shell 11 and the second shell 12 can be rotated around the connecting assembly to switch from the folded state to the unfolded state. If the terminal device is a scroll type folding device, that is, the second shell 12 includes a receiving space for receiving the first shell 11, when the terminal device is in the collapsed state, the first shell 11 is received in the second shell 12, if the terminal device needs to be unfolded, the first shell 11 is moved away from the second shell 12 under the guidance of the connecting assembly, so that the terminal device switches from the collapsed state to the unfolded state; similarly, if the terminal device needs to be collapsed, the first shell 11 is moved relative to the second shell 12 under the guidance of the connecting assembly, so that the terminal device switches from the unfolded state to the collapsed state.

[0170] It can be seen that in the present example, the terminal device transmits data between the first shell 11 and the second shell 12 through a single transmission line 13, which ensures transmission quality while saving space in the connecting assembly, thereby reducing the weight and volume of the terminal device and improving user experience.

[0171] In one possible example, the transmission line 13 includes an input line and an output line, the input line is connected to the first FPGA module and the second FPGA module, and the output line is connected to the first FPGA and the second FPGA module.

[0172] In one possible example, the transmission line 13 includes an input line and an output line, the input line is connected to the first FPGA module and the second FPGA module, and the output line is connected to the first FPGA and the second FPGA module.

[0173] The above mainly introduces the scheme of the embodiments of the present application from the perspective of the execution process of the method. It can be understood that the electronic device includes hardware structure and / or software modules corresponding to the execution of each function in order to realize the above functions. Those skilled in the art should easily realize that the units and algorithm steps of each example described in the embodiments provided in the present text can be realized in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed in the form of hardware or computer software driven hardware depends on the specific application and design constraints of the technical scheme. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0174] The embodiments of the present application can divide the functional units of the electronic device according to the above method examples. For example, each functional unit can be divided according to each function, or two or more functions can be integrated in one processing unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit. It should be noted that the division of the units in the embodiments of the present application is illustrative, and is only a logical function division. In actual implementation, another division manner can be used.

[0175] In the case of dividing each functional module according to each function, the following will be described in combination with Figure 13 The data transmission device in the embodiments of the present application will be described in detail, Figure 13 The functional unit component block diagram of the data transmission device provided by the embodiments of the present application is as follows. The data transmission device comprises:

[0176] The first receiving unit 1301 is configured to receive first data sent by a first circuit module at a first time, and send the first data to a second circuit module through a second FPGA module, wherein the first data is used to request the second circuit module to feed back data, the first circuit module is connected to the second FPGA module through a first field programmable gate array (FPGA) module, and the second FPGA module is connected to the second circuit module.

[0177] The second receiving unit 1302 is configured to receive second data from the second circuit module through the second FPGA module, and save third data in the second data at a second time.

[0178] The first sending unit 1303 is configured to send the third data to the first circuit module at a third time, wherein the third time is determined by the first circuit module, and the time length between the third time and the second time is greater than or equal to the data time delay of the terminal device.

[0179] It can be seen that the data transmission device first receives first data sent by a first circuit module at a first time through a first FPGA module, and sends the first data to a second circuit module through a second FPGA module. Second data from the second circuit module is received through the second FPGA module, and third data in the second data is saved at a second time. The third data is sent to the first circuit module at a third time, the third time is determined by the first circuit module, and the time length between the third time and the second time is greater than or equal to the data time delay of the terminal device, so as to avoid the time delay of the internal device of the terminal device and the transmission time delay during data transmission, and improve the accuracy of transmission.

[0180] In the case of adopting respective functional modules corresponding to respective functions, the following is combined with Figure 14 Another data transmission device in the embodiment of the application is described in detail. Figure 14 The functional unit composition block diagram of another data transmission device provided by the embodiment of the application is as follows: a data transmission device comprises:

[0181] The second sending unit 1401 is configured to send first data to a first field programmable gate array (FPGA) module at a first time point, the first data is transmitted to a second circuit module through the first FPGA module and a second FPGA module to request the second circuit module to feed back data, the first FPGA module is connected to the second FPGA module, and the second FPGA module is connected to the second circuit module.

[0182] The third receiving unit 1402 is configured to insert Y bytes of empty packet data in data received from the first FPGA module, Y is a positive integer, and the length of the Y bytes is determined by taking the length of bytes occupied by the data time delay of the terminal device upwards.

[0183] The fourth receiving unit 1403 is configured to receive third data sent by the first FPGA module at a third time point, the third data belongs to the second data, the third time point is determined by the first circuit module, and the length of time between the third time point and the second time point is greater than or equal to the data time delay, the second time point is the time point at which the first FPGA module receives the second data from the second circuit module through the second FPGA module and saves the third data.

[0184] In the case of adopting an integrated unit, the following is combined with Figure 15 Another data transmission device in the embodiment of the application is described in detail. Please refer to Figure 15 , Figure 15 The functional unit composition block diagram of another data transmission device provided by the embodiment of the application is as follows: the data transmission device 1500 comprises a processing unit 1501 and a communication unit 1502, wherein the processing unit 1501 is configured to perform any step in the above method embodiments, and when performing data transmission such as sending, the communication unit 1502 can be selectively called to complete the corresponding operation.

[0185] The data transmission device 1500 can further comprise a storage unit 1503 configured to store program codes and data. The processing unit 1501 can be a processor, the communication unit 1502 can be a wireless communication module, and the storage unit 1503 can be a memory.

[0186] The processing unit 1501 is specifically configured to:

[0187] receive first data sent by the first circuit module at a first time, and send the first data to the second circuit module through the second FPGA module, the first data being used to request the second circuit module to feed back data;

[0188] receive second data from the second circuit module through the second FPGA module, and save third data in the second data at a second time;

[0189] send the third data to the first circuit module at a third time, the third time being determined by the first circuit module, and a time length between the third time and the second time being greater than or equal to a data time delay of the terminal device.

[0190] Alternatively, the processing unit 1501 is specifically configured to:

[0191] send first data to the first FPGA module at a first time, the first data being transmitted to the second circuit module through the first FPGA module and the second FPGA module to request the second circuit module to feed back data;

[0192] insert Y bytes of empty packet data in the data received from the first FPGA module, Y being a positive integer, and the Y bytes of time length being determined by taking an upper limit of a byte time length occupied by the data time delay of the terminal device;

[0193] receive third data sent by the first circuit module at a third time, the third data belonging to the second data, the third time being determined by the first circuit module, and a time length between the third time and the second time being greater than or equal to the data time delay, the second time being a time when the first FPGA module receives second data from the second circuit module through the second FPGA module and saves the third data.

[0194] The embodiment of the application further provides a computer storage medium, wherein the computer storage medium stores a computer program for electronic data exchange, and the computer program causes a computer to execute part or all steps of any method described in the above method embodiments.

[0195] The embodiment of the application further provides a computer program product, and the computer program product includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to cause a computer to execute part or all steps of any method described in the above method embodiments. The computer program product can be a software installation package, and the computer includes an electronic device.

[0196] It should be noted that, for the foregoing method embodiments, the sequences of the described actions are not the only ones that can be used to implement the present application. In some embodiments, the sequences of the actions described above can be changed or re-ordered. In some embodiments, additional actions can be added or some actions can be omitted. In some embodiments, actions can be performed simultaneously or concurrently. In some embodiments, actions can be performed by different entities than those described above. In some embodiments, actions can be performed by the same entity using different resources or in different manners. In some embodiments, actions can be performed by different entities using the same or different resources or in the same or different manners.

[0197] In the above embodiments, the description of each embodiment focuses on different aspects. For the parts not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0198] In several embodiments provided in the present application, it should be understood that the disclosed apparatus can be implemented in other manners. For example, the described apparatus embodiments are merely schematic. For example, the division of the units is merely a logical function division. There can be another division manner for the actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections can be indirect couplings or communication connections through some interfaces, devices or units, and can be electrical, mechanical or in other forms.

[0199] The units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units, i.e., can be located in one place or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purposes of the embodiments of the present application.

[0200] In addition, each functional unit in the embodiments of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

[0201] If the above integrated unit is realized in the form of a software function unit and sold or used as an independent product, it can be stored in a computer readable memory. Based on this understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a memory and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server or a network device, etc.) to execute all or part of the steps of the above-mentioned method of each embodiment of the present application. The aforementioned memory includes: a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store program codes.

[0202] A person of ordinary skill in the art can understand that all or part of the steps in the above-mentioned embodiments can be completed by instructing the relevant hardware through a program, which can be stored in a computer readable memory. The memory can include: a flash disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0203] The embodiments of the present application are described in detail above, and the specific examples are applied to the principles and implementation modes of the present application. The above embodiment description is only used to help understand the method of the present application and its core idea; at the same time, for those skilled in the art, according to the idea of the present application, the specific implementation mode and application range will be changed; in summary, the content of the specification should not be understood as a limitation of the present application.

Claims

1. A data transmission method, characterized in that, A first field-programmable gate array (FPGA) module applied to a terminal device. The terminal device further includes a first circuit module connected to the first FPGA module, a second FPGA module connected to the first FPGA module, and a second circuit module connected to the second FPGA module. The method includes: Receiving first data sent by the first circuit module at a first moment, and sending the first data to the second circuit module through the second FPGA module. The first data is used to request the second circuit module to feedback data; Receiving second data from the second circuit module through the second FPGA module, and saving third data in the second data at a second moment; Sending the third data to the first circuit module at a third moment. The third moment is determined by the first circuit module, and the time duration between the third moment and the second moment is greater than or equal to the data delay of the terminal device.

2. The method according to claim 1, wherein: The time duration between the third moment and the first moment is N byte durations, and N is a positive integer.

3. The method according to claim 2, wherein: The time duration between the second moment and the moment when the second data is received is M byte durations, M is a positive integer, and M < N. The end point of the moment of the sum of M byte durations and the data delay is the third moment.

4. The method according to claim 2, wherein: The time duration between the third moment and the second moment is less than 1 byte duration.

5. The method according to claim 2, wherein: The time duration between the third moment and the second moment is greater than or equal to 1 byte duration.

6. The method according to any one of claims 1-5, wherein: The third moment is determined by the first circuit module according to the data delay.

7. The method according to claim 1, wherein: The first data includes first clock data and master output slave input (MOSI) data; The second data includes second clock data and master input slave output (MISO) data; The third data is the MISO data.

8. The method according to claim 7, characterized in that, The receiving the second data from the second circuit module through the second FPGA module includes: The second FPGA module packs the second clock data and the MISO data from the second circuit module into the second data by byte bits and sends it to the first FPGA module; The first FPGA module receives the second data.

9. The method according to claim 1, characterized in that, The method further includes After the first moment, the first circuit module inserts Y bytes of empty packet data (Y is a positive integer) into the received data. The Y byte durations are determined by rounding up the byte durations occupied by the data delay.

10. A data transmission method, characterized in that, A first circuit module applied to a terminal device, the terminal device further comprising a first field programmable gate array (FPGA) module connected to the first circuit module, a second FPGA module connected to the first FPGA module, and a second circuit module connected to the second FPGA module, the method comprising: Sending first data to the first FPGA module at a first moment, the first data being transmitted to the second circuit module through the first FPGA module and the second FPGA module to request the second circuit module to feedback data; Inserting Y bytes of empty packet data into the data received from the first FPGA module, Y being a positive integer, and the duration of the Y bytes being determined by rounding up the byte duration occupied by the data delay of the terminal device; Receiving third data sent by the first circuit module at a third moment, the third data belonging to the second data, the third moment being determined by the first circuit module, and the duration between the third moment and the second moment being greater than or equal to the data delay, the second moment being the moment when the first FPGA module receives the second data from the second circuit module through the second FPGA module and saves the third data.

11. The method according to claim 10, wherein: The duration between the third moment and the first moment is N byte durations, N being a positive integer.

12. The method according to claim 11, wherein: The duration between the second moment and the moment when the second data is received is M byte durations, M being a positive integer, and M < N, and the end point of the moment of the sum of the M byte durations and the data delay is the third moment.

13. The method according to claim 11, wherein: The duration between the third moment and the second moment is less than 1 byte duration.

14. The method according to claim 11, wherein: The duration between the third moment and the second moment is greater than or equal to 1 byte duration.

15. The method according to any one of claims 10-14, wherein: The third moment is determined by the second circuit module according to the data delay.

16. The method according to claim 10, wherein: The first data includes first clock data and master output slave input (MOSI) data; The second data includes second clock data and master input slave output (MISO) data; The third data is the MISO data.

17. A data transmission method, characterized in that, Applied to a terminal device, the terminal device comprising a first field programmable gate array (FPGA) module, a second FPGA module, a first circuit module, and a second circuit module, the first circuit module, the first FPGA module, the second FPGA module, and the second circuit module being connected in sequence, the method comprising: The first circuit module sends first data to the first FPGA module at a first moment, the first data being used to request the second circuit module to feedback data; The first FPGA module receives the first data and sends the first data to the second circuit module through the second FPGA module; After receiving the first data, the second circuit module sends second data to the first FPGA module through the second FPGA module; The first FPGA module receives the second data and saves the third data in the second data at the second moment; The first FPGA module sends the third data to the first circuit module at the third moment, the third moment is determined by the first circuit module, and the time duration between the third moment and the second moment is greater than or equal to the data delay of the terminal device.

18. The method according to claim 17, wherein The time duration between the third moment and the first moment is N byte durations, and N is a positive integer.

19. The method according to claim 18, wherein The time duration between the second moment and the moment when the second data is received is M byte durations, M is a positive integer, and M < N. The end point of the moment of the sum of M byte durations and the data delay is the third moment.

20. The method according to claim 18, wherein The time duration between the third moment and the second moment is less than 1 byte duration.

21. The method according to claim 18, wherein The time duration between the third moment and the second moment is greater than or equal to 1 byte duration.

22. The method according to any one of claims 17-21, wherein The third moment is determined by the first circuit module according to the data delay.

23. The method according to claim 17, wherein The first data includes first clock data and master output slave input MOSI data; The second data includes second clock data and master input slave output MISO data; The third data is the MISO data.

24. The method according to claim 23, characterized in that, After receiving the first data, the second circuit module sends second data to the first FPGA module through the second FPGA module, including: The second FPGA module packs the second clock data and the MISO data from the second circuit module into the second data by byte bits and sends it to the first FPGA module.

25. The method according to claim 17, characterized in that, The method further includes: After the first moment, the first circuit module inserts Y bytes of empty packet data into the received data, Y is a positive integer, and the byte duration of the Y bytes is determined by rounding up the byte duration occupied by the data delay.

26. A terminal device, characterized in that, The terminal device includes a first field programmable gate array FPGA module, a second FPGA module, a first circuit module and a second circuit module. The first circuit module, the first FPGA module, the second FPGA module, and the second circuit module are connected in sequence. The terminal device is used to execute the data transmission method according to any one of claims 1-9, claims 10-16 or claims 17-25.

27. The terminal device according to claim 26, characterized in that, The first FPGA module is connected to the first circuit module through the first SPI signal line group, which includes four signal lines.

28. The terminal device according to claim 26, characterized in that, The second FPGA module is connected to the second circuit module through the second SPI signal line group, which includes four signal lines.

29. The terminal device according to claim 26, characterized in that, The terminal device further includes a first housing, a second housing, and a connection component disposed between the first housing and the second housing. The first FPGA module and the first circuit module are disposed within the first housing, and the second FPGA module and the second circuit module are disposed within the second housing. The first FPGA module is connected to the second FPGA module via a transmission line, a portion of which is disposed within the connection component. The first housing and the second housing can rotate around the connection component to switch between a folded state and an unfolded state. Alternatively, the first housing can move away from or relative to the second housing under the guidance of the connection component, so that the first housing and the second housing can switch between an unfolded state and a retracted state.

30. A data transmission device, characterized in that, include: The first receiving unit is used to receive the first data sent by the first circuit module at a first moment, and send the first data to the second circuit module through the second FPGA module. The first data is used to request the second circuit module to provide feedback data. The first circuit module is connected to the second FPGA module through the first field programmable gate array (FPGA) module, and the second FPGA module is connected to the second circuit module. The second receiving unit is used to receive second data from the second circuit module through the second FPGA module, and to save the third data in the second data at a second time. A first transmitting unit is configured to transmit the third data to the first circuit module at a third time, wherein the third time is determined by the first circuit module, and the duration between the third time and the second time is greater than or equal to the data delay of the terminal device.

31. A data transmission device, characterized in that, include: The second transmitting unit is used to send first data to the first field-programmable gate array (FPGA) module at a first moment. The first data is transmitted to the second circuit module after passing through the first FPGA module and the second FPGA module to request the second circuit module to provide feedback data. The first FPGA module is connected to the second FPGA module, and the second FPGA module is connected to the second circuit module. The third receiving unit is used to insert Y bytes of empty packet data into the data received from the first FPGA module, where Y is a positive integer, and the duration of the Y bytes is determined by rounding up the byte duration occupied by the data delay of the terminal device. The fourth receiving unit is used to receive the third data sent by the first circuit module at a third time. The third data belongs to the second data. The third time is determined by the first circuit module, and the duration between the third time and the second time is greater than or equal to the data delay. The second time is the time when the first FPGA module receives the second data from the second circuit module through the second FPGA module and saves the third data.

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