Nitride power device with reinforced comprehensive performance

Abstract

The invention relates to the technical field of semiconductor power devices, in particular to a nitride power device with comprehensive performance reinforcement. The nitride power device with the comprehensive performance reinforcement comprises a main power transistor and a modulator used for accurately modulating port current and voltage of the main power transistor so as to realize steady work of the main power transistor. The main power transistor is a high-power component for adjusting input / output or blocking high-voltage and high-current based on a grid electrode; the modulator is one or more of a current and voltage controller, a gate potential clamp, a substrate potential modulator, an electrostatic protection device and a short circuit protection trigger. According to the invention, the main power transistor and the modulator are integrated to realize comprehensive protection of performance degradation of the nitride power device in multiple complex environments.

Description

Technical Field

[0001] This application relates to the technical field of semiconductor power devices, and in particular to a nitride power device with enhanced overall performance. Background Technology

[0002] Nitride power devices, exemplified by high electron mobility transistors (HEMTs), exhibit superior power handling capabilities in power electronics. Compared to silicon or arsenide power devices, nitride power devices demonstrate advantages such as high frequency, high voltage, integrability, high efficiency, high temperature resistance, and radiation resistance.

[0003] To maintain compatibility with silicon power device production capacity and high cost-effectiveness, nitride materials are heteroepitaxially grown on silicon, sapphire, silicon carbide, ceramic polymer materials, and other materials. Nitride devices fabricated based on heteroepitaxial nitride materials face multiple performance degradation challenges under high voltage, high frequency, high temperature, and high energy irradiation conditions, which limits the application scenarios of nitride power devices.

[0004] The structural features of nitride power devices lie in their thin barrier layers and fragile gate structures, which exhibit low gate threshold voltage and low gate breakdown voltage. In high-end industrial power electronics applications such as aerospace, data centers, field power supplies, oil drilling, wind power, and solar power, nitride power devices operate under multiple extreme environments involving high voltage, high frequency, high temperature, high-energy radiation, or dryness.

[0005] Therefore, nitride power devices are potentially subject to several performance degradations, such as increased dynamic on-resistance, threshold voltage drift, gate false turn-on, short-circuit burnout, drain transient breakdown, gate breakdown, reverse high power loss, and electrostatic breakdown. Summary of the Invention

[0006] To reduce the risk of multiple performance degradations faced by nitride power devices under various interactive extreme environments, this application provides a nitride power device with comprehensive performance hardening.

[0007] This application provides a nitride power device with enhanced overall performance, employing the following technical solution:

[0008] A nitride power device with enhanced overall performance includes a main power transistor and a modulator for precisely regulating the port current and voltage of the main power transistor to achieve robust operation of the main power transistor. The main power transistor is a high-power component based on gate-regulated input / output or blocking of high voltage and high current. The modulator is one or more of a current-voltage controller, a gate potential clamper, a substrate potential modulator, and an electrostatic discharge protector.

[0009] In summary, this application has the following beneficial effects:

[0010] 1. Integrated Device-Level Hardening Technology. This invention integrates device-level hardening technology on a basic nitride power device, which includes at least one of the following: a stepped field plate, a locally regenerated barrier layer, or a stack of a locally regenerated barrier layer and a locally regenerated bulk p-GaN layer, a secondary gate, a second barrier layer, a source quantum pump, a drain quantum pump, or a locally in-situ oxide nitride layer. The stepped field plate is used to smooth the electric field distribution in the drift region. The locally regenerated barrier layer locally thickens the main barrier layer to increase the two-dimensional electron gas at the top of the channel layer and reduce the defects at the top of the main barrier layer. The stack of the locally regenerated barrier layer and the locally regenerated bulk p-GaN layer injects holes and emits photons into the channel layer through the locally regenerated bulk p-GaN layer to extract excess electrons generated by high-energy irradiation or hot electron bombardment and accelerate the release of trapped electrons. The secondary gate suppresses drain voltage-induced main gate threshold voltage drift, short circuits, and gate malfunctions caused by the Miller effect, such as gate false turn-on, burn-out, or gate breakdown, by pinching off the drain high voltage, limiting the source-drain current, and conducting Miller current. The second barrier layer can form negative polarization charges, two-dimensional hole gas, and electron barriers to suppress channel electrons from entering the buffer layer. The negative polarization charges assist in the depletion of the high voltage and the smoothing of the electric field in the drift region at the top of the channel layer to improve the high voltage performance of the device. The source quantum pump and drain quantum pump can extract excess electrons from the channel layer and inject holes and emit photons into the channel layer to extract excess electrons generated by high-energy irradiation or hot electron bombardment and accelerate the release of trapped electrons. The local in-situ nitride layer has high bond energy and a wide bandgap to resist the bombardment of hot electrons and high-energy particles on the nitride surface and enhances the polarization of the main barrier layer to increase the concentration of two-dimensional electron gas at the top of the channel layer.

[0011] 2. Integrated Circuit-Level Hardening Technology. This invention integrates a nitride power device with a modulator. The modulator includes at least one of the following: a current-voltage controller, a gate potential clamp, a substrate potential modulator, an electrostatic discharge (ESD) protector, or a short-circuit protection trigger. The current-voltage controller manages the voltages on the main gate and secondary gate, enabling the nitride power device to achieve high gate withstand voltage and a high gate threshold voltage. The gate potential clamp stabilizes the gate threshold voltage, suppresses drain-to-channel barrier reduction, and achieves a low reverse conduction turn-on voltage. The substrate potential modulator modulates the substrate potential of the main power transistor to achieve high source-drain withstand voltage and suppress back-gate effect-induced on-resistance decay. The ESD protector discharges electrostatic charge between ports to prevent ESD breakdown of the main power transistor. The short-circuit protection trigger clamps the transistor gate potential to the source potential at the instant a short circuit occurs, turning off the transistor channel and preventing short-circuit burnout.

[0012] 3. Bidirectional power management function. The main power transistor of the present invention is provided with a reverse withstand voltage power transistor, a dual-drive anti-parallel reverse withstand voltage power transistor, a single-drive bidirectional withstand voltage power transistor, a dual-drive bidirectional withstand voltage power transistor, or an integrated dual-drive bidirectional withstand voltage power transistor, which has bidirectional withstand voltage and current conduction capability; and when the main power transistor is a unidirectional withstand voltage power transistor, a low reverse conduction turn-on voltage is achieved through an integrated gate potential clamp. Attached Figure Description

[0013] Figure 1a An electrical layout example is shown when the main power transistor is a bidirectional voltage-resistant nitride power device;

[0014] Figure 1b An electrical layout example is shown when the main power transistor is a single-drive bidirectional withstand voltage power transistor;

[0015] Figure 1c An electrical layout example is shown when the main power transistor is a unidirectional voltage-rated power transistor;

[0016] Figure 2a The basic main power transistor or secondary power transistor is illustrated.

[0017] Figure 2b The schematic diagram illustrates the principle structure of a main power transistor or a secondary power transistor with a seed metal on a first-step field plate.

[0018] Figure 2c The schematic diagram illustrates the principle structure of a main power transistor or a secondary power transistor with self-stop selective etching of the dielectric layer;

[0019] Figure 2d The schematic diagram illustrates the principle structure of a main power transistor or a secondary power transistor with a seed metal of a second-step field plate.

[0020] Figure 2e The cross-sectional schematic diagram and device symbol of a unidirectional voltage-resistant power transistor are shown.

[0021] Figure 3a The cross-sectional schematic diagram of the epitaxial structure of a main power transistor or a secondary power transistor with a regeneration mask is shown.

[0022] Figure 3b The cross-sectional schematic diagram illustrates the principle structure of a main power transistor or a secondary power transistor with selectively etched bulk p-GaN layers;

[0023] Figure 3c The cross-sectional schematic diagrams of the main power transistor or the secondary power transistor for two optional regeneration schemes are shown.

[0024] Figure 3dThe cross-sectional schematic structure of a main power transistor or a secondary power transistor with selective etching of a bulk p-GaN layer or / and local regeneration of a bulk p-GaN layer is illustrated.

[0025] Figure 3e Cross-sectional schematic diagrams of two alternative main power transistors or secondary power transistors with regrown nitride layers are shown.

[0026] Figure 4a The cross-sectional schematic diagram of a unidirectional voltage-resistant power transistor with a second barrier layer is shown.

[0027] Figure 4b The cross-sectional schematic diagram of a unidirectional voltage-resistant power transistor with a second barrier layer and a source quantum pump is shown.

[0028] Figure 4c The schematic cross-sectional structure of a unidirectional voltage-resistant power transistor with a second barrier layer and a drain quantum pump is shown by an AA' secant line.

[0029] Figure 4d The top view and cross-sectional view of a unidirectional voltage-resistant power transistor with a second barrier layer and a drain quantum pump are shown.

[0030] Figure 4e The cross-sectional schematic diagram of a unidirectional voltage-resistant power transistor with a drain quantum pump is shown.

[0031] Figure 4f The cross-sectional schematic structure of a unidirectional breakdown voltage power transistor with the local in-situ oxynitride layer on top of the main barrier layer and the bulk p-GaN layer is illustrated.

[0032] Figure 4g The cross-sectional schematic structure and device symbol of a unidirectional voltage-resistant power transistor with the aforementioned secondary gate are illustrated.

[0033] Figure 4h The diagram illustrates the top-view schematic of a unidirectional breakdown voltage power transistor with alternating Schottky contacts and P-type ohmic contacts at the main gate.

[0034] Figure 4i The schematic cross-sectional structure of a unidirectional breakdown voltage power transistor with alternating Schottky contacts and P-type ohmic contacts at its main gate is illustrated by an AA' secant line.

[0035] Figure 4j The diagram illustrates a device symbol for a unidirectional breakdown voltage power transistor having a secondary gate and a main gate with alternating Schottky contacts and P-type ohmic contacts.

[0036] Figure 5aThe cross-sectional schematic structure and device symbol of a reverse breakdown voltage power transistor with a secondary gate, a locally regenerated barrier layer, a second barrier layer and a locally in-situ oxide nitride layer are shown.

[0037] Figure 5b The diagram illustrates a reverse breakdown power transistor having a secondary gate and a primary gate with alternating Schottky and P-type ohmic contacts.

[0038] Figure 6 The diagram illustrates a device symbol for a dual-drive anti-parallel reverse breakdown voltage power transistor having a secondary gate and a main gate with alternating Schottky contacts and P-type ohmic contacts.

[0039] Figure 7a The cross-sectional schematic structure and device symbol of a single-drive bidirectional breakdown voltage power transistor with a secondary gate, a local regenerated barrier layer, a second barrier layer and a local in-situ oxynitride layer are shown.

[0040] Figure 7b The diagram illustrates a device symbol for a single-drive bidirectional breakdown voltage power transistor having a secondary gate and a main gate with alternating Schottky contacts and P-type ohmic contacts.

[0041] Figure 8a The cross-sectional schematic structure and device symbol of a dual-drive bidirectional breakdown voltage power transistor with a secondary gate, a local regenerated barrier layer, a second barrier layer and a local in-situ oxynitride layer are shown.

[0042] Figure 8b The diagram illustrates a device symbol for a dual-drive bidirectional breakdown voltage power transistor having a secondary gate and a main gate with alternating Schottky contacts and P-type ohmic contacts.

[0043] Figure 9 The diagram illustrates a device symbol for an integrated dual-drive bidirectional breakdown voltage power transistor having a secondary gate and a main gate with alternating Schottky contacts and P-type ohmic contacts.

[0044] Figure 10 The device symbols for the optional semiconductor components of the withstand voltage transformer are shown;

[0045] Figure 11 The device symbol for the optional semiconductor components of the low-open clamp is shown.

[0046] Figure 12 The device symbol for the optional semiconductor components of the high-opening clamp is shown;

[0047] Figure 13a The illustration shows alternative layout examples of the current-voltage controller interconnected with a main power transistor or a secondary power transistor, with different numbers of ports.

[0048] Figure 13b A first alternative configuration example of the current-voltage controller is illustrated;

[0049] Figure 13c A first alternative configuration example of the current-voltage controller is illustrated;

[0050] Figure 13d A second alternative configuration example of the current-voltage controller is illustrated;

[0051] Figure 13e A third alternative configuration example of the current-voltage controller is illustrated;

[0052] Figure 13f A third alternative configuration example of the current-voltage controller is illustrated;

[0053] Figure 13g A fourth alternative configuration example of the current-voltage controller is illustrated;

[0054] Figure 13h A fifth alternative configuration example of the current-voltage controller is illustrated;

[0055] Figure 14a The illustration shows alternative layout examples of interconnecting the gate potential clamp with the main power transistor or the secondary power transistor;

[0056] Figure 14b Layout examples of optional gate potential clamps are illustrated;

[0057] Figure 15a A component example of the first optional substrate potential modulator is illustrated;

[0058] Figure 15b A component example of an optional second substrate potential modulator is illustrated;

[0059] Figure 15c -d illustrates a component example of an optional third substrate potential modulator;

[0060] Figure 16a -h illustrates a layout example of an optional substrate potential modulator interconnected with a main power transistor;

[0061] Figure 17a Layout examples of optional electrostatic discharge (ESD) protectors are illustrated;

[0062] Figure 17b A layout example of an optional electrostatic discharge (ESD) protection device interconnected with the main power transistor is illustrated.

[0063] Figure 18a-b illustrates a component example of an optional short-circuit protection trigger;

[0064] Figure 18c The illustration shows a component example of an optional short-circuit protection trigger interconnected with a main power transistor;

[0065] Figure 19 The cross-sectional schematic structure and device symbols of a commercial p-GaN gate HEMT integrated circuit platform are illustrated.

[0066] Figure 20a An example of interconnecting a current-voltage controller with a unidirectional withstand voltage power transistor is illustrated;

[0067] Figure 20b An example of a substrate potential modulator interconnected dual-drive bidirectional breakdown voltage power transistor is illustrated;

[0068] Figure 20c An example of a unidirectional breakdown voltage power transistor with gate potential clamp interconnect is illustrated;

[0069] Figure 20d An example of an electrostatic discharge (ESD) protector interconnecting the unidirectional withstand voltage power transistor is illustrated;

[0070] Figure 20e An example of interconnecting the unidirectional withstand voltage power transistor with a combined hardened electrostatic discharge protector is illustrated;

[0071] Figure 20f The illustration shows an example of the second type of substrate potential modulator interconnecting the unidirectional breakdown voltage power transistor in the off state;

[0072] Figure 20g An example of the second type of substrate potential modulator interconnecting the unidirectional breakdown voltage power transistor in the on state is illustrated;

[0073] Figure 20h The illustration shows an example of a short-circuit protection trigger interconnecting the unidirectional withstand voltage power transistor to trigger short-circuit protection.

[0074] In the figure, 01, locally regrowth barrier layer; 02, locally regrowth bulk p-GaN layer; 1, main power transistor; 1a, secondary power transistor; 2, current and voltage controller; 3, gate potential clamp; 4, substrate potential modulator; 5, withstand voltage; 6, low turn-on clamp; 7, electrostatic discharge protector; 8, high turn-on clamp; 9, drift region; 10, short-circuit protection trigger; 11, substrate layer; 12, nucleation layer; 13, buffer layer; 14, channel layer; 15, main barrier layer; 16, bulk p-GaN layer; 17, dielectric layer; 18, N-type ohmic contact; 19, Schottky contact; 21, clamping port; 22, main output port; 23, input port; 24, secondary output port; 31, potential. 31. Stable port; 32. Pull-down port; 33. Pull-up port; 41. Modulation gate port; 42. Modulation source port; 43. Modulation drain port; 51. Voltage-rated gate; 52. Voltage-rated source; 53. Voltage-rated drain; 61. Low-turn-on anode; 62. Low-turn-on cathode; 71. Static first port; 72. Static second port; 81. High-turn-on anode; 82. High-turn-on cathode; 91. Gate-source short-circuit enhancement-mode transistor; 92. Schottky diode; 94. Enhancement-mode transistor; 95. Resistor; 96. Capacitor; 97. Depletion-mode transistor; 98. Gate-source short-circuit depletion-mode transistor; 99. PN junction diode; 101. Unidirectional voltage-rated power transistor; 102. Reverse voltage-rated power transistor; 103. Dual-mode power transistor; 104. Single-drive bidirectional voltage-resistant power transistor; 105. Dual-drive bidirectional voltage-resistant power transistor; 106. Integrated dual-drive bidirectional voltage-resistant power transistor; 110. Isolation region; 111. P-type ohmic contact; 112. Stepped field plate; 113. Substrate electrode; 151. Second barrier layer; 152. Two-dimensional electron gas; 153. Two-dimensional hole gas; 155. Local in-situ oxynitride layer; 161. N-type nitride layer; 162. Lightly doped p-GaN layer; 163. Iron / hydrogen / carbon doped nitride layer; 164. Unintentionally doped nitride layer; 181. Source; 182. Drain; 191. Main gate; 192. Secondary gate; 201. First optional structure; 2 02. Second optional structure; 203. Third optional structure; 204. Fourth optional structure; 205. Fifth optional structure; 401. First substrate potential modulator; 402. Second substrate potential modulator; 403. Third substrate potential modulator; 901. First main gate port; 902. Second main gate port; 903. First power port; 904. Second power port; 905. Substrate port; 906. First gate port; 907. Second gate port; 908. First sub-gate port; 909. Second sub-gate port; 1001. Short-circuited gate port; 1002. Short-circuited source port; 1003. Short-circuited drain port; 1811. Source quantum pump; 1821. Drain quantum pump. Detailed Implementation

[0075] The present application will be further described in detail below with reference to the accompanying drawings.

[0076] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0077] In the following description, numerous specific details are set forth for explanatory purposes in order to provide a thorough understanding of the inventive concept. As part of this specification, some of the accompanying drawings of this disclosure are block diagrams illustrating structures and devices to avoid complicating the disclosed principles. For clarity, not all features of the actual embodiment need to be described. Furthermore, the language used in this disclosure has been primarily chosen for readability and instructional purposes and may not have been chosen to define or limit the subject matter of the invention in order to apply to the necessary claims to determine such inventive subject matter. Additionally, the specialized terminology used in this disclosure is for readability and instructional purposes and may not have been chosen to define or limit the subject matter of the invention in order to apply to the necessary claims to determine such inventive subject matter. References to “an embodiment” or “an embodiment” in this disclosure mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment, and multiple references to “an embodiment” or “an embodiment” should not be construed as necessarily referring to the same embodiment.

[0078] Unless explicitly defined, the terms “a,” “an,” and “the” are not intended to refer to a singular entity, but rather to include a general category whose specific examples can be used for illustration. Therefore, the use of the terms “a” or “an” can mean any number of at least one, including “a,” “one or more,” “at least one,” and “one or more.” The term “or” means any of the options and any combination of the options, including all options unless explicitly indicated that the options are mutually exclusive. The phrase “at least one of” when combined with a list of items refers to a single item in the list or any combination of items in the list. The phrase does not require all items listed unless explicitly defined as such.

[0079] This invention discloses a nitride power device with enhanced overall performance, wherein the resistors, transistors and diodes thereon are preferably monolithically integrated on a nitride substrate or monolithically integrated on a heteroepitaxial nitride substrate, and optionally formed on a printed circuit board as independent components.

[0080] The semiconductor component and port electrical layout method of this invention has multiple equivalent alternatives. To avoid redundancy, the accompanying drawings do not list all equivalent combinations of semiconductor devices or port interconnections. Those skilled in the art can make equivalent substitutions based on the technical features of this invention.

[0081] To illustrate the feasibility of this invention, see references. Figure 19 Cross-sectional structures of semiconductor devices and components based on a commercial nitride platform (silicon-based p-GaN gate HEMT integrated circuit platform) are depicted in this application. Those skilled in the art should understand that reference to... Figure 19 The cross-sectional structure shown is only an optional option.

[0082] In the accompanying drawings, "dashed boxes" are used to indicate components / modules; "hollow circles" are used to indicate ports of components / modules; "solid circles" are used to indicate nodes where wires are short-circuited; unless otherwise specified, the semiconductor components or parts involved are based on industry-standard symbols (compliant with IEC standards).

[0083] This application discloses the features and functions of a semiconductor component / module related to a nitride power device with comprehensive performance hardening, as explained below:

[0084] Regarding nitride power devices with enhanced overall performance:

[0085] (1) Features

[0086] Referring to Figure 1, the nitride power device with enhanced overall performance includes the main power transistor 1 and a modulator. Figure 1a The illustrations show electrical layout examples when the main power transistor 1 is a reverse withstand voltage power transistor 102, a dual-drive anti-parallel reverse withstand voltage power transistor 103, a dual-drive bidirectional withstand voltage power transistor 105, or an integrated dual-drive bidirectional withstand voltage power transistor 106. (Reference) Figure 1b and 1c Electrical layout examples are shown for the main power transistor 1 when it is a single-drive bidirectional withstand voltage power transistor 104 and a single-direction withstand voltage power transistor 101. To avoid redundancy, the main power transistor 1 shown in Figure 1 is equipped with the current and voltage controller 2, the gate potential clamp 3, the substrate potential modulator 4, the electrostatic discharge protector 7, and the short-circuit protection trigger 10 to demonstrate the compatibility of the circuit-level hardening technology of the present invention.

[0087] (2) Function

[0088] The present invention discloses a nitride power device with comprehensive performance reinforcement, which has higher threshold voltage, higher gate withstand voltage, higher drain-source withstand voltage, more robust nitride surface, suppression of short-circuit current, discharge of static electricity, suppression of Miller effect, substrate potential modulation or bidirectional power management functions to avoid gate mis-conduction, gate breakdown, drain transient breakdown, short-circuit burnout and increased dynamic on-resistance in the device under high voltage, high frequency, high temperature, dry or high radiation interactive environments.

[0089] Regarding main power transistor 1 or secondary power transistor 1a:

[0090] (1) Features

[0091] refer to Figure 2a The basic main power transistor 1 or secondary power transistor 1a is shown to be epitaxially formed on a substrate layer 11 in sequence with a nucleation layer 12, a buffer layer 13, a channel layer 14, and a main barrier layer 15. A bulk p-GaN layer 16, a dielectric layer 17, an N-type ohmic contact 18, a Schottky contact 19, and an isolation region 110 are formed on top of the main barrier layer 15. The N-type ohmic contact 18 is a source 181 or a drain 182 and is distributed around the bulk p-GaN layer 16. A main gate 191 is formed on top of the bulk p-GaN layer 16.

[0092] refer to Figure 2e A stepped field plate 112 is formed on the dielectric layer 17 above the main gate 191. The stepped field plate 112 is connected to the source 181 or the substrate electrode 113 at the bottom of the substrate 11. The method for forming the stepped field plate 112 is as follows, refer to... Figure 2b The seed metal of the dielectric layer 17 is deposited multiple times and the first stepped field plate 112 is evaporated to form a metal step; Reference Figure 2c The dielectric layer 17 on top of the seed metal of the first stepped field plate 112 is removed by selective etching after stopping; Reference Figure 2d Seed metal is deposited on the second stepped field plate 112; Reference Figure 2e Electroplating and deposition of the dielectric layer 17 form a unidirectional voltage-resistant power transistor 101; and either the main power transistor 1 or the secondary power transistor 1a semiconductor structure can be prepared based on the above-described formation method.

[0093] The substrate layer 11 is made of materials such as silicon, silicon carbide, diamond, sapphire, nitride, or ceramic polymer to support the nitride epitaxial layer; the nucleation layer 12, buffer layer 13, channel layer 14, main barrier layer 15, and bulk p-GaN layer 16 are nitride epitaxial layers formed based on the substrate layer 11, and the bulk p-GaN layer 16 is doped with acceptors (e.g., magnesium or zinc); the dielectric layer 17 is provided with at least one of the insulating materials such as aluminum nitride, silicon nitride, silicon oxide, aluminum oxide, hafnium oxide, and zirconium oxide; the N-type ohmic contact 18, Schottky contact 19, P-type ohmic contact 111, stepped field plate 112, or substrate electrode 113 is provided with at least one of the metal or alloy materials such as titanium, aluminum, nickel, copper, platinum, gold, tungsten, molybdenum, titanium nitride, tungsten nitride, and tantalum nitride; the isolation region 110 is formed into a high-resistivity region by ion implantation or etching to isolate each device.

[0094] refer to Figure 4h and 4i The main gate 191 may optionally be the Schottky contact 19, or an alternating distribution of the Schottky contact 19 and the P-type ohmic contact 111. The Schottky contact 19 and the bulk p-GaN layer 16 may optionally have the dielectric layer 17, or an N-type nitride layer 161, or a lightly doped p-GaN layer 162, or an oxygen / iron / hydrogen / carbon doped nitride layer 163, or an unintentionally doped nitride layer 164 to form a high gate input impedance between the Schottky contact 19 and the bulk p-GaN layer 16, thereby reducing gate leakage.

[0095] It should be noted that the nitride layers 161 to 164 contain at least one of the following metal elements: boron, aluminum, gallium, indium, and scandium, and the silicon / magnesium / oxygen / hydrogen / carbon / iron doping concentration is between 1e13 and 1e25 per cubic centimeter.

[0096] Referring to Figures 2-9, the main power transistor 1 or the secondary power transistor 1a is a unidirectional withstand voltage power transistor 101, a reverse withstand voltage power transistor 102, a dual-drive anti-parallel reverse withstand voltage power transistor 103, a unidirectional withstand voltage power transistor 104, a dual-drive bidirectional withstand voltage power transistor 105, or an integrated dual-drive bidirectional withstand voltage power transistor 106. The integrated dual-drive bidirectional withstand voltage power transistor 106 is formed in parallel with the dual-drive anti-parallel reverse withstand voltage power transistor 103 and the dual-drive bidirectional withstand voltage power transistor 105.

[0097] The main power transistor 1 or the secondary power transistor 1a may optionally include a stepped field plate 112, a locally regenerated barrier layer 01, a stack of the locally regenerated barrier layer 01 and the locally regenerated bulk p-GaN layer 02, a secondary gate 192, a second barrier layer 151, a source quantum pump 1811, a drain quantum pump 1821, or a locally in-situ oxide nitride layer 155; to avoid redundancy, refer toFigure 5a , Figure 7a , Figure 8a The reverse withstand voltage power transistor 102, the single-drive bidirectional withstand voltage power transistor 104, and the dual-drive bidirectional withstand voltage power transistor 105 are shown respectively. They are also provided with the stepped field plate 112, the locally regenerated barrier layer 01, the secondary gate 192, the second barrier layer 151, and the locally in-situ oxynitride layer 155 to demonstrate the compatibility between the device-level hardening technologies of the present invention.

[0098] (2) Function

[0099] The main power transistor 1 or the secondary power transistor 1a is a high-power component based on gate-regulated input / output or blocking of high voltage and high current. It achieves unidirectional withstand voltage, reverse blocking, or bidirectional withstand voltage functions based on different device structures. Referring to the accompanying drawings, to distinguish the main power transistor 1 with different port configurations, the main power transistor 1 or the secondary power transistor 1a has a custom device symbol.

[0100] Regarding the stacking of local regrowth barrier layer 01 or local regrowth barrier layer 01 and local regrowth bulk p-GaN layer 02:

[0101] (1) Features

[0102] refer to Figure 3e , Figure 5a , Figure 7a , Figure 8a The main power transistor 1 or / and the secondary power transistor 1a have a local regrowth barrier layer 01 or a local regrowth barrier layer 01 and a local regrowth blocky p-GaN layer 02 stacked on top of the main barrier layer 15.

[0103] refer to Figure 3a-e, its fabrication process is as follows: sequentially forming the substrate layer 11, the nucleation layer 12, the buffer layer 13, the channel layer 14, the main barrier layer 15, and the bulk p-GaN layer 16; the dielectric layer 17 formed on top of the bulk p-GaN layer 16 serves as a mask for etching and regeneration; based on the mask, the bulk p-GaN layer 16 is etched and the top of the main barrier layer 15 is partially exposed; based on the mask, the locally regenerated barrier layer 01 or the locally regenerated barrier layer 01 and the locally regenerated bulk p-GaN layer 02 are stacked; the dielectric layer 17 is cleaned and the bulk p-GaN layer 16 and the locally regenerated bulk p-GaN layer 15 are selectively etched. A bulk p-GaN layer 02 is partially regrown to partially expose the top of the main barrier layer 15 and the top of the partially regrown barrier layer 01; the N-type ohmic contact 18, the dielectric layer 17, and the isolation region 110 are formed on the top of the partially exposed main barrier layer 15 and the top of the partially regrown barrier layer 01, respectively; the main gate 191 and the P-type ohmic contact 111 are formed on the top of the bulk p-GaN layer 16 and the partially regrown bulk p-GaN layer 02, respectively, and the P-type ohmic contact 111 on the top of the partially regrown bulk p-GaN layer 02 is interconnected with the drain 182 through the Schottky contact 19;

[0104] The locally regenerated barrier layer 01, which is 1 nm to 100 nm thick, is one or more nitride stacks and contains at least one of the metal elements boron, aluminum, gallium, indium, and scandium, with a uniformly distributed composition between 5% and 100%. The locally regenerated barrier layer 01 is in contact with the drain electrode 182 in the horizontal direction and at a distance between it and the bulk p-GaN layer 16 or the Schottky contact 19 between 0 and 9 micrometers.

[0105] The locally regenerated bulk p-GaN layer 02, which is 1 nm to 200 nm thick, is in contact with the top of the locally regenerated barrier layer 01 and the bottom of the P-type ohmic contact 111; the distance between the locally regenerated bulk p-GaN layer 02 and the drain 182 is between 0 and 9 micrometers.

[0106] (2) Function

[0107] The locally regrown barrier layer 01 further generates nitrides on top of the main barrier layer 15 through a high-temperature recrystallization process to enhance the piezoelectric polarization of the bottom of the main barrier layer 15 on the top of the channel layer 14, thereby increasing the two-dimensional electron gas concentration 152 at the top of the channel layer 14. Additionally, the locally regrown barrier layer 01 has a higher quality surface, thus avoiding the high defect density at the top of the etched main barrier layer 15. The locally regrown barrier layer 01 and the locally regrown bulk p-GaN layer 02 are stacked together. Through the locally regrown bulk p-GaN layer 02, holes are injected into the channel layer 14 and photons are emitted to increase the two-dimensional electron gas concentration 152 at the top of the channel layer 14 based on the conductivity modulation effect and to accelerate trapped electron emission through the photoluminescence effect, thereby improving the dynamic characteristics of the main power transistor 1 and / or the secondary power transistor 1a.

[0108] Regarding the secondary gate 192:

[0109] (1) Features

[0110] refer to Figure 4g , Figure 4j-9 Optionally, a secondary gate 192 is provided on the main power transistor 1 and / or the secondary power transistor 1a. The secondary gate 192 is the Schottky contact 19. The secondary gate 192 is in contact with the top of the main barrier layer 15 in the drift region 9, or is located between the dielectric layer 17 and the main gate 191 or the drift region 9. If the dielectric layer 17 is provided below the secondary gate 192, its thickness is between 0 and 100 nm.

[0111] When the main power transistor 1 and / or the secondary power transistor 1a is the unidirectional withstand voltage power transistor 101, the reverse withstand voltage power transistor 102, or the unidirectional bidirectional withstand voltage power transistor 104, the number of secondary gates 192 is at least one, and the main power transistor 1 and / or the secondary power transistor 1a has four to six ports: a first main gate port 901, a first power port 903, a second power port 904, a substrate port 905, a first primary gate port 906, or a first secondary gate port 908; Reference Figure 6 The secondary gates 192 on the single-drive bidirectional withstand voltage power transistor 104 are electrically short-circuited with each other.

[0112] When the main power transistor 1 and / or the secondary power transistor 1a is the dual-drive anti-parallel reverse withstand voltage power transistor 103, the dual-drive bidirectional withstand voltage power transistor 105, or the integrated dual-drive bidirectional withstand voltage power transistor 106, the number of secondary gates 192 is at least two, and the main power transistor 1 and / or the secondary power transistor 1a has five to nine ports: a first main gate port 901, a second main gate port 902, a first power port 903, a second power port 904, a substrate port 905, a first gate port 906, a second gate port 907, a first secondary gate port 908, and a second secondary gate port 909.

[0113] The first main gate port 901 or the second main gate port 902 is interconnected with the Schottky contact 19 of the main gate 191; the first power port 903 or the second power port 904 is interconnected with the N-type ohmic contact 18; the substrate port 905 is interconnected with the substrate electrode 113; the first gate port 906 or the second gate port 907 is interconnected with the Schottky contact 19 of the secondary gate 192; and the first sub-gate port 908 or the second sub-gate port 909 is interconnected with the P-type ohmic contact 111 of the main gate 191.

[0114] (2) Function

[0115] The secondary gate 192 suppresses high-voltage-induced main gate threshold voltage drift, limits the maximum input / output current, and suppresses gate false turn-on, device burnout, or gate breakdown caused by the Miller effect by pinching off the high voltage on the drift region 9 of the main power transistor 1 and / or the secondary power transistor 1a, limiting the port current of the main power transistor 1 and / or the secondary power transistor 1a, and conducting the Miller current of the main power transistor 1 and / or the secondary power transistor 1a.

[0116] Regarding the second barrier layer 151:

[0117] (1) Features

[0118] refer to Figure 4a-4d , Figure 5a , Figure 7a , Figure 8a The second barrier layer 151 contacts the top of the buffer layer 13 and the bottom of the channel layer 14; the second barrier layer 151, which is 1 nanometer to 4 micrometer thick, is one or more nitride stacks and contains at least one of the metal elements boron, aluminum, gallium, indium, and scandium, and the uniformly distributed component is between 5% and 100%, or the component with a gradually increasing distribution increases from 0% at the bottom to 5% to 100% at the top. The thickness of the second barrier layer 151 is between 1 nanometer and 5 micrometers.

[0119] (2) Function

[0120] The second barrier layer 151 is polarized at the bottom of the channel layer 14 to form a two-dimensional hole gas 153; the second barrier layer 151 forms an electron barrier between the buffer layer 13 and the channel layer 14 to suppress channel electrons from entering the buffer layer; the negative polarization charge at the top of the second barrier layer 151 can help deplete the two-dimensional electron gas 152 at the top of the channel layer when the high voltage is reached and smooth the electric field in the drift region to improve the high voltage performance of the device.

[0121] Regarding the source quantum pump 1811 or the drain quantum pump 1821:

[0122] (1) Features

[0123] refer to Figure 4b-4d The source quantum pump 1811 and the drain quantum pump 1821 are composed of the N-type ohmic contact 18, the bulk p-GaN layer 16, the Schottky contact 19, and the P-type ohmic contact 111. The bottom of the N-type ohmic contact 18 contacts the top of the main barrier layer 15 and surrounds or partially surrounds the bulk p-GaN layer 16 in the horizontal direction. The bottom of the bulk p-GaN layer 16 contacts the top of the main barrier layer 15, and its top contacts the bottom of the P-type ohmic contact 111. The Schottky contact 19 penetrates at least from top to bottom through the main barrier layer 15, the channel layer 14, and the second barrier layer 151 in the spacer region of the bulk p-GaN layer 16 to interconnect the two-dimensional hole gas 153, the N-type ohmic contact 18, and the P-type ohmic contact 111.

[0124] refer to Figure 4e The Schottky contact 19 may optionally not penetrate the nitride and is horizontally interconnected with the N-type ohmic contact 18 and the P-type ohmic contact 111.

[0125] (2) Function

[0126] The source quantum pump 1811 and the drain quantum pump 1821 extract excess electrons from the channel layer 14 through the Schottky contact 19; the source quantum pump 1811 and the drain quantum pump 1821 inject holes into the channel layer 14 and emit photons through the P-type ohmic contact 111 and the bulk p-GaN layer 16 to accelerate the release of trapped electrons generated by high-energy irradiation or hot electron bombardment, thereby improving the dynamic characteristics of the main power transistor 1.

[0127] Regarding the local in-situ nitride layer 155:

[0128] (1) Features

[0129] refer to Figure 4f , Figure 5a , Figure 7a and Figure 8aThe main barrier layer 15, the locally regenerated barrier layer 01, or the top of the bulk p-GaN layer 16 of the main power transistor 1 and / or the secondary power transistor 1a may optionally undergo at least one plasma treatment and annealing to form a local in-situ oxide nitride layer 155; when on top of the main barrier layer 15, the local in-situ oxide nitride layer 155 is in contact with the drain 182 in the horizontal direction and is at a distance of 0 to 9 micrometers from the bulk p-GaN layer 16 or the Schottky contact 19; when on top of the bulk p-GaN layer 16, the top of the local in-situ oxide nitride layer 155 is in contact with the Schottky contact 19 and not in contact with the P-type ohmic contact 111; the local in-situ oxide nitride layer 155 is intersected between the dielectric layer 17 and the secondary gate 192 or the stepped field plate 112. The plasma treatment employs at least one of the following: hydrogen, oxygen, nitrogen, or argon plasma treatments. The power ranges from 1 to 500 W, the gas flow rate ranges from 1 to 200 sccm, and the time ranges from 30 s to 100 min. The annealing is performed in at least one of the following environments: oxygen, nitrogen, ammonia, silane, hydrogen, or argon. The temperature ranges from 100 to 1000 °C, and the time ranges from 30 s to 200 min.

[0130] (2) Function

[0131] The localized in-situ nitride layer 155 possesses high chemical bond energy and a wide bandgap, enabling it to resist bombardment of the nitride surface by hot electrons and high-energy irradiated particles, and enhances the polarization of the main barrier layer to increase the concentration of the two-dimensional electron gas 152 at the top of the channel layer. The localized in-situ nitride layer 155 reduces the surface states of the nitride to improve the dynamic characteristics of the main power transistor 1 under high voltage and high frequency.

[0132] Regarding modulators:

[0133] (1) Features

[0134] Referring to Figures 1 and 13-20, the modulator is equipped with at least one of the following: a current-voltage controller 2, a gate potential clamp 3, a substrate potential modulator 4, an electrostatic discharge protector 7, or a short-circuit protection trigger 10; the modulator is composed of the sub-power transistor 1a, a withstand voltage transformer 5, a low-turn-on clamp 6, or a high-turn-on clamp 8; Figure 20e The case demonstrates that the sub-power transistor 1a on the modulator can be optionally replaced by the "nitride power device with gate voltage management function" described in patent number 202510716194.3, or by the sub-power transistor 1a reinforced in this application.

[0135] refer to Figure 10 The withstand voltage device 5 is an enhancement-mode transistor 94 or a depletion-mode transistor 97, which has three ports: a withstand voltage gate 51, a withstand voltage source 52, and a withstand voltage drain 53.

[0136] refer to Figure 11 The low-open clamp 6 is a gate-source short-circuit enhancement-mode transistor 91, a Schottky diode 92, a resistor 95, or a gate-source short-circuit depletion-mode transistor 98, which has two ports: a low-open anode 61 and a low-open cathode 62.

[0137] refer to Figure 12 The high-open-time clamp 8 consists of M gate-source short-circuit enhancement-mode transistors 91 connected in series or M Schottky diodes 92 connected in series, and has two ports: a high-open-time anode 81 and a high-open-time cathode 82. Where M = 1, 2, 3, ...

[0138] (2) Function

[0139] The modulator precisely modulates the port current and voltage of the main power transistor 1 or the secondary power transistor 1a to achieve robust operation of the main power transistor 1 or the secondary power transistor 1a. The withstand voltage 5, the low-turn-on clamp 6, or the high-turn-on clamp 8 form the basic semiconductor module for the current and voltage controller 2, the gate potential clamp 3, the substrate potential modulator 4, the electrostatic discharge protector 7, or the short-circuit protection trigger 10.

[0140] Regarding current and voltage controller 2:

[0141] (1) Features

[0142] refer to Figure 13a The case demonstrates that the current and voltage controller 2 has three or four ports: clamping port 21, main output port 22, input port 23 or secondary output port 24, and the electrical layout features between the current and voltage controller 2 and the main power transistor 1 and / or the secondary power transistor 1a.

[0143] refer to Figure 13b-13c The example illustrates a first optional structure 201 of the current-voltage controller 2, which includes P withstand voltage transformers 5 and (P-1) low-opening clamps 6, wherein the P withstand voltage transformers 5 are E enhancement-type transistors 94 and F depletion-type transistors 97, i.e., P = F + E; P = 1, 2, 3, ...; E = 0, 1, 2, 3, ...; F = 0, 1, 2, 3, ...

[0144] The first withstand voltage source 52 of the withstand voltage transformer 5 is connected to the main output port 22.

[0145] If any one of the first to (P-1)th withstand voltage devices 5 and the first to (P-1)th low-open clamp devices 6 is defined as the Xth withstand voltage device 5 and the Xth low-open clamp device 6 respectively, then the withstand voltage gate 51 of the Xth withstand voltage device 5 is interconnected with the withstand voltage source 52 of the (X+1)th withstand voltage device 5 and the low-open cathode 62 of the Xth low-open clamp device 6.

[0146] The withstand gate 51 of the Pth withstand voltage device 5 is interconnected with the low-open anode 61 of all the low-open clamps 6 and the clamp port 21.

[0147] The withstand drain 53 of all the withstand voltage transformers 5 is connected to the input port 23.

[0148] If E≠0, then the first to the Eth voltage withstand transistor 5 are the enhancement transistor 94.

[0149] refer to Figure 13d The example demonstrates a second optional structure 202 of the current-voltage controller 2, which connects the withstand voltage gate 51 of the Nth withstand voltage transformer 5 to the secondary output port 24 based on the first optional structure 201, where 1≤N<P, N=1,2,3,….

[0150] refer to Figure 13e-13f The example demonstrates a third optional structure 203 of the current-voltage controller 2, which adds Q of the aforementioned withstand voltage devices 5 or Q of the aforementioned low-opening clamps 6 to the first optional structure 201 or the second optional structure 202. The withstand voltage gates 51 of the added Q withstand voltage devices 5 are connected to the clamping port 21, their withstand voltage sources 52 are connected to the main output port 22 or the secondary output port 24, and their withstand voltage drains 53 are connected to the input port 23. The low-opening anodes 61 of the added Q low-opening clamps 6 are connected to the main output port 22 or the secondary output port 24, and their low-opening cathodes 62 are connected to the input port 23, where Q = 1, 2, 3, ...

[0151] refer to Figure 13gThe example demonstrates a fourth optional structure 204 of the current-voltage controller 2, which replaces the Pth withstand voltage transformer 5 with the (P+Q)th low-opening clamp 6 and the (P-1)th low-opening clamp 6 with the high-opening clamp 8, based on the first optional structure 201, the second optional structure 202, or the third optional structure 203. The low-opening anode 61 of the (P+Q)th low-opening clamp 6 is interconnected with the withstand voltage gate 51 of the (P-1)th withstand voltage transformer 5 and the high-opening anode 81 of the high-opening clamp 8, and its low-opening cathode 62 is connected to the input port 23. The high-opening cathode 82 of the high-opening clamp 8 is connected to the clamping port 21.

[0152] refer to Figure 13h The example demonstrates a fifth optional structure 205 of the current-voltage controller 2, which, based on the first optional structure 201, disconnects the withstand gate 51 of the Pth withstand voltage device 5 from the clamping port 21 and connects it to the input port 23; or replaces the Pth withstand voltage device 5 with the high-opening clamp 8, whose high-opening cathode 82 is interconnected with the withstand gate 51 of the (P-1)th withstand voltage device 5 and the low-opening cathode 62 of the (P-1)th low-opening clamp 6, whose high-opening anode 81 is connected to the input port 23, and P = E.

[0153] When the modulated main power transistor 1 or the secondary power transistor 1a is the unidirectional withstand voltage power transistor 101, the reverse withstand voltage power transistor 102, or the single-drive bidirectional withstand voltage power transistor 104, at least one current and voltage controller 2 is provided.

[0154] When the modulated main power transistor 1 or the secondary power transistor 1a is the dual-drive anti-parallel reverse withstand voltage power transistor 103, the dual-drive bidirectional withstand voltage power transistor 105, or the integrated dual-drive bidirectional withstand voltage power transistor 106, at least two current and voltage controllers 2 are provided, which are located on the left and right sides respectively.

[0155] The clamping port 21 of the current-voltage controller 2 is interconnected with the first power port 903, the second power port 904, or the substrate port 905 of the modulated main power transistor 1 or the secondary power transistor 1a. Its main output port 22 is interconnected with the first main gate port 901 or the second main gate port 902 of the modulated main power transistor 1 or the secondary power transistor 1a. Its secondary output port 24 is interconnected with the first gate port 906 or the second gate port 907 of the modulated main power transistor 1 or the secondary power transistor 1a.

[0156] Referring to Figure 13, only five examples and three electrical interconnection layouts controlling the main power transistor 1 or the secondary power transistor 1a are shown. Those skilled in the art can implement different layouts based on the characteristics of the current-voltage controller 2. Figure 12 To avoid redundancy, not all implementation cases are listed in the accompanying diagrams.

[0157] (2) Function

[0158] The current-voltage controller 2 precisely modulates the bias voltage on the main gate 191 or secondary gate 192 of the main power transistor 1 or the secondary power transistor 1a to set the drive turn-on voltage and drive rated operating voltage of the main power transistor 1 or the secondary power transistor 1a; the main power transistor 1 or the secondary power transistor 1a of the current-voltage controller 2 is configured to achieve a higher threshold voltage and a higher gate withstand voltage, while maintaining fast switching capability, and excessive drive voltage is applied to the current-voltage controller 2.

[0159] Regarding gate potential clamp 3:

[0160] (1) Features

[0161] refer to Figure 14a The gate potential clamp 3 has a potential stabilization port 31, a pull-down port 32 or a pull-up port 33. The potential stabilization port 31 is interconnected with the first sub-gate port 908 or the second sub-gate port 909 of the modulated main power transistor 1 or the sub-power transistor 1a. The pull-down port 32 is interconnected with the first main gate port 901 or the second main gate port 902 of the modulated main power transistor 1 or the sub-power transistor 1a or the input port 23 of the current and voltage controller 2. The pull-up port 33 is interconnected with the first power port 903, the second power port 904 or the substrate port 905 of the modulated main power transistor 1 or the sub-power transistor 1a.

[0162] refer to Figure 14b The withstand gate 51 of the withstand voltage transformer 5, optionally mounted on the gate potential clamp 3, is interconnected with the pull-up port 33. In this embodiment, the withstand voltage transformer 5 is described using a depletion-type transistor 97 as an example. (See attached diagram.) Figure 10 The withstand voltage source 52 of the withstand voltage device 5 is interconnected with the potential stabilization port 31, and its withstand voltage drain 53 is interconnected with the pull-down port 32; the low-opening anode 61 of the first low-opening clamp 6 provided on the gate potential clamp 3 is interconnected with the potential stabilization port 31, and its low-opening cathode 62 is interconnected with the pull-down port 32; the low-opening anode 61 of the second low-opening clamp 6 provided on the gate potential clamp 3 is interconnected with the pull-up port 33, and its low-opening cathode 62 is interconnected with the potential stabilization port 31.

[0163] (2) Function

[0164] The gate potential clamp 3 locks the p-GaN potential of the main power transistor 1 or the secondary power transistor 1a within the range of ΔVon. That is, if the turn-on voltage of the low-turn-on clamp 6 is Von, the potential difference between the P-type ohmic contact 111 of the main gate 191 and the source 181 is Von, and the potential difference between the source 181 and the Schottky contact 19 of the main gate 191 is -Von, so as to suppress the p-GaN potential drift caused by high voltage stress.

[0165] In addition, the first low-turn-on clamp 6 or the withstand voltage 5 of the gate potential clamp 3 can eliminate the p-GaN potential floating effect (or gate-drain capacitance coupling effect) and pull down the p-GaN potential to avoid the p-GaN potential being too high and turning on erroneously.

[0166] The second low-turn-on clamp 6 of the gate potential clamp 3 can reduce the reverse conduction turn-on voltage of the main power transistor 1 to (Von-p+Von) and pull up the p-GaN potential to avoid increasing the on-resistance due to excessively low p-GaN potential. Here, Von-p is the turn-on voltage of the PN junction diode 99 formed by the p-GaN and the source 181. The voltage withstand voltage 5 optionally provided on the gate potential clamp 3 reduces the potential difference between the P-type ohmic contact 111 and the Schottky contact 19 of the main gate 191 to 0V.

[0167] Regarding substrate potential modulator 4:

[0168] (1) Features

[0169] Referring to Figure 15, the substrate potential modulator 4 can have three optional structures; the secondary power transistor 1a provided on the substrate potential modulator 4 is the unidirectional withstand voltage power transistor 101, and it is provided with the current voltage controller 2, the low turn-on clamp 6 or the gate potential clamp 3, and the electrical interconnection method between the current voltage controller 2 and the gate potential clamp 3 and the unidirectional withstand voltage power transistor 101 is the same as the interconnection method in the above-mentioned current voltage controller 2 and gate potential clamp 3;

[0170] The first type of substrate potential modulator 401 has two ports. The first type of substrate potential modulator 401 is provided with a low-open clamp 6, whose low-open anode 61 is interconnected with the modulation source port 42, and whose low-open cathode 62 is connected to the modulation drain port 43.

[0171] The second type of substrate potential modulator 402 has three ports. The secondary power transistor 1a on the second type of substrate potential modulator 402 is the unidirectional withstand voltage power transistor 101, and it is provided with two anti-parallel high-opening clamps 8 and low-opening clamps 6. The first power port 903 of the unidirectional withstand voltage power transistor 101 is interconnected with the modulation source port 42, its second power port 904 is interconnected with one end of the two anti-parallel high-opening clamps 8, and its first main gate port 901 is interconnected with the low-opening anode 61 of the low-opening clamp 6 and the modulation gate port 41. The low-opening cathode 62 of the low-opening clamp 6 is interconnected with the other end of the two anti-parallel high-opening clamps 8 and the modulation drain port 43.

[0172] The third type of substrate potential modulator 403 has three ports. The secondary power transistor 1a on the third type of substrate potential modulator 403 is a unidirectional voltage-resistant power transistor 101, and it is equipped with the current-voltage controller 2, or the low-turn-on clamp 6, or the gate potential clamp 3. When the unidirectional voltage-resistant power transistor 101 is provided, the first power port 903 of the unidirectional voltage-resistant power transistor 101 is interconnected with the modulation source port 42, and its second power port 904 is interconnected with the modulation drain port 43. When the current-voltage controller 2 is provided, the input port 23 of the current-voltage controller 2 is connected to the modulation gate port 41. When the low-turn-on clamp 6 is provided, the low-turn-on anode 61 of the low-turn-on clamp 6 is interconnected with the modulation source port 42, and its low-turn-on cathode 62 is connected to the modulation drain port 43.

[0173] refer to Figure 1c When the modulated main power transistor 1 is a unidirectional voltage-resistant power transistor 101, the modulation source port 42 of the first type of substrate potential modulator 401 is interconnected with the input port 23 of the external current-voltage controller 2 or with the first main gate port 901 of the modulated main power transistor 1, and its modulation drain port 43 is connected to the substrate port 905 of the modulated main power transistor 1; or / and the modulation gate port 41 of the second type of substrate potential modulator 402 is interconnected with the first main gate port 901 of the modulated main power transistor 1, its modulation source port 42 is interconnected with the first power port 903 of the modulated main power transistor 1, and its modulation drain port 43 is interconnected with the substrate port 905 of the modulated main power transistor 1;

[0174] refer to Figure 1a-b and Figure 16, when the modulated main power transistor 1 is a reverse withstand voltage power transistor 102, a dual-drive anti-parallel reverse withstand voltage power transistor 103, a single-drive bidirectional withstand voltage power transistor 104, a dual-drive bidirectional withstand voltage power transistor 105, or an integrated dual-drive bidirectional withstand voltage power transistor 106, the two columns of substrate potential modulators 4 provided are a first type of substrate potential modulator 401 or / and a third type of substrate potential modulator 403, and at least one of the third type of substrate potential modulator 403 is provided;

[0175] In this configuration, the modulation gate port 41 of the substrate potential modulator 4 in the left column is interconnected with the second power port 904 or the second main gate port 902 of the modulated main power transistor 1, or the input port 23 of the external current and voltage controller 2 on the right; its modulation source port 42 is interconnected with the substrate port 905 of the modulated main power transistor 1; and its modulation drain port 43 is interconnected with the first power port 903 or the first main gate port 901 of the modulated main power transistor 1, or the input port 23 of the external current and voltage controller 2 on the left.

[0176] The modulation gate port 41 of the substrate potential modulator 4 in the right column is interconnected with the first power port 903 or the first main gate port 901 of the modulated main power transistor 1, or the input port 23 of the external current and voltage controller 2 on the left. Its modulation source port 42 is interconnected with the substrate port 905 of the modulated main power transistor 1, and its modulation drain port 43 is interconnected with the second power port 904 or the second main gate port 902 of the modulated main power transistor 1, or the input port 23 of the external current and voltage controller 2 on the right.

[0177] (2) Function

[0178] refer to Figure 20f -g, the substrate potential modulator 4 can take over the potential of the substrate port 905 when the modulated unidirectional withstand voltage power transistor 101 is withstand voltage to improve the withstand voltage capability of the unidirectional withstand voltage power transistor 101, and apply a gate drive voltage to the substrate port 905 when the modulated unidirectional withstand voltage power transistor 101 is turned on to pull down the potential energy on the channel layer 14 and reduce the on-resistance; and the second substrate potential modulator 402 clamps the potential of the substrate port 905 of the unidirectional withstand voltage power transistor 101 at a lower positive potential, avoiding the back gate effect from affecting the on-resistance.

[0179] refer to Figure 20bThe substrate potential modulator 4 clamps the substrate potential of the modulated reverse withstand voltage power transistor 102, dual-drive anti-parallel reverse withstand voltage power transistor 103, single-drive bidirectional withstand voltage power transistor 104, dual-drive bidirectional withstand voltage power transistor 105, or integrated dual-drive bidirectional withstand voltage power transistor 106 to the lowest potential level among the first main gate port 901, the second main gate port 902, the first power port 903, or the second power port 904 to avoid the back gate effect causing the substrate port 905 to have an excessively low potential and thus reduce the on-resistance.

[0180] Regarding electrostatic discharge protector 7:

[0181] (1) Features

[0182] Referring to Figure 17, the secondary power transistor 1a provided on the electrostatic discharge (ESD) protector 7, which serves as the modulator, is either the single-drive bidirectional withstand voltage power transistor 104 or the single-direction withstand voltage power transistor 101, and is provided with the current-voltage controller 2, the Schottky diode 92, or the low-turn-on clamp 6; and the ESD protector 7 has an ESD first port 71 and an ESD second port 72, which are interconnected with any two ports among the first main gate port 901, the second main gate port 902, the first power port 903, the second power port 904, the substrate port 905 of the modulated main power transistor 1, or the input port 23 of the external current-voltage controller 2;

[0183] refer to Figure 17a The first main gate port 901 of the single-drive bidirectional withstand voltage power transistor 104 or the single-directional withstand voltage power transistor 101 provided on the electrostatic protector (7) is interconnected with the clamping port 21 and main output port 22 of the first and second current and voltage controllers 2, and the low-opening cathode 62 of the first and second low-opening clamps 6. Its first power port 903 is interconnected with the input port 23 of the first current and voltage controller 2, the cathode of the first Schottky diode 92 and the first electrostatic port 71. Its second power port 904 is interconnected with the input port 23 of the second current and voltage controller 2, the cathode of the second Schottky diode 92 and the second electrostatic port 72.

[0184] The anode of the first Schottky diode 92 is interconnected with the low-open anode 61 of the first low-open clamp 6; the anode of the second Schottky diode 92 is interconnected with the low-open anode 61 of the second low-open clamp 6.

[0185] (2) Function

[0186] refer to Figure 20dThe electrostatic discharge (ESD) protector 7 is connected between the two ports of the modulated main power transistor 1 to handle ESD events; when ESD triggers the ESD protector 7 to activate and discharge ESD charge, ESD breakdown of the modulated main power transistor 1 can be prevented. (Reference) Figure 20e If the single-drive bidirectional withstand voltage power transistor 104 or the single-directional withstand voltage power transistor 101 on the electrostatic discharge protector 7 are replaced with the main power transistor 1 reinforced in this application or the "nitride power device with gate voltage management function" described in patent number 202510716194.3, the electrostatic discharge protector 7 will exhibit a larger electrostatic tolerance window under the same active area.

[0187] Regarding short-circuit protection trigger 10:

[0188] (1) Features

[0189] Referring to Figure 18, the short-circuit protection trigger 10, which serves as the modulator, has a short-circuit gate port 1001, a short-circuit source port 1002, and a short-circuit drain port 1003. The sub-power transistor 1a provided on the short-circuit protection trigger 10 is a unidirectional withstand voltage power transistor 101, and is provided with the current-voltage controller 2 or the gate potential clamp 3. The first power port 903 of the unidirectional withstand voltage power transistor 101 is interconnected with the short-circuit source port 1002, and its second power port 904 is interconnected with the short-circuit drain port 1003. The input port 23 of the current-voltage controller 2 is connected to the short-circuit gate port 1001. The electrical interconnection method between the current-voltage controller 2, the gate potential clamp 3, and the unidirectional withstand voltage power transistor 101 is the same as the interconnection method of the current-voltage controller 2 and the gate potential clamp 3 described above.

[0190] refer to Figure 1c When the modulated main power transistor 1 is the unidirectional withstand voltage power transistor 101 and the reverse withstand voltage power transistor 102, the number of short-circuit protection triggers 10 is one, and its short-circuit gate port 1001 is interconnected with the second power port 904 of the modulated main power transistor 1, its short-circuit source port 1002 is interconnected with the first power port 903 or the substrate port 905 of the modulated main power transistor 1, and its short-circuit drain port 1003 is interconnected with the first main gate port 901 of the modulated main power transistor 1;

[0191] refer to Figure 1aWhen the modulated main power transistor 1 is the dual-drive anti-parallel reverse withstand voltage power transistor 103, the dual-drive bidirectional withstand voltage power transistor 105, or the integrated dual-drive bidirectional withstand voltage power transistor 106, the number of short-circuit protection triggers 10 is two; the short-circuit gate port 1001 of the first short-circuit protection trigger 10 is interconnected with the second power port 904 or the second main gate port 902 of the modulated main power transistor 1, and its short-circuit source port 1002 is connected to the first power port 903 or the substrate of the modulated main power transistor 1. The short-circuit drain port 1003 of the second short-circuit protection trigger 10 is interconnected with the first main gate port 901 of the modulated main power transistor 1; the short-circuit gate port 1001 of the second short-circuit protection trigger 10 is interconnected with the first power port 903 or the first main gate port 901 of the modulated main power transistor 1, the short-circuit source port 1002 is interconnected with the second power port 904 or the substrate port 905 of the modulated main power transistor 1, and the short-circuit drain port 1003 is interconnected with the second main gate port 902 of the modulated main power transistor 1.

[0192] refer to Figure 1b When the modulated main power transistor 1 is the single-drive bidirectional withstand voltage power transistor 104, the number of short-circuit protection triggers 10 is two; the short-circuit gate port 1001 of the first short-circuit protection trigger 10 is interconnected with the second power port 904 of the modulated main power transistor 1, its short-circuit source port 1002 is interconnected with the first power port 903 or substrate port 905 of the modulated main power transistor 1, and its short-circuit drain port 1003 is interconnected with the first main gate port 901 of the modulated main power transistor 1; the short-circuit gate port 1001 of the second short-circuit protection trigger 10 is interconnected with the first power port 903 of the modulated main power transistor 1, its short-circuit source port 1002 is interconnected with the second power port 904 or substrate port 905 of the modulated main power transistor 1, and its short-circuit drain port 1003 is interconnected with the first main gate port 901 of the modulated main power transistor 1.

[0193] (2) Function

[0194] refer to Figure 20h When the modulated main power transistor 1 is short-circuited, the short-circuit protection trigger will immediately trigger the unidirectional withstand voltage power transistor 101 on the short-circuit protection trigger to conduct, and clamp the gate potential of the modulated main power transistor 1 to the source potential to turn off the channel of the modulated main power transistor 1, thereby preventing the modulated main power transistor 1 from being short-circuited and burned out.

[0195] This application discloses a representative embodiment of a nitride power device with enhanced overall performance:

[0196] Case 1: Nitride power devices with high gate breakdown voltage and high gate threshold

[0197] refer to Figure 20a This example employs a third optional structure 203 of the integrated current-voltage controller 2 and the unidirectional withstand voltage power transistor 101 with the subgate. The third optional structure 203 has four (P) withstand voltage transistors 5 and five (P+Q-1) low-turn-on clamps 6. The first withstand voltage transistor 5 is an enhancement-mode transistor 94, the second to fourth withstand voltage transistors 5 are depletion-mode transistors 97, and all the low-turn-on clamps 6 are Schottky diodes 92.

[0198] If the threshold voltage of the depletion-type transistor 97 is -3V, the threshold voltage of the enhancement-type transistor 94 is 3V, and the input voltage Vin at input port 23 is 20V, then the drain 53 of all the withstand voltage transformers 5 is biased at 20V. First, the gate bias of the third depletion-type transistor 97 after pinch-off is 0V, and the source bias is 3V; subsequently, the gate bias of the second depletion-type transistor 97 is 3V, and the source bias is 6V; subsequently, the gate bias of the first depletion-type transistor 97 is 6V, and the source bias is 9V; subsequently, the gate bias of the enhancement-type transistor 94 is 9V, and the source bias is 6V; finally, the main gate bias of the unidirectional withstand voltage power transistor 101 is 6V, and the secondary gate bias is 3V. Based on the above mechanism, the excess voltage of the input voltage Vin is shared by the withstand voltage transformers 5. After the enhancement-type transistor 94 is turned on, the input voltage Vin begins to apply voltage to the main gate.

[0199] In summary, the modulator equipped with the current and voltage controller 2 increases the gate turn-on voltage of the modulated unidirectional withstand voltage power transistor 101 by 3V, and the gate withstand voltage of the modulated unidirectional withstand voltage power transistor 101 is determined by the withstand voltage capability of the withstand voltage device 5.

[0200] Case 2: Nitride power devices with substrate potential modulation

[0201] Sub-case 2.1:

[0202] refer to Figure 20bThis case utilizes an integrated dual-column substrate potential modulator 4 and a dual-drive bidirectional withstand voltage power transistor 105. The substrate potential modulator 4 is equipped with a current-voltage controller 2, a unidirectional withstand voltage power transistor 101, and a gate-source short-circuit enhancement-mode transistor 91. If the modulated dual-drive bidirectional withstand voltage power transistor 105 is in bidirectional blocking mode, then the first main gate port 901 and the second main gate port 902 are equivalently shorted to the first power port 903 and the second power port 904, respectively. Assuming the first power port 903 is biased to 0V and the second power port 904 is biased to 600V, then the first main gate port 901 is in a withstand voltage state.

[0203] Subsequently, the left gate-source short-circuit enhancement-mode transistor 91 in the two columns of substrate potential modulators 4 is turned on, while the right gate-source short-circuit enhancement-mode transistor 91 is blocked, thus clamping the substrate port 905 at a low potential; at the same time, 600V is applied to the left modulation gate port 41, and thanks to the potential modulation effect of the current-voltage controller 2 (refer to Case 1), the gate of the left unidirectional withstand voltage power transistor 101 is biased by 6V to turn on the left unidirectional withstand voltage power transistor 101;

[0204] Ultimately, the potential of port 905 is the same as that of the first power port 903, which is 0V. Similarly, if the first power port 903 is biased at 600V and the second power port 904 is biased at 0V, then the potential of port 905 is the same as that of the second power port 904, which is 0V.

[0205] In summary, the substrate potential of the main power transistor 1 with bidirectional withstand voltage integrated with the substrate potential modulator 4 is always consistent with the lowest potential of other ports to achieve the technical effect of suppressing the back gate effect, thereby avoiding the back gate effect from reducing the on-resistance of the main power transistor 1 with bidirectional withstand voltage.

[0206] Sub-case 2.2:

[0207] refer to Figure 20f -g, In this case, the modulated main power transistor 1 is the unidirectional withstand voltage power transistor 101, and a second substrate potential modulator 402 is used to modulate the substrate potential; the second substrate potential modulator 402 has a secondary power transistor 1a which is the unidirectional withstand voltage power transistor 101, a low-turn-on clamp 6 which is a gate-source short-circuit enhancement transistor 91, and a high-turn-on clamp 8 which is four gate-source short-circuit enhancement transistors 91 connected in series (i.e., M=4); assuming the threshold voltage of the enhancement transistor 94 is 3V.

[0208] refer to Figure 20fIn state one (off state), when a high voltage of 600V is applied to the second power port 904 of the modulated main power transistor 1, the potential of the substrate port 905 of the modulated main power transistor 1 is raised to 300V (i.e., half of the stress voltage); subsequently, the secondary power transistor 1a provided in the second substrate potential modulator 402 and the low-turn-on clamp 6 are both in a blocking state. Due to the clamping effect of the low-turn-on clamp 6, the potential of the substrate port 905 will not be lower than the turn-on voltage of the low-turn-on clamp 6.

[0209] refer to Figure 20g In state two (on state), when the stress voltage drops from 600V to 1V, a 10V drive voltage is applied to the first main gate port 901 of the modulated main power transistor 1. Subsequently, the secondary power transistor 1a provided in the second substrate potential modulator 402 turns on. Since the positive turn-on voltage of the high-turn-on clamp 8 is 20V, the 10V drive voltage is applied to the substrate port 905 through the low-turn-on clamp 6, so the drive voltage will not leak through the high-turn-on clamp 8. Due to the potential modulation effect of the second substrate potential modulator 402, the potential of the substrate port 905 of the modulated main power transistor 1 is at most 300V and at least 7V, and it will not be biased at a negative voltage. Therefore, the back gate effect on the on-resistance of the modulated main power transistor 1 is avoided. If the breakdown voltage from the substrate port 905 to the first power port 903 or the second power port 904 of the modulated main power transistor 1 is 600V, then the modulated main power transistor 1 can withstand a maximum voltage of 1200V, which is twice that of the unmodified main power transistor 1.

[0210] Case 3: Nitride power devices with stable gate threshold voltage and low reverse conductance turn-on

[0211] refer to Figure 18cIn this case, an integrated gate potential clamp 3 and a unidirectional voltage-resistant power transistor 101 with alternating Schottky contacts 19 and P-type ohmic contacts 111 on the main gate 191 are used. The gate potential clamp 3 is provided with two low-turn-on clamps 6. The low-turn-on clamps 6 are Schottky diodes 92; if the turn-on voltage of the Schottky diode 92 is 0.3V, the threshold voltage of the main gate 191 of the P-type ohmic contact 111 of the modulated unidirectional voltage-resistant power transistor 101 is 0.8V, and the threshold voltage of the main gate 191 of the Schottky contact 19 of the modulated unidirectional voltage-resistant power transistor 101 is 3V. Due to the clamping effect of the pull-up low-open clamp 6, the potential of the first subgate port 908 is at most 0.3V lower than the potential of the first power port 903 (i.e., the rightward drift of the threshold voltage of the main gate 191 does not exceed 0.3V); due to the clamping effect of the pull-down low-open clamp 6, the potential of the first main gate port 901 is at most 0.3V lower than the potential of the first subgate port 908 (i.e., the negative drift of the threshold voltage of the main gate 191 does not exceed 0.3V); when 7V is applied to the main gate 191 of the Schottky contact 19, due to When the low-open clamp 6 is pulled down and reverse biased, the entire input voltage is applied to the main gate 191 of the Schottky contact 19. The unidirectional withstand voltage power transistor 101 only turns on when the potential of the main gate 191 reaches 3V. When the reverse freewheeling current is applied, reverse conduction can only be triggered when the potential on the main gate 191 reaches the sum of the turn-on voltage of the low-open clamp 6 pulled up and the threshold voltage of the main gate 191 of the P-type ohmic contact 111 (i.e., the reverse conduction turn-on voltage is 1.1V, which is less than the threshold voltage of the main gate 191 of the Schottky contact 19).

[0212] In summary, integrating the gate potential clamp 3 can achieve the technical effects of stable gate threshold voltage and low reverse conduction turn-on.

[0213] Case 4: Nitride power devices with bidirectional electrostatic protection

[0214] refer to Figure 20d and Figure 20e Both cases employ the integrated electrostatic discharge protector 7 and the unidirectional withstand voltage power transistor 101.

[0215] Sub-case 4.1:

[0216] refer to Figure 20dThe electrostatic discharge (ESD) protector 7 is equipped with a unidirectional bidirectional withstand voltage power transistor 104, two Schottky diodes 92, two gate-source short-circuit depletion-type transistors 98, and two fifth optional structures 205 of the current-voltage controller 2 (P=E=4, i.e., four enhancement-type transistors 94). The first ESD port 71 and the second ESD port 72 are respectively shorted to the first main gate port 901 and the first power port 903 of the modulated unidirectional withstand voltage power transistor 101. Assume the threshold voltage of the enhancement-type transistor 94 is 3V and the turn-on voltage of the Schottky diode 92 is 0.3V. If an electrostatic event occurs between the first main gate port 901 and the first power port 903, and the first main gate port 901 is a high-voltage terminal, the electrostatic voltage reaches 12V, which can trigger the conduction of the fifth optional structure 205 on the right. If the electrostatic voltage increases by another 0.3V, the left Schottky diode 92 is triggered to turn on. As the current in the path of the left Schottky diode 92 increases rapidly, due to the reverse bias current limiting effect of the left gate-source short-circuit depletion transistor 98, the bias on the first main gate port 901 of the electrostatic protector 7, which is equipped with a unidirectional bidirectional withstand voltage power transistor 104, immediately increases to 3V, causing the unidirectional bidirectional withstand voltage power transistor 104 to turn on and release electrostatic charge. Finally, at least 15.3V is applied between the first main gate port 901 and the first power port 903 of the modulated unidirectional withstand voltage power transistor 101 to trigger electrostatic discharge. Since the transient gate withstand voltage of nitrides is typically 20V, the electrostatic discharge window is only 4.7V. The smaller electrostatic discharge window requires the single-drive bidirectional withstand voltage power transistor 104 on the electrostatic protector 7 to have low on-resistance, which will increase the chip area.

[0217] Sub-case 4.2:

[0218] refer to Figure 20eBased on sub-case 4.1, the single-drive bidirectional withstand voltage power transistor 104 on the electrostatic discharge protector 7 equivalently replaces the "nitride power device with gate voltage management function" described in patent number 202510716194.3, and a third optional structure 203 of the current-voltage controller 2 is added between the electrostatic discharge protector 7 and the modulated unidirectional withstand voltage power transistor 101. Based on case 1, the modulated unidirectional withstand voltage power transistor 101 with the third optional structure 203 of the current-voltage controller 2 exhibits a larger gate withstand voltage, assuming the maximum pulse breakdown voltage is increased to 50V. Based on patent number 202510716194.3, the nitride power device with gate voltage management function has a high gate withstand voltage, assuming the maximum gate breakdown voltage is increased to 50V. Therefore, compared to the solution described in sub-case 4.1, this solution demonstrates a 34.7V electrostatic discharge window, which occupies a smaller chip area. Thus, the ruggedization technology described in this invention has complementary technical effects.

[0219] Case 5: Nitride power devices with short-circuit protection

[0220] refer to Figure 20h This case adopted Figure 18bThe short-circuit protection trigger 10 is shown. Since the modulated main power transistor 1 is the unidirectional withstand voltage power transistor 101, only one short-circuit protection trigger 10 is used in this case. The short-circuit protection trigger 10 has a second optional structure 202 of the current-voltage controller 2, which includes one enhancement transistor 94 (i.e., E=1). Referring to Case 1, triggering the unidirectional withstand voltage power transistor 101 in the short-circuit protection trigger 10 requires a short-circuit stress of at least 6V. When the modulated main power transistor 1 is normally turned on, the drain stress of the main power transistor 1 is less than 2V, so the unidirectional withstand voltage power transistor 101 in the short-circuit protection trigger 10 will not be triggered to turn on. Under normal circumstances, when a 10V input gate bias is applied to the first main gate port 901 of the modulated main power transistor 1, the modulated main power transistor 1 is in the on state. If a short-circuit event suddenly occurs in the modulated main power transistor 1... If a short-circuit stress of 600V is suddenly applied to the drain, the short-circuit stress will trigger the unidirectional withstand voltage power transistor 101 in the short-circuit protection trigger 10 to conduct through the short-circuit gate port 1001. At this time, the short-circuit protection trigger 10 will clamp the potential of the first main gate port 901 of the modulated main power transistor 1 to the potential of the first power port 903 at 0V (normally the input impedance of the modulated main power transistor 1 is set to 10Ω, so the potential of the first main gate port 901 of the modulated main power transistor 1 is close to 0V), and then the modulated main power transistor 1 will immediately turn off. Thus, the short-circuit protection trigger 10 of the present invention demonstrates the technical effect of handling sudden short-circuit events.

[0221] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A nitride power device with enhanced comprehensive performance, characterized in that: Includes a main power transistor (1) and a modulator for precisely modulating the port current and voltage of the main power transistor (1) to achieve robust operation of the main power transistor (1), wherein the main power transistor (1) is a high-power component based on gate-regulated input / output or blocking high voltage and high current; The modulator is one or more of the following: current-voltage controller (2), gate potential clamper (3), substrate potential modulator (4), electrostatic discharge protector (7), and short-circuit protection trigger (10).

2. The nitride power device with comprehensive performance reinforcement according to claim 1, characterized in that: The modulator includes one or more of a secondary power transistor (1a), a withstand voltage transistor (5), a low-turn-on clamp (6), and a high-turn-on clamp (8); wherein the withstand voltage transistor (5) is an enhancement-mode transistor (94) or a depletion-mode transistor (97); the low-turn-on clamp (6) is a gate-source short-circuit enhancement-mode transistor (91), a Schottky diode (92), a resistor (95), or a gate-source short-circuit depletion-mode transistor (98); and the high-turn-on clamp (8) is M gate-source short-circuit enhancement-mode transistors (91) or M Schottky diodes (92) connected in series.

3. A nitride power device with enhanced comprehensive performance according to claim 2, characterized in that: The main power transistor (1) and the secondary power transistor (1a) include a substrate layer (11), a nucleation layer (12), a buffer layer (13), a channel layer (14), and a main barrier layer (15) formed sequentially. A bulk p-GaN layer (16), a dielectric layer (17), an N-type ohmic contact (18), a Schottky contact (19), and an isolation region (110) are formed on top of the main barrier layer (15). The N-type ohmic contact (18) is either a source (181) or a drain (182) and is distributed around the bulk p-GaN layer (16). A main gate (191) is formed on top of the bulk p-GaN layer (16). A stepped field plate (112) is formed on the dielectric layer (17) above the main gate (191), and the stepped field plate (112) is connected to the source (181) or the substrate electrode (113) at the bottom of the substrate layer (11); the main gate (191) may be the Schottky contact (19), or an alternating distribution of the Schottky contact (19) and the P-type ohmic contact (111), and the dielectric layer (17), or an N-type nitride layer (161), or a lightly doped p-GaN layer (162), or an iron / hydrogen / carbon doped nitride layer (163), or an unintentionally doped nitride layer (164) may be provided between the Schottky contact (19) and the bulk p-GaN layer (16).

4. A nitride power device with enhanced comprehensive performance according to claim 3, characterized in that: The main power transistor (1) and the secondary power transistor (1a) have a local regeneration barrier layer (01) or a local regeneration barrier layer (01) and a local regeneration bulk p-GaN layer (02) stacked on top of the main barrier layer (15). The fabrication process is to sequentially form the substrate layer (11), the nucleation layer (12), the buffer layer (13), the channel layer (14), the main barrier layer (15) and the bulk p-GaN layer (16). The dielectric layer (17) formed on top of the bulk p-GaN layer (16) serves as a mask for etching and regeneration; the bulk p-GaN layer (16) is etched based on the mask, and the top of the main barrier layer (15) is partially exposed; the locally regenerated barrier layer (01) or the locally regenerated barrier layer (01) and the locally regenerated bulk p-GaN layer (02) are stacked based on the mask; the dielectric layer (17) is cleaned, and the bulk p-GaN layer (16) and the locally regenerated bulk p-GaN layer (02) are selectively etched to partially expose the top of the main barrier layer (15) and the locally regenerated layer. The N-type ohmic contact (18), the dielectric layer (17), and the isolation region (110) are formed on the top of the locally exposed main barrier layer (15) and the top of the locally regenerated barrier layer (01), respectively; the main gate (191) and the P-type ohmic contact (111) are formed on the top of the bulk p-GaN layer (16) and the locally regenerated bulk p-GaN layer (02), respectively, and the P-type ohmic contact (111) on the top of the locally regenerated bulk p-GaN layer (02) is interconnected with the drain (182) through the Schottky contact (19); The locally regenerated barrier layer (01) with a thickness of 1 nanometer to 100 nanometers is one or more nitride stacks and has at least one of the metal elements boron, aluminum, gallium, indium and scandium, and the composition is uniformly distributed between 5% and 100%; the locally regenerated barrier layer (01) is in contact with the drain (182) in the horizontal direction and at a distance between it and the bulk p-GaN layer (16) or the Schottky contact (19) between 0 and 9 micrometers; The locally regenerated bulk p-GaN layer (02) with a thickness of 1 nanometer to 200 nanometers is in contact with the top of the locally regenerated barrier layer (01) and the bottom of the P-type ohmic contact (111); the distance between the locally regenerated bulk p-GaN layer (02) and the drain (182) is between 0 and 9 micrometers.

5. A nitride power device with enhanced comprehensive performance according to claim 3 or 4, characterized in that: The main power transistor (1) and the secondary power transistor (1a) are unidirectional voltage-resistant power transistors (101), reverse voltage-resistant power transistors (102), dual-drive anti-parallel reverse voltage-resistant power transistors (103), unidirectional bidirectional voltage-resistant power transistors (104), dual-drive bidirectional voltage-resistant power transistors (105), or integrated dual-drive bidirectional voltage-resistant power transistors (106); the integrated dual-drive bidirectional voltage-resistant power transistor (106) is formed in parallel with the dual-drive anti-parallel reverse voltage-resistant power transistor (103) and the dual-drive bidirectional voltage-resistant power transistor (105).

6. A nitride power device with enhanced comprehensive performance according to claim 5, characterized in that: The main power transistor (1) and / or the secondary power transistor (1a) are provided with a secondary gate (192), the secondary gate (192) is a Schottky contact (19), the secondary gate (192) is in contact with the top of the main barrier layer (15) in the drift region (9), or is intersected between the dielectric layer (17) and the main gate (191) or the drift region (9); When the main power transistor (1) and / or the secondary power transistor (1a) is the unidirectional withstand voltage power transistor (101), the reverse withstand voltage power transistor (102), or the single-drive bidirectional withstand voltage power transistor (104), the number of the secondary gates (192) is at least one. When the main power transistor (1) and / or the secondary power transistor (1a) is the dual-drive anti-parallel reverse withstand voltage power transistor (103), the dual-drive bidirectional withstand voltage power transistor (105), or the integrated dual-drive bidirectional withstand voltage power transistor (106), the number of the secondary gates (192) is at least two.

7. A nitride power device with enhanced comprehensive performance according to claim 5, characterized in that: The main power transistor (1) and / or the secondary power transistor (1a) are provided with a second barrier layer (151) that forms a two-dimensional hole gas (153) polarized at the bottom of the channel layer (14), or are provided with a second barrier layer (151) that forms a two-dimensional hole gas (153) polarized at the bottom of the channel layer (14), and a source quantum pump (1811) or a drain quantum pump (1821). The second barrier layer (151) is in contact with the top of the buffer layer (13) and the bottom of the channel layer (14); the second barrier layer (151), which is 1 nanometer to 4 micrometer thick, is one or more nitride stacks and has at least one of the metal elements boron, aluminum, gallium, indium and scandium, and the uniformly distributed component is between 5% and 100%, or the component with a gradually distributed component increases from 0% at the bottom to 5% to 100% at the top; The source quantum pump (1811) and the drain quantum pump (1821) are composed of the N-type ohmic contact (18), the bulk p-GaN layer (16), the Schottky contact (19), and the P-type ohmic contact (111). The bottom of the N-type ohmic contact (18) contacts the top of the main barrier layer (15) and surrounds or partially surrounds the bulk p-GaN layer (16) in the horizontal direction. The bottom of the bulk p-GaN layer (16) contacts the top of the main barrier layer (15), and its top contacts the bottom of the P-type ohmic contact (111). The Schottky contact (19) penetrates at least from top to bottom through the main barrier layer (15), the channel layer (14), and the second barrier layer (151) in the spacer region of the bulk p-GaN layer (16) to interconnect the two-dimensional hole gas (153), the N-type ohmic contact (18), and the P-type ohmic contact (111); or, the Schottky contact (19) does not penetrate the nitride and is interconnected with the N-type ohmic contact (18) and the P-type ohmic contact (111) in the horizontal direction.

8. A nitride power device with enhanced comprehensive performance according to claim 4, characterized in that: The main barrier layer (15) of the main power transistor (1) or / and the secondary power transistor (1a), or the top of the local regeneration barrier layer (01), or the bulk p-GaN layer (16) is subjected to at least one plasma treatment and annealing to form a local in-situ oxynitride layer (155). When the main barrier layer (15) or the local regenerated barrier layer (01) is on top, the local in-situ oxynitride layer (155) is in contact with the drain (182) in the horizontal direction and at a distance between the blocky p-GaN layer (16) or the Schottky contact (19) and between 0 and 9 micrometers. When on top of the bulk p-GaN layer (16), the top of the local in-situ oxynitride layer (155) is in contact with the Schottky contact (19) and not with the P-type ohmic contact (111). The local in-situ oxynitride layer (155) is located between the dielectric layer (17) and the secondary gate (192) or the stepped field plate (112).

9. A nitride power device with enhanced comprehensive performance according to claim 2, characterized in that: The current and voltage controller (2) of the modulator can have five optional structures. The current and voltage controller (2) has three or four ports, namely a clamping port (21), a main output port (22), an input port (23), or a secondary output port (24). The first optional structure (201) of the current-voltage controller (2) is provided with P withstand voltage transformers (5) and P-1 low-open clamps (6), and the P withstand voltage transformers (5) are E enhancement-mode transistors (94) and F depletion-mode transistors (97); the withstand voltage source (52) of the first withstand voltage transformer (5) is connected to the main output port (22); any one of the first to P-1 withstand voltage transformers (5) and the first to P-1 low-open clamps (6) is defined as the Xth withstand voltage transformer (5) and the Xth low-open clamp, respectively. (6) The withstand gate (51) of the Xth withstand voltage transformer (5) is interconnected with the withstand source (52) of the (X+1)th withstand voltage transformer (5) and the low-open cathode (62) of the Xth low-open clamp (6); the withstand gate (51) of the Pth withstand voltage transformer (5) is interconnected with the low-open anode (61) of all the low-open clamps (6) and the clamping port (21); the withstand drain (53) of all the withstand voltage transformers (5) is connected to the input port (23); if E≠0, then the withstand voltage transformers (5) from the first to the Eth are the enhancement-mode transistors (94); The second optional structure (202) of the current-voltage controller (2) is based on the first optional structure (201) by connecting the withstand gate (51) of the Nth withstand voltage transformer (5) to the secondary output port (24), where 1≤N<P; The third optional structure (203) of the current and voltage controller (2) adds Q of the voltage withstandrs (5) or Q of the low-opening clamps (6) to the first optional structure (201) or the second optional structure (202); and the voltage withstand gate (51) of the added Q voltage withstandrs (5) is connected to the clamping port (21), its voltage withstand source (52) is connected to the main output port (22) or the secondary output port (24), and its voltage withstand drain (53) is connected to the input port (23); and the low-opening anode (61) of the added Q low-opening clamps (6) is connected to the main output port (22) or the secondary output port (24), and its low-opening cathode (62) is connected to the input port (23); The fourth optional structure (204) of the current and voltage controller (2) replaces the Pth withstand voltage device (5) with the P+Qth low-opening clamp (6) and replaces the P-1th low-opening clamp (6) with the high-opening clamp (8) based on the first optional structure (201), the second optional structure (202) or the third optional structure (203); and the low-opening anode (61) of the P+Qth low-opening clamp (6) is interconnected with the withstand voltage gate (51) of the P-1th withstand voltage device (5) and the high-opening anode (81) of the high-opening clamp (8), and its low-opening cathode (62) is connected to the input port (23); and the high-opening cathode (82) of the high-opening clamp (8) is connected to the clamping port (21). The fifth optional structure (205) of the current and voltage controller (2) is based on the first optional structure (201) by disconnecting the withstand gate (51) of the Pth withstand voltage device (5) from the clamping port (21) and connecting it to the input port (23); or by replacing the Pth withstand voltage device (5) with the high-opening clamp (8), whose high-opening cathode (82) is interconnected with the withstand gate (51) of the P-1th withstand voltage device (5) and the low-opening cathode (62) of the P-1th low-opening clamp (6), whose high-opening anode (81) is connected to the input port (23), and P=E.

10. A nitride power device with enhanced comprehensive performance according to claim 5 or 9, characterized in that: When the modulated main power transistor (1) or the secondary power transistor (1a) is a unidirectional withstand voltage power transistor (101), a reverse withstand voltage power transistor (102), or a single-drive bidirectional withstand voltage power transistor (104), at least one current and voltage controller (2) is provided. When the modulated main power transistor (1) or the secondary power transistor (1a) is a dual-drive anti-parallel reverse withstand voltage power transistor (103), a dual-drive bidirectional withstand voltage power transistor (105), or an integrated dual-drive bidirectional withstand voltage power transistor (106), at least two current and voltage controllers (2) are provided, and the two current and voltage controllers (2) are located on the left and right sides, respectively. The clamping port (21) of the current-voltage controller (2) is interconnected with the first power port (903), the second power port (904), or the substrate port (905) of the modulated main power transistor (1) or the secondary power transistor (1a). Its main output port (22) is interconnected with the first main gate port (901) or the second main gate port (902) of the modulated main power transistor (1) or the secondary power transistor (1a). Its secondary output port (24) is interconnected with the first gate port (906) or the second gate port (907) of the modulated main power transistor (1) or the secondary power transistor (1a).

11. A nitride power device with enhanced comprehensive performance according to claim 5, characterized in that: The gate potential clamp (3) of the modulator has a potential stabilizing port (31), a pull-down port (32) and / or a pull-up port (33), the potential stabilizing port (31) being interconnected with the first sub-gate port (908) or the second sub-gate port (909) of the modulated main power transistor (1) or the sub-power transistor (1a), the pull-down port (32) being interconnected with the first main gate port (901) or the second main gate port (902) of the modulated main power transistor (1) or the sub-power transistor (1a), or the input port (23) of the current and voltage controller (2), and the pull-up port (33) being interconnected with the first power port (903) or the second power port (904) or the substrate port (905) of the modulated main power transistor (1) or the sub-power transistor (1a). The withstand gate (51) of the withstand voltage device (5) optionally provided on the gate potential clamp (3) is interconnected with the pull-up port (33), its withstand source (52) is interconnected with the potential stabilization port (31), and its withstand drain (53) is interconnected with the pull-down port (32); the low-opening anode (61) of the first low-opening clamp (6) provided on the gate potential clamp (3) is interconnected with the potential stabilization port (31), and its low-opening cathode (62) is interconnected with the pull-down port (32); the low-opening anode (61) of the second low-opening clamp (6) provided on the gate potential clamp (3) is interconnected with the pull-up port (33), and its low-opening cathode (62) is interconnected with the potential stabilization port (31).

12. A nitride power device with enhanced comprehensive performance according to claim 10 or 11, characterized in that: The substrate potential modulator (4) used as the modulator can have three optional structures; The first type of substrate potential modulator (401) has two ports. The first type of substrate potential modulator (401) is provided with a low-open clamp (6), whose low-open anode (61) is interconnected with the modulation source port (42), and whose low-open cathode (62) is connected to the modulation drain port (43). The second type of substrate potential modulator (402) has three ports. The secondary power transistor (1a) provided on the second type of substrate potential modulator (402) is the unidirectional withstand voltage power transistor (101), and is provided with two anti-parallel high-turn-on clamps (8) and low-turn-on clamps (6). The first power port (903) of the unidirectional withstand voltage power transistor (101) is interconnected with the modulation source port (42), its second power port (904) is interconnected with one end of the two anti-parallel high-turn-on clamps (8), and its first main gate port (901) is interconnected with the low-turn-on anode (61) of the low-turn-on clamp (6) and the modulation gate port (41). The low-turn-on cathode (62) of the low-turn-on clamp (6) is interconnected with the other end of the two anti-parallel high-turn-on clamps (8) and the modulation drain port (43). The third type of substrate potential modulator (403) has three ports. The sub-power transistor (1a) provided on the third type of substrate potential modulator (403) is a unidirectional voltage-resistant power transistor (101), and is provided with the current-voltage controller (2), or the low-turn-on clamp (6), or the gate potential clamp (3). When the unidirectional voltage-resistant power transistor (101) is provided, the first power port (903) of the unidirectional voltage-resistant power transistor (101) is interconnected with the modulation source port (42), and its second power port (904) is interconnected with the modulation drain port (43). When the current-voltage controller (2) is provided, the input port (23) of the current-voltage controller (2) is connected to the modulation gate port (41). When the low-turn-on clamp (6) is provided, the low-turn-on anode (61) of the low-turn-on clamp (6) is interconnected with the modulation source port (42), and its low-turn-on cathode (62) is connected to the modulation drain port (43).

13. A nitride power device with enhanced comprehensive performance according to claim 12, characterized in that: When the modulated main power transistor (1) is a unidirectional voltage-resistant power transistor (101), the modulation source port (42) of the first type of substrate potential modulator (401) is interconnected with the input port (23) of the external current and voltage controller (2) or with the first main gate port (901) of the modulated main power transistor (1), and its modulation drain port (43) is connected to the substrate port (905) of the modulated main power transistor (1); or / and the modulation gate port (41) of the second type of substrate potential modulator (402) is interconnected with the first main gate port (901) of the modulated main power transistor (1), its modulation source port (42) is interconnected with the first power port (903) of the modulated main power transistor (1), and its modulation drain port (43) is interconnected with the substrate port (905) of the modulated main power transistor (1); When the modulated main power transistor (1) is a reverse voltage withstand power transistor (102), a dual-drive anti-parallel reverse voltage withstand power transistor (103), a single-drive bidirectional voltage withstand power transistor (104), a dual-drive bidirectional voltage withstand power transistor (105), or an integrated dual-drive bidirectional voltage withstand power transistor (106), the two columns of substrate potential modulators (4) provided are a first type of substrate potential modulator (401) or / and a third type of substrate potential modulator (403), and at least one of the third type of substrate potential modulators (403) is provided. Among them, the modulation gate port (41) of the substrate potential modulator (4) in the left column is interconnected with the second power port (904) or the second main gate port (902) of the modulated main power transistor (1) or the input port (23) of the external current and voltage controller (2) on the right, its modulation source port (42) is interconnected with the substrate port (905) of the modulated main power transistor (1), and its modulation drain port (43) is interconnected with the first power port (903) or the first main gate port (901) of the modulated main power transistor (1) or the input port (23) of the external current and voltage controller (2) on the left. The modulation gate port (41) of the substrate potential modulator (4) in the right column is interconnected with the first power port (903) or the first main gate port (901) of the modulated main power transistor (1) or the input port (23) of the external current and voltage controller (2) on the left. Its modulation source port (42) is interconnected with the substrate port (905) of the modulated main power transistor (1). Its modulation drain port (43) is interconnected with the second power port (904) or the second main gate port (902) of the modulated main power transistor (1) or the input port (23) of the external current and voltage controller (2) on the right.

14. A nitride power device with enhanced comprehensive performance according to claim 2, characterized in that: The electrostatic discharge protector (7) of the modulator is provided with a secondary power transistor (1a) which is a single-drive bidirectional withstand voltage power transistor (104) or a unidirectional withstand voltage power transistor (101), and is provided with the current and voltage controller (2), the Schottky diode (92) and the low-turn-on clamp (6); and the electrostatic discharge protector (7) has an electrostatic first port (71) and an electrostatic second port (72), the electrostatic first port (71) and the electrostatic second port (72) being interconnected with any two ports among the first main gate port (901), the second main gate port (902), the first power port (903), the second power port (904), the substrate port (905) of the modulated main power transistor (1) or the input port (23) of the external current and voltage controller (2); The first main gate port (901) of the single-drive bidirectional withstand voltage power transistor (104) or the unidirectional withstand voltage power transistor (101) provided on the electrostatic protector (7) is interconnected with the clamping port (21) and the main output port (22) of the first and second current and voltage controllers (2), and the low-opening cathode (62) of the first and second low-opening clamps (6). Its first power port (903) is interconnected with the input port (23) of the first current and voltage controller (2), the cathode of the first Schottky diode (92) and the first electrostatic port (71). Its second power port (904) is interconnected with the input port (23) of the second current and voltage controller (2), the cathode of the second Schottky diode (92) and the second electrostatic port (72). The anode of the first Schottky diode (92) is interconnected with the low-open anode (61) of the first low-open clamp (6); the anode of the second Schottky diode (92) is interconnected with the low-open anode (61) of the second low-open clamp (6).

15. A nitride power device with enhanced comprehensive performance according to claim 2, 10, or 11, characterized in that: The short-circuit protection trigger (10) of the modulator has a short-circuit gate port (1001), a short-circuit source port (1002) and a short-circuit drain port (1003). The sub-power transistor (1a) provided on the short-circuit protection trigger (10) is a unidirectional voltage-resistant power transistor (101), and is provided with the current and voltage controller (2) or the gate potential clamp (3). The first power port (903) of the unidirectional withstand voltage power transistor (101) is interconnected with the short-circuit source port (1002), and its second power port (904) is interconnected with the short-circuit drain port (1003); the input port (23) of the current and voltage controller (2) is connected to the short-circuit gate port (1001). When the modulated main power transistor (1) is the unidirectional withstand voltage power transistor (101) and the reverse withstand voltage power transistor (102), the number of the short-circuit protection trigger (10) is one, and its short-circuit gate port (1001) is interconnected with the second power port (904) of the modulated main power transistor (1), its short-circuit source port (1002) is interconnected with the first power port (903) or substrate port (905) of the modulated main power transistor (1), and its short-circuit drain port (1003) is interconnected with the first main gate port (901) of the modulated main power transistor (1); When the modulated main power transistor (1) is the dual-drive anti-parallel reverse withstand voltage power transistor (103), the dual-drive bidirectional withstand voltage power transistor (105), or the integrated dual-drive bidirectional withstand voltage power transistor (106), the number of short-circuit protection triggers (10) is two; the short-circuit gate port (1001) of the first short-circuit protection trigger (10) is interconnected with the second power port (904) or the second main gate port (902) of the modulated main power transistor (1), and its short-circuit source port (1002) is interconnected with the first power port (903) or the substrate port (904) of the modulated main power transistor (1). 5) Interconnection, wherein the short-circuit drain port (1003) of the second short-circuit protection trigger (10) is interconnected with the first main gate port (901) of the modulated main power transistor (1); the short-circuit gate port (1001) of the second short-circuit protection trigger (10) is interconnected with the first power port (903) or the first main gate port (901) of the modulated main power transistor (1), wherein the short-circuit source port (1002) is interconnected with the second power port (904) or the substrate port (905) of the modulated main power transistor (1), wherein the short-circuit drain port (1003) of the second short-circuit protection trigger (1) is interconnected with the second main gate port (902) of the modulated main power transistor (1); When the modulated main power transistor (1) is the single-drive bidirectional withstand voltage power transistor (104), the number of short-circuit protection triggers (10) is two; the short-circuit gate port (1001) of the first short-circuit protection trigger (10) is interconnected with the second power port (904) of the modulated main power transistor (1), its short-circuit source port (1002) is interconnected with the first power port (903) or substrate port (905) of the modulated main power transistor (1), and its short-circuit drain port (1003) is interconnected with the modulated main power transistor (1). The first main gate port (901) of the modulated main power transistor (1) is interconnected; the short-circuit gate port (1001) of the second short-circuit protection trigger (10) is interconnected with the first power port (903) of the modulated main power transistor (1), the short-circuit source port (1002) is interconnected with the second power port (904) or substrate port (905) of the modulated main power transistor (1), and the short-circuit drain port (1003) is interconnected with the first main gate port (901) of the modulated main power transistor (1).

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