An integrated digital eddy current sensor system

Abstract

This invention provides an integrated digital eddy current sensor system, belonging to the field of eddy current sensor technology, which can at least partially solve the problem of poor dynamic response accuracy in existing systems. The integrated digital eddy current sensor system of this invention is characterized by having a three-level collaborative structure, comprising a dynamic polynomial engine, a hardware acceleration unit, and a phase compensation module. The dynamic polynomial engine generates a frequency-amplitude-phase three-dimensional mapping table using polynomial equations and outputs multiple sets of parallel coefficients to the hardware acceleration unit. The hardware acceleration unit constructs a pipelined computing architecture to achieve parameter updates and compressed encoding at set intervals. The phase compensation module establishes a phase error feedback closed loop to control the phase error within a set error range under a reference signal.

Description

Technical Field

[0001] This invention relates to the field of sensor technology, specifically to an integrated digital eddy current sensor system, which is mainly used in scenarios requiring high acceleration measurement accuracy, such as rotating machinery condition monitoring and precision bearing fault diagnosis. Background Technology

[0002] Digital eddy current sensors are widely used in industrial equipment condition monitoring due to their advantages such as non-contact measurement and fast response. Their core technology is to simulate mechanical vibration characteristics through frequency scanning. However, traditional architectures have bottlenecks in terms of dynamic response accuracy, high-frequency signal integrity, and phase synchronization.

[0003] Specifically, traditional eddy current sensor systems suffer from the following technical defects: First, dynamic response defects. They employ a piecewise step-frequency scanning method to simulate mechanical vibration, neglecting the nonlinearity and continuity of acceleration changes. This results in broken acceleration curve gradients and a synthesis error exceeding 15%, failing to meet the requirements of precision bearing monitoring. Second, limited dynamic parameter refresh. Relying on a DSP processor for parameter updates, the refresh rate is difficult to exceed 500ns due to instruction cycle and pipeline delays, leading to the loss of high-frequency vibration characteristics. Third, large phase synchronization deviations. The open-loop compensation mechanism is susceptible to temperature drift and harmonic interference, with phase synchronization deviations exceeding 3°, affecting the accuracy of vibration phase spectrum analysis. Fourth, insufficient high-frequency signal integrity. Traditional SRAM cache architectures experience a 3dB bandwidth attenuation when sweeping frequencies above 100kHz, restricting high-frequency signal integrity.

[0004] Existing technologies employ piecewise fitting techniques for improvement, but piecewise polynomial fitting fails to resolve the mismatch between order and hardware computation delay, and phase correction is only applicable to steady-state signals, resulting in lag in transient response. These issues lead to performance degradation in ultra-low-speed (<1Hz / s) and high-speed (>50kHz / s) frequency sweeping scenarios, necessitating new solutions to overcome the limitations of dynamic frequency synthesis and real-time compensation technologies. Summary of the Invention

[0005] The present invention aims to solve at least one of the technical problems existing in the prior art and to provide an integrated digital eddy current sensor system.

[0006] One aspect of the present invention provides an integrated digital eddy current sensor system, wherein the integrated digital eddy current sensor system has a three-level collaborative structure, the three-level collaborative structure including a dynamic polynomial engine, a hardware acceleration unit, and a phase compensation module, wherein the dynamic polynomial engine is used to generate a frequency-amplitude-phase three-dimensional mapping table using polynomial equations and output multiple sets of parallel coefficients to the hardware acceleration unit; the hardware acceleration unit is used to construct a pipelined computing architecture to realize parameter updates and compression encoding at a set period; the phase compensation module is used to establish a phase error feedback closed loop to control the phase error within a set error range under a reference signal.

[0007] Optionally, the dynamic polynomial engine includes a dynamic constraint module that introduces jerk constraints during the parallel coefficient calculation process:

[0008] ;

[0009] J max The maximum permissible jerk of the tested mechanical system is constrained by a three-dimensional parameter space mapping table, which defines the slope of the frequency, the gradient of the amplitude, and the rate of change of the phase. For the polynomial equation The third derivative of .

[0010] Preferably, the hardware acceleration unit includes a dual-port BRAM cache matrix and a customized pipelined computation unit, wherein the customized pipelined computation unit is configured to include: a coefficient loading module for loading the multiple sets of parallel coefficients into a register file in parallel; a pipelined operation module for performing staged computation based on timestamps; and a result synthesis module for weighted summation of the computation results of each stage and outputting them to the digital-to-analog conversion module.

[0011] Optionally, the phase compensation module includes an adaptive delay compensation model and a Hilbert filter bank, wherein the expression for the adaptive delay compensation model is:

[0012] ;

[0013] In the formula This is the phase compensation amount. For the target phase, The current phase error, =0.85、 =0.15 is the empirically optimized parameter, and τ is the time variable. Closed-loop tracking is achieved by adjusting the phase of the output signal in real time.

[0014] In a preferred embodiment, the dynamic polynomial engine employs fifth-degree polynomial equations. Generate the frequency-amplitude-phase three-dimensional mapping table, where a5 to a0 are polynomial coefficients and t is time;

[0015] The hardware acceleration unit is based on FPGA to build the pipeline computing architecture and implements parameter updates and Δ-Sigma compression encoding with a 100ns cycle.

[0016] The phase compensation module establishes a phase error feedback closed loop through Hilbert transform and controls the phase error within the range of ≤0.3° under the reference signal at 10kHz.

[0017] More specifically, the Δ-Sigma compression coding adopts a second-order modulator architecture, including: first, preprocessing: differential coding of the original frequency curve; second, compression: compressing and storing the data through Δ-Sigma modulation; and third, decompression: restoring the original data through low-pass filtering.

[0018] Alternatively, the second-order modulator may employ a cascaded integrator feedback topology.

[0019] Preferably, the integrated digital eddy current sensor system achieves a frequency sweep range covering 0.001 Hz / s to 100 kHz / s through the following combination: In ultra-low speed mode, the phase-locked loop bandwidth is set to 1 mHz, corresponding to a frequency sweep rate R low =0.001Hz / s; In high-speed mode: signal slew rate Corresponding to the maximum sweep rate .

[0020] Optionally, the FPGA hardware acceleration unit includes timing control logic, and its interface timing satisfies: clock period ≤ 100ns; setup time ≥ 2ns; and hold time ≥ 0.5ns.

[0021] Preferably, the phase error feedback closed loop includes a phase detection network employing a digital phase keyer structure.

[0022] The integrated digital eddy current sensor system of the present invention solves the error problem of traditional digital eddy current sensors when simulating mechanical acceleration characteristics. By integrating a polynomial curve engine, hardware acceleration calculation and phase compensation algorithm, it achieves high-precision acceleration simulation and is suitable for scenarios with high requirements for acceleration measurement accuracy, such as rotating machinery condition monitoring and precision bearing fault diagnosis.

[0023] In particular, in the preferred embodiment, the integrated digital eddy current sensor system of this invention solves the problem of excessive acceleration simulation errors caused by traditional step frequency scanning through the collaborative design of a fifth-order polynomial dynamic fitting engine and an FPGA hardware acceleration unit. It employs an adaptive phase synchronization compensation algorithm to achieve high-precision tracking with a phase error ≤0.3° under a 10kHz reference signal. Combined with Δ-Sigma compression storage technology, it can support 1 million frequency curves (compression ratio 1:8) within 4GB of storage space, meeting the ultra-wide frequency sweep requirements from 0.001Hz / s to 100kHz / s (corresponding to a phase-locked loop bandwidth of 1mHz to a conversion rate ≥200V / μs). This invention overcomes the dynamic response bottleneck of traditional DSP processors through real-time polynomial coefficient calculation and a hardware-accelerated pipeline (100ns / parameter update cycle). Verified by a laser interferometric reference, the vibration phase spectrum analysis accuracy is improved to over 99.5%. Attached Figure Description

[0024] Figure 1 This is an architectural block diagram of the three-level collaborative structure of the integrated digital eddy current sensor system according to some embodiments of the present invention;

[0025] Figure 2 This is an architecture diagram of the mathematical model layer of the fifth-order dynamic polynomial engine in some embodiments of the present invention, which includes accelerometer constraints;

[0026] Figure 3 This is an architecture diagram of the pipeline architecture of a fifth-order dynamic polynomial engine in some embodiments of the present invention.

[0027] Figure 4 This is an architecture diagram of the constraint embedding mechanism of the fifth-order dynamic polynomial engine in some embodiments of the present invention;

[0028] Figure 5 This is a schematic representation of the frequency-amplitude-phase three-dimensional mapping in some embodiments of the present invention;

[0029] Figure 6 This is a block diagram of the FPGA pipeline topology in some embodiments of the present invention;

[0030] Figure 7 These are open-loop amplitude-frequency characteristic curves of the phase closed-loop compensation structure in some embodiments of the present invention;

[0031] Figure 8 These are open-loop phase frequency characteristic curves of the phase closed-loop compensation structure in some embodiments of the present invention;

[0032] Figure 9 This is a block diagram of the phase closed-loop compensation structure in some embodiments of the present invention; and

[0033] Figure 10This is a flowchart of the Δ-Sigma compression encoding process in some embodiments of the present invention. Detailed Implementation

[0034] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0035] See Figures 1 to 10 An integrated digital eddy current sensor system according to a basic embodiment of the present invention has a three-level collaborative structure, which includes a dynamic polynomial engine, a hardware acceleration unit, and a phase compensation module. The dynamic polynomial engine is used to generate a three-dimensional frequency-amplitude-phase mapping table using polynomial equations and output multiple sets of parallel coefficients to the hardware acceleration unit. The hardware acceleration unit is used to construct a pipelined computing architecture to realize parameter updates and compression encoding at a set period. The phase compensation module is used to establish a phase error feedback closed loop to control the phase error within a set error range under a reference signal.

[0036] In the above basic implementation, the integrated digital eddy current sensor system of the present invention adopts a three-level collaborative structure. By integrating a polynomial curve engine, hardware accelerated calculation and phase compensation algorithm, it solves the acceleration error of traditional step scanning and realizes high-precision acceleration simulation.

[0037] In some embodiments, the dynamic polynomial engine uses fifth-degree polynomial equations to generate a three-dimensional frequency-amplitude-phase mapping table in real time: Furthermore, jerk constraints are introduced:

[0038] ;

[0039] J max To determine the maximum permissible jerk of the tested mechanical system, a three-dimensional parameter space mapping table is used to constrain the slope of the frequency, the gradient of the amplitude, and the rate of change of the phase. This ensures frequency sweep continuity, eliminates acceleration gradient breaks, and controls the acceleration error to ≤0.5%. For example, in some applications of the aforementioned fifth-order polynomial, J... max The parameter range can be set to 0.1–5 g / s. This constraint ensures that the fifth-degree polynomial satisfies C in the time domain. 3 The continuity requirement effectively suppresses transient impacts caused by sudden changes in acceleration. The above... It is a dynamic fifth-degree polynomial. a 5 to a 0 represents the polynomial coefficients, and t represents time. For polynomials The third derivative of, where the coefficients a 5 to a 0 is solved in real time using Newton's iterative method, and the convergence condition of the iteration is: It should be noted that the above description only uses a fifth-degree polynomial as an example. Within the scope of the technical concept of this invention, It can be a polynomial of other powers.

[0040] In some embodiments, the hardware acceleration unit may employ a three-stage pipeline architecture built on an FPGA, implementing parameter updates and Δ-Sigma compression encoding with a 100ns cycle. Specifically, the hardware acceleration unit may include a dual-port BRAM cache matrix and a customized pipelined computation unit, wherein the customized pipelined computation unit is configured to include: a coefficient loading module for loading the multiple sets of parallel coefficients into a register file in parallel; a pipelined computation module for performing staged computations based on timestamps; and a result synthesis module for weighted summation of the computation results at each stage and outputting them to the digital-to-analog conversion module.

[0041] Typically, the above specific calculation process may include: coefficient loading: dual-port BRAM caching, for example, a 512×64-bit coefficient matrix; parallel operation: distributed arithmetic optimization calculation; result synthesis, weighted accumulation, and output to the digital-to-analog conversion module.

[0042] In other implementations, the FPGA hardware acceleration unit may also include timing control logic whose interface timing satisfies: clock cycle ≤ 100ns; setup time ≥ 2ns; and hold time ≥ 0.5ns.

[0043] In some embodiments, Δ-Sigma compression coding can employ a second-order modulator architecture, typically a cascaded integrator feedback topology. The specific process may include: preprocessing: differentially encoding the original frequency curve; compression: compressing and storing the data using Δ-Sigma modulation; and decompression: recovering the original data using low-pass filtering. For example, by integrating Δ-Sigma compression, such as 16-bit to 2-bit compression (compression ratio 1:8), 1 million points of the curve can be stored in 4GB of space.

[0044] This preferred method has a data throughput of 100ns / parameter group (about 5 times higher than DSP) and a passband flatness of ≤±0.15dB.

[0045] In some embodiments, the phase compensation module can establish a phase error feedback closed loop through Hilbert transform and control the phase error within ≤0.3° under the reference signal at 10kHz. See also Figures 7 to 9 Specifically, the phase compensation module can adopt a closed-loop structure: the instantaneous phase is extracted through a Hilbert filter bank and input into an adaptive delay compensation model (ADCM).

[0046]

[0047] In the formula This is the phase compensation amount. For the target phase, The current phase error, =0.85、 =0.15 is an empirically optimized parameter, and τ is a time variable. Closed-loop tracking is achieved by adjusting the phase of the output signal in real time. This optimized method can achieve a phase error ≤0.3° and a convergence time ≤50μs. The adaptive delay compensation model adopts a proportional-integral control law, in which the proportional term quickly responds to sudden errors, and the integral term eliminates steady-state deviations; the integrator is set with a ±5V saturation limit to prevent integral overshoot. Experimental results show that the phase error convergence time is ≤50μs under a 10kHz reference signal, and the system stability margin is >45°. In some embodiments, the phase error feedback closed loop may optionally include a phase detection network using a digital phase keyer structure.

[0048] In some embodiments, the integrated digital eddy current sensor system achieves a frequency sweep range covering 0.001 Hz / s to 100 kHz / s through the following combination: In ultra-low speed mode, the phase-locked loop bandwidth is set to 1 mHz, corresponding to a frequency sweep rate R. low =0.001Hz / s; In high-speed mode: signal slew rate Corresponding to the maximum sweep rate .

[0049] As can be seen from the descriptions of the above embodiments, this invention, through the collaborative design of a fifth-order polynomial dynamic fitting engine and an FPGA hardware acceleration unit, introduces jerk constraints into the field of eddy current sensor signal synthesis for the first time, while ensuring C 5 While maintaining continuity, the frequency-amplitude-phase three-dimensional mapping relationship is dynamically adjusted in real time by solving multiple sets, such as 12 sets of parallel coefficients. This scheme reduces the acceleration simulation error caused by traditional step frequency scanning from >15% to ≤0.5%, and achieves a vibration phase spectrum analysis accuracy of over 99.5% in the typical vibration frequency band of 10Hz to 20kHz. This performance improvement stems from the polynomial engine's accurate modeling capability of the transient characteristics of mechanical systems: by introducing acceleration constraints. (Typical value range) =0.1–5g / s), effectively suppressing the acceleration gradient breakage phenomenon caused by abrupt changes in order in traditional piecewise polynomial fitting.

[0050] In terms of frequency sweep performance, the system achieves an ultra-wide sweep range of 0.001Hz / s to 100kHz / s through a dual technical approach of optimizing the phase-locked loop bandwidth and improving the signal conversion rate. In ultra-low speed mode, the phase-locked loop bandwidth is set to 1mHz, which can accurately capture the micro-amplitude resonance characteristics of large rotating machinery (such as steam turbines); in high-speed mode, the digital-to-analog converter driven by the FPGA hardware acceleration unit achieves a signal conversion rate of ≥200V / μs, meeting the high-frequency vibration monitoring requirements of aero-engine blades. Compared with existing technologies, this solution improves signal integrity by 3 times at a sweep rate of 100kHz / s, and achieves a passband flatness of ±0.15dB (within a 20kHz bandwidth).

[0051] The storage system employs Δ-Sigma compression technology, enabling the storage of 1 million frequency curves (compression ratio 1:8) within a 4GB storage space, breaking through the bandwidth bottleneck of traditional SRAM cache architectures. A second-order modulator compresses 16-bit raw data into 2-bit storage, achieving a decompression signal fidelity of -80dBc harmonic distortion, with a storage loading time ≤2ms. This innovation allows the system to maintain full-band signal integrity even in continuous frequency sweep mode. Compared to uncompressed storage solutions, storage density is increased by 8 times while high-frequency signal attenuation is reduced by 5dB, meeting the requirements for capturing weak harmonic components in precision bearing fault diagnosis.

[0052] In terms of phase control, the closed-loop compensation algorithm based on Hilbert transform reduces the phase error from >3° in existing technologies to ≤0.3° (10kHz benchmark test). The Adaptive Delay Compensation Model (ADCM) utilizes a proportional-integral control law. The system achieves a phase tracking error convergence time of ≤50μs under dynamic acceleration variations. Verified using laser interferometry, the closed-loop system demonstrates a phase consistency better than 0.5° across the entire frequency band from 0.1 to 100kHz, representing a more than 10-fold improvement in tracking accuracy compared to open-loop compensation schemes. Furthermore, the integrated temperature compensation circuit (±0.05% / ℃ stability) and 50Ω characteristic impedance matching network ensure measurement consistency across an ambient temperature range of -40℃ to +85℃, meeting the application requirements of complex industrial environments.

[0053] To help those skilled in the art to understand the present invention more deeply, a more detailed and comprehensive embodiment is described below to help understand the technical concept of the present invention at the implementation level.

[0054] In terms of hardware platform construction and core component selection

[0055] This invention revolves around the FPGA main control unit, signal generation module and peripheral interface to systematically construct the system. By deeply optimizing the circuit topology and key component selection, it achieves the engineering feasibility of dynamic frequency synthesis and phase compensation while ensuring a parameter update cycle of 100ns.

[0056] (1) Selection and architecture design of main control unit

[0057] The core processor is selected from the Xilinx Zynq UltraScale+ MPSoC series (such as XCZU9EG), whose heterogeneous architecture of a hard-core FPGA (containing 354K logic units) and a quad-core ARM Cortex-A53 processor matches the real-time solution and closed-loop control requirements of the fifth-order polynomial proposed in this invention. The FPGA part is responsible for 100ns-level parameter updates and Δ-Sigma compression calculations, while the ARM subsystem undertakes host computer communication and system calibration tasks. Interconnection via the AXI4-ACE high-speed bus ensures that the multi-core collaborative latency is ≤10ns. The 19nm process technology of this chip reduces its power consumption by 30% compared to the previous generation (typical power consumption is only 5W), and with the heat sink and airflow design, it meets the wide temperature range requirements of industrial environments from -40℃ to +85℃.

[0058] (2) Multilayer PCB layout and signal integrity

[0059] A 6-layer high-frequency PCB design is employed, with layer 3 being a complete ground plane and layer 5 featuring 50Ω characteristic impedance transmission lines to ensure isolation of mixed-signal signals. Power layer partitioning follows the 20H rule (power layers are 20 times smaller than ground layers in terms of dielectric thickness) to reduce edge-radiated interference. Critical signal lines (such as clock lines) utilize stripline routing, with length errors controlled within ±0.1mm (corresponding to a delay deviation ≤0.5ps). For FPGA high-speed I / O (3.3V LVDS@1Gbps), a 10° tapered fan-out angle routing is used to reduce reflection losses. Simulation results demonstrate that at a 100MHz clock frequency, SSN (Synchronous Switching Noise) suppression reaches -65dBc, meeting the requirements for high-precision phase control.

[0060] (3) Construction of power management system

[0061] The power supply module employs a layered power supply strategy: First, the FPGA core power supply uses a TI LMZ31501 step-down module (1.0V / 3A output), whose integrated inductor and MOSFET design ensures ripple noise <30mVpp (within a 20MHz bandwidth). An external RC network sets the soft-start time to 10ms to avoid power-up surges. Second, the analog front-end power supply uses an ADI ADP7118 low-dropout linear regulator (5V→3.3V@500mA), achieving a PSRR of 70dB at 1kHz, ensuring a signal-to-noise ratio ≥82dB for the DAC (e.g., TI DAC5687). Third, the digital interface power supply uses an ON Semiconductor NCP1117 regulator to provide 2.5V to the Ethernet PHY (e.g., TI DP83848), with an output voltage accuracy of ±2%, meeting the IEEE 802.3u physical layer specification.

[0062] (4) Clock circuit design and stability

[0063] The clock source is a SiTime Si570 programmable oscillator, outputting a 125MHz differential clock (LVDS format) with a phase jitter (RMS) of <50fs@12kHz-20MHz, meeting the jitter budget of the FPGA global clock network (system requirement <100fs). Frequency fine-tuning is achieved through the Si570's I2C interface, supporting a frequency resolution of ±0.01%. Clock distribution uses a TICDCL6800 fan-out buffer, distributing the single input clock into four low-skew outputs (Skew <50ps) to drive the FPGA global clock tree and the DAC sampling clock. Actual measurements show that the output frequency stability reaches ±20ppm within a temperature range of -40℃ to +85℃, superior to traditional quartz crystal oscillators (±50ppm).

[0064] (5) Implementation of signal generation and conditioning module

[0065] The signal generation section employs a combination architecture of a high-speed DAC (such as the TI DAC5687) and a wideband amplifier (such as the Analog Devices AD8138): First, DAC selection: The DAC5687 supports 16-bit resolution and a 125MSPS sampling rate, with INL ±1.5LSB and DNL ±0.5LSB, ensuring that the harmonic distortion (THD) of the fifth-order polynomial synthesized signal is ≤-80dBc. Second, driver circuit: The AD8138 differential amplifier converts the current signal output by the DAC into a ±5V voltage signal (Rout=50Ω), with a bandwidth of 250MHz (-3dB) and a slew rate of 2700V / μs, meeting the transient response requirements for a 100kHz / s sweep frequency. Third, filtering network: A fifth-order elliptic low-pass filter (cutoff frequency 60MHz) is added at the DAC output to suppress the image frequency (attenuation >40dB at fs / 2=62.5MHz), while a common-mode choke is used to suppress high-frequency noise (100MHz@600Ω).

[0066] (6) Storage system design and data throughput optimization

[0067] The storage module uses Micron MT48LC16M16A-6A DDR4 chips (256MB×16bit), achieving data transfer at a clock speed of 400MHz (bandwidth 6.4GB / s) through the Xilinx MIGIP core. Key design features include: First, ECC verification: MIG's ECC function is enabled, using Hamming codes to detect and correct single-bit errors, achieving a bit error rate of <10%. -18 Second, burst transmission: A burst length of 128 is set, allowing for 2KB of data transfer per DMA operation. The PCIe 3.0 x1 interface achieves an effective bandwidth of 500MB / s (theoretical rate 985MB / s). Third, compression acceleration: A second-order Δ-Sigma modulator is deployed in the FPGA to compress 16-bit raw data into 2-bit storage (compression ratio 1:8). The decompressed SNR reaches 82dB (measured value), increasing storage density by 3 times compared to traditional lossless compression algorithms (such as LZ77).

[0068] (7) Interface and communication module configuration

[0069] First, the Ethernet interface: A TI DP83848 PHY chip is used to implement Gigabit Ethernet communication, connecting to the FPGA via an RGMII interface (clock frequency 125MHz). In the PCB layout, the MDI differential pair trace length matching error is <50mil (corresponding to a delay difference <10ps), ensuring a bit error rate <10% over a 100m transmission distance. -6Second, the PCIe interface: configured with a Xilinx LogiCOREPCIe 3.0 Endpoint IP core, using Gen3x1 mode, and achieving zero-copy data transmission through the TLP message mechanism. The physical layer uses an Avago AFBR-57J1CD optical module (transmission distance 2km) to avoid electromagnetic interference in industrial environments. Third, the debugging interface: reserved JTAG and UART debugging channels, with the UART baud rate set to 115.2kbps, and interaction with the PC achieved through an FTDI FT232RLUSB-to-serial converter chip.

[0070] Regarding the fifth-order polynomial dynamic engine

[0071] (1) Mathematical model construction and physical continuity assurance

[0072] This invention uses a fifth-degree polynomial Introduced into the field of eddy current sensor signal synthesis, through its C 5 The continuity property resolves the acceleration gradient breakage problem caused by traditional step-frequency scanning. Compared to the third-order polynomial, the fifth-order polynomial provides higher-order smoothness in its time derivative:

[0073] ① First derivative (velocity): ;

[0074] ② Second derivative (acceleration): ;

[0075] ③ Third derivative (jerk): ;

[0076] By guarantee The continuity of the system can eliminate transient shocks caused by sudden changes in acceleration in mechanical systems.

[0077] (2) Jerk constraint embedding and dynamic coefficient calculation

[0078] To achieve a balance between physical feasibility and dynamic response, this scheme will add jerk constraints. The process of solving embedded polynomial coefficients: First, setting constraint parameters: The algorithm is dynamically adjusted based on the maximum permissible impact value of the tested mechanical system, typically ranging from 0.1 to 5 g / s². Secondly, the real-time solution algorithm employs Newton's iteration method to construct a system of nonlinear equations, with the target acceleration 'a' as the input. target After timestamp t, the 12 sets of parallel coefficients are updated within 100ns. Specific steps: Initialization: Set initial coefficients; Iterative calculation: Solving for the correction using the Jacobian matrix until satisfied ; Convergence criterion: When the coefficient change between two consecutive iterations... The operation will terminate when the time is right.

[0079] The algorithm is implemented using an FPGA pipeline architecture, which breaks down the coefficient calculation into a five-stage pipeline (coefficient loading → exponentiation calculation → constraint application → parallel generation → cache writing), reducing latency by 5 times compared to traditional serial calculation.

[0080] (3) Optimization of 3D mapping table generation and storage

[0081] To support signal integrity in high-frequency sweep scenarios, this solution adopts a hierarchical three-dimensional mapping table design:

[0082] First, the offline generation stage: MATLAB scripts are used to generate a frequency-amplitude-phase mapping table of 1 million points, covering the sweep frequency range from 0.001Hz / s to 100kHz / s; the Δ-Sigma compression algorithm is applied to compress the 16-bit original data into 2-bit storage (compression ratio 1:8), and the passband flatness after decompression reaches ±0.15dB (within 20kHz bandwidth).

[0083] Second, online interpolation calculation: Deploy a linear interpolation module in the FPGA. When the target timestamp t lies between two mapping points, the interpolation is performed using the formula... Intermediate values ​​are generated; interpolation errors are controlled within ±0.05%. This design reduces storage bandwidth requirements by 8 times and solves the 3dB bandwidth attenuation problem that occurs when traditional SRAM caches are swept at frequencies above 100kHz.

[0084] (4) Hardware acceleration implementation and pipeline optimization

[0085] A three-stage pipeline architecture is constructed in the FPGA to achieve parameter update throughput of 100ns: First, the coefficient loading stage: reading from the dual-port BRAM via the AXI4-Stream protocol. a 5 to a Zero coefficient; a ping-pong buffer mechanism is used for alternating read and write operations to ensure a blockage-free pipeline. Second, the parallel computing stage: distributed arithmetic optimization is utilized, using LUT6 to implement t. 5 To t 0 Parallel computation of the items; critical path delay optimized to ≤95ns (clock period 100ns), timing jitter ≤0.1ns (3σ statistics). Third, result synthesis stage: weighted accumulation of the results of each order of operation, output to 16bit DAC; elimination of combinational logic glitches through register balancing, measured signal harmonic distortion THD ≤-80dBc.

[0086] Regarding the implementation of FPGA hardware acceleration units

[0087] The FPGA hardware acceleration unit of this invention aims for high-performance computing and low-latency response. Through a customized pipeline architecture and distributed arithmetic optimization, it achieves a parameter update throughput of 100ns for a fifth-order polynomial dynamic fitting engine. This unit not only needs to perform polynomial operations but also integrate Δ-Sigma compression coding functionality to achieve system performance targets under the constraints of limited FPGA resources (such as LUTs and DSP slices).

[0088] (1) Pipeline architecture design and stage decomposition

[0089] The hardware acceleration unit adopts a three-stage pipeline architecture, which breaks down the fifth-order polynomial operation into three stages: coefficient loading, parallel operation, and result synthesis.

[0090] (2) Timing optimization and resource allocation strategies

[0091] To meet the 100ns-level parameter update cycle, granular management of FPGA resources is required: First, critical path analysis: using the Vivado timing analysis tool to identify the longest path, and discovering t 5 The multiplier latency accounts for 60% of the total path latency. By inserting a two-stage pipelined register, the critical path latency was reduced from 12ns to 5ns. Second, LUT and DSP Slice allocation: Five-order polynomial operations require 30 multipliers (one for each exponentiation term), occupying 15% of the DSP48E2 Slice resources. The remaining LUT resources are used for Δ-Sigma compression coding and phase compensation algorithms. Third, clock domain management: The global clock network uses a BUFGCE buffer to ensure clock skew <50ps. For the Δ-Sigma modulator, a separate 125MHz clock domain is configured, and cross-clock domain data synchronization is achieved through asynchronous FIFO.

[0092] (3) Δ-Sigma compression coding implementation

[0093] To address the storage bandwidth bottleneck in high-frequency sweep scenarios, this solution deploys a second-order Δ-Sigma modulator in an FPGA: First, the modulator architecture adopts a cascaded integrator feedback (CIFB) topology, comprising two integrator stages and a 1-bit quantizer. The first-stage integrator accumulates the input data and feedback signal, while the second-stage integrator performs a second integration of the residual signal, ultimately generating a 1-bit output through a comparator. Second, hardware resource consumption: the modulator uses 120 LUTs and 4 DSP slices to achieve 16-bit to 2-bit compression (compression ratio 1:8). Third, data flow control: compressed data is written to the DDR4 storage module via a DMA engine, employing a burst length of 128 bytes, achieving an effective bandwidth of 500MB / s, and loading a 1 million-point curve takes only 2ms.

[0094] Regarding the deployment of phase synchronization compensation algorithms

[0095] The phase synchronization compensation algorithm of this invention is based on a closed-loop feedback architecture. Through the synergistic effect of Hilbert transform and adaptive integral control, it achieves high-precision tracking with a phase error ≤0.3° under a 10kHz reference signal, thus solving the phase delay accumulation problem of eddy current sensors in high-frequency sweeping scenarios.

[0096] (1) Phase detection and error generation

[0097] A phase detection network is constructed using a 64-tap FIR Hilbert transform filter to generate instantaneous phase signals (I / Q). The instantaneous phase is compared with the target phase. Comparison yields the error signal. To suppress high-frequency noise interference, the error signal is smoothed by a low-pass filter (cutoff frequency 20kHz) and the input amplitude is normalized by an automatic gain control (AGC) module to ensure that the Hilbert converter operates in the linear region.

[0098] (2) Adaptive Delay Compensation Model (ADCM)

[0099] The ADCM model employs a proportional-integral control law. The proportional term rapidly responds to sudden errors, while the integral term eliminates steady-state bias. In the specific implementation, the integrator employs a dual-integrator structure with a saturation limit (±5V) to prevent integral overshoot; the proportional gain K... p Dynamically adjusted via lookup table, K is set segmentally according to the error amplitude (e.g., K is set when |e(t)| < 1°). p =0.7), improving convergence speed in scenarios with large errors. The compensation signal is output to the VCO through a 16-bit DAC to dynamically adjust the signal phase.

[0100] In terms of storage system design and data loading

[0101] This invention's storage system, through a collaborative design of Δ-Sigma compression technology and a high-speed cache architecture, achieves the storage of 1 million frequency curves (compression ratio 1:8) within 4GB of physical space, breaking through the bandwidth bottleneck of traditional eddy current sensor storage. The solution employs a second-order modulation compression algorithm to reduce data redundancy while ensuring signal integrity after decompression, supporting real-time data throughput across an ultra-wide sweep frequency range of 0.001Hz / s to 100kHz / s.

[0102] (1) Hardware architecture and compression algorithm

[0103] The storage module is built using Micron MT48LC16M16A-6A DDR4 chips and achieves data transmission at a clock speed of 400MHz (bandwidth 6.4GB / s) through a Xilinx MIG IP core. The core innovation lies in the first-ever introduction of a second-order Δ-Sigma modulator for data compression in an eddy current sensor: employing a cascaded integrator feedback (CIFB) topology, the 16-bit original frequency curve is compressed into 2 bits for storage (compression ratio 1:8), resulting in a decompressed harmonic distortion (THD) ≤-80dBc and a passband flatness of ±0.15dB (within a 20kHz bandwidth). This algorithm utilizes only 120 LUTs and 4 DSP slices on the FPGA, ensuring that remaining resources can be used for polynomial operations and phase compensation.

[0104] (2) Data loading and fast access optimization

[0105] The data loading process is divided into three stages: host computer transmission, FPGA compression, and storage writing. First, host computer transmission: 1 million frequency curve points are sent to the DDR4 cache via Gigabit Ethernet, using a UDP protocol stack to optimize transmission efficiency (measured throughput 850Mbps). Second, FPGA compression: A Δ-Sigma modulation program is initiated to compress the 16-bit raw data into 2 bits and write it to a 4GB storage module (actually occupying 512MB of physical space). Third, a fast loading mechanism: A 512×64-bit dual-port BRAM is configured as a buffer between the FPGA and DDR4, supporting 12 sets of parallel coefficient read / write; the PCIe 3.0 x1 interface uses a DMA transmission mode with a burst length of 128, loading 1 million curve points takes only 2ms, meeting the real-time requirement of 100kHz / s frequency sweep.

[0106] In terms of system integration and testing verification

[0107] The system integration of this invention revolves around the collaborative optimization of the hardware platform and the core algorithm. Through module joint debugging, functional verification and environmental adaptability testing, the system ultimately achieves the following performance indicators: acceleration simulation error ≤0.5%, phase error ≤0.3° and rapid loading of 1 million frequency curves.

[0108] (1) Hardware integration and functional verification

[0109] After completing the development of each module, the first step is to perform hardware integration testing:

[0110] ① Signal Link Test: Connect the FPGA output signal to the eddy current sensor probe and observe the integrity of the output signal using an oscilloscope. Configure an impedance matching network (50Ω series resistor + 200pF DC blocking capacitor) to ensure a VSWR < 1.2 and a signal transmission efficiency > 95%.

[0111] ② Phase closed-loop test: A 10kHz reference signal was injected, and the Hilbert transform and ADCM algorithm were started to monitor the phase error convergence process in real time. The test results showed that the phase error was ≤0.3° and the convergence time was ≤50μs, meeting the 100kHz / s frequency sweep requirement.

[0112] ③ Storage system verification: Play back 1 million points of frequency curve through PCIe 3.0 interface, loading time is 1.8ms (theoretical value is 2ms), after decompression signal THD≤-80dBc, passband flatness ±0.15dB (within 20kHz bandwidth).

[0113] (2) Environmental adaptability testing and calibration

[0114] To ensure reliability in industrial field applications, multi-dimensional environmental testing is required:

[0115] First, temperature cycling test: continuous operation for 100 hours in a temperature chamber ranging from -40℃ to +85℃, with temperature drift monitored to be ≤±0.05% / ℃. Real-time compensation of DAC output offset via an onboard temperature sensor (such as TI LM75) improves signal stability by 3 times.

[0116] Second, vibration and shock testing: The mechanical structure stability was verified by running on a 10g acceleration vibration table. The polynomial coefficients were dynamically adjusted using jerk constraints to suppress harmonic distortion by ≥5dB.

[0117] Third, long-term stability calibration: using a laser interferometer (resolution 0.1 μm / s). 2 ) Collect 100 sets of acceleration data, generate an error compensation matrix Δai, and correct the output signal in real time, so that the acceleration synthesis error is reduced from the initial 15% to ≤0.5%.

[0118] As can be seen from the description of the various embodiments of the present invention, this invention proposes an integrated digital eddy current sensor system, aiming to solve the problems of excessive acceleration simulation errors, limited high-frequency sweep response, and insufficient storage bandwidth caused by traditional step-frequency scanning. This solution, through deep collaborative design of a fifth-order polynomial dynamic fitting engine and an FPGA hardware acceleration unit, introduces jerk constraints into the field of eddy current sensor signal synthesis for the first time, overcoming the order-delay mismatch contradiction of traditional piecewise polynomial fitting. Specifically, the system of this invention employs a fifth-order polynomial equation... A dynamic frequency-amplitude-phase three-dimensional mapping table is constructed, and multiple sets of parallel coefficients are calculated in real time, while ensuring C 5 Continuity (C) 5 The continuity representation function and its first five derivatives are continuous, while introducing jerk constraints. ,in The dynamic adjustment is based on the maximum permissible impact value of the tested mechanical system (typical range 0.1–5 g / s). This innovative design reduces the acceleration synthesis error from >15% in existing technologies to ≤0.5%, while supporting an ultra-wide sweep frequency range of 0.001 Hz / s to 100 kHz / s, covering the needs of ultra-low speed and high speed extreme operating conditions.

[0119] At the hardware implementation level, this invention employs a customized FPGA pipeline architecture to achieve a parameter update throughput of 100ns, a 5-fold performance improvement compared to the 500ns latency of traditional DSP processors. This architecture comprises a three-stage pipelined computation unit: the first-stage coefficient loading module reads coefficients a5 to a0 in parallel through a dual-port BRAM cache matrix (512×64bit); the second-stage computation module calculates terms t5 to t0 in stages based on timestamp t, employing distributed arithmetic optimization to reduce multiplier resource consumption; and the final-stage synthesis module generates the final output signal through weighted accumulation. To meet the requirements of high-frequency signal integrity, the system integrates Δ-Sigma compression storage technology, enabling, for example, storage of 1 million frequency curve points (compression ratio 1:8) within a 4GB storage space. This technology uses a second-order modulator architecture to compress 16-bit raw data into 2-bit storage, achieving a passband flatness better than ±0.15dB (within a 20kHz bandwidth) after decompression, effectively solving the 3dB bandwidth attenuation problem that occurs when traditional SRAM caches sweep frequencies above 100kHz.

[0120] In terms of phase control, the system innovatively adopts a closed-loop compensation algorithm based on Hilbert transform, overcoming the dynamic response limitations of existing open-loop compensation schemes. Specifically, the phase detection network extracts the instantaneous phase of the signal through a Hilbert filter bank, compares it with the target phase, and generates an error signal e(t). This error signal is input to the adaptive delay compensation model (ADCM), whose control equation is: The system suppresses high-frequency noise interference through the integral term and rapidly responds to abrupt signal changes through the proportional term. Verified by laser interferometry benchmark testing, this scheme achieves a phase error ≤0.3° with a 10kHz reference signal. Furthermore, the system integrates a temperature compensation circuit (±0.05% / ℃ stability) and an impedance matching network (50Ω characteristic impedance) to ensure measurement consistency across an ambient temperature range of -40℃ to +85℃.

[0121] Therefore, the integrated digital eddy current sensor architecture proposed in this invention uses a fifth-order polynomial curve engine to fit the continuous acceleration variation characteristics, replacing the traditional step-like simulation method. Combined with FPGA hardware acceleration unit co-design, it introduces jerk constraints to achieve a parameter update throughput of 100ns. A closed-loop phase correction algorithm using Hilbert transform and an adaptive delay compensation model controls the phase error to ≤0.3°. Through Δ-Sigma compression storage technology, it supports 1 million frequency curves (compression ratio 1:8) within 4GB of space, covering an ultra-wide sweep frequency range from 0.001Hz / s to 100kHz / s. This solution solves the problem of excessive acceleration simulation error (error ≤0.5%) caused by traditional step-like frequency scanning, breaking through the technical bottlenecks of existing eddy current sensors in dynamic response accuracy and high-frequency signal integrity. This invention achieves a breakthrough in core indicators such as dynamic response accuracy, sweep frequency range coverage, and storage efficiency.

[0122] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. An integrated digital eddy current sensor system, characterized by, The integrated digital eddy current sensor system has a three-level cooperative structure, including a dynamic polynomial engine, a hardware acceleration unit and a phase compensation module, wherein The dynamic polynomial engine is used to generate a frequency-amplitude-phase three-dimensional mapping table by using a polynomial equation, and output a plurality of sets of parallel coefficients to the hardware acceleration unit; The hardware acceleration unit is used to construct a pipeline computing architecture to realize parameter updating and compression encoding with a set period; The phase compensation module is used to establish a phase error feedback closed loop to control the phase error within a set error range under a reference signal; The dynamic polynomial engine includes a dynamic constraint module, which introduces a jerk constraint condition in the solution process of the plurality of sets of parallel coefficients: ； wherein J max is the maximum allowed jerk of the mechanical system under test, which constrains the slope of the frequency, the gradient of the amplitude and the rate of change of the phase by a three-dimensional parametric space map, is the third derivative of the polynomial equation ​ The hardware acceleration unit includes a dual-port BRAM cache matrix and a customized pipeline computing unit, wherein The customized pipeline computing unit is configured to include: A coefficient loading module for parallel loading of the plurality of sets of parallel coefficients to a register stack; A pipeline operation module for phased calculation based on a timestamp; and A result synthesis module for weighted accumulation of the operation results of each stage and output to a digital-to-analog conversion module; The phase compensation module includes an adaptive delay compensation model and a Hilbert filter group, wherein the expression of the adaptive delay compensation model is: ； In the formula is a phase compensation amount, is a target phase, is a current phase error, =0.85, =0.15 are empirical optimization parameters, and τ is a time variable, and closed-loop tracking is achieved by adjusting the phase of the output signal in real time. The dynamic polynomial engine employs a fifth order polynomial equation generating the frequency-magnitude-phase three-dimensional map, where a5 to a0 are polynomial coefficients and t is time; The hardware acceleration unit constructs the pipeline computing architecture based on FPGA, and realizes parameter updating and Δ-Sigma compression encoding with a period of 100 ns; The phase compensation module establishes a phase error feedback closed loop through Hilbert transform, and controls the phase error within a range of ≤0.3° under a reference signal of 10 kHz.

2. The integrated digital eddy current sensor system of claim 1, wherein, The Δ-Sigma compression encoding adopts a second-order modulator architecture, including: First, preprocessing: differential encoding of the original frequency curve; Second, compression: compress and store data through Δ-Sigma modulation; Third, decompression: recover the original data through low-pass filtering.

3. The integrated digital eddy current sensor system of claim 2, wherein, The second-order modulator adopts a cascade integrator feedback type topology structure.

4. The integrated digital eddy current sensor system of claim 1, wherein, The hardware acceleration unit includes timing control logic, which interfaces timing that satisfies: clock period ≤100 ns; setup time ≥2 ns; and hold time ≥0.5 ns.

5. The integrated digital eddy current sensor system of claim 1, wherein, The phase error feedback closed loop includes a phase detection network using a digital phase detector structure.

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